1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPIO driver for AMD 4 * 5 * Copyright (c) 2014,2015 AMD Corporation. 6 * Authors: Ken Xue <Ken.Xue@amd.com> 7 * Wu, Jeff <Jeff.Wu@amd.com> 8 * 9 * Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com> 10 * Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 11 */ 12 13 #include <linux/err.h> 14 #include <linux/bug.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/spinlock.h> 18 #include <linux/compiler.h> 19 #include <linux/types.h> 20 #include <linux/errno.h> 21 #include <linux/log2.h> 22 #include <linux/io.h> 23 #include <linux/gpio/driver.h> 24 #include <linux/slab.h> 25 #include <linux/platform_device.h> 26 #include <linux/mutex.h> 27 #include <linux/acpi.h> 28 #include <linux/seq_file.h> 29 #include <linux/interrupt.h> 30 #include <linux/list.h> 31 #include <linux/bitops.h> 32 #include <linux/pinctrl/pinconf.h> 33 #include <linux/pinctrl/pinconf-generic.h> 34 35 #include "core.h" 36 #include "pinctrl-utils.h" 37 #include "pinctrl-amd.h" 38 39 static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset) 40 { 41 unsigned long flags; 42 u32 pin_reg; 43 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 44 45 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 46 pin_reg = readl(gpio_dev->base + offset * 4); 47 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 48 49 return !(pin_reg & BIT(OUTPUT_ENABLE_OFF)); 50 } 51 52 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 53 { 54 unsigned long flags; 55 u32 pin_reg; 56 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 57 58 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 59 pin_reg = readl(gpio_dev->base + offset * 4); 60 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); 61 writel(pin_reg, gpio_dev->base + offset * 4); 62 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 63 64 return 0; 65 } 66 67 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 68 int value) 69 { 70 u32 pin_reg; 71 unsigned long flags; 72 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 73 74 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 75 pin_reg = readl(gpio_dev->base + offset * 4); 76 pin_reg |= BIT(OUTPUT_ENABLE_OFF); 77 if (value) 78 pin_reg |= BIT(OUTPUT_VALUE_OFF); 79 else 80 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 81 writel(pin_reg, gpio_dev->base + offset * 4); 82 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 83 84 return 0; 85 } 86 87 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) 88 { 89 u32 pin_reg; 90 unsigned long flags; 91 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 92 93 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 94 pin_reg = readl(gpio_dev->base + offset * 4); 95 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 96 97 return !!(pin_reg & BIT(PIN_STS_OFF)); 98 } 99 100 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) 101 { 102 u32 pin_reg; 103 unsigned long flags; 104 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 105 106 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 107 pin_reg = readl(gpio_dev->base + offset * 4); 108 if (value) 109 pin_reg |= BIT(OUTPUT_VALUE_OFF); 110 else 111 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 112 writel(pin_reg, gpio_dev->base + offset * 4); 113 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 114 } 115 116 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, 117 unsigned debounce) 118 { 119 u32 time; 120 u32 pin_reg; 121 int ret = 0; 122 unsigned long flags; 123 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 124 125 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 126 pin_reg = readl(gpio_dev->base + offset * 4); 127 128 if (debounce) { 129 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 130 pin_reg &= ~DB_TMR_OUT_MASK; 131 /* 132 Debounce Debounce Timer Max 133 TmrLarge TmrOutUnit Unit Debounce 134 Time 135 0 0 61 usec (2 RtcClk) 976 usec 136 0 1 244 usec (8 RtcClk) 3.9 msec 137 1 0 15.6 msec (512 RtcClk) 250 msec 138 1 1 62.5 msec (2048 RtcClk) 1 sec 139 */ 140 141 if (debounce < 61) { 142 pin_reg |= 1; 143 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 144 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 145 } else if (debounce < 976) { 146 time = debounce / 61; 147 pin_reg |= time & DB_TMR_OUT_MASK; 148 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 149 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 150 } else if (debounce < 3900) { 151 time = debounce / 244; 152 pin_reg |= time & DB_TMR_OUT_MASK; 153 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 154 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 155 } else if (debounce < 250000) { 156 time = debounce / 15600; 157 pin_reg |= time & DB_TMR_OUT_MASK; 158 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 159 pin_reg |= BIT(DB_TMR_LARGE_OFF); 160 } else if (debounce < 1000000) { 161 time = debounce / 62500; 162 pin_reg |= time & DB_TMR_OUT_MASK; 163 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 164 pin_reg |= BIT(DB_TMR_LARGE_OFF); 165 } else { 166 pin_reg &= ~DB_CNTRl_MASK; 167 ret = -EINVAL; 168 } 169 } else { 170 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 171 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 172 pin_reg &= ~DB_TMR_OUT_MASK; 173 pin_reg &= ~DB_CNTRl_MASK; 174 } 175 writel(pin_reg, gpio_dev->base + offset * 4); 176 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 177 178 return ret; 179 } 180 181 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset, 182 unsigned long config) 183 { 184 u32 debounce; 185 186 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 187 return -ENOTSUPP; 188 189 debounce = pinconf_to_config_argument(config); 190 return amd_gpio_set_debounce(gc, offset, debounce); 191 } 192 193 #ifdef CONFIG_DEBUG_FS 194 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) 195 { 196 u32 pin_reg; 197 unsigned long flags; 198 unsigned int bank, i, pin_num; 199 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 200 201 char *level_trig; 202 char *active_level; 203 char *interrupt_enable; 204 char *interrupt_mask; 205 char *wake_cntrl0; 206 char *wake_cntrl1; 207 char *wake_cntrl2; 208 char *pin_sts; 209 char *pull_up_sel; 210 char *pull_up_enable; 211 char *pull_down_enable; 212 char *output_value; 213 char *output_enable; 214 215 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { 216 seq_printf(s, "GPIO bank%d\t", bank); 217 218 switch (bank) { 219 case 0: 220 i = 0; 221 pin_num = AMD_GPIO_PINS_BANK0; 222 break; 223 case 1: 224 i = 64; 225 pin_num = AMD_GPIO_PINS_BANK1 + i; 226 break; 227 case 2: 228 i = 128; 229 pin_num = AMD_GPIO_PINS_BANK2 + i; 230 break; 231 case 3: 232 i = 192; 233 pin_num = AMD_GPIO_PINS_BANK3 + i; 234 break; 235 default: 236 /* Illegal bank number, ignore */ 237 continue; 238 } 239 for (; i < pin_num; i++) { 240 seq_printf(s, "pin%d\t", i); 241 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 242 pin_reg = readl(gpio_dev->base + i * 4); 243 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 244 245 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { 246 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) & 247 ACTIVE_LEVEL_MASK; 248 interrupt_enable = "interrupt is enabled|"; 249 250 if (level == ACTIVE_LEVEL_HIGH) 251 active_level = "Active high|"; 252 else if (level == ACTIVE_LEVEL_LOW) 253 active_level = "Active low|"; 254 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) && 255 level == ACTIVE_LEVEL_BOTH) 256 active_level = "Active on both|"; 257 else 258 active_level = "Unknown Active level|"; 259 260 if (pin_reg & BIT(LEVEL_TRIG_OFF)) 261 level_trig = "Level trigger|"; 262 else 263 level_trig = "Edge trigger|"; 264 265 } else { 266 interrupt_enable = 267 "interrupt is disabled|"; 268 active_level = " "; 269 level_trig = " "; 270 } 271 272 if (pin_reg & BIT(INTERRUPT_MASK_OFF)) 273 interrupt_mask = 274 "interrupt is unmasked|"; 275 else 276 interrupt_mask = 277 "interrupt is masked|"; 278 279 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) 280 wake_cntrl0 = "enable wakeup in S0i3 state|"; 281 else 282 wake_cntrl0 = "disable wakeup in S0i3 state|"; 283 284 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) 285 wake_cntrl1 = "enable wakeup in S3 state|"; 286 else 287 wake_cntrl1 = "disable wakeup in S3 state|"; 288 289 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) 290 wake_cntrl2 = "enable wakeup in S4/S5 state|"; 291 else 292 wake_cntrl2 = "disable wakeup in S4/S5 state|"; 293 294 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { 295 pull_up_enable = "pull-up is enabled|"; 296 if (pin_reg & BIT(PULL_UP_SEL_OFF)) 297 pull_up_sel = "8k pull-up|"; 298 else 299 pull_up_sel = "4k pull-up|"; 300 } else { 301 pull_up_enable = "pull-up is disabled|"; 302 pull_up_sel = " "; 303 } 304 305 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) 306 pull_down_enable = "pull-down is enabled|"; 307 else 308 pull_down_enable = "Pull-down is disabled|"; 309 310 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { 311 pin_sts = " "; 312 output_enable = "output is enabled|"; 313 if (pin_reg & BIT(OUTPUT_VALUE_OFF)) 314 output_value = "output is high|"; 315 else 316 output_value = "output is low|"; 317 } else { 318 output_enable = "output is disabled|"; 319 output_value = " "; 320 321 if (pin_reg & BIT(PIN_STS_OFF)) 322 pin_sts = "input is high|"; 323 else 324 pin_sts = "input is low|"; 325 } 326 327 seq_printf(s, "%s %s %s %s %s %s\n" 328 " %s %s %s %s %s %s %s 0x%x\n", 329 level_trig, active_level, interrupt_enable, 330 interrupt_mask, wake_cntrl0, wake_cntrl1, 331 wake_cntrl2, pin_sts, pull_up_sel, 332 pull_up_enable, pull_down_enable, 333 output_value, output_enable, pin_reg); 334 } 335 } 336 } 337 #else 338 #define amd_gpio_dbg_show NULL 339 #endif 340 341 static void amd_gpio_irq_enable(struct irq_data *d) 342 { 343 u32 pin_reg; 344 unsigned long flags; 345 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 346 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 347 348 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 349 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 350 pin_reg |= BIT(INTERRUPT_ENABLE_OFF); 351 pin_reg |= BIT(INTERRUPT_MASK_OFF); 352 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 353 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 354 } 355 356 static void amd_gpio_irq_disable(struct irq_data *d) 357 { 358 u32 pin_reg; 359 unsigned long flags; 360 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 361 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 362 363 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 364 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 365 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); 366 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 367 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 368 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 369 } 370 371 static void amd_gpio_irq_mask(struct irq_data *d) 372 { 373 u32 pin_reg; 374 unsigned long flags; 375 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 376 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 377 378 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 379 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 380 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 381 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 382 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 383 } 384 385 static void amd_gpio_irq_unmask(struct irq_data *d) 386 { 387 u32 pin_reg; 388 unsigned long flags; 389 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 390 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 391 392 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 393 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 394 pin_reg |= BIT(INTERRUPT_MASK_OFF); 395 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 396 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 397 } 398 399 static void amd_gpio_irq_eoi(struct irq_data *d) 400 { 401 u32 reg; 402 unsigned long flags; 403 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 404 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 405 406 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 407 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 408 reg |= EOI_MASK; 409 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 410 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 411 } 412 413 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) 414 { 415 int ret = 0; 416 u32 pin_reg, pin_reg_irq_en, mask; 417 unsigned long flags, irq_flags; 418 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 419 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 420 421 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 422 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 423 424 /* Ignore the settings coming from the client and 425 * read the values from the ACPI tables 426 * while setting the trigger type 427 */ 428 429 irq_flags = irq_get_trigger_type(d->irq); 430 if (irq_flags != IRQ_TYPE_NONE) 431 type = irq_flags; 432 433 switch (type & IRQ_TYPE_SENSE_MASK) { 434 case IRQ_TYPE_EDGE_RISING: 435 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 436 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 437 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 438 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 439 irq_set_handler_locked(d, handle_edge_irq); 440 break; 441 442 case IRQ_TYPE_EDGE_FALLING: 443 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 444 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 445 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 446 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 447 irq_set_handler_locked(d, handle_edge_irq); 448 break; 449 450 case IRQ_TYPE_EDGE_BOTH: 451 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 452 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 453 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; 454 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 455 irq_set_handler_locked(d, handle_edge_irq); 456 break; 457 458 case IRQ_TYPE_LEVEL_HIGH: 459 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 460 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 461 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 462 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 463 pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF; 464 irq_set_handler_locked(d, handle_level_irq); 465 break; 466 467 case IRQ_TYPE_LEVEL_LOW: 468 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 469 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 470 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 471 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 472 pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF; 473 irq_set_handler_locked(d, handle_level_irq); 474 break; 475 476 case IRQ_TYPE_NONE: 477 break; 478 479 default: 480 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); 481 ret = -EINVAL; 482 } 483 484 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; 485 /* 486 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the 487 * debounce registers of any GPIO will block wake/interrupt status 488 * generation for *all* GPIOs for a length of time that depends on 489 * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the 490 * INTERRUPT_ENABLE bit will read as 0. 491 * 492 * We temporarily enable irq for the GPIO whose configuration is 493 * changing, and then wait for it to read back as 1 to know when 494 * debounce has settled and then disable the irq again. 495 * We do this polling with the spinlock held to ensure other GPIO 496 * access routines do not read an incorrect value for the irq enable 497 * bit of other GPIOs. We keep the GPIO masked while polling to avoid 498 * spurious irqs, and disable the irq again after polling. 499 */ 500 mask = BIT(INTERRUPT_ENABLE_OFF); 501 pin_reg_irq_en = pin_reg; 502 pin_reg_irq_en |= mask; 503 pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF); 504 writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4); 505 while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask) 506 continue; 507 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 508 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 509 510 return ret; 511 } 512 513 static void amd_irq_ack(struct irq_data *d) 514 { 515 /* 516 * based on HW design,there is no need to ack HW 517 * before handle current irq. But this routine is 518 * necessary for handle_edge_irq 519 */ 520 } 521 522 static struct irq_chip amd_gpio_irqchip = { 523 .name = "amd_gpio", 524 .irq_ack = amd_irq_ack, 525 .irq_enable = amd_gpio_irq_enable, 526 .irq_disable = amd_gpio_irq_disable, 527 .irq_mask = amd_gpio_irq_mask, 528 .irq_unmask = amd_gpio_irq_unmask, 529 .irq_eoi = amd_gpio_irq_eoi, 530 .irq_set_type = amd_gpio_irq_set_type, 531 .flags = IRQCHIP_SKIP_SET_WAKE, 532 }; 533 534 #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF)) 535 536 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id) 537 { 538 struct amd_gpio *gpio_dev = dev_id; 539 struct gpio_chip *gc = &gpio_dev->gc; 540 irqreturn_t ret = IRQ_NONE; 541 unsigned int i, irqnr; 542 unsigned long flags; 543 u32 *regs, regval; 544 u64 status, mask; 545 546 /* Read the wake status */ 547 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 548 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); 549 status <<= 32; 550 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0); 551 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 552 553 /* Bit 0-45 contain the relevant status bits */ 554 status &= (1ULL << 46) - 1; 555 regs = gpio_dev->base; 556 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) { 557 if (!(status & mask)) 558 continue; 559 status &= ~mask; 560 561 /* Each status bit covers four pins */ 562 for (i = 0; i < 4; i++) { 563 regval = readl(regs + i); 564 if (!(regval & PIN_IRQ_PENDING) || 565 !(regval & BIT(INTERRUPT_MASK_OFF))) 566 continue; 567 irq = irq_find_mapping(gc->irq.domain, irqnr + i); 568 if (irq != 0) 569 generic_handle_irq(irq); 570 571 /* Clear interrupt. 572 * We must read the pin register again, in case the 573 * value was changed while executing 574 * generic_handle_irq() above. 575 * If we didn't find a mapping for the interrupt, 576 * disable it in order to avoid a system hang caused 577 * by an interrupt storm. 578 */ 579 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 580 regval = readl(regs + i); 581 if (irq == 0) { 582 regval &= ~BIT(INTERRUPT_ENABLE_OFF); 583 dev_dbg(&gpio_dev->pdev->dev, 584 "Disabling spurious GPIO IRQ %d\n", 585 irqnr + i); 586 } 587 writel(regval, regs + i); 588 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 589 ret = IRQ_HANDLED; 590 } 591 } 592 593 /* Signal EOI to the GPIO unit */ 594 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 595 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 596 regval |= EOI_MASK; 597 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG); 598 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 599 600 return ret; 601 } 602 603 static int amd_get_groups_count(struct pinctrl_dev *pctldev) 604 { 605 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 606 607 return gpio_dev->ngroups; 608 } 609 610 static const char *amd_get_group_name(struct pinctrl_dev *pctldev, 611 unsigned group) 612 { 613 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 614 615 return gpio_dev->groups[group].name; 616 } 617 618 static int amd_get_group_pins(struct pinctrl_dev *pctldev, 619 unsigned group, 620 const unsigned **pins, 621 unsigned *num_pins) 622 { 623 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 624 625 *pins = gpio_dev->groups[group].pins; 626 *num_pins = gpio_dev->groups[group].npins; 627 return 0; 628 } 629 630 static const struct pinctrl_ops amd_pinctrl_ops = { 631 .get_groups_count = amd_get_groups_count, 632 .get_group_name = amd_get_group_name, 633 .get_group_pins = amd_get_group_pins, 634 #ifdef CONFIG_OF 635 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 636 .dt_free_map = pinctrl_utils_free_map, 637 #endif 638 }; 639 640 static int amd_pinconf_get(struct pinctrl_dev *pctldev, 641 unsigned int pin, 642 unsigned long *config) 643 { 644 u32 pin_reg; 645 unsigned arg; 646 unsigned long flags; 647 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 648 enum pin_config_param param = pinconf_to_config_param(*config); 649 650 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 651 pin_reg = readl(gpio_dev->base + pin*4); 652 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 653 switch (param) { 654 case PIN_CONFIG_INPUT_DEBOUNCE: 655 arg = pin_reg & DB_TMR_OUT_MASK; 656 break; 657 658 case PIN_CONFIG_BIAS_PULL_DOWN: 659 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); 660 break; 661 662 case PIN_CONFIG_BIAS_PULL_UP: 663 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); 664 break; 665 666 case PIN_CONFIG_DRIVE_STRENGTH: 667 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; 668 break; 669 670 default: 671 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n", 672 param); 673 return -ENOTSUPP; 674 } 675 676 *config = pinconf_to_config_packed(param, arg); 677 678 return 0; 679 } 680 681 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 682 unsigned long *configs, unsigned num_configs) 683 { 684 int i; 685 u32 arg; 686 int ret = 0; 687 u32 pin_reg; 688 unsigned long flags; 689 enum pin_config_param param; 690 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 691 692 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 693 for (i = 0; i < num_configs; i++) { 694 param = pinconf_to_config_param(configs[i]); 695 arg = pinconf_to_config_argument(configs[i]); 696 pin_reg = readl(gpio_dev->base + pin*4); 697 698 switch (param) { 699 case PIN_CONFIG_INPUT_DEBOUNCE: 700 pin_reg &= ~DB_TMR_OUT_MASK; 701 pin_reg |= arg & DB_TMR_OUT_MASK; 702 break; 703 704 case PIN_CONFIG_BIAS_PULL_DOWN: 705 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); 706 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; 707 break; 708 709 case PIN_CONFIG_BIAS_PULL_UP: 710 pin_reg &= ~BIT(PULL_UP_SEL_OFF); 711 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; 712 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); 713 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; 714 break; 715 716 case PIN_CONFIG_DRIVE_STRENGTH: 717 pin_reg &= ~(DRV_STRENGTH_SEL_MASK 718 << DRV_STRENGTH_SEL_OFF); 719 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) 720 << DRV_STRENGTH_SEL_OFF; 721 break; 722 723 default: 724 dev_err(&gpio_dev->pdev->dev, 725 "Invalid config param %04x\n", param); 726 ret = -ENOTSUPP; 727 } 728 729 writel(pin_reg, gpio_dev->base + pin*4); 730 } 731 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 732 733 return ret; 734 } 735 736 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, 737 unsigned int group, 738 unsigned long *config) 739 { 740 const unsigned *pins; 741 unsigned npins; 742 int ret; 743 744 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 745 if (ret) 746 return ret; 747 748 if (amd_pinconf_get(pctldev, pins[0], config)) 749 return -ENOTSUPP; 750 751 return 0; 752 } 753 754 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, 755 unsigned group, unsigned long *configs, 756 unsigned num_configs) 757 { 758 const unsigned *pins; 759 unsigned npins; 760 int i, ret; 761 762 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 763 if (ret) 764 return ret; 765 for (i = 0; i < npins; i++) { 766 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) 767 return -ENOTSUPP; 768 } 769 return 0; 770 } 771 772 static const struct pinconf_ops amd_pinconf_ops = { 773 .pin_config_get = amd_pinconf_get, 774 .pin_config_set = amd_pinconf_set, 775 .pin_config_group_get = amd_pinconf_group_get, 776 .pin_config_group_set = amd_pinconf_group_set, 777 }; 778 779 #ifdef CONFIG_PM_SLEEP 780 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) 781 { 782 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 783 784 if (!pd) 785 return false; 786 787 /* 788 * Only restore the pin if it is actually in use by the kernel (or 789 * by userspace). 790 */ 791 if (pd->mux_owner || pd->gpio_owner || 792 gpiochip_line_is_irq(&gpio_dev->gc, pin)) 793 return true; 794 795 return false; 796 } 797 798 static int amd_gpio_suspend(struct device *dev) 799 { 800 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 801 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 802 int i; 803 804 for (i = 0; i < desc->npins; i++) { 805 int pin = desc->pins[i].number; 806 807 if (!amd_gpio_should_save(gpio_dev, pin)) 808 continue; 809 810 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin*4); 811 } 812 813 return 0; 814 } 815 816 static int amd_gpio_resume(struct device *dev) 817 { 818 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 819 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 820 int i; 821 822 for (i = 0; i < desc->npins; i++) { 823 int pin = desc->pins[i].number; 824 825 if (!amd_gpio_should_save(gpio_dev, pin)) 826 continue; 827 828 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin*4); 829 } 830 831 return 0; 832 } 833 834 static const struct dev_pm_ops amd_gpio_pm_ops = { 835 SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend, 836 amd_gpio_resume) 837 }; 838 #endif 839 840 static struct pinctrl_desc amd_pinctrl_desc = { 841 .pins = kerncz_pins, 842 .npins = ARRAY_SIZE(kerncz_pins), 843 .pctlops = &amd_pinctrl_ops, 844 .confops = &amd_pinconf_ops, 845 .owner = THIS_MODULE, 846 }; 847 848 static int amd_gpio_probe(struct platform_device *pdev) 849 { 850 int ret = 0; 851 int irq_base; 852 struct resource *res; 853 struct amd_gpio *gpio_dev; 854 855 gpio_dev = devm_kzalloc(&pdev->dev, 856 sizeof(struct amd_gpio), GFP_KERNEL); 857 if (!gpio_dev) 858 return -ENOMEM; 859 860 raw_spin_lock_init(&gpio_dev->lock); 861 862 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 863 if (!res) { 864 dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); 865 return -EINVAL; 866 } 867 868 gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start, 869 resource_size(res)); 870 if (!gpio_dev->base) 871 return -ENOMEM; 872 873 irq_base = platform_get_irq(pdev, 0); 874 if (irq_base < 0) 875 return irq_base; 876 877 #ifdef CONFIG_PM_SLEEP 878 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins, 879 sizeof(*gpio_dev->saved_regs), 880 GFP_KERNEL); 881 if (!gpio_dev->saved_regs) 882 return -ENOMEM; 883 #endif 884 885 gpio_dev->pdev = pdev; 886 gpio_dev->gc.get_direction = amd_gpio_get_direction; 887 gpio_dev->gc.direction_input = amd_gpio_direction_input; 888 gpio_dev->gc.direction_output = amd_gpio_direction_output; 889 gpio_dev->gc.get = amd_gpio_get_value; 890 gpio_dev->gc.set = amd_gpio_set_value; 891 gpio_dev->gc.set_config = amd_gpio_set_config; 892 gpio_dev->gc.dbg_show = amd_gpio_dbg_show; 893 894 gpio_dev->gc.base = -1; 895 gpio_dev->gc.label = pdev->name; 896 gpio_dev->gc.owner = THIS_MODULE; 897 gpio_dev->gc.parent = &pdev->dev; 898 gpio_dev->gc.ngpio = resource_size(res) / 4; 899 #if defined(CONFIG_OF_GPIO) 900 gpio_dev->gc.of_node = pdev->dev.of_node; 901 #endif 902 903 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64; 904 gpio_dev->groups = kerncz_groups; 905 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); 906 907 amd_pinctrl_desc.name = dev_name(&pdev->dev); 908 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, 909 gpio_dev); 910 if (IS_ERR(gpio_dev->pctrl)) { 911 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 912 return PTR_ERR(gpio_dev->pctrl); 913 } 914 915 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); 916 if (ret) 917 return ret; 918 919 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), 920 0, 0, gpio_dev->gc.ngpio); 921 if (ret) { 922 dev_err(&pdev->dev, "Failed to add pin range\n"); 923 goto out2; 924 } 925 926 ret = gpiochip_irqchip_add(&gpio_dev->gc, 927 &amd_gpio_irqchip, 928 0, 929 handle_simple_irq, 930 IRQ_TYPE_NONE); 931 if (ret) { 932 dev_err(&pdev->dev, "could not add irqchip\n"); 933 ret = -ENODEV; 934 goto out2; 935 } 936 937 ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, 938 IRQF_SHARED, KBUILD_MODNAME, gpio_dev); 939 if (ret) 940 goto out2; 941 942 platform_set_drvdata(pdev, gpio_dev); 943 944 dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); 945 return ret; 946 947 out2: 948 gpiochip_remove(&gpio_dev->gc); 949 950 return ret; 951 } 952 953 static int amd_gpio_remove(struct platform_device *pdev) 954 { 955 struct amd_gpio *gpio_dev; 956 957 gpio_dev = platform_get_drvdata(pdev); 958 959 gpiochip_remove(&gpio_dev->gc); 960 961 return 0; 962 } 963 964 static const struct acpi_device_id amd_gpio_acpi_match[] = { 965 { "AMD0030", 0 }, 966 { "AMDI0030", 0}, 967 { }, 968 }; 969 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); 970 971 static struct platform_driver amd_gpio_driver = { 972 .driver = { 973 .name = "amd_gpio", 974 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), 975 #ifdef CONFIG_PM_SLEEP 976 .pm = &amd_gpio_pm_ops, 977 #endif 978 }, 979 .probe = amd_gpio_probe, 980 .remove = amd_gpio_remove, 981 }; 982 983 module_platform_driver(amd_gpio_driver); 984 985 MODULE_LICENSE("GPL v2"); 986 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); 987 MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); 988