1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPIO driver for AMD 4 * 5 * Copyright (c) 2014,2015 AMD Corporation. 6 * Authors: Ken Xue <Ken.Xue@amd.com> 7 * Wu, Jeff <Jeff.Wu@amd.com> 8 * 9 * Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com> 10 * Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 11 */ 12 13 #include <linux/err.h> 14 #include <linux/bug.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/spinlock.h> 18 #include <linux/compiler.h> 19 #include <linux/types.h> 20 #include <linux/errno.h> 21 #include <linux/log2.h> 22 #include <linux/io.h> 23 #include <linux/gpio/driver.h> 24 #include <linux/slab.h> 25 #include <linux/platform_device.h> 26 #include <linux/mutex.h> 27 #include <linux/acpi.h> 28 #include <linux/seq_file.h> 29 #include <linux/interrupt.h> 30 #include <linux/list.h> 31 #include <linux/bitops.h> 32 #include <linux/pinctrl/pinconf.h> 33 #include <linux/pinctrl/pinconf-generic.h> 34 35 #include "core.h" 36 #include "pinctrl-utils.h" 37 #include "pinctrl-amd.h" 38 39 static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset) 40 { 41 unsigned long flags; 42 u32 pin_reg; 43 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 44 45 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 46 pin_reg = readl(gpio_dev->base + offset * 4); 47 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 48 49 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) 50 return GPIO_LINE_DIRECTION_OUT; 51 52 return GPIO_LINE_DIRECTION_IN; 53 } 54 55 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 56 { 57 unsigned long flags; 58 u32 pin_reg; 59 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 60 61 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 62 pin_reg = readl(gpio_dev->base + offset * 4); 63 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); 64 writel(pin_reg, gpio_dev->base + offset * 4); 65 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 66 67 return 0; 68 } 69 70 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 71 int value) 72 { 73 u32 pin_reg; 74 unsigned long flags; 75 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 76 77 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 78 pin_reg = readl(gpio_dev->base + offset * 4); 79 pin_reg |= BIT(OUTPUT_ENABLE_OFF); 80 if (value) 81 pin_reg |= BIT(OUTPUT_VALUE_OFF); 82 else 83 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 84 writel(pin_reg, gpio_dev->base + offset * 4); 85 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 86 87 return 0; 88 } 89 90 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) 91 { 92 u32 pin_reg; 93 unsigned long flags; 94 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 95 96 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 97 pin_reg = readl(gpio_dev->base + offset * 4); 98 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 99 100 return !!(pin_reg & BIT(PIN_STS_OFF)); 101 } 102 103 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) 104 { 105 u32 pin_reg; 106 unsigned long flags; 107 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 108 109 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 110 pin_reg = readl(gpio_dev->base + offset * 4); 111 if (value) 112 pin_reg |= BIT(OUTPUT_VALUE_OFF); 113 else 114 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 115 writel(pin_reg, gpio_dev->base + offset * 4); 116 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 117 } 118 119 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, 120 unsigned debounce) 121 { 122 u32 time; 123 u32 pin_reg; 124 int ret = 0; 125 unsigned long flags; 126 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 127 128 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 129 pin_reg = readl(gpio_dev->base + offset * 4); 130 131 if (debounce) { 132 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 133 pin_reg &= ~DB_TMR_OUT_MASK; 134 /* 135 Debounce Debounce Timer Max 136 TmrLarge TmrOutUnit Unit Debounce 137 Time 138 0 0 61 usec (2 RtcClk) 976 usec 139 0 1 244 usec (8 RtcClk) 3.9 msec 140 1 0 15.6 msec (512 RtcClk) 250 msec 141 1 1 62.5 msec (2048 RtcClk) 1 sec 142 */ 143 144 if (debounce < 61) { 145 pin_reg |= 1; 146 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 147 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 148 } else if (debounce < 976) { 149 time = debounce / 61; 150 pin_reg |= time & DB_TMR_OUT_MASK; 151 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 152 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 153 } else if (debounce < 3900) { 154 time = debounce / 244; 155 pin_reg |= time & DB_TMR_OUT_MASK; 156 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 157 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 158 } else if (debounce < 250000) { 159 time = debounce / 15625; 160 pin_reg |= time & DB_TMR_OUT_MASK; 161 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 162 pin_reg |= BIT(DB_TMR_LARGE_OFF); 163 } else if (debounce < 1000000) { 164 time = debounce / 62500; 165 pin_reg |= time & DB_TMR_OUT_MASK; 166 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 167 pin_reg |= BIT(DB_TMR_LARGE_OFF); 168 } else { 169 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 170 ret = -EINVAL; 171 } 172 } else { 173 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 174 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 175 pin_reg &= ~DB_TMR_OUT_MASK; 176 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 177 } 178 writel(pin_reg, gpio_dev->base + offset * 4); 179 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 180 181 return ret; 182 } 183 184 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset, 185 unsigned long config) 186 { 187 u32 debounce; 188 189 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 190 return -ENOTSUPP; 191 192 debounce = pinconf_to_config_argument(config); 193 return amd_gpio_set_debounce(gc, offset, debounce); 194 } 195 196 #ifdef CONFIG_DEBUG_FS 197 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) 198 { 199 u32 pin_reg; 200 u32 db_cntrl; 201 unsigned long flags; 202 unsigned int bank, i, pin_num; 203 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 204 205 bool tmr_out_unit; 206 unsigned int time; 207 unsigned int unit; 208 bool tmr_large; 209 210 char *level_trig; 211 char *active_level; 212 char *interrupt_enable; 213 char *interrupt_mask; 214 char *wake_cntrl0; 215 char *wake_cntrl1; 216 char *wake_cntrl2; 217 char *pin_sts; 218 char *pull_up_sel; 219 char *pull_up_enable; 220 char *pull_down_enable; 221 char *output_value; 222 char *output_enable; 223 char debounce_value[40]; 224 char *debounce_enable; 225 226 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { 227 seq_printf(s, "GPIO bank%d\t", bank); 228 229 switch (bank) { 230 case 0: 231 i = 0; 232 pin_num = AMD_GPIO_PINS_BANK0; 233 break; 234 case 1: 235 i = 64; 236 pin_num = AMD_GPIO_PINS_BANK1 + i; 237 break; 238 case 2: 239 i = 128; 240 pin_num = AMD_GPIO_PINS_BANK2 + i; 241 break; 242 case 3: 243 i = 192; 244 pin_num = AMD_GPIO_PINS_BANK3 + i; 245 break; 246 default: 247 /* Illegal bank number, ignore */ 248 continue; 249 } 250 for (; i < pin_num; i++) { 251 seq_printf(s, "pin%d\t", i); 252 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 253 pin_reg = readl(gpio_dev->base + i * 4); 254 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 255 256 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { 257 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) & 258 ACTIVE_LEVEL_MASK; 259 interrupt_enable = "interrupt is enabled|"; 260 261 if (level == ACTIVE_LEVEL_HIGH) 262 active_level = "Active high|"; 263 else if (level == ACTIVE_LEVEL_LOW) 264 active_level = "Active low|"; 265 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) && 266 level == ACTIVE_LEVEL_BOTH) 267 active_level = "Active on both|"; 268 else 269 active_level = "Unknown Active level|"; 270 271 if (pin_reg & BIT(LEVEL_TRIG_OFF)) 272 level_trig = "Level trigger|"; 273 else 274 level_trig = "Edge trigger|"; 275 276 } else { 277 interrupt_enable = 278 "interrupt is disabled|"; 279 active_level = " "; 280 level_trig = " "; 281 } 282 283 if (pin_reg & BIT(INTERRUPT_MASK_OFF)) 284 interrupt_mask = 285 "interrupt is unmasked|"; 286 else 287 interrupt_mask = 288 "interrupt is masked|"; 289 290 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) 291 wake_cntrl0 = "enable wakeup in S0i3 state|"; 292 else 293 wake_cntrl0 = "disable wakeup in S0i3 state|"; 294 295 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) 296 wake_cntrl1 = "enable wakeup in S3 state|"; 297 else 298 wake_cntrl1 = "disable wakeup in S3 state|"; 299 300 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) 301 wake_cntrl2 = "enable wakeup in S4/S5 state|"; 302 else 303 wake_cntrl2 = "disable wakeup in S4/S5 state|"; 304 305 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { 306 pull_up_enable = "pull-up is enabled|"; 307 if (pin_reg & BIT(PULL_UP_SEL_OFF)) 308 pull_up_sel = "8k pull-up|"; 309 else 310 pull_up_sel = "4k pull-up|"; 311 } else { 312 pull_up_enable = "pull-up is disabled|"; 313 pull_up_sel = " "; 314 } 315 316 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) 317 pull_down_enable = "pull-down is enabled|"; 318 else 319 pull_down_enable = "Pull-down is disabled|"; 320 321 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { 322 pin_sts = " "; 323 output_enable = "output is enabled|"; 324 if (pin_reg & BIT(OUTPUT_VALUE_OFF)) 325 output_value = "output is high|"; 326 else 327 output_value = "output is low|"; 328 } else { 329 output_enable = "output is disabled|"; 330 output_value = " "; 331 332 if (pin_reg & BIT(PIN_STS_OFF)) 333 pin_sts = "input is high|"; 334 else 335 pin_sts = "input is low|"; 336 } 337 338 db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg; 339 if (db_cntrl) { 340 tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF); 341 tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF); 342 time = pin_reg & DB_TMR_OUT_MASK; 343 if (tmr_large) { 344 if (tmr_out_unit) 345 unit = 62500; 346 else 347 unit = 15625; 348 } else { 349 if (tmr_out_unit) 350 unit = 244; 351 else 352 unit = 61; 353 } 354 if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl) 355 debounce_enable = "debouncing filter (high and low) enabled|"; 356 else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl) 357 debounce_enable = "debouncing filter (low) enabled|"; 358 else 359 debounce_enable = "debouncing filter (high) enabled|"; 360 361 snprintf(debounce_value, sizeof(debounce_value), 362 "debouncing timeout is %u (us)|", time * unit); 363 } else { 364 debounce_enable = "debouncing filter disabled|"; 365 snprintf(debounce_value, sizeof(debounce_value), " "); 366 } 367 368 seq_printf(s, "%s %s %s %s %s %s\n" 369 " %s %s %s %s %s %s %s %s %s 0x%x\n", 370 level_trig, active_level, interrupt_enable, 371 interrupt_mask, wake_cntrl0, wake_cntrl1, 372 wake_cntrl2, pin_sts, pull_up_sel, 373 pull_up_enable, pull_down_enable, 374 output_value, output_enable, 375 debounce_enable, debounce_value, pin_reg); 376 } 377 } 378 } 379 #else 380 #define amd_gpio_dbg_show NULL 381 #endif 382 383 static void amd_gpio_irq_enable(struct irq_data *d) 384 { 385 u32 pin_reg; 386 unsigned long flags; 387 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 388 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 389 390 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 391 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 392 pin_reg |= BIT(INTERRUPT_ENABLE_OFF); 393 pin_reg |= BIT(INTERRUPT_MASK_OFF); 394 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 395 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 396 } 397 398 static void amd_gpio_irq_disable(struct irq_data *d) 399 { 400 u32 pin_reg; 401 unsigned long flags; 402 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 403 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 404 405 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 406 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 407 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); 408 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 409 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 410 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 411 } 412 413 static void amd_gpio_irq_mask(struct irq_data *d) 414 { 415 u32 pin_reg; 416 unsigned long flags; 417 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 418 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 419 420 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 421 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 422 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 423 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 424 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 425 } 426 427 static void amd_gpio_irq_unmask(struct irq_data *d) 428 { 429 u32 pin_reg; 430 unsigned long flags; 431 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 432 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 433 434 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 435 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 436 pin_reg |= BIT(INTERRUPT_MASK_OFF); 437 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 438 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 439 } 440 441 static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 442 { 443 u32 pin_reg; 444 unsigned long flags; 445 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 446 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 447 u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3); 448 449 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 450 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 451 452 if (on) 453 pin_reg |= wake_mask; 454 else 455 pin_reg &= ~wake_mask; 456 457 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 458 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 459 460 return 0; 461 } 462 463 static void amd_gpio_irq_eoi(struct irq_data *d) 464 { 465 u32 reg; 466 unsigned long flags; 467 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 468 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 469 470 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 471 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 472 reg |= EOI_MASK; 473 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 474 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 475 } 476 477 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) 478 { 479 int ret = 0; 480 u32 pin_reg, pin_reg_irq_en, mask; 481 unsigned long flags; 482 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 483 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 484 485 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 486 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 487 488 switch (type & IRQ_TYPE_SENSE_MASK) { 489 case IRQ_TYPE_EDGE_RISING: 490 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 491 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 492 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 493 irq_set_handler_locked(d, handle_edge_irq); 494 break; 495 496 case IRQ_TYPE_EDGE_FALLING: 497 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 498 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 499 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 500 irq_set_handler_locked(d, handle_edge_irq); 501 break; 502 503 case IRQ_TYPE_EDGE_BOTH: 504 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 505 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 506 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; 507 irq_set_handler_locked(d, handle_edge_irq); 508 break; 509 510 case IRQ_TYPE_LEVEL_HIGH: 511 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 512 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 513 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 514 irq_set_handler_locked(d, handle_level_irq); 515 break; 516 517 case IRQ_TYPE_LEVEL_LOW: 518 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 519 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 520 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 521 irq_set_handler_locked(d, handle_level_irq); 522 break; 523 524 case IRQ_TYPE_NONE: 525 break; 526 527 default: 528 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); 529 ret = -EINVAL; 530 } 531 532 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; 533 /* 534 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the 535 * debounce registers of any GPIO will block wake/interrupt status 536 * generation for *all* GPIOs for a length of time that depends on 537 * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the 538 * INTERRUPT_ENABLE bit will read as 0. 539 * 540 * We temporarily enable irq for the GPIO whose configuration is 541 * changing, and then wait for it to read back as 1 to know when 542 * debounce has settled and then disable the irq again. 543 * We do this polling with the spinlock held to ensure other GPIO 544 * access routines do not read an incorrect value for the irq enable 545 * bit of other GPIOs. We keep the GPIO masked while polling to avoid 546 * spurious irqs, and disable the irq again after polling. 547 */ 548 mask = BIT(INTERRUPT_ENABLE_OFF); 549 pin_reg_irq_en = pin_reg; 550 pin_reg_irq_en |= mask; 551 pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF); 552 writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4); 553 while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask) 554 continue; 555 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 556 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 557 558 return ret; 559 } 560 561 static void amd_irq_ack(struct irq_data *d) 562 { 563 /* 564 * based on HW design,there is no need to ack HW 565 * before handle current irq. But this routine is 566 * necessary for handle_edge_irq 567 */ 568 } 569 570 static struct irq_chip amd_gpio_irqchip = { 571 .name = "amd_gpio", 572 .irq_ack = amd_irq_ack, 573 .irq_enable = amd_gpio_irq_enable, 574 .irq_disable = amd_gpio_irq_disable, 575 .irq_mask = amd_gpio_irq_mask, 576 .irq_unmask = amd_gpio_irq_unmask, 577 .irq_set_wake = amd_gpio_irq_set_wake, 578 .irq_eoi = amd_gpio_irq_eoi, 579 .irq_set_type = amd_gpio_irq_set_type, 580 /* 581 * We need to set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND so that a wake event 582 * also generates an IRQ. We need the IRQ so the irq_handler can clear 583 * the wake event. Otherwise the wake event will never clear and 584 * prevent the system from suspending. 585 */ 586 .flags = IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND, 587 }; 588 589 #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF)) 590 591 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id) 592 { 593 struct amd_gpio *gpio_dev = dev_id; 594 struct gpio_chip *gc = &gpio_dev->gc; 595 irqreturn_t ret = IRQ_NONE; 596 unsigned int i, irqnr; 597 unsigned long flags; 598 u32 __iomem *regs; 599 u32 regval; 600 u64 status, mask; 601 602 /* Read the wake status */ 603 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 604 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); 605 status <<= 32; 606 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0); 607 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 608 609 /* Bit 0-45 contain the relevant status bits */ 610 status &= (1ULL << 46) - 1; 611 regs = gpio_dev->base; 612 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) { 613 if (!(status & mask)) 614 continue; 615 status &= ~mask; 616 617 /* Each status bit covers four pins */ 618 for (i = 0; i < 4; i++) { 619 regval = readl(regs + i); 620 if (!(regval & PIN_IRQ_PENDING) || 621 !(regval & BIT(INTERRUPT_MASK_OFF))) 622 continue; 623 irq = irq_find_mapping(gc->irq.domain, irqnr + i); 624 if (irq != 0) 625 generic_handle_irq(irq); 626 627 /* Clear interrupt. 628 * We must read the pin register again, in case the 629 * value was changed while executing 630 * generic_handle_irq() above. 631 * If we didn't find a mapping for the interrupt, 632 * disable it in order to avoid a system hang caused 633 * by an interrupt storm. 634 */ 635 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 636 regval = readl(regs + i); 637 if (irq == 0) { 638 regval &= ~BIT(INTERRUPT_ENABLE_OFF); 639 dev_dbg(&gpio_dev->pdev->dev, 640 "Disabling spurious GPIO IRQ %d\n", 641 irqnr + i); 642 } 643 writel(regval, regs + i); 644 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 645 ret = IRQ_HANDLED; 646 } 647 } 648 649 /* Signal EOI to the GPIO unit */ 650 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 651 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 652 regval |= EOI_MASK; 653 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG); 654 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 655 656 return ret; 657 } 658 659 static int amd_get_groups_count(struct pinctrl_dev *pctldev) 660 { 661 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 662 663 return gpio_dev->ngroups; 664 } 665 666 static const char *amd_get_group_name(struct pinctrl_dev *pctldev, 667 unsigned group) 668 { 669 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 670 671 return gpio_dev->groups[group].name; 672 } 673 674 static int amd_get_group_pins(struct pinctrl_dev *pctldev, 675 unsigned group, 676 const unsigned **pins, 677 unsigned *num_pins) 678 { 679 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 680 681 *pins = gpio_dev->groups[group].pins; 682 *num_pins = gpio_dev->groups[group].npins; 683 return 0; 684 } 685 686 static const struct pinctrl_ops amd_pinctrl_ops = { 687 .get_groups_count = amd_get_groups_count, 688 .get_group_name = amd_get_group_name, 689 .get_group_pins = amd_get_group_pins, 690 #ifdef CONFIG_OF 691 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 692 .dt_free_map = pinctrl_utils_free_map, 693 #endif 694 }; 695 696 static int amd_pinconf_get(struct pinctrl_dev *pctldev, 697 unsigned int pin, 698 unsigned long *config) 699 { 700 u32 pin_reg; 701 unsigned arg; 702 unsigned long flags; 703 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 704 enum pin_config_param param = pinconf_to_config_param(*config); 705 706 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 707 pin_reg = readl(gpio_dev->base + pin*4); 708 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 709 switch (param) { 710 case PIN_CONFIG_INPUT_DEBOUNCE: 711 arg = pin_reg & DB_TMR_OUT_MASK; 712 break; 713 714 case PIN_CONFIG_BIAS_PULL_DOWN: 715 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); 716 break; 717 718 case PIN_CONFIG_BIAS_PULL_UP: 719 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); 720 break; 721 722 case PIN_CONFIG_DRIVE_STRENGTH: 723 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; 724 break; 725 726 default: 727 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n", 728 param); 729 return -ENOTSUPP; 730 } 731 732 *config = pinconf_to_config_packed(param, arg); 733 734 return 0; 735 } 736 737 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 738 unsigned long *configs, unsigned num_configs) 739 { 740 int i; 741 u32 arg; 742 int ret = 0; 743 u32 pin_reg; 744 unsigned long flags; 745 enum pin_config_param param; 746 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 747 748 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 749 for (i = 0; i < num_configs; i++) { 750 param = pinconf_to_config_param(configs[i]); 751 arg = pinconf_to_config_argument(configs[i]); 752 pin_reg = readl(gpio_dev->base + pin*4); 753 754 switch (param) { 755 case PIN_CONFIG_INPUT_DEBOUNCE: 756 pin_reg &= ~DB_TMR_OUT_MASK; 757 pin_reg |= arg & DB_TMR_OUT_MASK; 758 break; 759 760 case PIN_CONFIG_BIAS_PULL_DOWN: 761 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); 762 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; 763 break; 764 765 case PIN_CONFIG_BIAS_PULL_UP: 766 pin_reg &= ~BIT(PULL_UP_SEL_OFF); 767 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; 768 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); 769 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; 770 break; 771 772 case PIN_CONFIG_DRIVE_STRENGTH: 773 pin_reg &= ~(DRV_STRENGTH_SEL_MASK 774 << DRV_STRENGTH_SEL_OFF); 775 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) 776 << DRV_STRENGTH_SEL_OFF; 777 break; 778 779 default: 780 dev_err(&gpio_dev->pdev->dev, 781 "Invalid config param %04x\n", param); 782 ret = -ENOTSUPP; 783 } 784 785 writel(pin_reg, gpio_dev->base + pin*4); 786 } 787 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 788 789 return ret; 790 } 791 792 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, 793 unsigned int group, 794 unsigned long *config) 795 { 796 const unsigned *pins; 797 unsigned npins; 798 int ret; 799 800 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 801 if (ret) 802 return ret; 803 804 if (amd_pinconf_get(pctldev, pins[0], config)) 805 return -ENOTSUPP; 806 807 return 0; 808 } 809 810 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, 811 unsigned group, unsigned long *configs, 812 unsigned num_configs) 813 { 814 const unsigned *pins; 815 unsigned npins; 816 int i, ret; 817 818 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 819 if (ret) 820 return ret; 821 for (i = 0; i < npins; i++) { 822 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) 823 return -ENOTSUPP; 824 } 825 return 0; 826 } 827 828 static const struct pinconf_ops amd_pinconf_ops = { 829 .pin_config_get = amd_pinconf_get, 830 .pin_config_set = amd_pinconf_set, 831 .pin_config_group_get = amd_pinconf_group_get, 832 .pin_config_group_set = amd_pinconf_group_set, 833 }; 834 835 #ifdef CONFIG_PM_SLEEP 836 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) 837 { 838 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 839 840 if (!pd) 841 return false; 842 843 /* 844 * Only restore the pin if it is actually in use by the kernel (or 845 * by userspace). 846 */ 847 if (pd->mux_owner || pd->gpio_owner || 848 gpiochip_line_is_irq(&gpio_dev->gc, pin)) 849 return true; 850 851 return false; 852 } 853 854 static int amd_gpio_suspend(struct device *dev) 855 { 856 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 857 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 858 int i; 859 860 for (i = 0; i < desc->npins; i++) { 861 int pin = desc->pins[i].number; 862 863 if (!amd_gpio_should_save(gpio_dev, pin)) 864 continue; 865 866 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin*4); 867 } 868 869 return 0; 870 } 871 872 static int amd_gpio_resume(struct device *dev) 873 { 874 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 875 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 876 int i; 877 878 for (i = 0; i < desc->npins; i++) { 879 int pin = desc->pins[i].number; 880 881 if (!amd_gpio_should_save(gpio_dev, pin)) 882 continue; 883 884 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin*4); 885 } 886 887 return 0; 888 } 889 890 static const struct dev_pm_ops amd_gpio_pm_ops = { 891 SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend, 892 amd_gpio_resume) 893 }; 894 #endif 895 896 static struct pinctrl_desc amd_pinctrl_desc = { 897 .pins = kerncz_pins, 898 .npins = ARRAY_SIZE(kerncz_pins), 899 .pctlops = &amd_pinctrl_ops, 900 .confops = &amd_pinconf_ops, 901 .owner = THIS_MODULE, 902 }; 903 904 static int amd_gpio_probe(struct platform_device *pdev) 905 { 906 int ret = 0; 907 int irq_base; 908 struct resource *res; 909 struct amd_gpio *gpio_dev; 910 struct gpio_irq_chip *girq; 911 912 gpio_dev = devm_kzalloc(&pdev->dev, 913 sizeof(struct amd_gpio), GFP_KERNEL); 914 if (!gpio_dev) 915 return -ENOMEM; 916 917 raw_spin_lock_init(&gpio_dev->lock); 918 919 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 920 if (!res) { 921 dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); 922 return -EINVAL; 923 } 924 925 gpio_dev->base = devm_ioremap(&pdev->dev, res->start, 926 resource_size(res)); 927 if (!gpio_dev->base) 928 return -ENOMEM; 929 930 irq_base = platform_get_irq(pdev, 0); 931 if (irq_base < 0) 932 return irq_base; 933 934 #ifdef CONFIG_PM_SLEEP 935 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins, 936 sizeof(*gpio_dev->saved_regs), 937 GFP_KERNEL); 938 if (!gpio_dev->saved_regs) 939 return -ENOMEM; 940 #endif 941 942 gpio_dev->pdev = pdev; 943 gpio_dev->gc.get_direction = amd_gpio_get_direction; 944 gpio_dev->gc.direction_input = amd_gpio_direction_input; 945 gpio_dev->gc.direction_output = amd_gpio_direction_output; 946 gpio_dev->gc.get = amd_gpio_get_value; 947 gpio_dev->gc.set = amd_gpio_set_value; 948 gpio_dev->gc.set_config = amd_gpio_set_config; 949 gpio_dev->gc.dbg_show = amd_gpio_dbg_show; 950 951 gpio_dev->gc.base = -1; 952 gpio_dev->gc.label = pdev->name; 953 gpio_dev->gc.owner = THIS_MODULE; 954 gpio_dev->gc.parent = &pdev->dev; 955 gpio_dev->gc.ngpio = resource_size(res) / 4; 956 #if defined(CONFIG_OF_GPIO) 957 gpio_dev->gc.of_node = pdev->dev.of_node; 958 #endif 959 960 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64; 961 gpio_dev->groups = kerncz_groups; 962 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); 963 964 amd_pinctrl_desc.name = dev_name(&pdev->dev); 965 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, 966 gpio_dev); 967 if (IS_ERR(gpio_dev->pctrl)) { 968 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 969 return PTR_ERR(gpio_dev->pctrl); 970 } 971 972 girq = &gpio_dev->gc.irq; 973 girq->chip = &amd_gpio_irqchip; 974 /* This will let us handle the parent IRQ in the driver */ 975 girq->parent_handler = NULL; 976 girq->num_parents = 0; 977 girq->parents = NULL; 978 girq->default_type = IRQ_TYPE_NONE; 979 girq->handler = handle_simple_irq; 980 981 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); 982 if (ret) 983 return ret; 984 985 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), 986 0, 0, gpio_dev->gc.ngpio); 987 if (ret) { 988 dev_err(&pdev->dev, "Failed to add pin range\n"); 989 goto out2; 990 } 991 992 ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, 993 IRQF_SHARED, KBUILD_MODNAME, gpio_dev); 994 if (ret) 995 goto out2; 996 997 platform_set_drvdata(pdev, gpio_dev); 998 999 dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); 1000 return ret; 1001 1002 out2: 1003 gpiochip_remove(&gpio_dev->gc); 1004 1005 return ret; 1006 } 1007 1008 static int amd_gpio_remove(struct platform_device *pdev) 1009 { 1010 struct amd_gpio *gpio_dev; 1011 1012 gpio_dev = platform_get_drvdata(pdev); 1013 1014 gpiochip_remove(&gpio_dev->gc); 1015 1016 return 0; 1017 } 1018 1019 #ifdef CONFIG_ACPI 1020 static const struct acpi_device_id amd_gpio_acpi_match[] = { 1021 { "AMD0030", 0 }, 1022 { "AMDI0030", 0}, 1023 { "AMDI0031", 0}, 1024 { }, 1025 }; 1026 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); 1027 #endif 1028 1029 static struct platform_driver amd_gpio_driver = { 1030 .driver = { 1031 .name = "amd_gpio", 1032 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), 1033 #ifdef CONFIG_PM_SLEEP 1034 .pm = &amd_gpio_pm_ops, 1035 #endif 1036 }, 1037 .probe = amd_gpio_probe, 1038 .remove = amd_gpio_remove, 1039 }; 1040 1041 module_platform_driver(amd_gpio_driver); 1042 1043 MODULE_LICENSE("GPL v2"); 1044 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); 1045 MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); 1046