1 /* 2 * GPIO driver for AMD 3 * 4 * Copyright (c) 2014,2015 AMD Corporation. 5 * Authors: Ken Xue <Ken.Xue@amd.com> 6 * Wu, Jeff <Jeff.Wu@amd.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2, as published by the Free Software Foundation. 11 * 12 * Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com> 13 * Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 14 * 15 */ 16 17 #include <linux/err.h> 18 #include <linux/bug.h> 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/spinlock.h> 22 #include <linux/compiler.h> 23 #include <linux/types.h> 24 #include <linux/errno.h> 25 #include <linux/log2.h> 26 #include <linux/io.h> 27 #include <linux/gpio.h> 28 #include <linux/slab.h> 29 #include <linux/platform_device.h> 30 #include <linux/mutex.h> 31 #include <linux/acpi.h> 32 #include <linux/seq_file.h> 33 #include <linux/interrupt.h> 34 #include <linux/list.h> 35 #include <linux/bitops.h> 36 #include <linux/pinctrl/pinconf.h> 37 #include <linux/pinctrl/pinconf-generic.h> 38 39 #include "core.h" 40 #include "pinctrl-utils.h" 41 #include "pinctrl-amd.h" 42 43 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 44 { 45 unsigned long flags; 46 u32 pin_reg; 47 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 48 49 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 50 pin_reg = readl(gpio_dev->base + offset * 4); 51 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); 52 writel(pin_reg, gpio_dev->base + offset * 4); 53 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 54 55 return 0; 56 } 57 58 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 59 int value) 60 { 61 u32 pin_reg; 62 unsigned long flags; 63 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 64 65 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 66 pin_reg = readl(gpio_dev->base + offset * 4); 67 pin_reg |= BIT(OUTPUT_ENABLE_OFF); 68 if (value) 69 pin_reg |= BIT(OUTPUT_VALUE_OFF); 70 else 71 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 72 writel(pin_reg, gpio_dev->base + offset * 4); 73 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 74 75 return 0; 76 } 77 78 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) 79 { 80 u32 pin_reg; 81 unsigned long flags; 82 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 83 84 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 85 pin_reg = readl(gpio_dev->base + offset * 4); 86 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 87 88 return !!(pin_reg & BIT(PIN_STS_OFF)); 89 } 90 91 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) 92 { 93 u32 pin_reg; 94 unsigned long flags; 95 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 96 97 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 98 pin_reg = readl(gpio_dev->base + offset * 4); 99 if (value) 100 pin_reg |= BIT(OUTPUT_VALUE_OFF); 101 else 102 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 103 writel(pin_reg, gpio_dev->base + offset * 4); 104 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 105 } 106 107 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, 108 unsigned debounce) 109 { 110 u32 time; 111 u32 pin_reg; 112 int ret = 0; 113 unsigned long flags; 114 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 115 116 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 117 pin_reg = readl(gpio_dev->base + offset * 4); 118 119 if (debounce) { 120 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 121 pin_reg &= ~DB_TMR_OUT_MASK; 122 /* 123 Debounce Debounce Timer Max 124 TmrLarge TmrOutUnit Unit Debounce 125 Time 126 0 0 61 usec (2 RtcClk) 976 usec 127 0 1 244 usec (8 RtcClk) 3.9 msec 128 1 0 15.6 msec (512 RtcClk) 250 msec 129 1 1 62.5 msec (2048 RtcClk) 1 sec 130 */ 131 132 if (debounce < 61) { 133 pin_reg |= 1; 134 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 135 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 136 } else if (debounce < 976) { 137 time = debounce / 61; 138 pin_reg |= time & DB_TMR_OUT_MASK; 139 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 140 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 141 } else if (debounce < 3900) { 142 time = debounce / 244; 143 pin_reg |= time & DB_TMR_OUT_MASK; 144 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 145 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 146 } else if (debounce < 250000) { 147 time = debounce / 15600; 148 pin_reg |= time & DB_TMR_OUT_MASK; 149 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 150 pin_reg |= BIT(DB_TMR_LARGE_OFF); 151 } else if (debounce < 1000000) { 152 time = debounce / 62500; 153 pin_reg |= time & DB_TMR_OUT_MASK; 154 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 155 pin_reg |= BIT(DB_TMR_LARGE_OFF); 156 } else { 157 pin_reg &= ~DB_CNTRl_MASK; 158 ret = -EINVAL; 159 } 160 } else { 161 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 162 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 163 pin_reg &= ~DB_TMR_OUT_MASK; 164 pin_reg &= ~DB_CNTRl_MASK; 165 } 166 writel(pin_reg, gpio_dev->base + offset * 4); 167 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 168 169 return ret; 170 } 171 172 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset, 173 unsigned long config) 174 { 175 u32 debounce; 176 177 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 178 return -ENOTSUPP; 179 180 debounce = pinconf_to_config_argument(config); 181 return amd_gpio_set_debounce(gc, offset, debounce); 182 } 183 184 #ifdef CONFIG_DEBUG_FS 185 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) 186 { 187 u32 pin_reg; 188 unsigned long flags; 189 unsigned int bank, i, pin_num; 190 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 191 192 char *level_trig; 193 char *active_level; 194 char *interrupt_enable; 195 char *interrupt_mask; 196 char *wake_cntrl0; 197 char *wake_cntrl1; 198 char *wake_cntrl2; 199 char *pin_sts; 200 char *pull_up_sel; 201 char *pull_up_enable; 202 char *pull_down_enable; 203 char *output_value; 204 char *output_enable; 205 206 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { 207 seq_printf(s, "GPIO bank%d\t", bank); 208 209 switch (bank) { 210 case 0: 211 i = 0; 212 pin_num = AMD_GPIO_PINS_BANK0; 213 break; 214 case 1: 215 i = 64; 216 pin_num = AMD_GPIO_PINS_BANK1 + i; 217 break; 218 case 2: 219 i = 128; 220 pin_num = AMD_GPIO_PINS_BANK2 + i; 221 break; 222 case 3: 223 i = 192; 224 pin_num = AMD_GPIO_PINS_BANK3 + i; 225 break; 226 default: 227 /* Illegal bank number, ignore */ 228 continue; 229 } 230 for (; i < pin_num; i++) { 231 seq_printf(s, "pin%d\t", i); 232 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 233 pin_reg = readl(gpio_dev->base + i * 4); 234 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 235 236 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { 237 interrupt_enable = "interrupt is enabled|"; 238 239 if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) && 240 !(pin_reg & BIT(ACTIVE_LEVEL_OFF + 1))) 241 active_level = "Active low|"; 242 else if (pin_reg & BIT(ACTIVE_LEVEL_OFF) && 243 !(pin_reg & BIT(ACTIVE_LEVEL_OFF + 1))) 244 active_level = "Active high|"; 245 else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) && 246 pin_reg & BIT(ACTIVE_LEVEL_OFF + 1)) 247 active_level = "Active on both|"; 248 else 249 active_level = "Unknown Active level|"; 250 251 if (pin_reg & BIT(LEVEL_TRIG_OFF)) 252 level_trig = "Level trigger|"; 253 else 254 level_trig = "Edge trigger|"; 255 256 } else { 257 interrupt_enable = 258 "interrupt is disabled|"; 259 active_level = " "; 260 level_trig = " "; 261 } 262 263 if (pin_reg & BIT(INTERRUPT_MASK_OFF)) 264 interrupt_mask = 265 "interrupt is unmasked|"; 266 else 267 interrupt_mask = 268 "interrupt is masked|"; 269 270 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) 271 wake_cntrl0 = "enable wakeup in S0i3 state|"; 272 else 273 wake_cntrl0 = "disable wakeup in S0i3 state|"; 274 275 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) 276 wake_cntrl1 = "enable wakeup in S3 state|"; 277 else 278 wake_cntrl1 = "disable wakeup in S3 state|"; 279 280 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) 281 wake_cntrl2 = "enable wakeup in S4/S5 state|"; 282 else 283 wake_cntrl2 = "disable wakeup in S4/S5 state|"; 284 285 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { 286 pull_up_enable = "pull-up is enabled|"; 287 if (pin_reg & BIT(PULL_UP_SEL_OFF)) 288 pull_up_sel = "8k pull-up|"; 289 else 290 pull_up_sel = "4k pull-up|"; 291 } else { 292 pull_up_enable = "pull-up is disabled|"; 293 pull_up_sel = " "; 294 } 295 296 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) 297 pull_down_enable = "pull-down is enabled|"; 298 else 299 pull_down_enable = "Pull-down is disabled|"; 300 301 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { 302 pin_sts = " "; 303 output_enable = "output is enabled|"; 304 if (pin_reg & BIT(OUTPUT_VALUE_OFF)) 305 output_value = "output is high|"; 306 else 307 output_value = "output is low|"; 308 } else { 309 output_enable = "output is disabled|"; 310 output_value = " "; 311 312 if (pin_reg & BIT(PIN_STS_OFF)) 313 pin_sts = "input is high|"; 314 else 315 pin_sts = "input is low|"; 316 } 317 318 seq_printf(s, "%s %s %s %s %s %s\n" 319 " %s %s %s %s %s %s %s 0x%x\n", 320 level_trig, active_level, interrupt_enable, 321 interrupt_mask, wake_cntrl0, wake_cntrl1, 322 wake_cntrl2, pin_sts, pull_up_sel, 323 pull_up_enable, pull_down_enable, 324 output_value, output_enable, pin_reg); 325 } 326 } 327 } 328 #else 329 #define amd_gpio_dbg_show NULL 330 #endif 331 332 static void amd_gpio_irq_enable(struct irq_data *d) 333 { 334 u32 pin_reg; 335 unsigned long flags; 336 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 337 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 338 339 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 340 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 341 pin_reg |= BIT(INTERRUPT_ENABLE_OFF); 342 pin_reg |= BIT(INTERRUPT_MASK_OFF); 343 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 344 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 345 } 346 347 static void amd_gpio_irq_disable(struct irq_data *d) 348 { 349 u32 pin_reg; 350 unsigned long flags; 351 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 352 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 353 354 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 355 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 356 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); 357 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 358 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 359 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 360 } 361 362 static void amd_gpio_irq_mask(struct irq_data *d) 363 { 364 u32 pin_reg; 365 unsigned long flags; 366 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 367 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 368 369 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 370 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 371 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 372 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 373 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 374 } 375 376 static void amd_gpio_irq_unmask(struct irq_data *d) 377 { 378 u32 pin_reg; 379 unsigned long flags; 380 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 381 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 382 383 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 384 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 385 pin_reg |= BIT(INTERRUPT_MASK_OFF); 386 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 387 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 388 } 389 390 static void amd_gpio_irq_eoi(struct irq_data *d) 391 { 392 u32 reg; 393 unsigned long flags; 394 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 395 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 396 397 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 398 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 399 reg |= EOI_MASK; 400 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 401 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 402 } 403 404 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) 405 { 406 int ret = 0; 407 u32 pin_reg; 408 unsigned long flags, irq_flags; 409 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 410 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 411 412 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 413 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 414 415 /* Ignore the settings coming from the client and 416 * read the values from the ACPI tables 417 * while setting the trigger type 418 */ 419 420 irq_flags = irq_get_trigger_type(d->irq); 421 if (irq_flags != IRQ_TYPE_NONE) 422 type = irq_flags; 423 424 switch (type & IRQ_TYPE_SENSE_MASK) { 425 case IRQ_TYPE_EDGE_RISING: 426 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 427 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 428 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 429 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 430 irq_set_handler_locked(d, handle_edge_irq); 431 break; 432 433 case IRQ_TYPE_EDGE_FALLING: 434 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 435 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 436 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 437 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 438 irq_set_handler_locked(d, handle_edge_irq); 439 break; 440 441 case IRQ_TYPE_EDGE_BOTH: 442 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 443 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 444 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; 445 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 446 irq_set_handler_locked(d, handle_edge_irq); 447 break; 448 449 case IRQ_TYPE_LEVEL_HIGH: 450 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 451 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 452 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 453 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 454 pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF; 455 irq_set_handler_locked(d, handle_level_irq); 456 break; 457 458 case IRQ_TYPE_LEVEL_LOW: 459 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 460 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 461 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 462 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 463 pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF; 464 irq_set_handler_locked(d, handle_level_irq); 465 break; 466 467 case IRQ_TYPE_NONE: 468 break; 469 470 default: 471 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); 472 ret = -EINVAL; 473 } 474 475 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; 476 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 477 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 478 479 return ret; 480 } 481 482 static void amd_irq_ack(struct irq_data *d) 483 { 484 /* 485 * based on HW design,there is no need to ack HW 486 * before handle current irq. But this routine is 487 * necessary for handle_edge_irq 488 */ 489 } 490 491 static struct irq_chip amd_gpio_irqchip = { 492 .name = "amd_gpio", 493 .irq_ack = amd_irq_ack, 494 .irq_enable = amd_gpio_irq_enable, 495 .irq_disable = amd_gpio_irq_disable, 496 .irq_mask = amd_gpio_irq_mask, 497 .irq_unmask = amd_gpio_irq_unmask, 498 .irq_eoi = amd_gpio_irq_eoi, 499 .irq_set_type = amd_gpio_irq_set_type, 500 .flags = IRQCHIP_SKIP_SET_WAKE, 501 }; 502 503 #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF)) 504 505 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id) 506 { 507 struct amd_gpio *gpio_dev = dev_id; 508 struct gpio_chip *gc = &gpio_dev->gc; 509 irqreturn_t ret = IRQ_NONE; 510 unsigned int i, irqnr; 511 unsigned long flags; 512 u32 *regs, regval; 513 u64 status, mask; 514 515 /* Read the wake status */ 516 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 517 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); 518 status <<= 32; 519 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0); 520 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 521 522 /* Bit 0-45 contain the relevant status bits */ 523 status &= (1ULL << 46) - 1; 524 regs = gpio_dev->base; 525 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) { 526 if (!(status & mask)) 527 continue; 528 status &= ~mask; 529 530 /* Each status bit covers four pins */ 531 for (i = 0; i < 4; i++) { 532 regval = readl(regs + i); 533 if (!(regval & PIN_IRQ_PENDING)) 534 continue; 535 irq = irq_find_mapping(gc->irq.domain, irqnr + i); 536 generic_handle_irq(irq); 537 538 /* Clear interrupt. 539 * We must read the pin register again, in case the 540 * value was changed while executing 541 * generic_handle_irq() above. 542 */ 543 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 544 regval = readl(regs + i); 545 writel(regval, regs + i); 546 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 547 ret = IRQ_HANDLED; 548 } 549 } 550 551 /* Signal EOI to the GPIO unit */ 552 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 553 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 554 regval |= EOI_MASK; 555 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG); 556 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 557 558 return ret; 559 } 560 561 static int amd_get_groups_count(struct pinctrl_dev *pctldev) 562 { 563 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 564 565 return gpio_dev->ngroups; 566 } 567 568 static const char *amd_get_group_name(struct pinctrl_dev *pctldev, 569 unsigned group) 570 { 571 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 572 573 return gpio_dev->groups[group].name; 574 } 575 576 static int amd_get_group_pins(struct pinctrl_dev *pctldev, 577 unsigned group, 578 const unsigned **pins, 579 unsigned *num_pins) 580 { 581 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 582 583 *pins = gpio_dev->groups[group].pins; 584 *num_pins = gpio_dev->groups[group].npins; 585 return 0; 586 } 587 588 static const struct pinctrl_ops amd_pinctrl_ops = { 589 .get_groups_count = amd_get_groups_count, 590 .get_group_name = amd_get_group_name, 591 .get_group_pins = amd_get_group_pins, 592 #ifdef CONFIG_OF 593 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 594 .dt_free_map = pinctrl_utils_free_map, 595 #endif 596 }; 597 598 static int amd_pinconf_get(struct pinctrl_dev *pctldev, 599 unsigned int pin, 600 unsigned long *config) 601 { 602 u32 pin_reg; 603 unsigned arg; 604 unsigned long flags; 605 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 606 enum pin_config_param param = pinconf_to_config_param(*config); 607 608 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 609 pin_reg = readl(gpio_dev->base + pin*4); 610 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 611 switch (param) { 612 case PIN_CONFIG_INPUT_DEBOUNCE: 613 arg = pin_reg & DB_TMR_OUT_MASK; 614 break; 615 616 case PIN_CONFIG_BIAS_PULL_DOWN: 617 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); 618 break; 619 620 case PIN_CONFIG_BIAS_PULL_UP: 621 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); 622 break; 623 624 case PIN_CONFIG_DRIVE_STRENGTH: 625 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; 626 break; 627 628 default: 629 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n", 630 param); 631 return -ENOTSUPP; 632 } 633 634 *config = pinconf_to_config_packed(param, arg); 635 636 return 0; 637 } 638 639 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 640 unsigned long *configs, unsigned num_configs) 641 { 642 int i; 643 u32 arg; 644 int ret = 0; 645 u32 pin_reg; 646 unsigned long flags; 647 enum pin_config_param param; 648 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 649 650 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 651 for (i = 0; i < num_configs; i++) { 652 param = pinconf_to_config_param(configs[i]); 653 arg = pinconf_to_config_argument(configs[i]); 654 pin_reg = readl(gpio_dev->base + pin*4); 655 656 switch (param) { 657 case PIN_CONFIG_INPUT_DEBOUNCE: 658 pin_reg &= ~DB_TMR_OUT_MASK; 659 pin_reg |= arg & DB_TMR_OUT_MASK; 660 break; 661 662 case PIN_CONFIG_BIAS_PULL_DOWN: 663 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); 664 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; 665 break; 666 667 case PIN_CONFIG_BIAS_PULL_UP: 668 pin_reg &= ~BIT(PULL_UP_SEL_OFF); 669 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; 670 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); 671 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; 672 break; 673 674 case PIN_CONFIG_DRIVE_STRENGTH: 675 pin_reg &= ~(DRV_STRENGTH_SEL_MASK 676 << DRV_STRENGTH_SEL_OFF); 677 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) 678 << DRV_STRENGTH_SEL_OFF; 679 break; 680 681 default: 682 dev_err(&gpio_dev->pdev->dev, 683 "Invalid config param %04x\n", param); 684 ret = -ENOTSUPP; 685 } 686 687 writel(pin_reg, gpio_dev->base + pin*4); 688 } 689 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 690 691 return ret; 692 } 693 694 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, 695 unsigned int group, 696 unsigned long *config) 697 { 698 const unsigned *pins; 699 unsigned npins; 700 int ret; 701 702 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 703 if (ret) 704 return ret; 705 706 if (amd_pinconf_get(pctldev, pins[0], config)) 707 return -ENOTSUPP; 708 709 return 0; 710 } 711 712 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, 713 unsigned group, unsigned long *configs, 714 unsigned num_configs) 715 { 716 const unsigned *pins; 717 unsigned npins; 718 int i, ret; 719 720 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 721 if (ret) 722 return ret; 723 for (i = 0; i < npins; i++) { 724 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) 725 return -ENOTSUPP; 726 } 727 return 0; 728 } 729 730 static const struct pinconf_ops amd_pinconf_ops = { 731 .pin_config_get = amd_pinconf_get, 732 .pin_config_set = amd_pinconf_set, 733 .pin_config_group_get = amd_pinconf_group_get, 734 .pin_config_group_set = amd_pinconf_group_set, 735 }; 736 737 #ifdef CONFIG_PM_SLEEP 738 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) 739 { 740 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 741 742 if (!pd) 743 return false; 744 745 /* 746 * Only restore the pin if it is actually in use by the kernel (or 747 * by userspace). 748 */ 749 if (pd->mux_owner || pd->gpio_owner || 750 gpiochip_line_is_irq(&gpio_dev->gc, pin)) 751 return true; 752 753 return false; 754 } 755 756 static int amd_gpio_suspend(struct device *dev) 757 { 758 struct platform_device *pdev = to_platform_device(dev); 759 struct amd_gpio *gpio_dev = platform_get_drvdata(pdev); 760 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 761 int i; 762 763 for (i = 0; i < desc->npins; i++) { 764 int pin = desc->pins[i].number; 765 766 if (!amd_gpio_should_save(gpio_dev, pin)) 767 continue; 768 769 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin*4); 770 } 771 772 return 0; 773 } 774 775 static int amd_gpio_resume(struct device *dev) 776 { 777 struct platform_device *pdev = to_platform_device(dev); 778 struct amd_gpio *gpio_dev = platform_get_drvdata(pdev); 779 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 780 int i; 781 782 for (i = 0; i < desc->npins; i++) { 783 int pin = desc->pins[i].number; 784 785 if (!amd_gpio_should_save(gpio_dev, pin)) 786 continue; 787 788 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin*4); 789 } 790 791 return 0; 792 } 793 794 static const struct dev_pm_ops amd_gpio_pm_ops = { 795 SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend, 796 amd_gpio_resume) 797 }; 798 #endif 799 800 static struct pinctrl_desc amd_pinctrl_desc = { 801 .pins = kerncz_pins, 802 .npins = ARRAY_SIZE(kerncz_pins), 803 .pctlops = &amd_pinctrl_ops, 804 .confops = &amd_pinconf_ops, 805 .owner = THIS_MODULE, 806 }; 807 808 static int amd_gpio_probe(struct platform_device *pdev) 809 { 810 int ret = 0; 811 int irq_base; 812 struct resource *res; 813 struct amd_gpio *gpio_dev; 814 815 gpio_dev = devm_kzalloc(&pdev->dev, 816 sizeof(struct amd_gpio), GFP_KERNEL); 817 if (!gpio_dev) 818 return -ENOMEM; 819 820 raw_spin_lock_init(&gpio_dev->lock); 821 822 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 823 if (!res) { 824 dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); 825 return -EINVAL; 826 } 827 828 gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start, 829 resource_size(res)); 830 if (!gpio_dev->base) 831 return -ENOMEM; 832 833 irq_base = platform_get_irq(pdev, 0); 834 if (irq_base < 0) { 835 dev_err(&pdev->dev, "Failed to get gpio IRQ: %d\n", irq_base); 836 return irq_base; 837 } 838 839 #ifdef CONFIG_PM_SLEEP 840 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins, 841 sizeof(*gpio_dev->saved_regs), 842 GFP_KERNEL); 843 if (!gpio_dev->saved_regs) 844 return -ENOMEM; 845 #endif 846 847 gpio_dev->pdev = pdev; 848 gpio_dev->gc.direction_input = amd_gpio_direction_input; 849 gpio_dev->gc.direction_output = amd_gpio_direction_output; 850 gpio_dev->gc.get = amd_gpio_get_value; 851 gpio_dev->gc.set = amd_gpio_set_value; 852 gpio_dev->gc.set_config = amd_gpio_set_config; 853 gpio_dev->gc.dbg_show = amd_gpio_dbg_show; 854 855 gpio_dev->gc.base = -1; 856 gpio_dev->gc.label = pdev->name; 857 gpio_dev->gc.owner = THIS_MODULE; 858 gpio_dev->gc.parent = &pdev->dev; 859 gpio_dev->gc.ngpio = resource_size(res) / 4; 860 #if defined(CONFIG_OF_GPIO) 861 gpio_dev->gc.of_node = pdev->dev.of_node; 862 #endif 863 864 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64; 865 gpio_dev->groups = kerncz_groups; 866 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); 867 868 amd_pinctrl_desc.name = dev_name(&pdev->dev); 869 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, 870 gpio_dev); 871 if (IS_ERR(gpio_dev->pctrl)) { 872 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 873 return PTR_ERR(gpio_dev->pctrl); 874 } 875 876 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); 877 if (ret) 878 return ret; 879 880 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), 881 0, 0, gpio_dev->gc.ngpio); 882 if (ret) { 883 dev_err(&pdev->dev, "Failed to add pin range\n"); 884 goto out2; 885 } 886 887 ret = gpiochip_irqchip_add(&gpio_dev->gc, 888 &amd_gpio_irqchip, 889 0, 890 handle_simple_irq, 891 IRQ_TYPE_NONE); 892 if (ret) { 893 dev_err(&pdev->dev, "could not add irqchip\n"); 894 ret = -ENODEV; 895 goto out2; 896 } 897 898 ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, 0, 899 KBUILD_MODNAME, gpio_dev); 900 if (ret) 901 goto out2; 902 903 platform_set_drvdata(pdev, gpio_dev); 904 905 dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); 906 return ret; 907 908 out2: 909 gpiochip_remove(&gpio_dev->gc); 910 911 return ret; 912 } 913 914 static int amd_gpio_remove(struct platform_device *pdev) 915 { 916 struct amd_gpio *gpio_dev; 917 918 gpio_dev = platform_get_drvdata(pdev); 919 920 gpiochip_remove(&gpio_dev->gc); 921 922 return 0; 923 } 924 925 static const struct acpi_device_id amd_gpio_acpi_match[] = { 926 { "AMD0030", 0 }, 927 { "AMDI0030", 0}, 928 { }, 929 }; 930 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); 931 932 static struct platform_driver amd_gpio_driver = { 933 .driver = { 934 .name = "amd_gpio", 935 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), 936 #ifdef CONFIG_PM_SLEEP 937 .pm = &amd_gpio_pm_ops, 938 #endif 939 }, 940 .probe = amd_gpio_probe, 941 .remove = amd_gpio_remove, 942 }; 943 944 module_platform_driver(amd_gpio_driver); 945 946 MODULE_LICENSE("GPL v2"); 947 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); 948 MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); 949