1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPIO driver for AMD 4 * 5 * Copyright (c) 2014,2015 AMD Corporation. 6 * Authors: Ken Xue <Ken.Xue@amd.com> 7 * Wu, Jeff <Jeff.Wu@amd.com> 8 * 9 */ 10 11 #include <linux/err.h> 12 #include <linux/bug.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/spinlock.h> 16 #include <linux/compiler.h> 17 #include <linux/types.h> 18 #include <linux/errno.h> 19 #include <linux/log2.h> 20 #include <linux/io.h> 21 #include <linux/gpio/driver.h> 22 #include <linux/slab.h> 23 #include <linux/platform_device.h> 24 #include <linux/mutex.h> 25 #include <linux/acpi.h> 26 #include <linux/seq_file.h> 27 #include <linux/interrupt.h> 28 #include <linux/list.h> 29 #include <linux/bitops.h> 30 #include <linux/pinctrl/pinconf.h> 31 #include <linux/pinctrl/pinconf-generic.h> 32 #include <linux/pinctrl/pinmux.h> 33 #include <linux/suspend.h> 34 35 #include "core.h" 36 #include "pinctrl-utils.h" 37 #include "pinctrl-amd.h" 38 39 static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset) 40 { 41 unsigned long flags; 42 u32 pin_reg; 43 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 44 45 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 46 pin_reg = readl(gpio_dev->base + offset * 4); 47 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 48 49 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) 50 return GPIO_LINE_DIRECTION_OUT; 51 52 return GPIO_LINE_DIRECTION_IN; 53 } 54 55 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 56 { 57 unsigned long flags; 58 u32 pin_reg; 59 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 60 61 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 62 pin_reg = readl(gpio_dev->base + offset * 4); 63 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); 64 writel(pin_reg, gpio_dev->base + offset * 4); 65 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 66 67 return 0; 68 } 69 70 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 71 int value) 72 { 73 u32 pin_reg; 74 unsigned long flags; 75 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 76 77 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 78 pin_reg = readl(gpio_dev->base + offset * 4); 79 pin_reg |= BIT(OUTPUT_ENABLE_OFF); 80 if (value) 81 pin_reg |= BIT(OUTPUT_VALUE_OFF); 82 else 83 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 84 writel(pin_reg, gpio_dev->base + offset * 4); 85 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 86 87 return 0; 88 } 89 90 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) 91 { 92 u32 pin_reg; 93 unsigned long flags; 94 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 95 96 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 97 pin_reg = readl(gpio_dev->base + offset * 4); 98 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 99 100 return !!(pin_reg & BIT(PIN_STS_OFF)); 101 } 102 103 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) 104 { 105 u32 pin_reg; 106 unsigned long flags; 107 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 108 109 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 110 pin_reg = readl(gpio_dev->base + offset * 4); 111 if (value) 112 pin_reg |= BIT(OUTPUT_VALUE_OFF); 113 else 114 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 115 writel(pin_reg, gpio_dev->base + offset * 4); 116 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 117 } 118 119 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, 120 unsigned debounce) 121 { 122 u32 time; 123 u32 pin_reg; 124 int ret = 0; 125 unsigned long flags; 126 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 127 128 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 129 130 /* Use special handling for Pin0 debounce */ 131 pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 132 if (pin_reg & INTERNAL_GPIO0_DEBOUNCE) 133 debounce = 0; 134 135 pin_reg = readl(gpio_dev->base + offset * 4); 136 137 if (debounce) { 138 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 139 pin_reg &= ~DB_TMR_OUT_MASK; 140 /* 141 Debounce Debounce Timer Max 142 TmrLarge TmrOutUnit Unit Debounce 143 Time 144 0 0 61 usec (2 RtcClk) 976 usec 145 0 1 244 usec (8 RtcClk) 3.9 msec 146 1 0 15.6 msec (512 RtcClk) 250 msec 147 1 1 62.5 msec (2048 RtcClk) 1 sec 148 */ 149 150 if (debounce < 61) { 151 pin_reg |= 1; 152 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 153 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 154 } else if (debounce < 976) { 155 time = debounce / 61; 156 pin_reg |= time & DB_TMR_OUT_MASK; 157 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 158 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 159 } else if (debounce < 3900) { 160 time = debounce / 244; 161 pin_reg |= time & DB_TMR_OUT_MASK; 162 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 163 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 164 } else if (debounce < 250000) { 165 time = debounce / 15625; 166 pin_reg |= time & DB_TMR_OUT_MASK; 167 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 168 pin_reg |= BIT(DB_TMR_LARGE_OFF); 169 } else if (debounce < 1000000) { 170 time = debounce / 62500; 171 pin_reg |= time & DB_TMR_OUT_MASK; 172 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 173 pin_reg |= BIT(DB_TMR_LARGE_OFF); 174 } else { 175 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 176 ret = -EINVAL; 177 } 178 } else { 179 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 180 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 181 pin_reg &= ~DB_TMR_OUT_MASK; 182 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 183 } 184 writel(pin_reg, gpio_dev->base + offset * 4); 185 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 186 187 return ret; 188 } 189 190 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset, 191 unsigned long config) 192 { 193 u32 debounce; 194 195 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 196 return -ENOTSUPP; 197 198 debounce = pinconf_to_config_argument(config); 199 return amd_gpio_set_debounce(gc, offset, debounce); 200 } 201 202 #ifdef CONFIG_DEBUG_FS 203 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) 204 { 205 u32 pin_reg; 206 u32 db_cntrl; 207 unsigned long flags; 208 unsigned int bank, i, pin_num; 209 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 210 211 bool tmr_out_unit; 212 bool tmr_large; 213 214 char *level_trig; 215 char *active_level; 216 char *interrupt_mask; 217 char *wake_cntrl0; 218 char *wake_cntrl1; 219 char *wake_cntrl2; 220 char *pin_sts; 221 char *interrupt_sts; 222 char *wake_sts; 223 char *pull_up_sel; 224 char *orientation; 225 char debounce_value[40]; 226 char *debounce_enable; 227 char *wake_cntrlz; 228 229 seq_printf(s, "WAKE_INT_MASTER_REG: 0x%08x\n", readl(gpio_dev->base + WAKE_INT_MASTER_REG)); 230 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { 231 unsigned int time = 0; 232 unsigned int unit = 0; 233 234 switch (bank) { 235 case 0: 236 i = 0; 237 pin_num = AMD_GPIO_PINS_BANK0; 238 break; 239 case 1: 240 i = 64; 241 pin_num = AMD_GPIO_PINS_BANK1 + i; 242 break; 243 case 2: 244 i = 128; 245 pin_num = AMD_GPIO_PINS_BANK2 + i; 246 break; 247 case 3: 248 i = 192; 249 pin_num = AMD_GPIO_PINS_BANK3 + i; 250 break; 251 default: 252 /* Illegal bank number, ignore */ 253 continue; 254 } 255 seq_printf(s, "GPIO bank%d\n", bank); 256 seq_puts(s, "gpio\t int|active|trigger|S0i3| S3|S4/S5| Z|wake|pull| orient| debounce|reg\n"); 257 for (; i < pin_num; i++) { 258 seq_printf(s, "#%d\t", i); 259 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 260 pin_reg = readl(gpio_dev->base + i * 4); 261 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 262 263 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { 264 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) & 265 ACTIVE_LEVEL_MASK; 266 267 if (level == ACTIVE_LEVEL_HIGH) 268 active_level = "↑"; 269 else if (level == ACTIVE_LEVEL_LOW) 270 active_level = "↓"; 271 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) && 272 level == ACTIVE_LEVEL_BOTH) 273 active_level = "b"; 274 else 275 active_level = "?"; 276 277 if (pin_reg & BIT(LEVEL_TRIG_OFF)) 278 level_trig = "level"; 279 else 280 level_trig = " edge"; 281 282 if (pin_reg & BIT(INTERRUPT_MASK_OFF)) 283 interrupt_mask = "��"; 284 else 285 interrupt_mask = "��"; 286 287 if (pin_reg & BIT(INTERRUPT_STS_OFF)) 288 interrupt_sts = "��"; 289 else 290 interrupt_sts = " "; 291 292 seq_printf(s, "%s %s| %s| %s|", 293 interrupt_sts, 294 interrupt_mask, 295 active_level, 296 level_trig); 297 } else 298 seq_puts(s, " ∅| | |"); 299 300 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) 301 wake_cntrl0 = "⏰"; 302 else 303 wake_cntrl0 = " "; 304 seq_printf(s, " %s| ", wake_cntrl0); 305 306 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) 307 wake_cntrl1 = "⏰"; 308 else 309 wake_cntrl1 = " "; 310 seq_printf(s, "%s|", wake_cntrl1); 311 312 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) 313 wake_cntrl2 = "⏰"; 314 else 315 wake_cntrl2 = " "; 316 seq_printf(s, " %s|", wake_cntrl2); 317 318 if (pin_reg & BIT(WAKECNTRL_Z_OFF)) 319 wake_cntrlz = "⏰"; 320 else 321 wake_cntrlz = " "; 322 seq_printf(s, "%s|", wake_cntrlz); 323 324 if (pin_reg & BIT(WAKE_STS_OFF)) 325 wake_sts = "��"; 326 else 327 wake_sts = " "; 328 seq_printf(s, " %s|", wake_sts); 329 330 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { 331 if (pin_reg & BIT(PULL_UP_SEL_OFF)) 332 pull_up_sel = "8k"; 333 else 334 pull_up_sel = "4k"; 335 seq_printf(s, "%s ↑|", 336 pull_up_sel); 337 } else if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) { 338 seq_puts(s, " ↓|"); 339 } else { 340 seq_puts(s, " |"); 341 } 342 343 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { 344 pin_sts = "output"; 345 if (pin_reg & BIT(OUTPUT_VALUE_OFF)) 346 orientation = "↑"; 347 else 348 orientation = "↓"; 349 } else { 350 pin_sts = "input "; 351 if (pin_reg & BIT(PIN_STS_OFF)) 352 orientation = "↑"; 353 else 354 orientation = "↓"; 355 } 356 seq_printf(s, "%s %s|", pin_sts, orientation); 357 358 db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg; 359 if (db_cntrl) { 360 tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF); 361 tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF); 362 time = pin_reg & DB_TMR_OUT_MASK; 363 if (tmr_large) { 364 if (tmr_out_unit) 365 unit = 62500; 366 else 367 unit = 15625; 368 } else { 369 if (tmr_out_unit) 370 unit = 244; 371 else 372 unit = 61; 373 } 374 if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl) 375 debounce_enable = "b"; 376 else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl) 377 debounce_enable = "↓"; 378 else 379 debounce_enable = "↑"; 380 snprintf(debounce_value, sizeof(debounce_value), "%06u", time * unit); 381 seq_printf(s, "%s (�� %sus)|", debounce_enable, debounce_value); 382 } else { 383 seq_puts(s, " |"); 384 } 385 seq_printf(s, "0x%x\n", pin_reg); 386 } 387 } 388 } 389 #else 390 #define amd_gpio_dbg_show NULL 391 #endif 392 393 static void amd_gpio_irq_enable(struct irq_data *d) 394 { 395 u32 pin_reg; 396 unsigned long flags; 397 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 398 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 399 400 gpiochip_enable_irq(gc, d->hwirq); 401 402 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 403 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 404 pin_reg |= BIT(INTERRUPT_ENABLE_OFF); 405 pin_reg |= BIT(INTERRUPT_MASK_OFF); 406 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 407 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 408 } 409 410 static void amd_gpio_irq_disable(struct irq_data *d) 411 { 412 u32 pin_reg; 413 unsigned long flags; 414 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 415 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 416 417 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 418 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 419 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); 420 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 421 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 422 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 423 424 gpiochip_disable_irq(gc, d->hwirq); 425 } 426 427 static void amd_gpio_irq_mask(struct irq_data *d) 428 { 429 u32 pin_reg; 430 unsigned long flags; 431 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 432 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 433 434 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 435 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 436 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 437 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 438 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 439 } 440 441 static void amd_gpio_irq_unmask(struct irq_data *d) 442 { 443 u32 pin_reg; 444 unsigned long flags; 445 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 446 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 447 448 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 449 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 450 pin_reg |= BIT(INTERRUPT_MASK_OFF); 451 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 452 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 453 } 454 455 static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 456 { 457 u32 pin_reg; 458 unsigned long flags; 459 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 460 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 461 u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3); 462 int err; 463 464 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 465 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 466 467 if (on) 468 pin_reg |= wake_mask; 469 else 470 pin_reg &= ~wake_mask; 471 472 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 473 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 474 475 if (on) 476 err = enable_irq_wake(gpio_dev->irq); 477 else 478 err = disable_irq_wake(gpio_dev->irq); 479 480 if (err) 481 dev_err(&gpio_dev->pdev->dev, "failed to %s wake-up interrupt\n", 482 on ? "enable" : "disable"); 483 484 return 0; 485 } 486 487 static void amd_gpio_irq_eoi(struct irq_data *d) 488 { 489 u32 reg; 490 unsigned long flags; 491 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 492 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 493 494 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 495 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 496 reg |= EOI_MASK; 497 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 498 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 499 } 500 501 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) 502 { 503 int ret = 0; 504 u32 pin_reg, pin_reg_irq_en, mask; 505 unsigned long flags; 506 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 507 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 508 509 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 510 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 511 512 switch (type & IRQ_TYPE_SENSE_MASK) { 513 case IRQ_TYPE_EDGE_RISING: 514 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 515 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 516 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 517 irq_set_handler_locked(d, handle_edge_irq); 518 break; 519 520 case IRQ_TYPE_EDGE_FALLING: 521 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 522 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 523 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 524 irq_set_handler_locked(d, handle_edge_irq); 525 break; 526 527 case IRQ_TYPE_EDGE_BOTH: 528 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 529 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 530 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; 531 irq_set_handler_locked(d, handle_edge_irq); 532 break; 533 534 case IRQ_TYPE_LEVEL_HIGH: 535 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 536 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 537 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 538 irq_set_handler_locked(d, handle_level_irq); 539 break; 540 541 case IRQ_TYPE_LEVEL_LOW: 542 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 543 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 544 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 545 irq_set_handler_locked(d, handle_level_irq); 546 break; 547 548 case IRQ_TYPE_NONE: 549 break; 550 551 default: 552 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); 553 ret = -EINVAL; 554 } 555 556 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; 557 /* 558 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the 559 * debounce registers of any GPIO will block wake/interrupt status 560 * generation for *all* GPIOs for a length of time that depends on 561 * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the 562 * INTERRUPT_ENABLE bit will read as 0. 563 * 564 * We temporarily enable irq for the GPIO whose configuration is 565 * changing, and then wait for it to read back as 1 to know when 566 * debounce has settled and then disable the irq again. 567 * We do this polling with the spinlock held to ensure other GPIO 568 * access routines do not read an incorrect value for the irq enable 569 * bit of other GPIOs. We keep the GPIO masked while polling to avoid 570 * spurious irqs, and disable the irq again after polling. 571 */ 572 mask = BIT(INTERRUPT_ENABLE_OFF); 573 pin_reg_irq_en = pin_reg; 574 pin_reg_irq_en |= mask; 575 pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF); 576 writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4); 577 while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask) 578 continue; 579 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 580 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 581 582 return ret; 583 } 584 585 static void amd_irq_ack(struct irq_data *d) 586 { 587 /* 588 * based on HW design,there is no need to ack HW 589 * before handle current irq. But this routine is 590 * necessary for handle_edge_irq 591 */ 592 } 593 594 static const struct irq_chip amd_gpio_irqchip = { 595 .name = "amd_gpio", 596 .irq_ack = amd_irq_ack, 597 .irq_enable = amd_gpio_irq_enable, 598 .irq_disable = amd_gpio_irq_disable, 599 .irq_mask = amd_gpio_irq_mask, 600 .irq_unmask = amd_gpio_irq_unmask, 601 .irq_set_wake = amd_gpio_irq_set_wake, 602 .irq_eoi = amd_gpio_irq_eoi, 603 .irq_set_type = amd_gpio_irq_set_type, 604 /* 605 * We need to set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND so that a wake event 606 * also generates an IRQ. We need the IRQ so the irq_handler can clear 607 * the wake event. Otherwise the wake event will never clear and 608 * prevent the system from suspending. 609 */ 610 .flags = IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND | IRQCHIP_IMMUTABLE, 611 GPIOCHIP_IRQ_RESOURCE_HELPERS, 612 }; 613 614 #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF)) 615 616 static bool do_amd_gpio_irq_handler(int irq, void *dev_id) 617 { 618 struct amd_gpio *gpio_dev = dev_id; 619 struct gpio_chip *gc = &gpio_dev->gc; 620 unsigned int i, irqnr; 621 unsigned long flags; 622 u32 __iomem *regs; 623 bool ret = false; 624 u32 regval; 625 u64 status, mask; 626 627 /* Read the wake status */ 628 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 629 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); 630 status <<= 32; 631 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0); 632 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 633 634 /* Bit 0-45 contain the relevant status bits */ 635 status &= (1ULL << 46) - 1; 636 regs = gpio_dev->base; 637 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) { 638 if (!(status & mask)) 639 continue; 640 status &= ~mask; 641 642 /* Each status bit covers four pins */ 643 for (i = 0; i < 4; i++) { 644 regval = readl(regs + i); 645 646 if (regval & PIN_IRQ_PENDING) 647 pm_pr_dbg("GPIO %d is active: 0x%x", 648 irqnr + i, regval); 649 650 /* caused wake on resume context for shared IRQ */ 651 if (irq < 0 && (regval & BIT(WAKE_STS_OFF))) 652 return true; 653 654 if (!(regval & PIN_IRQ_PENDING) || 655 !(regval & BIT(INTERRUPT_MASK_OFF))) 656 continue; 657 generic_handle_domain_irq_safe(gc->irq.domain, irqnr + i); 658 659 /* Clear interrupt. 660 * We must read the pin register again, in case the 661 * value was changed while executing 662 * generic_handle_domain_irq() above. 663 * If the line is not an irq, disable it in order to 664 * avoid a system hang caused by an interrupt storm. 665 */ 666 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 667 regval = readl(regs + i); 668 if (!gpiochip_line_is_irq(gc, irqnr + i)) { 669 regval &= ~BIT(INTERRUPT_MASK_OFF); 670 dev_dbg(&gpio_dev->pdev->dev, 671 "Disabling spurious GPIO IRQ %d\n", 672 irqnr + i); 673 } else { 674 ret = true; 675 } 676 writel(regval, regs + i); 677 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 678 } 679 } 680 /* did not cause wake on resume context for shared IRQ */ 681 if (irq < 0) 682 return false; 683 684 /* Signal EOI to the GPIO unit */ 685 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 686 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 687 regval |= EOI_MASK; 688 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG); 689 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 690 691 return ret; 692 } 693 694 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id) 695 { 696 return IRQ_RETVAL(do_amd_gpio_irq_handler(irq, dev_id)); 697 } 698 699 static bool __maybe_unused amd_gpio_check_wake(void *dev_id) 700 { 701 return do_amd_gpio_irq_handler(-1, dev_id); 702 } 703 704 static int amd_get_groups_count(struct pinctrl_dev *pctldev) 705 { 706 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 707 708 return gpio_dev->ngroups; 709 } 710 711 static const char *amd_get_group_name(struct pinctrl_dev *pctldev, 712 unsigned group) 713 { 714 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 715 716 return gpio_dev->groups[group].name; 717 } 718 719 static int amd_get_group_pins(struct pinctrl_dev *pctldev, 720 unsigned group, 721 const unsigned **pins, 722 unsigned *num_pins) 723 { 724 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 725 726 *pins = gpio_dev->groups[group].pins; 727 *num_pins = gpio_dev->groups[group].npins; 728 return 0; 729 } 730 731 static const struct pinctrl_ops amd_pinctrl_ops = { 732 .get_groups_count = amd_get_groups_count, 733 .get_group_name = amd_get_group_name, 734 .get_group_pins = amd_get_group_pins, 735 #ifdef CONFIG_OF 736 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 737 .dt_free_map = pinctrl_utils_free_map, 738 #endif 739 }; 740 741 static int amd_pinconf_get(struct pinctrl_dev *pctldev, 742 unsigned int pin, 743 unsigned long *config) 744 { 745 u32 pin_reg; 746 unsigned arg; 747 unsigned long flags; 748 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 749 enum pin_config_param param = pinconf_to_config_param(*config); 750 751 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 752 pin_reg = readl(gpio_dev->base + pin*4); 753 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 754 switch (param) { 755 case PIN_CONFIG_INPUT_DEBOUNCE: 756 arg = pin_reg & DB_TMR_OUT_MASK; 757 break; 758 759 case PIN_CONFIG_BIAS_PULL_DOWN: 760 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); 761 break; 762 763 case PIN_CONFIG_BIAS_PULL_UP: 764 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); 765 break; 766 767 case PIN_CONFIG_DRIVE_STRENGTH: 768 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; 769 break; 770 771 default: 772 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n", 773 param); 774 return -ENOTSUPP; 775 } 776 777 *config = pinconf_to_config_packed(param, arg); 778 779 return 0; 780 } 781 782 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 783 unsigned long *configs, unsigned num_configs) 784 { 785 int i; 786 u32 arg; 787 int ret = 0; 788 u32 pin_reg; 789 unsigned long flags; 790 enum pin_config_param param; 791 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 792 793 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 794 for (i = 0; i < num_configs; i++) { 795 param = pinconf_to_config_param(configs[i]); 796 arg = pinconf_to_config_argument(configs[i]); 797 pin_reg = readl(gpio_dev->base + pin*4); 798 799 switch (param) { 800 case PIN_CONFIG_INPUT_DEBOUNCE: 801 pin_reg &= ~DB_TMR_OUT_MASK; 802 pin_reg |= arg & DB_TMR_OUT_MASK; 803 break; 804 805 case PIN_CONFIG_BIAS_PULL_DOWN: 806 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); 807 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; 808 break; 809 810 case PIN_CONFIG_BIAS_PULL_UP: 811 pin_reg &= ~BIT(PULL_UP_SEL_OFF); 812 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; 813 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); 814 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; 815 break; 816 817 case PIN_CONFIG_DRIVE_STRENGTH: 818 pin_reg &= ~(DRV_STRENGTH_SEL_MASK 819 << DRV_STRENGTH_SEL_OFF); 820 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) 821 << DRV_STRENGTH_SEL_OFF; 822 break; 823 824 default: 825 dev_err(&gpio_dev->pdev->dev, 826 "Invalid config param %04x\n", param); 827 ret = -ENOTSUPP; 828 } 829 830 writel(pin_reg, gpio_dev->base + pin*4); 831 } 832 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 833 834 return ret; 835 } 836 837 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, 838 unsigned int group, 839 unsigned long *config) 840 { 841 const unsigned *pins; 842 unsigned npins; 843 int ret; 844 845 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 846 if (ret) 847 return ret; 848 849 if (amd_pinconf_get(pctldev, pins[0], config)) 850 return -ENOTSUPP; 851 852 return 0; 853 } 854 855 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, 856 unsigned group, unsigned long *configs, 857 unsigned num_configs) 858 { 859 const unsigned *pins; 860 unsigned npins; 861 int i, ret; 862 863 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 864 if (ret) 865 return ret; 866 for (i = 0; i < npins; i++) { 867 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) 868 return -ENOTSUPP; 869 } 870 return 0; 871 } 872 873 static const struct pinconf_ops amd_pinconf_ops = { 874 .pin_config_get = amd_pinconf_get, 875 .pin_config_set = amd_pinconf_set, 876 .pin_config_group_get = amd_pinconf_group_get, 877 .pin_config_group_set = amd_pinconf_group_set, 878 }; 879 880 #ifdef CONFIG_PM_SLEEP 881 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) 882 { 883 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 884 885 if (!pd) 886 return false; 887 888 /* 889 * Only restore the pin if it is actually in use by the kernel (or 890 * by userspace). 891 */ 892 if (pd->mux_owner || pd->gpio_owner || 893 gpiochip_line_is_irq(&gpio_dev->gc, pin)) 894 return true; 895 896 return false; 897 } 898 899 static int amd_gpio_suspend(struct device *dev) 900 { 901 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 902 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 903 unsigned long flags; 904 int i; 905 906 for (i = 0; i < desc->npins; i++) { 907 int pin = desc->pins[i].number; 908 909 if (!amd_gpio_should_save(gpio_dev, pin)) 910 continue; 911 912 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 913 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING; 914 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 915 } 916 917 return 0; 918 } 919 920 static int amd_gpio_resume(struct device *dev) 921 { 922 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 923 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 924 unsigned long flags; 925 int i; 926 927 for (i = 0; i < desc->npins; i++) { 928 int pin = desc->pins[i].number; 929 930 if (!amd_gpio_should_save(gpio_dev, pin)) 931 continue; 932 933 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 934 gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING; 935 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin * 4); 936 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 937 } 938 939 return 0; 940 } 941 942 static const struct dev_pm_ops amd_gpio_pm_ops = { 943 SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend, 944 amd_gpio_resume) 945 }; 946 #endif 947 948 static int amd_get_functions_count(struct pinctrl_dev *pctldev) 949 { 950 return ARRAY_SIZE(pmx_functions); 951 } 952 953 static const char *amd_get_fname(struct pinctrl_dev *pctrldev, unsigned int selector) 954 { 955 return pmx_functions[selector].name; 956 } 957 958 static int amd_get_groups(struct pinctrl_dev *pctrldev, unsigned int selector, 959 const char * const **groups, 960 unsigned int * const num_groups) 961 { 962 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev); 963 964 if (!gpio_dev->iomux_base) { 965 dev_err(&gpio_dev->pdev->dev, "iomux function %d group not supported\n", selector); 966 return -EINVAL; 967 } 968 969 *groups = pmx_functions[selector].groups; 970 *num_groups = pmx_functions[selector].ngroups; 971 return 0; 972 } 973 974 static int amd_set_mux(struct pinctrl_dev *pctrldev, unsigned int function, unsigned int group) 975 { 976 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev); 977 struct device *dev = &gpio_dev->pdev->dev; 978 struct pin_desc *pd; 979 int ind, index; 980 981 if (!gpio_dev->iomux_base) 982 return -EINVAL; 983 984 for (index = 0; index < NSELECTS; index++) { 985 if (strcmp(gpio_dev->groups[group].name, pmx_functions[function].groups[index])) 986 continue; 987 988 if (readb(gpio_dev->iomux_base + pmx_functions[function].index) == 989 FUNCTION_INVALID) { 990 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n", 991 pmx_functions[function].index); 992 return -EINVAL; 993 } 994 995 writeb(index, gpio_dev->iomux_base + pmx_functions[function].index); 996 997 if (index != (readb(gpio_dev->iomux_base + pmx_functions[function].index) & 998 FUNCTION_MASK)) { 999 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n", 1000 pmx_functions[function].index); 1001 return -EINVAL; 1002 } 1003 1004 for (ind = 0; ind < gpio_dev->groups[group].npins; ind++) { 1005 if (strncmp(gpio_dev->groups[group].name, "IMX_F", strlen("IMX_F"))) 1006 continue; 1007 1008 pd = pin_desc_get(gpio_dev->pctrl, gpio_dev->groups[group].pins[ind]); 1009 pd->mux_owner = gpio_dev->groups[group].name; 1010 } 1011 break; 1012 } 1013 1014 return 0; 1015 } 1016 1017 static const struct pinmux_ops amd_pmxops = { 1018 .get_functions_count = amd_get_functions_count, 1019 .get_function_name = amd_get_fname, 1020 .get_function_groups = amd_get_groups, 1021 .set_mux = amd_set_mux, 1022 }; 1023 1024 static struct pinctrl_desc amd_pinctrl_desc = { 1025 .pins = kerncz_pins, 1026 .npins = ARRAY_SIZE(kerncz_pins), 1027 .pctlops = &amd_pinctrl_ops, 1028 .pmxops = &amd_pmxops, 1029 .confops = &amd_pinconf_ops, 1030 .owner = THIS_MODULE, 1031 }; 1032 1033 static void amd_get_iomux_res(struct amd_gpio *gpio_dev) 1034 { 1035 struct pinctrl_desc *desc = &amd_pinctrl_desc; 1036 struct device *dev = &gpio_dev->pdev->dev; 1037 int index; 1038 1039 index = device_property_match_string(dev, "pinctrl-resource-names", "iomux"); 1040 if (index < 0) { 1041 dev_dbg(dev, "iomux not supported\n"); 1042 goto out_no_pinmux; 1043 } 1044 1045 gpio_dev->iomux_base = devm_platform_ioremap_resource(gpio_dev->pdev, index); 1046 if (IS_ERR(gpio_dev->iomux_base)) { 1047 dev_dbg(dev, "iomux not supported %d io resource\n", index); 1048 goto out_no_pinmux; 1049 } 1050 1051 return; 1052 1053 out_no_pinmux: 1054 desc->pmxops = NULL; 1055 } 1056 1057 static int amd_gpio_probe(struct platform_device *pdev) 1058 { 1059 int ret = 0; 1060 struct resource *res; 1061 struct amd_gpio *gpio_dev; 1062 struct gpio_irq_chip *girq; 1063 1064 gpio_dev = devm_kzalloc(&pdev->dev, 1065 sizeof(struct amd_gpio), GFP_KERNEL); 1066 if (!gpio_dev) 1067 return -ENOMEM; 1068 1069 raw_spin_lock_init(&gpio_dev->lock); 1070 1071 gpio_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1072 if (IS_ERR(gpio_dev->base)) { 1073 dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); 1074 return PTR_ERR(gpio_dev->base); 1075 } 1076 1077 gpio_dev->irq = platform_get_irq(pdev, 0); 1078 if (gpio_dev->irq < 0) 1079 return gpio_dev->irq; 1080 1081 #ifdef CONFIG_PM_SLEEP 1082 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins, 1083 sizeof(*gpio_dev->saved_regs), 1084 GFP_KERNEL); 1085 if (!gpio_dev->saved_regs) 1086 return -ENOMEM; 1087 #endif 1088 1089 gpio_dev->pdev = pdev; 1090 gpio_dev->gc.get_direction = amd_gpio_get_direction; 1091 gpio_dev->gc.direction_input = amd_gpio_direction_input; 1092 gpio_dev->gc.direction_output = amd_gpio_direction_output; 1093 gpio_dev->gc.get = amd_gpio_get_value; 1094 gpio_dev->gc.set = amd_gpio_set_value; 1095 gpio_dev->gc.set_config = amd_gpio_set_config; 1096 gpio_dev->gc.dbg_show = amd_gpio_dbg_show; 1097 1098 gpio_dev->gc.base = -1; 1099 gpio_dev->gc.label = pdev->name; 1100 gpio_dev->gc.owner = THIS_MODULE; 1101 gpio_dev->gc.parent = &pdev->dev; 1102 gpio_dev->gc.ngpio = resource_size(res) / 4; 1103 1104 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64; 1105 gpio_dev->groups = kerncz_groups; 1106 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); 1107 1108 amd_pinctrl_desc.name = dev_name(&pdev->dev); 1109 amd_get_iomux_res(gpio_dev); 1110 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, 1111 gpio_dev); 1112 if (IS_ERR(gpio_dev->pctrl)) { 1113 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 1114 return PTR_ERR(gpio_dev->pctrl); 1115 } 1116 1117 girq = &gpio_dev->gc.irq; 1118 gpio_irq_chip_set_chip(girq, &amd_gpio_irqchip); 1119 /* This will let us handle the parent IRQ in the driver */ 1120 girq->parent_handler = NULL; 1121 girq->num_parents = 0; 1122 girq->parents = NULL; 1123 girq->default_type = IRQ_TYPE_NONE; 1124 girq->handler = handle_simple_irq; 1125 1126 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); 1127 if (ret) 1128 return ret; 1129 1130 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), 1131 0, 0, gpio_dev->gc.ngpio); 1132 if (ret) { 1133 dev_err(&pdev->dev, "Failed to add pin range\n"); 1134 goto out2; 1135 } 1136 1137 ret = devm_request_irq(&pdev->dev, gpio_dev->irq, amd_gpio_irq_handler, 1138 IRQF_SHARED, KBUILD_MODNAME, gpio_dev); 1139 if (ret) 1140 goto out2; 1141 1142 platform_set_drvdata(pdev, gpio_dev); 1143 acpi_register_wakeup_handler(gpio_dev->irq, amd_gpio_check_wake, gpio_dev); 1144 1145 dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); 1146 return ret; 1147 1148 out2: 1149 gpiochip_remove(&gpio_dev->gc); 1150 1151 return ret; 1152 } 1153 1154 static int amd_gpio_remove(struct platform_device *pdev) 1155 { 1156 struct amd_gpio *gpio_dev; 1157 1158 gpio_dev = platform_get_drvdata(pdev); 1159 1160 gpiochip_remove(&gpio_dev->gc); 1161 acpi_unregister_wakeup_handler(amd_gpio_check_wake, gpio_dev); 1162 1163 return 0; 1164 } 1165 1166 #ifdef CONFIG_ACPI 1167 static const struct acpi_device_id amd_gpio_acpi_match[] = { 1168 { "AMD0030", 0 }, 1169 { "AMDI0030", 0}, 1170 { "AMDI0031", 0}, 1171 { }, 1172 }; 1173 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); 1174 #endif 1175 1176 static struct platform_driver amd_gpio_driver = { 1177 .driver = { 1178 .name = "amd_gpio", 1179 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), 1180 #ifdef CONFIG_PM_SLEEP 1181 .pm = &amd_gpio_pm_ops, 1182 #endif 1183 }, 1184 .probe = amd_gpio_probe, 1185 .remove = amd_gpio_remove, 1186 }; 1187 1188 module_platform_driver(amd_gpio_driver); 1189 1190 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); 1191 MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); 1192