1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPIO driver for AMD 4 * 5 * Copyright (c) 2014,2015 AMD Corporation. 6 * Authors: Ken Xue <Ken.Xue@amd.com> 7 * Wu, Jeff <Jeff.Wu@amd.com> 8 * 9 */ 10 11 #include <linux/err.h> 12 #include <linux/bug.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/spinlock.h> 16 #include <linux/compiler.h> 17 #include <linux/types.h> 18 #include <linux/errno.h> 19 #include <linux/log2.h> 20 #include <linux/io.h> 21 #include <linux/gpio/driver.h> 22 #include <linux/slab.h> 23 #include <linux/platform_device.h> 24 #include <linux/mutex.h> 25 #include <linux/acpi.h> 26 #include <linux/seq_file.h> 27 #include <linux/interrupt.h> 28 #include <linux/list.h> 29 #include <linux/bitops.h> 30 #include <linux/pinctrl/pinconf.h> 31 #include <linux/pinctrl/pinconf-generic.h> 32 #include <linux/pinctrl/pinmux.h> 33 34 #include "core.h" 35 #include "pinctrl-utils.h" 36 #include "pinctrl-amd.h" 37 38 static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset) 39 { 40 unsigned long flags; 41 u32 pin_reg; 42 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 43 44 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 45 pin_reg = readl(gpio_dev->base + offset * 4); 46 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 47 48 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) 49 return GPIO_LINE_DIRECTION_OUT; 50 51 return GPIO_LINE_DIRECTION_IN; 52 } 53 54 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 55 { 56 unsigned long flags; 57 u32 pin_reg; 58 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 59 60 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 61 pin_reg = readl(gpio_dev->base + offset * 4); 62 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); 63 writel(pin_reg, gpio_dev->base + offset * 4); 64 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 65 66 return 0; 67 } 68 69 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 70 int value) 71 { 72 u32 pin_reg; 73 unsigned long flags; 74 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 75 76 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 77 pin_reg = readl(gpio_dev->base + offset * 4); 78 pin_reg |= BIT(OUTPUT_ENABLE_OFF); 79 if (value) 80 pin_reg |= BIT(OUTPUT_VALUE_OFF); 81 else 82 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 83 writel(pin_reg, gpio_dev->base + offset * 4); 84 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 85 86 return 0; 87 } 88 89 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) 90 { 91 u32 pin_reg; 92 unsigned long flags; 93 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 94 95 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 96 pin_reg = readl(gpio_dev->base + offset * 4); 97 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 98 99 return !!(pin_reg & BIT(PIN_STS_OFF)); 100 } 101 102 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) 103 { 104 u32 pin_reg; 105 unsigned long flags; 106 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 107 108 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 109 pin_reg = readl(gpio_dev->base + offset * 4); 110 if (value) 111 pin_reg |= BIT(OUTPUT_VALUE_OFF); 112 else 113 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 114 writel(pin_reg, gpio_dev->base + offset * 4); 115 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 116 } 117 118 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, 119 unsigned debounce) 120 { 121 u32 time; 122 u32 pin_reg; 123 int ret = 0; 124 unsigned long flags; 125 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 126 127 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 128 pin_reg = readl(gpio_dev->base + offset * 4); 129 130 if (debounce) { 131 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 132 pin_reg &= ~DB_TMR_OUT_MASK; 133 /* 134 Debounce Debounce Timer Max 135 TmrLarge TmrOutUnit Unit Debounce 136 Time 137 0 0 61 usec (2 RtcClk) 976 usec 138 0 1 244 usec (8 RtcClk) 3.9 msec 139 1 0 15.6 msec (512 RtcClk) 250 msec 140 1 1 62.5 msec (2048 RtcClk) 1 sec 141 */ 142 143 if (debounce < 61) { 144 pin_reg |= 1; 145 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 146 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 147 } else if (debounce < 976) { 148 time = debounce / 61; 149 pin_reg |= time & DB_TMR_OUT_MASK; 150 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 151 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 152 } else if (debounce < 3900) { 153 time = debounce / 244; 154 pin_reg |= time & DB_TMR_OUT_MASK; 155 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 156 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 157 } else if (debounce < 250000) { 158 time = debounce / 15625; 159 pin_reg |= time & DB_TMR_OUT_MASK; 160 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 161 pin_reg |= BIT(DB_TMR_LARGE_OFF); 162 } else if (debounce < 1000000) { 163 time = debounce / 62500; 164 pin_reg |= time & DB_TMR_OUT_MASK; 165 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 166 pin_reg |= BIT(DB_TMR_LARGE_OFF); 167 } else { 168 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 169 ret = -EINVAL; 170 } 171 } else { 172 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 173 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 174 pin_reg &= ~DB_TMR_OUT_MASK; 175 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 176 } 177 writel(pin_reg, gpio_dev->base + offset * 4); 178 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 179 180 return ret; 181 } 182 183 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset, 184 unsigned long config) 185 { 186 u32 debounce; 187 188 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 189 return -ENOTSUPP; 190 191 debounce = pinconf_to_config_argument(config); 192 return amd_gpio_set_debounce(gc, offset, debounce); 193 } 194 195 #ifdef CONFIG_DEBUG_FS 196 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) 197 { 198 u32 pin_reg; 199 u32 db_cntrl; 200 unsigned long flags; 201 unsigned int bank, i, pin_num; 202 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 203 204 bool tmr_out_unit; 205 bool tmr_large; 206 207 char *level_trig; 208 char *active_level; 209 char *interrupt_mask; 210 char *wake_cntrl0; 211 char *wake_cntrl1; 212 char *wake_cntrl2; 213 char *pin_sts; 214 char *interrupt_sts; 215 char *wake_sts; 216 char *pull_up_sel; 217 char *orientation; 218 char debounce_value[40]; 219 char *debounce_enable; 220 char *wake_cntrlz; 221 222 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { 223 unsigned int time = 0; 224 unsigned int unit = 0; 225 226 switch (bank) { 227 case 0: 228 i = 0; 229 pin_num = AMD_GPIO_PINS_BANK0; 230 break; 231 case 1: 232 i = 64; 233 pin_num = AMD_GPIO_PINS_BANK1 + i; 234 break; 235 case 2: 236 i = 128; 237 pin_num = AMD_GPIO_PINS_BANK2 + i; 238 break; 239 case 3: 240 i = 192; 241 pin_num = AMD_GPIO_PINS_BANK3 + i; 242 break; 243 default: 244 /* Illegal bank number, ignore */ 245 continue; 246 } 247 seq_printf(s, "GPIO bank%d\n", bank); 248 seq_puts(s, "gpio\t int|active|trigger|S0i3| S3|S4/S5| Z|wake|pull| orient| debounce|reg\n"); 249 for (; i < pin_num; i++) { 250 seq_printf(s, "#%d\t", i); 251 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 252 pin_reg = readl(gpio_dev->base + i * 4); 253 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 254 255 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { 256 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) & 257 ACTIVE_LEVEL_MASK; 258 259 if (level == ACTIVE_LEVEL_HIGH) 260 active_level = "↑"; 261 else if (level == ACTIVE_LEVEL_LOW) 262 active_level = "↓"; 263 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) && 264 level == ACTIVE_LEVEL_BOTH) 265 active_level = "b"; 266 else 267 active_level = "?"; 268 269 if (pin_reg & BIT(LEVEL_TRIG_OFF)) 270 level_trig = "level"; 271 else 272 level_trig = " edge"; 273 274 if (pin_reg & BIT(INTERRUPT_MASK_OFF)) 275 interrupt_mask = "��"; 276 else 277 interrupt_mask = "��"; 278 279 if (pin_reg & BIT(INTERRUPT_STS_OFF)) 280 interrupt_sts = "��"; 281 else 282 interrupt_sts = " "; 283 284 seq_printf(s, "%s %s| %s| %s|", 285 interrupt_sts, 286 interrupt_mask, 287 active_level, 288 level_trig); 289 } else 290 seq_puts(s, " ∅| | |"); 291 292 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) 293 wake_cntrl0 = "⏰"; 294 else 295 wake_cntrl0 = " "; 296 seq_printf(s, " %s| ", wake_cntrl0); 297 298 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) 299 wake_cntrl1 = "⏰"; 300 else 301 wake_cntrl1 = " "; 302 seq_printf(s, "%s|", wake_cntrl1); 303 304 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) 305 wake_cntrl2 = "⏰"; 306 else 307 wake_cntrl2 = " "; 308 seq_printf(s, " %s|", wake_cntrl2); 309 310 if (pin_reg & BIT(WAKECNTRL_Z_OFF)) 311 wake_cntrlz = "⏰"; 312 else 313 wake_cntrlz = " "; 314 seq_printf(s, "%s|", wake_cntrlz); 315 316 if (pin_reg & BIT(WAKE_STS_OFF)) 317 wake_sts = "��"; 318 else 319 wake_sts = " "; 320 seq_printf(s, " %s|", wake_sts); 321 322 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { 323 if (pin_reg & BIT(PULL_UP_SEL_OFF)) 324 pull_up_sel = "8k"; 325 else 326 pull_up_sel = "4k"; 327 seq_printf(s, "%s ↑|", 328 pull_up_sel); 329 } else if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) { 330 seq_puts(s, " ↓|"); 331 } else { 332 seq_puts(s, " |"); 333 } 334 335 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { 336 pin_sts = "output"; 337 if (pin_reg & BIT(OUTPUT_VALUE_OFF)) 338 orientation = "↑"; 339 else 340 orientation = "↓"; 341 } else { 342 pin_sts = "input "; 343 if (pin_reg & BIT(PIN_STS_OFF)) 344 orientation = "↑"; 345 else 346 orientation = "↓"; 347 } 348 seq_printf(s, "%s %s|", pin_sts, orientation); 349 350 db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg; 351 if (db_cntrl) { 352 tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF); 353 tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF); 354 time = pin_reg & DB_TMR_OUT_MASK; 355 if (tmr_large) { 356 if (tmr_out_unit) 357 unit = 62500; 358 else 359 unit = 15625; 360 } else { 361 if (tmr_out_unit) 362 unit = 244; 363 else 364 unit = 61; 365 } 366 if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl) 367 debounce_enable = "b"; 368 else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl) 369 debounce_enable = "↓"; 370 else 371 debounce_enable = "↑"; 372 snprintf(debounce_value, sizeof(debounce_value), "%06u", time * unit); 373 seq_printf(s, "%s (�� %sus)|", debounce_enable, debounce_value); 374 } else { 375 seq_puts(s, " |"); 376 } 377 seq_printf(s, "0x%x\n", pin_reg); 378 } 379 } 380 } 381 #else 382 #define amd_gpio_dbg_show NULL 383 #endif 384 385 static void amd_gpio_irq_enable(struct irq_data *d) 386 { 387 u32 pin_reg; 388 unsigned long flags; 389 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 390 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 391 392 gpiochip_enable_irq(gc, d->hwirq); 393 394 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 395 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 396 pin_reg |= BIT(INTERRUPT_ENABLE_OFF); 397 pin_reg |= BIT(INTERRUPT_MASK_OFF); 398 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 399 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 400 } 401 402 static void amd_gpio_irq_disable(struct irq_data *d) 403 { 404 u32 pin_reg; 405 unsigned long flags; 406 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 407 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 408 409 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 410 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 411 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); 412 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 413 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 414 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 415 416 gpiochip_disable_irq(gc, d->hwirq); 417 } 418 419 static void amd_gpio_irq_mask(struct irq_data *d) 420 { 421 u32 pin_reg; 422 unsigned long flags; 423 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 424 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 425 426 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 427 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 428 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 429 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 430 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 431 } 432 433 static void amd_gpio_irq_unmask(struct irq_data *d) 434 { 435 u32 pin_reg; 436 unsigned long flags; 437 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 438 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 439 440 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 441 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 442 pin_reg |= BIT(INTERRUPT_MASK_OFF); 443 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 444 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 445 } 446 447 static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 448 { 449 u32 pin_reg; 450 unsigned long flags; 451 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 452 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 453 u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3); 454 int err; 455 456 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 457 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 458 459 if (on) 460 pin_reg |= wake_mask; 461 else 462 pin_reg &= ~wake_mask; 463 464 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 465 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 466 467 if (on) 468 err = enable_irq_wake(gpio_dev->irq); 469 else 470 err = disable_irq_wake(gpio_dev->irq); 471 472 if (err) 473 dev_err(&gpio_dev->pdev->dev, "failed to %s wake-up interrupt\n", 474 on ? "enable" : "disable"); 475 476 return 0; 477 } 478 479 static void amd_gpio_irq_eoi(struct irq_data *d) 480 { 481 u32 reg; 482 unsigned long flags; 483 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 484 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 485 486 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 487 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 488 reg |= EOI_MASK; 489 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 490 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 491 } 492 493 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) 494 { 495 int ret = 0; 496 u32 pin_reg, pin_reg_irq_en, mask; 497 unsigned long flags; 498 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 499 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 500 501 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 502 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 503 504 switch (type & IRQ_TYPE_SENSE_MASK) { 505 case IRQ_TYPE_EDGE_RISING: 506 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 507 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 508 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 509 irq_set_handler_locked(d, handle_edge_irq); 510 break; 511 512 case IRQ_TYPE_EDGE_FALLING: 513 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 514 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 515 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 516 irq_set_handler_locked(d, handle_edge_irq); 517 break; 518 519 case IRQ_TYPE_EDGE_BOTH: 520 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 521 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 522 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; 523 irq_set_handler_locked(d, handle_edge_irq); 524 break; 525 526 case IRQ_TYPE_LEVEL_HIGH: 527 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 528 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 529 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 530 irq_set_handler_locked(d, handle_level_irq); 531 break; 532 533 case IRQ_TYPE_LEVEL_LOW: 534 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 535 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 536 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 537 irq_set_handler_locked(d, handle_level_irq); 538 break; 539 540 case IRQ_TYPE_NONE: 541 break; 542 543 default: 544 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); 545 ret = -EINVAL; 546 } 547 548 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; 549 /* 550 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the 551 * debounce registers of any GPIO will block wake/interrupt status 552 * generation for *all* GPIOs for a length of time that depends on 553 * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the 554 * INTERRUPT_ENABLE bit will read as 0. 555 * 556 * We temporarily enable irq for the GPIO whose configuration is 557 * changing, and then wait for it to read back as 1 to know when 558 * debounce has settled and then disable the irq again. 559 * We do this polling with the spinlock held to ensure other GPIO 560 * access routines do not read an incorrect value for the irq enable 561 * bit of other GPIOs. We keep the GPIO masked while polling to avoid 562 * spurious irqs, and disable the irq again after polling. 563 */ 564 mask = BIT(INTERRUPT_ENABLE_OFF); 565 pin_reg_irq_en = pin_reg; 566 pin_reg_irq_en |= mask; 567 pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF); 568 writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4); 569 while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask) 570 continue; 571 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 572 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 573 574 return ret; 575 } 576 577 static void amd_irq_ack(struct irq_data *d) 578 { 579 /* 580 * based on HW design,there is no need to ack HW 581 * before handle current irq. But this routine is 582 * necessary for handle_edge_irq 583 */ 584 } 585 586 static const struct irq_chip amd_gpio_irqchip = { 587 .name = "amd_gpio", 588 .irq_ack = amd_irq_ack, 589 .irq_enable = amd_gpio_irq_enable, 590 .irq_disable = amd_gpio_irq_disable, 591 .irq_mask = amd_gpio_irq_mask, 592 .irq_unmask = amd_gpio_irq_unmask, 593 .irq_set_wake = amd_gpio_irq_set_wake, 594 .irq_eoi = amd_gpio_irq_eoi, 595 .irq_set_type = amd_gpio_irq_set_type, 596 /* 597 * We need to set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND so that a wake event 598 * also generates an IRQ. We need the IRQ so the irq_handler can clear 599 * the wake event. Otherwise the wake event will never clear and 600 * prevent the system from suspending. 601 */ 602 .flags = IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND | IRQCHIP_IMMUTABLE, 603 GPIOCHIP_IRQ_RESOURCE_HELPERS, 604 }; 605 606 #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF)) 607 608 static bool do_amd_gpio_irq_handler(int irq, void *dev_id) 609 { 610 struct amd_gpio *gpio_dev = dev_id; 611 struct gpio_chip *gc = &gpio_dev->gc; 612 unsigned int i, irqnr; 613 unsigned long flags; 614 u32 __iomem *regs; 615 bool ret = false; 616 u32 regval; 617 u64 status, mask; 618 619 /* Read the wake status */ 620 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 621 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); 622 status <<= 32; 623 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0); 624 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 625 626 /* Bit 0-45 contain the relevant status bits */ 627 status &= (1ULL << 46) - 1; 628 regs = gpio_dev->base; 629 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) { 630 if (!(status & mask)) 631 continue; 632 status &= ~mask; 633 634 /* Each status bit covers four pins */ 635 for (i = 0; i < 4; i++) { 636 regval = readl(regs + i); 637 638 if (regval & PIN_IRQ_PENDING) 639 dev_dbg(&gpio_dev->pdev->dev, 640 "GPIO %d is active: 0x%x", 641 irqnr + i, regval); 642 643 /* caused wake on resume context for shared IRQ */ 644 if (irq < 0 && (regval & BIT(WAKE_STS_OFF))) 645 return true; 646 647 if (!(regval & PIN_IRQ_PENDING) || 648 !(regval & BIT(INTERRUPT_MASK_OFF))) 649 continue; 650 generic_handle_domain_irq_safe(gc->irq.domain, irqnr + i); 651 652 /* Clear interrupt. 653 * We must read the pin register again, in case the 654 * value was changed while executing 655 * generic_handle_domain_irq() above. 656 * If we didn't find a mapping for the interrupt, 657 * disable it in order to avoid a system hang caused 658 * by an interrupt storm. 659 */ 660 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 661 regval = readl(regs + i); 662 if (irq == 0) { 663 regval &= ~BIT(INTERRUPT_ENABLE_OFF); 664 dev_dbg(&gpio_dev->pdev->dev, 665 "Disabling spurious GPIO IRQ %d\n", 666 irqnr + i); 667 } 668 writel(regval, regs + i); 669 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 670 ret = true; 671 } 672 } 673 /* did not cause wake on resume context for shared IRQ */ 674 if (irq < 0) 675 return false; 676 677 /* Signal EOI to the GPIO unit */ 678 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 679 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 680 regval |= EOI_MASK; 681 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG); 682 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 683 684 return ret; 685 } 686 687 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id) 688 { 689 return IRQ_RETVAL(do_amd_gpio_irq_handler(irq, dev_id)); 690 } 691 692 static bool __maybe_unused amd_gpio_check_wake(void *dev_id) 693 { 694 return do_amd_gpio_irq_handler(-1, dev_id); 695 } 696 697 static int amd_get_groups_count(struct pinctrl_dev *pctldev) 698 { 699 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 700 701 return gpio_dev->ngroups; 702 } 703 704 static const char *amd_get_group_name(struct pinctrl_dev *pctldev, 705 unsigned group) 706 { 707 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 708 709 return gpio_dev->groups[group].name; 710 } 711 712 static int amd_get_group_pins(struct pinctrl_dev *pctldev, 713 unsigned group, 714 const unsigned **pins, 715 unsigned *num_pins) 716 { 717 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 718 719 *pins = gpio_dev->groups[group].pins; 720 *num_pins = gpio_dev->groups[group].npins; 721 return 0; 722 } 723 724 static const struct pinctrl_ops amd_pinctrl_ops = { 725 .get_groups_count = amd_get_groups_count, 726 .get_group_name = amd_get_group_name, 727 .get_group_pins = amd_get_group_pins, 728 #ifdef CONFIG_OF 729 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 730 .dt_free_map = pinctrl_utils_free_map, 731 #endif 732 }; 733 734 static int amd_pinconf_get(struct pinctrl_dev *pctldev, 735 unsigned int pin, 736 unsigned long *config) 737 { 738 u32 pin_reg; 739 unsigned arg; 740 unsigned long flags; 741 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 742 enum pin_config_param param = pinconf_to_config_param(*config); 743 744 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 745 pin_reg = readl(gpio_dev->base + pin*4); 746 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 747 switch (param) { 748 case PIN_CONFIG_INPUT_DEBOUNCE: 749 arg = pin_reg & DB_TMR_OUT_MASK; 750 break; 751 752 case PIN_CONFIG_BIAS_PULL_DOWN: 753 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); 754 break; 755 756 case PIN_CONFIG_BIAS_PULL_UP: 757 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); 758 break; 759 760 case PIN_CONFIG_DRIVE_STRENGTH: 761 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; 762 break; 763 764 default: 765 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n", 766 param); 767 return -ENOTSUPP; 768 } 769 770 *config = pinconf_to_config_packed(param, arg); 771 772 return 0; 773 } 774 775 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 776 unsigned long *configs, unsigned num_configs) 777 { 778 int i; 779 u32 arg; 780 int ret = 0; 781 u32 pin_reg; 782 unsigned long flags; 783 enum pin_config_param param; 784 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 785 786 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 787 for (i = 0; i < num_configs; i++) { 788 param = pinconf_to_config_param(configs[i]); 789 arg = pinconf_to_config_argument(configs[i]); 790 pin_reg = readl(gpio_dev->base + pin*4); 791 792 switch (param) { 793 case PIN_CONFIG_INPUT_DEBOUNCE: 794 pin_reg &= ~DB_TMR_OUT_MASK; 795 pin_reg |= arg & DB_TMR_OUT_MASK; 796 break; 797 798 case PIN_CONFIG_BIAS_PULL_DOWN: 799 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); 800 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; 801 break; 802 803 case PIN_CONFIG_BIAS_PULL_UP: 804 pin_reg &= ~BIT(PULL_UP_SEL_OFF); 805 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; 806 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); 807 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; 808 break; 809 810 case PIN_CONFIG_DRIVE_STRENGTH: 811 pin_reg &= ~(DRV_STRENGTH_SEL_MASK 812 << DRV_STRENGTH_SEL_OFF); 813 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) 814 << DRV_STRENGTH_SEL_OFF; 815 break; 816 817 default: 818 dev_err(&gpio_dev->pdev->dev, 819 "Invalid config param %04x\n", param); 820 ret = -ENOTSUPP; 821 } 822 823 writel(pin_reg, gpio_dev->base + pin*4); 824 } 825 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 826 827 return ret; 828 } 829 830 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, 831 unsigned int group, 832 unsigned long *config) 833 { 834 const unsigned *pins; 835 unsigned npins; 836 int ret; 837 838 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 839 if (ret) 840 return ret; 841 842 if (amd_pinconf_get(pctldev, pins[0], config)) 843 return -ENOTSUPP; 844 845 return 0; 846 } 847 848 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, 849 unsigned group, unsigned long *configs, 850 unsigned num_configs) 851 { 852 const unsigned *pins; 853 unsigned npins; 854 int i, ret; 855 856 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 857 if (ret) 858 return ret; 859 for (i = 0; i < npins; i++) { 860 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) 861 return -ENOTSUPP; 862 } 863 return 0; 864 } 865 866 static const struct pinconf_ops amd_pinconf_ops = { 867 .pin_config_get = amd_pinconf_get, 868 .pin_config_set = amd_pinconf_set, 869 .pin_config_group_get = amd_pinconf_group_get, 870 .pin_config_group_set = amd_pinconf_group_set, 871 }; 872 873 static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) 874 { 875 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 876 unsigned long flags; 877 u32 pin_reg, mask; 878 int i; 879 880 mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) | 881 BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) | 882 BIT(WAKE_CNTRL_OFF_S4); 883 884 for (i = 0; i < desc->npins; i++) { 885 int pin = desc->pins[i].number; 886 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 887 888 if (!pd) 889 continue; 890 891 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 892 893 pin_reg = readl(gpio_dev->base + i * 4); 894 pin_reg &= ~mask; 895 writel(pin_reg, gpio_dev->base + i * 4); 896 897 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 898 } 899 } 900 901 #ifdef CONFIG_PM_SLEEP 902 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) 903 { 904 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 905 906 if (!pd) 907 return false; 908 909 /* 910 * Only restore the pin if it is actually in use by the kernel (or 911 * by userspace). 912 */ 913 if (pd->mux_owner || pd->gpio_owner || 914 gpiochip_line_is_irq(&gpio_dev->gc, pin)) 915 return true; 916 917 return false; 918 } 919 920 static int amd_gpio_suspend(struct device *dev) 921 { 922 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 923 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 924 unsigned long flags; 925 int i; 926 927 for (i = 0; i < desc->npins; i++) { 928 int pin = desc->pins[i].number; 929 930 if (!amd_gpio_should_save(gpio_dev, pin)) 931 continue; 932 933 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 934 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING; 935 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 936 } 937 938 return 0; 939 } 940 941 static int amd_gpio_resume(struct device *dev) 942 { 943 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 944 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 945 unsigned long flags; 946 int i; 947 948 for (i = 0; i < desc->npins; i++) { 949 int pin = desc->pins[i].number; 950 951 if (!amd_gpio_should_save(gpio_dev, pin)) 952 continue; 953 954 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 955 gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING; 956 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin * 4); 957 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 958 } 959 960 return 0; 961 } 962 963 static const struct dev_pm_ops amd_gpio_pm_ops = { 964 SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend, 965 amd_gpio_resume) 966 }; 967 #endif 968 969 static int amd_get_functions_count(struct pinctrl_dev *pctldev) 970 { 971 return ARRAY_SIZE(pmx_functions); 972 } 973 974 static const char *amd_get_fname(struct pinctrl_dev *pctrldev, unsigned int selector) 975 { 976 return pmx_functions[selector].name; 977 } 978 979 static int amd_get_groups(struct pinctrl_dev *pctrldev, unsigned int selector, 980 const char * const **groups, 981 unsigned int * const num_groups) 982 { 983 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev); 984 985 if (!gpio_dev->iomux_base) { 986 dev_err(&gpio_dev->pdev->dev, "iomux function %d group not supported\n", selector); 987 return -EINVAL; 988 } 989 990 *groups = pmx_functions[selector].groups; 991 *num_groups = pmx_functions[selector].ngroups; 992 return 0; 993 } 994 995 static int amd_set_mux(struct pinctrl_dev *pctrldev, unsigned int function, unsigned int group) 996 { 997 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev); 998 struct device *dev = &gpio_dev->pdev->dev; 999 struct pin_desc *pd; 1000 int ind, index; 1001 1002 if (!gpio_dev->iomux_base) 1003 return -EINVAL; 1004 1005 for (index = 0; index < NSELECTS; index++) { 1006 if (strcmp(gpio_dev->groups[group].name, pmx_functions[function].groups[index])) 1007 continue; 1008 1009 if (readb(gpio_dev->iomux_base + pmx_functions[function].index) == 1010 FUNCTION_INVALID) { 1011 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n", 1012 pmx_functions[function].index); 1013 return -EINVAL; 1014 } 1015 1016 writeb(index, gpio_dev->iomux_base + pmx_functions[function].index); 1017 1018 if (index != (readb(gpio_dev->iomux_base + pmx_functions[function].index) & 1019 FUNCTION_MASK)) { 1020 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n", 1021 pmx_functions[function].index); 1022 return -EINVAL; 1023 } 1024 1025 for (ind = 0; ind < gpio_dev->groups[group].npins; ind++) { 1026 if (strncmp(gpio_dev->groups[group].name, "IMX_F", strlen("IMX_F"))) 1027 continue; 1028 1029 pd = pin_desc_get(gpio_dev->pctrl, gpio_dev->groups[group].pins[ind]); 1030 pd->mux_owner = gpio_dev->groups[group].name; 1031 } 1032 break; 1033 } 1034 1035 return 0; 1036 } 1037 1038 static const struct pinmux_ops amd_pmxops = { 1039 .get_functions_count = amd_get_functions_count, 1040 .get_function_name = amd_get_fname, 1041 .get_function_groups = amd_get_groups, 1042 .set_mux = amd_set_mux, 1043 }; 1044 1045 static struct pinctrl_desc amd_pinctrl_desc = { 1046 .pins = kerncz_pins, 1047 .npins = ARRAY_SIZE(kerncz_pins), 1048 .pctlops = &amd_pinctrl_ops, 1049 .pmxops = &amd_pmxops, 1050 .confops = &amd_pinconf_ops, 1051 .owner = THIS_MODULE, 1052 }; 1053 1054 static void amd_get_iomux_res(struct amd_gpio *gpio_dev) 1055 { 1056 struct pinctrl_desc *desc = &amd_pinctrl_desc; 1057 struct device *dev = &gpio_dev->pdev->dev; 1058 int index; 1059 1060 index = device_property_match_string(dev, "pinctrl-resource-names", "iomux"); 1061 if (index < 0) { 1062 dev_dbg(dev, "iomux not supported\n"); 1063 goto out_no_pinmux; 1064 } 1065 1066 gpio_dev->iomux_base = devm_platform_ioremap_resource(gpio_dev->pdev, index); 1067 if (IS_ERR(gpio_dev->iomux_base)) { 1068 dev_dbg(dev, "iomux not supported %d io resource\n", index); 1069 goto out_no_pinmux; 1070 } 1071 1072 return; 1073 1074 out_no_pinmux: 1075 desc->pmxops = NULL; 1076 } 1077 1078 static int amd_gpio_probe(struct platform_device *pdev) 1079 { 1080 int ret = 0; 1081 struct resource *res; 1082 struct amd_gpio *gpio_dev; 1083 struct gpio_irq_chip *girq; 1084 1085 gpio_dev = devm_kzalloc(&pdev->dev, 1086 sizeof(struct amd_gpio), GFP_KERNEL); 1087 if (!gpio_dev) 1088 return -ENOMEM; 1089 1090 raw_spin_lock_init(&gpio_dev->lock); 1091 1092 gpio_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1093 if (IS_ERR(gpio_dev->base)) { 1094 dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); 1095 return PTR_ERR(gpio_dev->base); 1096 } 1097 1098 gpio_dev->irq = platform_get_irq(pdev, 0); 1099 if (gpio_dev->irq < 0) 1100 return gpio_dev->irq; 1101 1102 #ifdef CONFIG_PM_SLEEP 1103 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins, 1104 sizeof(*gpio_dev->saved_regs), 1105 GFP_KERNEL); 1106 if (!gpio_dev->saved_regs) 1107 return -ENOMEM; 1108 #endif 1109 1110 gpio_dev->pdev = pdev; 1111 gpio_dev->gc.get_direction = amd_gpio_get_direction; 1112 gpio_dev->gc.direction_input = amd_gpio_direction_input; 1113 gpio_dev->gc.direction_output = amd_gpio_direction_output; 1114 gpio_dev->gc.get = amd_gpio_get_value; 1115 gpio_dev->gc.set = amd_gpio_set_value; 1116 gpio_dev->gc.set_config = amd_gpio_set_config; 1117 gpio_dev->gc.dbg_show = amd_gpio_dbg_show; 1118 1119 gpio_dev->gc.base = -1; 1120 gpio_dev->gc.label = pdev->name; 1121 gpio_dev->gc.owner = THIS_MODULE; 1122 gpio_dev->gc.parent = &pdev->dev; 1123 gpio_dev->gc.ngpio = resource_size(res) / 4; 1124 1125 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64; 1126 gpio_dev->groups = kerncz_groups; 1127 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); 1128 1129 amd_pinctrl_desc.name = dev_name(&pdev->dev); 1130 amd_get_iomux_res(gpio_dev); 1131 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, 1132 gpio_dev); 1133 if (IS_ERR(gpio_dev->pctrl)) { 1134 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 1135 return PTR_ERR(gpio_dev->pctrl); 1136 } 1137 1138 /* Disable and mask interrupts */ 1139 amd_gpio_irq_init(gpio_dev); 1140 1141 girq = &gpio_dev->gc.irq; 1142 gpio_irq_chip_set_chip(girq, &amd_gpio_irqchip); 1143 /* This will let us handle the parent IRQ in the driver */ 1144 girq->parent_handler = NULL; 1145 girq->num_parents = 0; 1146 girq->parents = NULL; 1147 girq->default_type = IRQ_TYPE_NONE; 1148 girq->handler = handle_simple_irq; 1149 1150 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); 1151 if (ret) 1152 return ret; 1153 1154 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), 1155 0, 0, gpio_dev->gc.ngpio); 1156 if (ret) { 1157 dev_err(&pdev->dev, "Failed to add pin range\n"); 1158 goto out2; 1159 } 1160 1161 ret = devm_request_irq(&pdev->dev, gpio_dev->irq, amd_gpio_irq_handler, 1162 IRQF_SHARED, KBUILD_MODNAME, gpio_dev); 1163 if (ret) 1164 goto out2; 1165 1166 platform_set_drvdata(pdev, gpio_dev); 1167 acpi_register_wakeup_handler(gpio_dev->irq, amd_gpio_check_wake, gpio_dev); 1168 1169 dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); 1170 return ret; 1171 1172 out2: 1173 gpiochip_remove(&gpio_dev->gc); 1174 1175 return ret; 1176 } 1177 1178 static int amd_gpio_remove(struct platform_device *pdev) 1179 { 1180 struct amd_gpio *gpio_dev; 1181 1182 gpio_dev = platform_get_drvdata(pdev); 1183 1184 gpiochip_remove(&gpio_dev->gc); 1185 acpi_unregister_wakeup_handler(amd_gpio_check_wake, gpio_dev); 1186 1187 return 0; 1188 } 1189 1190 #ifdef CONFIG_ACPI 1191 static const struct acpi_device_id amd_gpio_acpi_match[] = { 1192 { "AMD0030", 0 }, 1193 { "AMDI0030", 0}, 1194 { "AMDI0031", 0}, 1195 { }, 1196 }; 1197 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); 1198 #endif 1199 1200 static struct platform_driver amd_gpio_driver = { 1201 .driver = { 1202 .name = "amd_gpio", 1203 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), 1204 #ifdef CONFIG_PM_SLEEP 1205 .pm = &amd_gpio_pm_ops, 1206 #endif 1207 }, 1208 .probe = amd_gpio_probe, 1209 .remove = amd_gpio_remove, 1210 }; 1211 1212 module_platform_driver(amd_gpio_driver); 1213 1214 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); 1215 MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); 1216