1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPIO driver for AMD 4 * 5 * Copyright (c) 2014,2015 AMD Corporation. 6 * Authors: Ken Xue <Ken.Xue@amd.com> 7 * Wu, Jeff <Jeff.Wu@amd.com> 8 * 9 */ 10 11 #include <linux/err.h> 12 #include <linux/bug.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/spinlock.h> 16 #include <linux/compiler.h> 17 #include <linux/types.h> 18 #include <linux/errno.h> 19 #include <linux/log2.h> 20 #include <linux/io.h> 21 #include <linux/gpio/driver.h> 22 #include <linux/slab.h> 23 #include <linux/platform_device.h> 24 #include <linux/mutex.h> 25 #include <linux/acpi.h> 26 #include <linux/seq_file.h> 27 #include <linux/interrupt.h> 28 #include <linux/list.h> 29 #include <linux/bitops.h> 30 #include <linux/pinctrl/pinconf.h> 31 #include <linux/pinctrl/pinconf-generic.h> 32 #include <linux/pinctrl/pinmux.h> 33 34 #include "core.h" 35 #include "pinctrl-utils.h" 36 #include "pinctrl-amd.h" 37 38 static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset) 39 { 40 unsigned long flags; 41 u32 pin_reg; 42 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 43 44 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 45 pin_reg = readl(gpio_dev->base + offset * 4); 46 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 47 48 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) 49 return GPIO_LINE_DIRECTION_OUT; 50 51 return GPIO_LINE_DIRECTION_IN; 52 } 53 54 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 55 { 56 unsigned long flags; 57 u32 pin_reg; 58 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 59 60 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 61 pin_reg = readl(gpio_dev->base + offset * 4); 62 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); 63 writel(pin_reg, gpio_dev->base + offset * 4); 64 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 65 66 return 0; 67 } 68 69 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 70 int value) 71 { 72 u32 pin_reg; 73 unsigned long flags; 74 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 75 76 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 77 pin_reg = readl(gpio_dev->base + offset * 4); 78 pin_reg |= BIT(OUTPUT_ENABLE_OFF); 79 if (value) 80 pin_reg |= BIT(OUTPUT_VALUE_OFF); 81 else 82 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 83 writel(pin_reg, gpio_dev->base + offset * 4); 84 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 85 86 return 0; 87 } 88 89 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) 90 { 91 u32 pin_reg; 92 unsigned long flags; 93 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 94 95 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 96 pin_reg = readl(gpio_dev->base + offset * 4); 97 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 98 99 return !!(pin_reg & BIT(PIN_STS_OFF)); 100 } 101 102 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) 103 { 104 u32 pin_reg; 105 unsigned long flags; 106 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 107 108 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 109 pin_reg = readl(gpio_dev->base + offset * 4); 110 if (value) 111 pin_reg |= BIT(OUTPUT_VALUE_OFF); 112 else 113 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 114 writel(pin_reg, gpio_dev->base + offset * 4); 115 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 116 } 117 118 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, 119 unsigned debounce) 120 { 121 u32 time; 122 u32 pin_reg; 123 int ret = 0; 124 unsigned long flags; 125 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 126 127 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 128 pin_reg = readl(gpio_dev->base + offset * 4); 129 130 if (debounce) { 131 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 132 pin_reg &= ~DB_TMR_OUT_MASK; 133 /* 134 Debounce Debounce Timer Max 135 TmrLarge TmrOutUnit Unit Debounce 136 Time 137 0 0 61 usec (2 RtcClk) 976 usec 138 0 1 244 usec (8 RtcClk) 3.9 msec 139 1 0 15.6 msec (512 RtcClk) 250 msec 140 1 1 62.5 msec (2048 RtcClk) 1 sec 141 */ 142 143 if (debounce < 61) { 144 pin_reg |= 1; 145 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 146 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 147 } else if (debounce < 976) { 148 time = debounce / 61; 149 pin_reg |= time & DB_TMR_OUT_MASK; 150 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 151 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 152 } else if (debounce < 3900) { 153 time = debounce / 244; 154 pin_reg |= time & DB_TMR_OUT_MASK; 155 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 156 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 157 } else if (debounce < 250000) { 158 time = debounce / 15625; 159 pin_reg |= time & DB_TMR_OUT_MASK; 160 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 161 pin_reg |= BIT(DB_TMR_LARGE_OFF); 162 } else if (debounce < 1000000) { 163 time = debounce / 62500; 164 pin_reg |= time & DB_TMR_OUT_MASK; 165 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 166 pin_reg |= BIT(DB_TMR_LARGE_OFF); 167 } else { 168 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 169 ret = -EINVAL; 170 } 171 } else { 172 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 173 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 174 pin_reg &= ~DB_TMR_OUT_MASK; 175 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 176 } 177 writel(pin_reg, gpio_dev->base + offset * 4); 178 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 179 180 return ret; 181 } 182 183 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset, 184 unsigned long config) 185 { 186 u32 debounce; 187 188 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 189 return -ENOTSUPP; 190 191 debounce = pinconf_to_config_argument(config); 192 return amd_gpio_set_debounce(gc, offset, debounce); 193 } 194 195 #ifdef CONFIG_DEBUG_FS 196 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) 197 { 198 u32 pin_reg; 199 u32 db_cntrl; 200 unsigned long flags; 201 unsigned int bank, i, pin_num; 202 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 203 204 bool tmr_out_unit; 205 bool tmr_large; 206 207 char *level_trig; 208 char *active_level; 209 char *interrupt_enable; 210 char *interrupt_mask; 211 char *wake_cntrl0; 212 char *wake_cntrl1; 213 char *wake_cntrl2; 214 char *pin_sts; 215 char *pull_up_sel; 216 char *pull_up_enable; 217 char *pull_down_enable; 218 char *orientation; 219 char debounce_value[40]; 220 char *debounce_enable; 221 char *wake_cntrlz; 222 223 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { 224 unsigned int time = 0; 225 unsigned int unit = 0; 226 227 switch (bank) { 228 case 0: 229 i = 0; 230 pin_num = AMD_GPIO_PINS_BANK0; 231 break; 232 case 1: 233 i = 64; 234 pin_num = AMD_GPIO_PINS_BANK1 + i; 235 break; 236 case 2: 237 i = 128; 238 pin_num = AMD_GPIO_PINS_BANK2 + i; 239 break; 240 case 3: 241 i = 192; 242 pin_num = AMD_GPIO_PINS_BANK3 + i; 243 break; 244 default: 245 /* Illegal bank number, ignore */ 246 continue; 247 } 248 seq_printf(s, "GPIO bank%d\n", bank); 249 for (; i < pin_num; i++) { 250 seq_printf(s, "#%d\t", i); 251 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 252 pin_reg = readl(gpio_dev->base + i * 4); 253 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 254 255 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { 256 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) & 257 ACTIVE_LEVEL_MASK; 258 interrupt_enable = "+"; 259 260 if (level == ACTIVE_LEVEL_HIGH) 261 active_level = "↑"; 262 else if (level == ACTIVE_LEVEL_LOW) 263 active_level = "↓"; 264 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) && 265 level == ACTIVE_LEVEL_BOTH) 266 active_level = "b"; 267 else 268 active_level = "?"; 269 270 if (pin_reg & BIT(LEVEL_TRIG_OFF)) 271 level_trig = "level"; 272 else 273 level_trig = " edge"; 274 275 } else { 276 interrupt_enable = "∅"; 277 active_level = "∅"; 278 level_trig = " ∅"; 279 } 280 281 if (pin_reg & BIT(INTERRUPT_MASK_OFF)) 282 interrupt_mask = "��"; 283 else 284 interrupt_mask = "��"; 285 seq_printf(s, "int %s (%s)| active-%s| %s-⚡| ", 286 interrupt_enable, 287 interrupt_mask, 288 active_level, 289 level_trig); 290 291 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) 292 wake_cntrl0 = "⏰"; 293 else 294 wake_cntrl0 = " ∅"; 295 seq_printf(s, "S0i3 %s| ", wake_cntrl0); 296 297 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) 298 wake_cntrl1 = "⏰"; 299 else 300 wake_cntrl1 = " ∅"; 301 seq_printf(s, "S3 %s| ", wake_cntrl1); 302 303 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) 304 wake_cntrl2 = "⏰"; 305 else 306 wake_cntrl2 = " ∅"; 307 seq_printf(s, "S4/S5 %s| ", wake_cntrl2); 308 309 if (pin_reg & BIT(WAKECNTRL_Z_OFF)) 310 wake_cntrlz = "⏰"; 311 else 312 wake_cntrlz = " ∅"; 313 seq_printf(s, "Z %s| ", wake_cntrlz); 314 315 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { 316 pull_up_enable = "+"; 317 if (pin_reg & BIT(PULL_UP_SEL_OFF)) 318 pull_up_sel = "8k"; 319 else 320 pull_up_sel = "4k"; 321 } else { 322 pull_up_enable = "∅"; 323 pull_up_sel = " "; 324 } 325 seq_printf(s, "pull-↑ %s (%s)| ", 326 pull_up_enable, 327 pull_up_sel); 328 329 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) 330 pull_down_enable = "+"; 331 else 332 pull_down_enable = "∅"; 333 seq_printf(s, "pull-↓ %s| ", pull_down_enable); 334 335 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { 336 pin_sts = "output"; 337 if (pin_reg & BIT(OUTPUT_VALUE_OFF)) 338 orientation = "↑"; 339 else 340 orientation = "↓"; 341 } else { 342 pin_sts = "input "; 343 if (pin_reg & BIT(PIN_STS_OFF)) 344 orientation = "↑"; 345 else 346 orientation = "↓"; 347 } 348 seq_printf(s, "%s %s| ", pin_sts, orientation); 349 350 db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg; 351 if (db_cntrl) { 352 tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF); 353 tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF); 354 time = pin_reg & DB_TMR_OUT_MASK; 355 if (tmr_large) { 356 if (tmr_out_unit) 357 unit = 62500; 358 else 359 unit = 15625; 360 } else { 361 if (tmr_out_unit) 362 unit = 244; 363 else 364 unit = 61; 365 } 366 if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl) 367 debounce_enable = "b +"; 368 else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl) 369 debounce_enable = "↓ +"; 370 else 371 debounce_enable = "↑ +"; 372 373 } else { 374 debounce_enable = " ∅"; 375 time = 0; 376 } 377 snprintf(debounce_value, sizeof(debounce_value), "%u", time * unit); 378 seq_printf(s, "debounce %s (�� %sus)| ", debounce_enable, debounce_value); 379 seq_printf(s, " 0x%x\n", pin_reg); 380 } 381 } 382 } 383 #else 384 #define amd_gpio_dbg_show NULL 385 #endif 386 387 static void amd_gpio_irq_enable(struct irq_data *d) 388 { 389 u32 pin_reg; 390 unsigned long flags; 391 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 392 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 393 394 gpiochip_enable_irq(gc, d->hwirq); 395 396 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 397 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 398 pin_reg |= BIT(INTERRUPT_ENABLE_OFF); 399 pin_reg |= BIT(INTERRUPT_MASK_OFF); 400 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 401 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 402 } 403 404 static void amd_gpio_irq_disable(struct irq_data *d) 405 { 406 u32 pin_reg; 407 unsigned long flags; 408 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 409 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 410 411 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 412 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 413 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); 414 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 415 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 416 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 417 418 gpiochip_disable_irq(gc, d->hwirq); 419 } 420 421 static void amd_gpio_irq_mask(struct irq_data *d) 422 { 423 u32 pin_reg; 424 unsigned long flags; 425 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 426 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 427 428 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 429 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 430 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 431 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 432 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 433 } 434 435 static void amd_gpio_irq_unmask(struct irq_data *d) 436 { 437 u32 pin_reg; 438 unsigned long flags; 439 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 440 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 441 442 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 443 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 444 pin_reg |= BIT(INTERRUPT_MASK_OFF); 445 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 446 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 447 } 448 449 static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 450 { 451 u32 pin_reg; 452 unsigned long flags; 453 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 454 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 455 u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3); 456 int err; 457 458 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 459 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 460 461 if (on) 462 pin_reg |= wake_mask; 463 else 464 pin_reg &= ~wake_mask; 465 466 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 467 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 468 469 if (on) 470 err = enable_irq_wake(gpio_dev->irq); 471 else 472 err = disable_irq_wake(gpio_dev->irq); 473 474 if (err) 475 dev_err(&gpio_dev->pdev->dev, "failed to %s wake-up interrupt\n", 476 on ? "enable" : "disable"); 477 478 return 0; 479 } 480 481 static void amd_gpio_irq_eoi(struct irq_data *d) 482 { 483 u32 reg; 484 unsigned long flags; 485 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 486 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 487 488 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 489 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 490 reg |= EOI_MASK; 491 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 492 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 493 } 494 495 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) 496 { 497 int ret = 0; 498 u32 pin_reg, pin_reg_irq_en, mask; 499 unsigned long flags; 500 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 501 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 502 503 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 504 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 505 506 switch (type & IRQ_TYPE_SENSE_MASK) { 507 case IRQ_TYPE_EDGE_RISING: 508 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 509 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 510 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 511 irq_set_handler_locked(d, handle_edge_irq); 512 break; 513 514 case IRQ_TYPE_EDGE_FALLING: 515 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 516 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 517 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 518 irq_set_handler_locked(d, handle_edge_irq); 519 break; 520 521 case IRQ_TYPE_EDGE_BOTH: 522 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 523 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 524 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; 525 irq_set_handler_locked(d, handle_edge_irq); 526 break; 527 528 case IRQ_TYPE_LEVEL_HIGH: 529 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 530 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 531 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 532 irq_set_handler_locked(d, handle_level_irq); 533 break; 534 535 case IRQ_TYPE_LEVEL_LOW: 536 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 537 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 538 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 539 irq_set_handler_locked(d, handle_level_irq); 540 break; 541 542 case IRQ_TYPE_NONE: 543 break; 544 545 default: 546 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); 547 ret = -EINVAL; 548 } 549 550 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; 551 /* 552 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the 553 * debounce registers of any GPIO will block wake/interrupt status 554 * generation for *all* GPIOs for a length of time that depends on 555 * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the 556 * INTERRUPT_ENABLE bit will read as 0. 557 * 558 * We temporarily enable irq for the GPIO whose configuration is 559 * changing, and then wait for it to read back as 1 to know when 560 * debounce has settled and then disable the irq again. 561 * We do this polling with the spinlock held to ensure other GPIO 562 * access routines do not read an incorrect value for the irq enable 563 * bit of other GPIOs. We keep the GPIO masked while polling to avoid 564 * spurious irqs, and disable the irq again after polling. 565 */ 566 mask = BIT(INTERRUPT_ENABLE_OFF); 567 pin_reg_irq_en = pin_reg; 568 pin_reg_irq_en |= mask; 569 pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF); 570 writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4); 571 while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask) 572 continue; 573 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 574 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 575 576 return ret; 577 } 578 579 static void amd_irq_ack(struct irq_data *d) 580 { 581 /* 582 * based on HW design,there is no need to ack HW 583 * before handle current irq. But this routine is 584 * necessary for handle_edge_irq 585 */ 586 } 587 588 static const struct irq_chip amd_gpio_irqchip = { 589 .name = "amd_gpio", 590 .irq_ack = amd_irq_ack, 591 .irq_enable = amd_gpio_irq_enable, 592 .irq_disable = amd_gpio_irq_disable, 593 .irq_mask = amd_gpio_irq_mask, 594 .irq_unmask = amd_gpio_irq_unmask, 595 .irq_set_wake = amd_gpio_irq_set_wake, 596 .irq_eoi = amd_gpio_irq_eoi, 597 .irq_set_type = amd_gpio_irq_set_type, 598 /* 599 * We need to set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND so that a wake event 600 * also generates an IRQ. We need the IRQ so the irq_handler can clear 601 * the wake event. Otherwise the wake event will never clear and 602 * prevent the system from suspending. 603 */ 604 .flags = IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND | IRQCHIP_IMMUTABLE, 605 GPIOCHIP_IRQ_RESOURCE_HELPERS, 606 }; 607 608 #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF)) 609 610 static bool do_amd_gpio_irq_handler(int irq, void *dev_id) 611 { 612 struct amd_gpio *gpio_dev = dev_id; 613 struct gpio_chip *gc = &gpio_dev->gc; 614 unsigned int i, irqnr; 615 unsigned long flags; 616 u32 __iomem *regs; 617 bool ret = false; 618 u32 regval; 619 u64 status, mask; 620 621 /* Read the wake status */ 622 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 623 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); 624 status <<= 32; 625 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0); 626 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 627 628 /* Bit 0-45 contain the relevant status bits */ 629 status &= (1ULL << 46) - 1; 630 regs = gpio_dev->base; 631 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) { 632 if (!(status & mask)) 633 continue; 634 status &= ~mask; 635 636 /* Each status bit covers four pins */ 637 for (i = 0; i < 4; i++) { 638 regval = readl(regs + i); 639 640 if (regval & PIN_IRQ_PENDING) 641 dev_dbg(&gpio_dev->pdev->dev, 642 "GPIO %d is active: 0x%x", 643 irqnr + i, regval); 644 645 /* caused wake on resume context for shared IRQ */ 646 if (irq < 0 && (regval & BIT(WAKE_STS_OFF))) 647 return true; 648 649 if (!(regval & PIN_IRQ_PENDING) || 650 !(regval & BIT(INTERRUPT_MASK_OFF))) 651 continue; 652 generic_handle_domain_irq_safe(gc->irq.domain, irqnr + i); 653 654 /* Clear interrupt. 655 * We must read the pin register again, in case the 656 * value was changed while executing 657 * generic_handle_domain_irq() above. 658 * If we didn't find a mapping for the interrupt, 659 * disable it in order to avoid a system hang caused 660 * by an interrupt storm. 661 */ 662 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 663 regval = readl(regs + i); 664 if (irq == 0) { 665 regval &= ~BIT(INTERRUPT_ENABLE_OFF); 666 dev_dbg(&gpio_dev->pdev->dev, 667 "Disabling spurious GPIO IRQ %d\n", 668 irqnr + i); 669 } 670 writel(regval, regs + i); 671 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 672 ret = true; 673 } 674 } 675 /* did not cause wake on resume context for shared IRQ */ 676 if (irq < 0) 677 return false; 678 679 /* Signal EOI to the GPIO unit */ 680 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 681 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 682 regval |= EOI_MASK; 683 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG); 684 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 685 686 return ret; 687 } 688 689 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id) 690 { 691 return IRQ_RETVAL(do_amd_gpio_irq_handler(irq, dev_id)); 692 } 693 694 static bool __maybe_unused amd_gpio_check_wake(void *dev_id) 695 { 696 return do_amd_gpio_irq_handler(-1, dev_id); 697 } 698 699 static int amd_get_groups_count(struct pinctrl_dev *pctldev) 700 { 701 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 702 703 return gpio_dev->ngroups; 704 } 705 706 static const char *amd_get_group_name(struct pinctrl_dev *pctldev, 707 unsigned group) 708 { 709 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 710 711 return gpio_dev->groups[group].name; 712 } 713 714 static int amd_get_group_pins(struct pinctrl_dev *pctldev, 715 unsigned group, 716 const unsigned **pins, 717 unsigned *num_pins) 718 { 719 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 720 721 *pins = gpio_dev->groups[group].pins; 722 *num_pins = gpio_dev->groups[group].npins; 723 return 0; 724 } 725 726 static const struct pinctrl_ops amd_pinctrl_ops = { 727 .get_groups_count = amd_get_groups_count, 728 .get_group_name = amd_get_group_name, 729 .get_group_pins = amd_get_group_pins, 730 #ifdef CONFIG_OF 731 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 732 .dt_free_map = pinctrl_utils_free_map, 733 #endif 734 }; 735 736 static int amd_pinconf_get(struct pinctrl_dev *pctldev, 737 unsigned int pin, 738 unsigned long *config) 739 { 740 u32 pin_reg; 741 unsigned arg; 742 unsigned long flags; 743 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 744 enum pin_config_param param = pinconf_to_config_param(*config); 745 746 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 747 pin_reg = readl(gpio_dev->base + pin*4); 748 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 749 switch (param) { 750 case PIN_CONFIG_INPUT_DEBOUNCE: 751 arg = pin_reg & DB_TMR_OUT_MASK; 752 break; 753 754 case PIN_CONFIG_BIAS_PULL_DOWN: 755 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); 756 break; 757 758 case PIN_CONFIG_BIAS_PULL_UP: 759 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); 760 break; 761 762 case PIN_CONFIG_DRIVE_STRENGTH: 763 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; 764 break; 765 766 default: 767 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n", 768 param); 769 return -ENOTSUPP; 770 } 771 772 *config = pinconf_to_config_packed(param, arg); 773 774 return 0; 775 } 776 777 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 778 unsigned long *configs, unsigned num_configs) 779 { 780 int i; 781 u32 arg; 782 int ret = 0; 783 u32 pin_reg; 784 unsigned long flags; 785 enum pin_config_param param; 786 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 787 788 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 789 for (i = 0; i < num_configs; i++) { 790 param = pinconf_to_config_param(configs[i]); 791 arg = pinconf_to_config_argument(configs[i]); 792 pin_reg = readl(gpio_dev->base + pin*4); 793 794 switch (param) { 795 case PIN_CONFIG_INPUT_DEBOUNCE: 796 pin_reg &= ~DB_TMR_OUT_MASK; 797 pin_reg |= arg & DB_TMR_OUT_MASK; 798 break; 799 800 case PIN_CONFIG_BIAS_PULL_DOWN: 801 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); 802 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; 803 break; 804 805 case PIN_CONFIG_BIAS_PULL_UP: 806 pin_reg &= ~BIT(PULL_UP_SEL_OFF); 807 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; 808 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); 809 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; 810 break; 811 812 case PIN_CONFIG_DRIVE_STRENGTH: 813 pin_reg &= ~(DRV_STRENGTH_SEL_MASK 814 << DRV_STRENGTH_SEL_OFF); 815 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) 816 << DRV_STRENGTH_SEL_OFF; 817 break; 818 819 default: 820 dev_err(&gpio_dev->pdev->dev, 821 "Invalid config param %04x\n", param); 822 ret = -ENOTSUPP; 823 } 824 825 writel(pin_reg, gpio_dev->base + pin*4); 826 } 827 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 828 829 return ret; 830 } 831 832 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, 833 unsigned int group, 834 unsigned long *config) 835 { 836 const unsigned *pins; 837 unsigned npins; 838 int ret; 839 840 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 841 if (ret) 842 return ret; 843 844 if (amd_pinconf_get(pctldev, pins[0], config)) 845 return -ENOTSUPP; 846 847 return 0; 848 } 849 850 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, 851 unsigned group, unsigned long *configs, 852 unsigned num_configs) 853 { 854 const unsigned *pins; 855 unsigned npins; 856 int i, ret; 857 858 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 859 if (ret) 860 return ret; 861 for (i = 0; i < npins; i++) { 862 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) 863 return -ENOTSUPP; 864 } 865 return 0; 866 } 867 868 static const struct pinconf_ops amd_pinconf_ops = { 869 .pin_config_get = amd_pinconf_get, 870 .pin_config_set = amd_pinconf_set, 871 .pin_config_group_get = amd_pinconf_group_get, 872 .pin_config_group_set = amd_pinconf_group_set, 873 }; 874 875 static void amd_gpio_irq_init_pin(struct amd_gpio *gpio_dev, int pin) 876 { 877 const struct pin_desc *pd; 878 unsigned long flags; 879 u32 pin_reg, mask; 880 881 mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) | 882 BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) | 883 BIT(WAKE_CNTRL_OFF_S4); 884 885 pd = pin_desc_get(gpio_dev->pctrl, pin); 886 if (!pd) 887 return; 888 889 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 890 pin_reg = readl(gpio_dev->base + pin * 4); 891 pin_reg &= ~mask; 892 writel(pin_reg, gpio_dev->base + pin * 4); 893 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 894 } 895 896 static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) 897 { 898 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 899 int i; 900 901 for (i = 0; i < desc->npins; i++) 902 amd_gpio_irq_init_pin(gpio_dev, i); 903 } 904 905 #ifdef CONFIG_PM_SLEEP 906 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) 907 { 908 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 909 910 if (!pd) 911 return false; 912 913 /* 914 * Only restore the pin if it is actually in use by the kernel (or 915 * by userspace). 916 */ 917 if (pd->mux_owner || pd->gpio_owner || 918 gpiochip_line_is_irq(&gpio_dev->gc, pin)) 919 return true; 920 921 return false; 922 } 923 924 static int amd_gpio_suspend(struct device *dev) 925 { 926 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 927 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 928 unsigned long flags; 929 int i; 930 931 for (i = 0; i < desc->npins; i++) { 932 int pin = desc->pins[i].number; 933 934 if (!amd_gpio_should_save(gpio_dev, pin)) 935 continue; 936 937 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 938 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING; 939 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 940 } 941 942 return 0; 943 } 944 945 static int amd_gpio_resume(struct device *dev) 946 { 947 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 948 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 949 unsigned long flags; 950 int i; 951 952 for (i = 0; i < desc->npins; i++) { 953 int pin = desc->pins[i].number; 954 955 if (!amd_gpio_should_save(gpio_dev, pin)) { 956 amd_gpio_irq_init_pin(gpio_dev, pin); 957 continue; 958 } 959 960 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 961 gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING; 962 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin * 4); 963 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 964 } 965 966 return 0; 967 } 968 969 static const struct dev_pm_ops amd_gpio_pm_ops = { 970 SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend, 971 amd_gpio_resume) 972 }; 973 #endif 974 975 static int amd_get_functions_count(struct pinctrl_dev *pctldev) 976 { 977 return ARRAY_SIZE(pmx_functions); 978 } 979 980 static const char *amd_get_fname(struct pinctrl_dev *pctrldev, unsigned int selector) 981 { 982 return pmx_functions[selector].name; 983 } 984 985 static int amd_get_groups(struct pinctrl_dev *pctrldev, unsigned int selector, 986 const char * const **groups, 987 unsigned int * const num_groups) 988 { 989 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev); 990 991 if (!gpio_dev->iomux_base) { 992 dev_err(&gpio_dev->pdev->dev, "iomux function %d group not supported\n", selector); 993 return -EINVAL; 994 } 995 996 *groups = pmx_functions[selector].groups; 997 *num_groups = pmx_functions[selector].ngroups; 998 return 0; 999 } 1000 1001 static int amd_set_mux(struct pinctrl_dev *pctrldev, unsigned int function, unsigned int group) 1002 { 1003 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev); 1004 struct device *dev = &gpio_dev->pdev->dev; 1005 struct pin_desc *pd; 1006 int ind, index; 1007 1008 if (!gpio_dev->iomux_base) 1009 return -EINVAL; 1010 1011 for (index = 0; index < NSELECTS; index++) { 1012 if (strcmp(gpio_dev->groups[group].name, pmx_functions[function].groups[index])) 1013 continue; 1014 1015 if (readb(gpio_dev->iomux_base + pmx_functions[function].index) == 1016 FUNCTION_INVALID) { 1017 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n", 1018 pmx_functions[function].index); 1019 return -EINVAL; 1020 } 1021 1022 writeb(index, gpio_dev->iomux_base + pmx_functions[function].index); 1023 1024 if (index != (readb(gpio_dev->iomux_base + pmx_functions[function].index) & 1025 FUNCTION_MASK)) { 1026 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n", 1027 pmx_functions[function].index); 1028 return -EINVAL; 1029 } 1030 1031 for (ind = 0; ind < gpio_dev->groups[group].npins; ind++) { 1032 if (strncmp(gpio_dev->groups[group].name, "IMX_F", strlen("IMX_F"))) 1033 continue; 1034 1035 pd = pin_desc_get(gpio_dev->pctrl, gpio_dev->groups[group].pins[ind]); 1036 pd->mux_owner = gpio_dev->groups[group].name; 1037 } 1038 break; 1039 } 1040 1041 return 0; 1042 } 1043 1044 static const struct pinmux_ops amd_pmxops = { 1045 .get_functions_count = amd_get_functions_count, 1046 .get_function_name = amd_get_fname, 1047 .get_function_groups = amd_get_groups, 1048 .set_mux = amd_set_mux, 1049 }; 1050 1051 static struct pinctrl_desc amd_pinctrl_desc = { 1052 .pins = kerncz_pins, 1053 .npins = ARRAY_SIZE(kerncz_pins), 1054 .pctlops = &amd_pinctrl_ops, 1055 .pmxops = &amd_pmxops, 1056 .confops = &amd_pinconf_ops, 1057 .owner = THIS_MODULE, 1058 }; 1059 1060 static void amd_get_iomux_res(struct amd_gpio *gpio_dev) 1061 { 1062 struct pinctrl_desc *desc = &amd_pinctrl_desc; 1063 struct device *dev = &gpio_dev->pdev->dev; 1064 int index; 1065 1066 index = device_property_match_string(dev, "pinctrl-resource-names", "iomux"); 1067 if (index < 0) { 1068 dev_dbg(dev, "iomux not supported\n"); 1069 goto out_no_pinmux; 1070 } 1071 1072 gpio_dev->iomux_base = devm_platform_ioremap_resource(gpio_dev->pdev, index); 1073 if (IS_ERR(gpio_dev->iomux_base)) { 1074 dev_dbg(dev, "iomux not supported %d io resource\n", index); 1075 goto out_no_pinmux; 1076 } 1077 1078 return; 1079 1080 out_no_pinmux: 1081 desc->pmxops = NULL; 1082 } 1083 1084 static int amd_gpio_probe(struct platform_device *pdev) 1085 { 1086 int ret = 0; 1087 struct resource *res; 1088 struct amd_gpio *gpio_dev; 1089 struct gpio_irq_chip *girq; 1090 1091 gpio_dev = devm_kzalloc(&pdev->dev, 1092 sizeof(struct amd_gpio), GFP_KERNEL); 1093 if (!gpio_dev) 1094 return -ENOMEM; 1095 1096 raw_spin_lock_init(&gpio_dev->lock); 1097 1098 gpio_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1099 if (IS_ERR(gpio_dev->base)) { 1100 dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); 1101 return PTR_ERR(gpio_dev->base); 1102 } 1103 1104 gpio_dev->irq = platform_get_irq(pdev, 0); 1105 if (gpio_dev->irq < 0) 1106 return gpio_dev->irq; 1107 1108 #ifdef CONFIG_PM_SLEEP 1109 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins, 1110 sizeof(*gpio_dev->saved_regs), 1111 GFP_KERNEL); 1112 if (!gpio_dev->saved_regs) 1113 return -ENOMEM; 1114 #endif 1115 1116 gpio_dev->pdev = pdev; 1117 gpio_dev->gc.get_direction = amd_gpio_get_direction; 1118 gpio_dev->gc.direction_input = amd_gpio_direction_input; 1119 gpio_dev->gc.direction_output = amd_gpio_direction_output; 1120 gpio_dev->gc.get = amd_gpio_get_value; 1121 gpio_dev->gc.set = amd_gpio_set_value; 1122 gpio_dev->gc.set_config = amd_gpio_set_config; 1123 gpio_dev->gc.dbg_show = amd_gpio_dbg_show; 1124 1125 gpio_dev->gc.base = -1; 1126 gpio_dev->gc.label = pdev->name; 1127 gpio_dev->gc.owner = THIS_MODULE; 1128 gpio_dev->gc.parent = &pdev->dev; 1129 gpio_dev->gc.ngpio = resource_size(res) / 4; 1130 1131 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64; 1132 gpio_dev->groups = kerncz_groups; 1133 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); 1134 1135 amd_pinctrl_desc.name = dev_name(&pdev->dev); 1136 amd_get_iomux_res(gpio_dev); 1137 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, 1138 gpio_dev); 1139 if (IS_ERR(gpio_dev->pctrl)) { 1140 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 1141 return PTR_ERR(gpio_dev->pctrl); 1142 } 1143 1144 /* Disable and mask interrupts */ 1145 amd_gpio_irq_init(gpio_dev); 1146 1147 girq = &gpio_dev->gc.irq; 1148 gpio_irq_chip_set_chip(girq, &amd_gpio_irqchip); 1149 /* This will let us handle the parent IRQ in the driver */ 1150 girq->parent_handler = NULL; 1151 girq->num_parents = 0; 1152 girq->parents = NULL; 1153 girq->default_type = IRQ_TYPE_NONE; 1154 girq->handler = handle_simple_irq; 1155 1156 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); 1157 if (ret) 1158 return ret; 1159 1160 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), 1161 0, 0, gpio_dev->gc.ngpio); 1162 if (ret) { 1163 dev_err(&pdev->dev, "Failed to add pin range\n"); 1164 goto out2; 1165 } 1166 1167 ret = devm_request_irq(&pdev->dev, gpio_dev->irq, amd_gpio_irq_handler, 1168 IRQF_SHARED, KBUILD_MODNAME, gpio_dev); 1169 if (ret) 1170 goto out2; 1171 1172 platform_set_drvdata(pdev, gpio_dev); 1173 acpi_register_wakeup_handler(gpio_dev->irq, amd_gpio_check_wake, gpio_dev); 1174 1175 dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); 1176 return ret; 1177 1178 out2: 1179 gpiochip_remove(&gpio_dev->gc); 1180 1181 return ret; 1182 } 1183 1184 static int amd_gpio_remove(struct platform_device *pdev) 1185 { 1186 struct amd_gpio *gpio_dev; 1187 1188 gpio_dev = platform_get_drvdata(pdev); 1189 1190 gpiochip_remove(&gpio_dev->gc); 1191 acpi_unregister_wakeup_handler(amd_gpio_check_wake, gpio_dev); 1192 1193 return 0; 1194 } 1195 1196 #ifdef CONFIG_ACPI 1197 static const struct acpi_device_id amd_gpio_acpi_match[] = { 1198 { "AMD0030", 0 }, 1199 { "AMDI0030", 0}, 1200 { "AMDI0031", 0}, 1201 { }, 1202 }; 1203 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); 1204 #endif 1205 1206 static struct platform_driver amd_gpio_driver = { 1207 .driver = { 1208 .name = "amd_gpio", 1209 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), 1210 #ifdef CONFIG_PM_SLEEP 1211 .pm = &amd_gpio_pm_ops, 1212 #endif 1213 }, 1214 .probe = amd_gpio_probe, 1215 .remove = amd_gpio_remove, 1216 }; 1217 1218 module_platform_driver(amd_gpio_driver); 1219 1220 MODULE_LICENSE("GPL v2"); 1221 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); 1222 MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); 1223