1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPIO driver for AMD 4 * 5 * Copyright (c) 2014,2015 AMD Corporation. 6 * Authors: Ken Xue <Ken.Xue@amd.com> 7 * Wu, Jeff <Jeff.Wu@amd.com> 8 * 9 */ 10 11 #include <linux/err.h> 12 #include <linux/bug.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/spinlock.h> 16 #include <linux/compiler.h> 17 #include <linux/types.h> 18 #include <linux/errno.h> 19 #include <linux/log2.h> 20 #include <linux/io.h> 21 #include <linux/gpio/driver.h> 22 #include <linux/slab.h> 23 #include <linux/platform_device.h> 24 #include <linux/mutex.h> 25 #include <linux/acpi.h> 26 #include <linux/seq_file.h> 27 #include <linux/interrupt.h> 28 #include <linux/list.h> 29 #include <linux/bitops.h> 30 #include <linux/pinctrl/pinconf.h> 31 #include <linux/pinctrl/pinconf-generic.h> 32 #include <linux/pinctrl/pinmux.h> 33 34 #include "core.h" 35 #include "pinctrl-utils.h" 36 #include "pinctrl-amd.h" 37 38 static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset) 39 { 40 unsigned long flags; 41 u32 pin_reg; 42 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 43 44 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 45 pin_reg = readl(gpio_dev->base + offset * 4); 46 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 47 48 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) 49 return GPIO_LINE_DIRECTION_OUT; 50 51 return GPIO_LINE_DIRECTION_IN; 52 } 53 54 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 55 { 56 unsigned long flags; 57 u32 pin_reg; 58 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 59 60 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 61 pin_reg = readl(gpio_dev->base + offset * 4); 62 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); 63 writel(pin_reg, gpio_dev->base + offset * 4); 64 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 65 66 return 0; 67 } 68 69 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 70 int value) 71 { 72 u32 pin_reg; 73 unsigned long flags; 74 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 75 76 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 77 pin_reg = readl(gpio_dev->base + offset * 4); 78 pin_reg |= BIT(OUTPUT_ENABLE_OFF); 79 if (value) 80 pin_reg |= BIT(OUTPUT_VALUE_OFF); 81 else 82 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 83 writel(pin_reg, gpio_dev->base + offset * 4); 84 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 85 86 return 0; 87 } 88 89 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) 90 { 91 u32 pin_reg; 92 unsigned long flags; 93 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 94 95 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 96 pin_reg = readl(gpio_dev->base + offset * 4); 97 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 98 99 return !!(pin_reg & BIT(PIN_STS_OFF)); 100 } 101 102 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) 103 { 104 u32 pin_reg; 105 unsigned long flags; 106 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 107 108 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 109 pin_reg = readl(gpio_dev->base + offset * 4); 110 if (value) 111 pin_reg |= BIT(OUTPUT_VALUE_OFF); 112 else 113 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 114 writel(pin_reg, gpio_dev->base + offset * 4); 115 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 116 } 117 118 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, 119 unsigned debounce) 120 { 121 u32 time; 122 u32 pin_reg; 123 int ret = 0; 124 unsigned long flags; 125 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 126 127 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 128 pin_reg = readl(gpio_dev->base + offset * 4); 129 130 if (debounce) { 131 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 132 pin_reg &= ~DB_TMR_OUT_MASK; 133 /* 134 Debounce Debounce Timer Max 135 TmrLarge TmrOutUnit Unit Debounce 136 Time 137 0 0 61 usec (2 RtcClk) 976 usec 138 0 1 244 usec (8 RtcClk) 3.9 msec 139 1 0 15.6 msec (512 RtcClk) 250 msec 140 1 1 62.5 msec (2048 RtcClk) 1 sec 141 */ 142 143 if (debounce < 61) { 144 pin_reg |= 1; 145 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 146 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 147 } else if (debounce < 976) { 148 time = debounce / 61; 149 pin_reg |= time & DB_TMR_OUT_MASK; 150 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 151 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 152 } else if (debounce < 3900) { 153 time = debounce / 244; 154 pin_reg |= time & DB_TMR_OUT_MASK; 155 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 156 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 157 } else if (debounce < 250000) { 158 time = debounce / 15625; 159 pin_reg |= time & DB_TMR_OUT_MASK; 160 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 161 pin_reg |= BIT(DB_TMR_LARGE_OFF); 162 } else if (debounce < 1000000) { 163 time = debounce / 62500; 164 pin_reg |= time & DB_TMR_OUT_MASK; 165 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 166 pin_reg |= BIT(DB_TMR_LARGE_OFF); 167 } else { 168 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 169 ret = -EINVAL; 170 } 171 } else { 172 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 173 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 174 pin_reg &= ~DB_TMR_OUT_MASK; 175 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 176 } 177 writel(pin_reg, gpio_dev->base + offset * 4); 178 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 179 180 return ret; 181 } 182 183 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset, 184 unsigned long config) 185 { 186 u32 debounce; 187 188 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 189 return -ENOTSUPP; 190 191 debounce = pinconf_to_config_argument(config); 192 return amd_gpio_set_debounce(gc, offset, debounce); 193 } 194 195 #ifdef CONFIG_DEBUG_FS 196 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) 197 { 198 u32 pin_reg; 199 u32 db_cntrl; 200 unsigned long flags; 201 unsigned int bank, i, pin_num; 202 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 203 204 bool tmr_out_unit; 205 bool tmr_large; 206 207 char *level_trig; 208 char *active_level; 209 char *interrupt_enable; 210 char *interrupt_mask; 211 char *wake_cntrl0; 212 char *wake_cntrl1; 213 char *wake_cntrl2; 214 char *pin_sts; 215 char *pull_up_sel; 216 char *pull_up_enable; 217 char *pull_down_enable; 218 char *orientation; 219 char debounce_value[40]; 220 char *debounce_enable; 221 222 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { 223 unsigned int time = 0; 224 unsigned int unit = 0; 225 226 switch (bank) { 227 case 0: 228 i = 0; 229 pin_num = AMD_GPIO_PINS_BANK0; 230 break; 231 case 1: 232 i = 64; 233 pin_num = AMD_GPIO_PINS_BANK1 + i; 234 break; 235 case 2: 236 i = 128; 237 pin_num = AMD_GPIO_PINS_BANK2 + i; 238 break; 239 case 3: 240 i = 192; 241 pin_num = AMD_GPIO_PINS_BANK3 + i; 242 break; 243 default: 244 /* Illegal bank number, ignore */ 245 continue; 246 } 247 seq_printf(s, "GPIO bank%d\n", bank); 248 for (; i < pin_num; i++) { 249 seq_printf(s, "#%d\t", i); 250 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 251 pin_reg = readl(gpio_dev->base + i * 4); 252 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 253 254 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { 255 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) & 256 ACTIVE_LEVEL_MASK; 257 interrupt_enable = "+"; 258 259 if (level == ACTIVE_LEVEL_HIGH) 260 active_level = "↑"; 261 else if (level == ACTIVE_LEVEL_LOW) 262 active_level = "↓"; 263 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) && 264 level == ACTIVE_LEVEL_BOTH) 265 active_level = "b"; 266 else 267 active_level = "?"; 268 269 if (pin_reg & BIT(LEVEL_TRIG_OFF)) 270 level_trig = "level"; 271 else 272 level_trig = " edge"; 273 274 } else { 275 interrupt_enable = "∅"; 276 active_level = "∅"; 277 level_trig = " ∅"; 278 } 279 280 if (pin_reg & BIT(INTERRUPT_MASK_OFF)) 281 interrupt_mask = "��"; 282 else 283 interrupt_mask = "��"; 284 seq_printf(s, "int %s (%s)| active-%s| %s-⚡| ", 285 interrupt_enable, 286 interrupt_mask, 287 active_level, 288 level_trig); 289 290 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) 291 wake_cntrl0 = "⏰"; 292 else 293 wake_cntrl0 = " ∅"; 294 seq_printf(s, "S0i3 %s| ", wake_cntrl0); 295 296 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) 297 wake_cntrl1 = "⏰"; 298 else 299 wake_cntrl1 = " ∅"; 300 seq_printf(s, "S3 %s| ", wake_cntrl1); 301 302 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) 303 wake_cntrl2 = "⏰"; 304 else 305 wake_cntrl2 = " ∅"; 306 seq_printf(s, "S4/S5 %s| ", wake_cntrl2); 307 308 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { 309 pull_up_enable = "+"; 310 if (pin_reg & BIT(PULL_UP_SEL_OFF)) 311 pull_up_sel = "8k"; 312 else 313 pull_up_sel = "4k"; 314 } else { 315 pull_up_enable = "∅"; 316 pull_up_sel = " "; 317 } 318 seq_printf(s, "pull-↑ %s (%s)| ", 319 pull_up_enable, 320 pull_up_sel); 321 322 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) 323 pull_down_enable = "+"; 324 else 325 pull_down_enable = "∅"; 326 seq_printf(s, "pull-↓ %s| ", pull_down_enable); 327 328 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { 329 pin_sts = "output"; 330 if (pin_reg & BIT(OUTPUT_VALUE_OFF)) 331 orientation = "↑"; 332 else 333 orientation = "↓"; 334 } else { 335 pin_sts = "input "; 336 if (pin_reg & BIT(PIN_STS_OFF)) 337 orientation = "↑"; 338 else 339 orientation = "↓"; 340 } 341 seq_printf(s, "%s %s| ", pin_sts, orientation); 342 343 db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg; 344 if (db_cntrl) { 345 tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF); 346 tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF); 347 time = pin_reg & DB_TMR_OUT_MASK; 348 if (tmr_large) { 349 if (tmr_out_unit) 350 unit = 62500; 351 else 352 unit = 15625; 353 } else { 354 if (tmr_out_unit) 355 unit = 244; 356 else 357 unit = 61; 358 } 359 if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl) 360 debounce_enable = "b +"; 361 else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl) 362 debounce_enable = "↓ +"; 363 else 364 debounce_enable = "↑ +"; 365 366 } else { 367 debounce_enable = " ∅"; 368 time = 0; 369 } 370 snprintf(debounce_value, sizeof(debounce_value), "%u", time * unit); 371 seq_printf(s, "debounce %s (�� %sus)| ", debounce_enable, debounce_value); 372 seq_printf(s, " 0x%x\n", pin_reg); 373 } 374 } 375 } 376 #else 377 #define amd_gpio_dbg_show NULL 378 #endif 379 380 static void amd_gpio_irq_enable(struct irq_data *d) 381 { 382 u32 pin_reg; 383 unsigned long flags; 384 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 385 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 386 387 gpiochip_enable_irq(gc, d->hwirq); 388 389 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 390 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 391 pin_reg |= BIT(INTERRUPT_ENABLE_OFF); 392 pin_reg |= BIT(INTERRUPT_MASK_OFF); 393 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 394 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 395 } 396 397 static void amd_gpio_irq_disable(struct irq_data *d) 398 { 399 u32 pin_reg; 400 unsigned long flags; 401 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 402 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 403 404 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 405 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 406 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); 407 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 408 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 409 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 410 411 gpiochip_disable_irq(gc, d->hwirq); 412 } 413 414 static void amd_gpio_irq_mask(struct irq_data *d) 415 { 416 u32 pin_reg; 417 unsigned long flags; 418 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 419 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 420 421 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 422 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 423 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 424 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 425 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 426 } 427 428 static void amd_gpio_irq_unmask(struct irq_data *d) 429 { 430 u32 pin_reg; 431 unsigned long flags; 432 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 433 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 434 435 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 436 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 437 pin_reg |= BIT(INTERRUPT_MASK_OFF); 438 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 439 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 440 } 441 442 static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 443 { 444 u32 pin_reg; 445 unsigned long flags; 446 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 447 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 448 u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3); 449 int err; 450 451 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 452 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 453 454 if (on) 455 pin_reg |= wake_mask; 456 else 457 pin_reg &= ~wake_mask; 458 459 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 460 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 461 462 if (on) 463 err = enable_irq_wake(gpio_dev->irq); 464 else 465 err = disable_irq_wake(gpio_dev->irq); 466 467 if (err) 468 dev_err(&gpio_dev->pdev->dev, "failed to %s wake-up interrupt\n", 469 on ? "enable" : "disable"); 470 471 return 0; 472 } 473 474 static void amd_gpio_irq_eoi(struct irq_data *d) 475 { 476 u32 reg; 477 unsigned long flags; 478 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 479 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 480 481 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 482 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 483 reg |= EOI_MASK; 484 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 485 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 486 } 487 488 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) 489 { 490 int ret = 0; 491 u32 pin_reg, pin_reg_irq_en, mask; 492 unsigned long flags; 493 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 494 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 495 496 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 497 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 498 499 switch (type & IRQ_TYPE_SENSE_MASK) { 500 case IRQ_TYPE_EDGE_RISING: 501 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 502 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 503 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 504 irq_set_handler_locked(d, handle_edge_irq); 505 break; 506 507 case IRQ_TYPE_EDGE_FALLING: 508 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 509 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 510 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 511 irq_set_handler_locked(d, handle_edge_irq); 512 break; 513 514 case IRQ_TYPE_EDGE_BOTH: 515 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 516 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 517 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; 518 irq_set_handler_locked(d, handle_edge_irq); 519 break; 520 521 case IRQ_TYPE_LEVEL_HIGH: 522 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 523 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 524 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 525 irq_set_handler_locked(d, handle_level_irq); 526 break; 527 528 case IRQ_TYPE_LEVEL_LOW: 529 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 530 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 531 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 532 irq_set_handler_locked(d, handle_level_irq); 533 break; 534 535 case IRQ_TYPE_NONE: 536 break; 537 538 default: 539 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); 540 ret = -EINVAL; 541 } 542 543 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; 544 /* 545 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the 546 * debounce registers of any GPIO will block wake/interrupt status 547 * generation for *all* GPIOs for a length of time that depends on 548 * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the 549 * INTERRUPT_ENABLE bit will read as 0. 550 * 551 * We temporarily enable irq for the GPIO whose configuration is 552 * changing, and then wait for it to read back as 1 to know when 553 * debounce has settled and then disable the irq again. 554 * We do this polling with the spinlock held to ensure other GPIO 555 * access routines do not read an incorrect value for the irq enable 556 * bit of other GPIOs. We keep the GPIO masked while polling to avoid 557 * spurious irqs, and disable the irq again after polling. 558 */ 559 mask = BIT(INTERRUPT_ENABLE_OFF); 560 pin_reg_irq_en = pin_reg; 561 pin_reg_irq_en |= mask; 562 pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF); 563 writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4); 564 while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask) 565 continue; 566 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 567 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 568 569 return ret; 570 } 571 572 static void amd_irq_ack(struct irq_data *d) 573 { 574 /* 575 * based on HW design,there is no need to ack HW 576 * before handle current irq. But this routine is 577 * necessary for handle_edge_irq 578 */ 579 } 580 581 static const struct irq_chip amd_gpio_irqchip = { 582 .name = "amd_gpio", 583 .irq_ack = amd_irq_ack, 584 .irq_enable = amd_gpio_irq_enable, 585 .irq_disable = amd_gpio_irq_disable, 586 .irq_mask = amd_gpio_irq_mask, 587 .irq_unmask = amd_gpio_irq_unmask, 588 .irq_set_wake = amd_gpio_irq_set_wake, 589 .irq_eoi = amd_gpio_irq_eoi, 590 .irq_set_type = amd_gpio_irq_set_type, 591 /* 592 * We need to set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND so that a wake event 593 * also generates an IRQ. We need the IRQ so the irq_handler can clear 594 * the wake event. Otherwise the wake event will never clear and 595 * prevent the system from suspending. 596 */ 597 .flags = IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND | IRQCHIP_IMMUTABLE, 598 GPIOCHIP_IRQ_RESOURCE_HELPERS, 599 }; 600 601 #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF)) 602 603 static bool do_amd_gpio_irq_handler(int irq, void *dev_id) 604 { 605 struct amd_gpio *gpio_dev = dev_id; 606 struct gpio_chip *gc = &gpio_dev->gc; 607 unsigned int i, irqnr; 608 unsigned long flags; 609 u32 __iomem *regs; 610 bool ret = false; 611 u32 regval; 612 u64 status, mask; 613 614 /* Read the wake status */ 615 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 616 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); 617 status <<= 32; 618 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0); 619 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 620 621 /* Bit 0-45 contain the relevant status bits */ 622 status &= (1ULL << 46) - 1; 623 regs = gpio_dev->base; 624 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) { 625 if (!(status & mask)) 626 continue; 627 status &= ~mask; 628 629 /* Each status bit covers four pins */ 630 for (i = 0; i < 4; i++) { 631 regval = readl(regs + i); 632 633 if (regval & PIN_IRQ_PENDING) 634 dev_dbg(&gpio_dev->pdev->dev, 635 "GPIO %d is active: 0x%x", 636 irqnr + i, regval); 637 638 /* caused wake on resume context for shared IRQ */ 639 if (irq < 0 && (regval & BIT(WAKE_STS_OFF))) 640 return true; 641 642 if (!(regval & PIN_IRQ_PENDING) || 643 !(regval & BIT(INTERRUPT_MASK_OFF))) 644 continue; 645 generic_handle_domain_irq_safe(gc->irq.domain, irqnr + i); 646 647 /* Clear interrupt. 648 * We must read the pin register again, in case the 649 * value was changed while executing 650 * generic_handle_domain_irq() above. 651 * If we didn't find a mapping for the interrupt, 652 * disable it in order to avoid a system hang caused 653 * by an interrupt storm. 654 */ 655 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 656 regval = readl(regs + i); 657 if (irq == 0) { 658 regval &= ~BIT(INTERRUPT_ENABLE_OFF); 659 dev_dbg(&gpio_dev->pdev->dev, 660 "Disabling spurious GPIO IRQ %d\n", 661 irqnr + i); 662 } 663 writel(regval, regs + i); 664 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 665 ret = true; 666 } 667 } 668 /* did not cause wake on resume context for shared IRQ */ 669 if (irq < 0) 670 return false; 671 672 /* Signal EOI to the GPIO unit */ 673 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 674 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 675 regval |= EOI_MASK; 676 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG); 677 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 678 679 return ret; 680 } 681 682 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id) 683 { 684 return IRQ_RETVAL(do_amd_gpio_irq_handler(irq, dev_id)); 685 } 686 687 static bool __maybe_unused amd_gpio_check_wake(void *dev_id) 688 { 689 return do_amd_gpio_irq_handler(-1, dev_id); 690 } 691 692 static int amd_get_groups_count(struct pinctrl_dev *pctldev) 693 { 694 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 695 696 return gpio_dev->ngroups; 697 } 698 699 static const char *amd_get_group_name(struct pinctrl_dev *pctldev, 700 unsigned group) 701 { 702 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 703 704 return gpio_dev->groups[group].name; 705 } 706 707 static int amd_get_group_pins(struct pinctrl_dev *pctldev, 708 unsigned group, 709 const unsigned **pins, 710 unsigned *num_pins) 711 { 712 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 713 714 *pins = gpio_dev->groups[group].pins; 715 *num_pins = gpio_dev->groups[group].npins; 716 return 0; 717 } 718 719 static const struct pinctrl_ops amd_pinctrl_ops = { 720 .get_groups_count = amd_get_groups_count, 721 .get_group_name = amd_get_group_name, 722 .get_group_pins = amd_get_group_pins, 723 #ifdef CONFIG_OF 724 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 725 .dt_free_map = pinctrl_utils_free_map, 726 #endif 727 }; 728 729 static int amd_pinconf_get(struct pinctrl_dev *pctldev, 730 unsigned int pin, 731 unsigned long *config) 732 { 733 u32 pin_reg; 734 unsigned arg; 735 unsigned long flags; 736 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 737 enum pin_config_param param = pinconf_to_config_param(*config); 738 739 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 740 pin_reg = readl(gpio_dev->base + pin*4); 741 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 742 switch (param) { 743 case PIN_CONFIG_INPUT_DEBOUNCE: 744 arg = pin_reg & DB_TMR_OUT_MASK; 745 break; 746 747 case PIN_CONFIG_BIAS_PULL_DOWN: 748 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); 749 break; 750 751 case PIN_CONFIG_BIAS_PULL_UP: 752 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); 753 break; 754 755 case PIN_CONFIG_DRIVE_STRENGTH: 756 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; 757 break; 758 759 default: 760 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n", 761 param); 762 return -ENOTSUPP; 763 } 764 765 *config = pinconf_to_config_packed(param, arg); 766 767 return 0; 768 } 769 770 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 771 unsigned long *configs, unsigned num_configs) 772 { 773 int i; 774 u32 arg; 775 int ret = 0; 776 u32 pin_reg; 777 unsigned long flags; 778 enum pin_config_param param; 779 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 780 781 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 782 for (i = 0; i < num_configs; i++) { 783 param = pinconf_to_config_param(configs[i]); 784 arg = pinconf_to_config_argument(configs[i]); 785 pin_reg = readl(gpio_dev->base + pin*4); 786 787 switch (param) { 788 case PIN_CONFIG_INPUT_DEBOUNCE: 789 pin_reg &= ~DB_TMR_OUT_MASK; 790 pin_reg |= arg & DB_TMR_OUT_MASK; 791 break; 792 793 case PIN_CONFIG_BIAS_PULL_DOWN: 794 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); 795 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; 796 break; 797 798 case PIN_CONFIG_BIAS_PULL_UP: 799 pin_reg &= ~BIT(PULL_UP_SEL_OFF); 800 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; 801 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); 802 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; 803 break; 804 805 case PIN_CONFIG_DRIVE_STRENGTH: 806 pin_reg &= ~(DRV_STRENGTH_SEL_MASK 807 << DRV_STRENGTH_SEL_OFF); 808 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) 809 << DRV_STRENGTH_SEL_OFF; 810 break; 811 812 default: 813 dev_err(&gpio_dev->pdev->dev, 814 "Invalid config param %04x\n", param); 815 ret = -ENOTSUPP; 816 } 817 818 writel(pin_reg, gpio_dev->base + pin*4); 819 } 820 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 821 822 return ret; 823 } 824 825 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, 826 unsigned int group, 827 unsigned long *config) 828 { 829 const unsigned *pins; 830 unsigned npins; 831 int ret; 832 833 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 834 if (ret) 835 return ret; 836 837 if (amd_pinconf_get(pctldev, pins[0], config)) 838 return -ENOTSUPP; 839 840 return 0; 841 } 842 843 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, 844 unsigned group, unsigned long *configs, 845 unsigned num_configs) 846 { 847 const unsigned *pins; 848 unsigned npins; 849 int i, ret; 850 851 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 852 if (ret) 853 return ret; 854 for (i = 0; i < npins; i++) { 855 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) 856 return -ENOTSUPP; 857 } 858 return 0; 859 } 860 861 static const struct pinconf_ops amd_pinconf_ops = { 862 .pin_config_get = amd_pinconf_get, 863 .pin_config_set = amd_pinconf_set, 864 .pin_config_group_get = amd_pinconf_group_get, 865 .pin_config_group_set = amd_pinconf_group_set, 866 }; 867 868 static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) 869 { 870 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 871 unsigned long flags; 872 u32 pin_reg, mask; 873 int i; 874 875 mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) | 876 BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) | 877 BIT(WAKE_CNTRL_OFF_S4); 878 879 for (i = 0; i < desc->npins; i++) { 880 int pin = desc->pins[i].number; 881 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 882 883 if (!pd) 884 continue; 885 886 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 887 888 pin_reg = readl(gpio_dev->base + i * 4); 889 pin_reg &= ~mask; 890 writel(pin_reg, gpio_dev->base + i * 4); 891 892 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 893 } 894 } 895 896 #ifdef CONFIG_PM_SLEEP 897 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) 898 { 899 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 900 901 if (!pd) 902 return false; 903 904 /* 905 * Only restore the pin if it is actually in use by the kernel (or 906 * by userspace). 907 */ 908 if (pd->mux_owner || pd->gpio_owner || 909 gpiochip_line_is_irq(&gpio_dev->gc, pin)) 910 return true; 911 912 return false; 913 } 914 915 static int amd_gpio_suspend(struct device *dev) 916 { 917 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 918 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 919 unsigned long flags; 920 int i; 921 922 for (i = 0; i < desc->npins; i++) { 923 int pin = desc->pins[i].number; 924 925 if (!amd_gpio_should_save(gpio_dev, pin)) 926 continue; 927 928 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 929 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING; 930 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 931 } 932 933 return 0; 934 } 935 936 static int amd_gpio_resume(struct device *dev) 937 { 938 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 939 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 940 unsigned long flags; 941 int i; 942 943 for (i = 0; i < desc->npins; i++) { 944 int pin = desc->pins[i].number; 945 946 if (!amd_gpio_should_save(gpio_dev, pin)) 947 continue; 948 949 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 950 gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING; 951 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin * 4); 952 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 953 } 954 955 return 0; 956 } 957 958 static const struct dev_pm_ops amd_gpio_pm_ops = { 959 SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend, 960 amd_gpio_resume) 961 }; 962 #endif 963 964 static int amd_get_functions_count(struct pinctrl_dev *pctldev) 965 { 966 return ARRAY_SIZE(pmx_functions); 967 } 968 969 static const char *amd_get_fname(struct pinctrl_dev *pctrldev, unsigned int selector) 970 { 971 return pmx_functions[selector].name; 972 } 973 974 static int amd_get_groups(struct pinctrl_dev *pctrldev, unsigned int selector, 975 const char * const **groups, 976 unsigned int * const num_groups) 977 { 978 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev); 979 980 if (!gpio_dev->iomux_base) { 981 dev_err(&gpio_dev->pdev->dev, "iomux function %d group not supported\n", selector); 982 return -EINVAL; 983 } 984 985 *groups = pmx_functions[selector].groups; 986 *num_groups = pmx_functions[selector].ngroups; 987 return 0; 988 } 989 990 static int amd_set_mux(struct pinctrl_dev *pctrldev, unsigned int function, unsigned int group) 991 { 992 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev); 993 struct device *dev = &gpio_dev->pdev->dev; 994 struct pin_desc *pd; 995 int ind, index; 996 997 if (!gpio_dev->iomux_base) 998 return -EINVAL; 999 1000 for (index = 0; index < NSELECTS; index++) { 1001 if (strcmp(gpio_dev->groups[group].name, pmx_functions[function].groups[index])) 1002 continue; 1003 1004 if (readb(gpio_dev->iomux_base + pmx_functions[function].index) == 1005 FUNCTION_INVALID) { 1006 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n", 1007 pmx_functions[function].index); 1008 return -EINVAL; 1009 } 1010 1011 writeb(index, gpio_dev->iomux_base + pmx_functions[function].index); 1012 1013 if (index != (readb(gpio_dev->iomux_base + pmx_functions[function].index) & 1014 FUNCTION_MASK)) { 1015 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n", 1016 pmx_functions[function].index); 1017 return -EINVAL; 1018 } 1019 1020 for (ind = 0; ind < gpio_dev->groups[group].npins; ind++) { 1021 if (strncmp(gpio_dev->groups[group].name, "IMX_F", strlen("IMX_F"))) 1022 continue; 1023 1024 pd = pin_desc_get(gpio_dev->pctrl, gpio_dev->groups[group].pins[ind]); 1025 pd->mux_owner = gpio_dev->groups[group].name; 1026 } 1027 break; 1028 } 1029 1030 return 0; 1031 } 1032 1033 static const struct pinmux_ops amd_pmxops = { 1034 .get_functions_count = amd_get_functions_count, 1035 .get_function_name = amd_get_fname, 1036 .get_function_groups = amd_get_groups, 1037 .set_mux = amd_set_mux, 1038 }; 1039 1040 static struct pinctrl_desc amd_pinctrl_desc = { 1041 .pins = kerncz_pins, 1042 .npins = ARRAY_SIZE(kerncz_pins), 1043 .pctlops = &amd_pinctrl_ops, 1044 .pmxops = &amd_pmxops, 1045 .confops = &amd_pinconf_ops, 1046 .owner = THIS_MODULE, 1047 }; 1048 1049 static void amd_get_iomux_res(struct amd_gpio *gpio_dev) 1050 { 1051 struct pinctrl_desc *desc = &amd_pinctrl_desc; 1052 struct device *dev = &gpio_dev->pdev->dev; 1053 int index; 1054 1055 index = device_property_match_string(dev, "pinctrl-resource-names", "iomux"); 1056 if (index < 0) { 1057 dev_dbg(dev, "iomux not supported\n"); 1058 goto out_no_pinmux; 1059 } 1060 1061 gpio_dev->iomux_base = devm_platform_ioremap_resource(gpio_dev->pdev, index); 1062 if (IS_ERR(gpio_dev->iomux_base)) { 1063 dev_dbg(dev, "iomux not supported %d io resource\n", index); 1064 goto out_no_pinmux; 1065 } 1066 1067 return; 1068 1069 out_no_pinmux: 1070 desc->pmxops = NULL; 1071 } 1072 1073 static int amd_gpio_probe(struct platform_device *pdev) 1074 { 1075 int ret = 0; 1076 struct resource *res; 1077 struct amd_gpio *gpio_dev; 1078 struct gpio_irq_chip *girq; 1079 1080 gpio_dev = devm_kzalloc(&pdev->dev, 1081 sizeof(struct amd_gpio), GFP_KERNEL); 1082 if (!gpio_dev) 1083 return -ENOMEM; 1084 1085 raw_spin_lock_init(&gpio_dev->lock); 1086 1087 gpio_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1088 if (IS_ERR(gpio_dev->base)) { 1089 dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); 1090 return PTR_ERR(gpio_dev->base); 1091 } 1092 1093 gpio_dev->irq = platform_get_irq(pdev, 0); 1094 if (gpio_dev->irq < 0) 1095 return gpio_dev->irq; 1096 1097 #ifdef CONFIG_PM_SLEEP 1098 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins, 1099 sizeof(*gpio_dev->saved_regs), 1100 GFP_KERNEL); 1101 if (!gpio_dev->saved_regs) 1102 return -ENOMEM; 1103 #endif 1104 1105 gpio_dev->pdev = pdev; 1106 gpio_dev->gc.get_direction = amd_gpio_get_direction; 1107 gpio_dev->gc.direction_input = amd_gpio_direction_input; 1108 gpio_dev->gc.direction_output = amd_gpio_direction_output; 1109 gpio_dev->gc.get = amd_gpio_get_value; 1110 gpio_dev->gc.set = amd_gpio_set_value; 1111 gpio_dev->gc.set_config = amd_gpio_set_config; 1112 gpio_dev->gc.dbg_show = amd_gpio_dbg_show; 1113 1114 gpio_dev->gc.base = -1; 1115 gpio_dev->gc.label = pdev->name; 1116 gpio_dev->gc.owner = THIS_MODULE; 1117 gpio_dev->gc.parent = &pdev->dev; 1118 gpio_dev->gc.ngpio = resource_size(res) / 4; 1119 1120 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64; 1121 gpio_dev->groups = kerncz_groups; 1122 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); 1123 1124 amd_pinctrl_desc.name = dev_name(&pdev->dev); 1125 amd_get_iomux_res(gpio_dev); 1126 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, 1127 gpio_dev); 1128 if (IS_ERR(gpio_dev->pctrl)) { 1129 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 1130 return PTR_ERR(gpio_dev->pctrl); 1131 } 1132 1133 /* Disable and mask interrupts */ 1134 amd_gpio_irq_init(gpio_dev); 1135 1136 girq = &gpio_dev->gc.irq; 1137 gpio_irq_chip_set_chip(girq, &amd_gpio_irqchip); 1138 /* This will let us handle the parent IRQ in the driver */ 1139 girq->parent_handler = NULL; 1140 girq->num_parents = 0; 1141 girq->parents = NULL; 1142 girq->default_type = IRQ_TYPE_NONE; 1143 girq->handler = handle_simple_irq; 1144 1145 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); 1146 if (ret) 1147 return ret; 1148 1149 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), 1150 0, 0, gpio_dev->gc.ngpio); 1151 if (ret) { 1152 dev_err(&pdev->dev, "Failed to add pin range\n"); 1153 goto out2; 1154 } 1155 1156 ret = devm_request_irq(&pdev->dev, gpio_dev->irq, amd_gpio_irq_handler, 1157 IRQF_SHARED, KBUILD_MODNAME, gpio_dev); 1158 if (ret) 1159 goto out2; 1160 1161 platform_set_drvdata(pdev, gpio_dev); 1162 acpi_register_wakeup_handler(gpio_dev->irq, amd_gpio_check_wake, gpio_dev); 1163 1164 dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); 1165 return ret; 1166 1167 out2: 1168 gpiochip_remove(&gpio_dev->gc); 1169 1170 return ret; 1171 } 1172 1173 static int amd_gpio_remove(struct platform_device *pdev) 1174 { 1175 struct amd_gpio *gpio_dev; 1176 1177 gpio_dev = platform_get_drvdata(pdev); 1178 1179 gpiochip_remove(&gpio_dev->gc); 1180 acpi_unregister_wakeup_handler(amd_gpio_check_wake, gpio_dev); 1181 1182 return 0; 1183 } 1184 1185 #ifdef CONFIG_ACPI 1186 static const struct acpi_device_id amd_gpio_acpi_match[] = { 1187 { "AMD0030", 0 }, 1188 { "AMDI0030", 0}, 1189 { "AMDI0031", 0}, 1190 { }, 1191 }; 1192 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); 1193 #endif 1194 1195 static struct platform_driver amd_gpio_driver = { 1196 .driver = { 1197 .name = "amd_gpio", 1198 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), 1199 #ifdef CONFIG_PM_SLEEP 1200 .pm = &amd_gpio_pm_ops, 1201 #endif 1202 }, 1203 .probe = amd_gpio_probe, 1204 .remove = amd_gpio_remove, 1205 }; 1206 1207 module_platform_driver(amd_gpio_driver); 1208 1209 MODULE_LICENSE("GPL v2"); 1210 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); 1211 MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); 1212