1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPIO driver for AMD 4 * 5 * Copyright (c) 2014,2015 AMD Corporation. 6 * Authors: Ken Xue <Ken.Xue@amd.com> 7 * Wu, Jeff <Jeff.Wu@amd.com> 8 * 9 */ 10 11 #include <linux/err.h> 12 #include <linux/bug.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/spinlock.h> 16 #include <linux/compiler.h> 17 #include <linux/types.h> 18 #include <linux/errno.h> 19 #include <linux/log2.h> 20 #include <linux/io.h> 21 #include <linux/gpio/driver.h> 22 #include <linux/slab.h> 23 #include <linux/platform_device.h> 24 #include <linux/mutex.h> 25 #include <linux/acpi.h> 26 #include <linux/seq_file.h> 27 #include <linux/interrupt.h> 28 #include <linux/list.h> 29 #include <linux/bitops.h> 30 #include <linux/pinctrl/pinconf.h> 31 #include <linux/pinctrl/pinconf-generic.h> 32 #include <linux/pinctrl/pinmux.h> 33 #include <linux/suspend.h> 34 35 #include "core.h" 36 #include "pinctrl-utils.h" 37 #include "pinctrl-amd.h" 38 39 static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset) 40 { 41 unsigned long flags; 42 u32 pin_reg; 43 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 44 45 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 46 pin_reg = readl(gpio_dev->base + offset * 4); 47 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 48 49 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) 50 return GPIO_LINE_DIRECTION_OUT; 51 52 return GPIO_LINE_DIRECTION_IN; 53 } 54 55 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 56 { 57 unsigned long flags; 58 u32 pin_reg; 59 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 60 61 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 62 pin_reg = readl(gpio_dev->base + offset * 4); 63 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); 64 writel(pin_reg, gpio_dev->base + offset * 4); 65 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 66 67 return 0; 68 } 69 70 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 71 int value) 72 { 73 u32 pin_reg; 74 unsigned long flags; 75 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 76 77 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 78 pin_reg = readl(gpio_dev->base + offset * 4); 79 pin_reg |= BIT(OUTPUT_ENABLE_OFF); 80 if (value) 81 pin_reg |= BIT(OUTPUT_VALUE_OFF); 82 else 83 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 84 writel(pin_reg, gpio_dev->base + offset * 4); 85 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 86 87 return 0; 88 } 89 90 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) 91 { 92 u32 pin_reg; 93 unsigned long flags; 94 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 95 96 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 97 pin_reg = readl(gpio_dev->base + offset * 4); 98 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 99 100 return !!(pin_reg & BIT(PIN_STS_OFF)); 101 } 102 103 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) 104 { 105 u32 pin_reg; 106 unsigned long flags; 107 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 108 109 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 110 pin_reg = readl(gpio_dev->base + offset * 4); 111 if (value) 112 pin_reg |= BIT(OUTPUT_VALUE_OFF); 113 else 114 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 115 writel(pin_reg, gpio_dev->base + offset * 4); 116 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 117 } 118 119 static int amd_gpio_set_debounce(struct amd_gpio *gpio_dev, unsigned int offset, 120 unsigned int debounce) 121 { 122 u32 time; 123 u32 pin_reg; 124 int ret = 0; 125 126 /* Use special handling for Pin0 debounce */ 127 if (offset == 0) { 128 pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 129 if (pin_reg & INTERNAL_GPIO0_DEBOUNCE) 130 debounce = 0; 131 } 132 133 pin_reg = readl(gpio_dev->base + offset * 4); 134 135 if (debounce) { 136 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 137 pin_reg &= ~DB_TMR_OUT_MASK; 138 /* 139 Debounce Debounce Timer Max 140 TmrLarge TmrOutUnit Unit Debounce 141 Time 142 0 0 61 usec (2 RtcClk) 976 usec 143 0 1 244 usec (8 RtcClk) 3.9 msec 144 1 0 15.6 msec (512 RtcClk) 250 msec 145 1 1 62.5 msec (2048 RtcClk) 1 sec 146 */ 147 148 if (debounce < 61) { 149 pin_reg |= 1; 150 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 151 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 152 } else if (debounce < 976) { 153 time = debounce / 61; 154 pin_reg |= time & DB_TMR_OUT_MASK; 155 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 156 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 157 } else if (debounce < 3900) { 158 time = debounce / 244; 159 pin_reg |= time & DB_TMR_OUT_MASK; 160 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 161 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 162 } else if (debounce < 250000) { 163 time = debounce / 15625; 164 pin_reg |= time & DB_TMR_OUT_MASK; 165 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 166 pin_reg |= BIT(DB_TMR_LARGE_OFF); 167 } else if (debounce < 1000000) { 168 time = debounce / 62500; 169 pin_reg |= time & DB_TMR_OUT_MASK; 170 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 171 pin_reg |= BIT(DB_TMR_LARGE_OFF); 172 } else { 173 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 174 ret = -EINVAL; 175 } 176 } else { 177 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 178 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 179 pin_reg &= ~DB_TMR_OUT_MASK; 180 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 181 } 182 writel(pin_reg, gpio_dev->base + offset * 4); 183 184 return ret; 185 } 186 187 #ifdef CONFIG_DEBUG_FS 188 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) 189 { 190 u32 pin_reg; 191 u32 db_cntrl; 192 unsigned long flags; 193 unsigned int bank, i, pin_num; 194 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 195 196 bool tmr_out_unit; 197 bool tmr_large; 198 199 char *level_trig; 200 char *active_level; 201 char *interrupt_mask; 202 char *wake_cntrl0; 203 char *wake_cntrl1; 204 char *wake_cntrl2; 205 char *pin_sts; 206 char *interrupt_sts; 207 char *wake_sts; 208 char *orientation; 209 char debounce_value[40]; 210 char *debounce_enable; 211 char *wake_cntrlz; 212 213 seq_printf(s, "WAKE_INT_MASTER_REG: 0x%08x\n", readl(gpio_dev->base + WAKE_INT_MASTER_REG)); 214 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { 215 unsigned int time = 0; 216 unsigned int unit = 0; 217 218 switch (bank) { 219 case 0: 220 i = 0; 221 pin_num = AMD_GPIO_PINS_BANK0; 222 break; 223 case 1: 224 i = 64; 225 pin_num = AMD_GPIO_PINS_BANK1 + i; 226 break; 227 case 2: 228 i = 128; 229 pin_num = AMD_GPIO_PINS_BANK2 + i; 230 break; 231 case 3: 232 i = 192; 233 pin_num = AMD_GPIO_PINS_BANK3 + i; 234 break; 235 default: 236 /* Illegal bank number, ignore */ 237 continue; 238 } 239 seq_printf(s, "GPIO bank%d\n", bank); 240 seq_puts(s, "gpio\t int|active|trigger|S0i3| S3|S4/S5| Z|wake|pull| orient| debounce|reg\n"); 241 for (; i < pin_num; i++) { 242 seq_printf(s, "#%d\t", i); 243 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 244 pin_reg = readl(gpio_dev->base + i * 4); 245 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 246 247 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { 248 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) & 249 ACTIVE_LEVEL_MASK; 250 251 if (level == ACTIVE_LEVEL_HIGH) 252 active_level = "↑"; 253 else if (level == ACTIVE_LEVEL_LOW) 254 active_level = "↓"; 255 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) && 256 level == ACTIVE_LEVEL_BOTH) 257 active_level = "b"; 258 else 259 active_level = "?"; 260 261 if (pin_reg & BIT(LEVEL_TRIG_OFF)) 262 level_trig = "level"; 263 else 264 level_trig = " edge"; 265 266 if (pin_reg & BIT(INTERRUPT_MASK_OFF)) 267 interrupt_mask = "��"; 268 else 269 interrupt_mask = "��"; 270 271 if (pin_reg & BIT(INTERRUPT_STS_OFF)) 272 interrupt_sts = "��"; 273 else 274 interrupt_sts = " "; 275 276 seq_printf(s, "%s %s| %s| %s|", 277 interrupt_sts, 278 interrupt_mask, 279 active_level, 280 level_trig); 281 } else 282 seq_puts(s, " ∅| | |"); 283 284 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) 285 wake_cntrl0 = "⏰"; 286 else 287 wake_cntrl0 = " "; 288 seq_printf(s, " %s| ", wake_cntrl0); 289 290 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) 291 wake_cntrl1 = "⏰"; 292 else 293 wake_cntrl1 = " "; 294 seq_printf(s, "%s|", wake_cntrl1); 295 296 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) 297 wake_cntrl2 = "⏰"; 298 else 299 wake_cntrl2 = " "; 300 seq_printf(s, " %s|", wake_cntrl2); 301 302 if (pin_reg & BIT(WAKECNTRL_Z_OFF)) 303 wake_cntrlz = "⏰"; 304 else 305 wake_cntrlz = " "; 306 seq_printf(s, "%s|", wake_cntrlz); 307 308 if (pin_reg & BIT(WAKE_STS_OFF)) 309 wake_sts = "��"; 310 else 311 wake_sts = " "; 312 seq_printf(s, " %s|", wake_sts); 313 314 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { 315 seq_puts(s, " ↑ |"); 316 } else if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) { 317 seq_puts(s, " ↓ |"); 318 } else { 319 seq_puts(s, " |"); 320 } 321 322 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { 323 pin_sts = "output"; 324 if (pin_reg & BIT(OUTPUT_VALUE_OFF)) 325 orientation = "↑"; 326 else 327 orientation = "↓"; 328 } else { 329 pin_sts = "input "; 330 if (pin_reg & BIT(PIN_STS_OFF)) 331 orientation = "↑"; 332 else 333 orientation = "↓"; 334 } 335 seq_printf(s, "%s %s|", pin_sts, orientation); 336 337 db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg; 338 if (db_cntrl) { 339 tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF); 340 tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF); 341 time = pin_reg & DB_TMR_OUT_MASK; 342 if (tmr_large) { 343 if (tmr_out_unit) 344 unit = 62500; 345 else 346 unit = 15625; 347 } else { 348 if (tmr_out_unit) 349 unit = 244; 350 else 351 unit = 61; 352 } 353 if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl) 354 debounce_enable = "b"; 355 else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl) 356 debounce_enable = "↓"; 357 else 358 debounce_enable = "↑"; 359 snprintf(debounce_value, sizeof(debounce_value), "%06u", time * unit); 360 seq_printf(s, "%s (�� %sus)|", debounce_enable, debounce_value); 361 } else { 362 seq_puts(s, " |"); 363 } 364 seq_printf(s, "0x%x\n", pin_reg); 365 } 366 } 367 } 368 #else 369 #define amd_gpio_dbg_show NULL 370 #endif 371 372 static void amd_gpio_irq_enable(struct irq_data *d) 373 { 374 u32 pin_reg; 375 unsigned long flags; 376 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 377 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 378 379 gpiochip_enable_irq(gc, d->hwirq); 380 381 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 382 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 383 pin_reg |= BIT(INTERRUPT_ENABLE_OFF); 384 pin_reg |= BIT(INTERRUPT_MASK_OFF); 385 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 386 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 387 } 388 389 static void amd_gpio_irq_disable(struct irq_data *d) 390 { 391 u32 pin_reg; 392 unsigned long flags; 393 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 394 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 395 396 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 397 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 398 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); 399 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 400 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 401 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 402 403 gpiochip_disable_irq(gc, d->hwirq); 404 } 405 406 static void amd_gpio_irq_mask(struct irq_data *d) 407 { 408 u32 pin_reg; 409 unsigned long flags; 410 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 411 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 412 413 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 414 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 415 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 416 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 417 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 418 } 419 420 static void amd_gpio_irq_unmask(struct irq_data *d) 421 { 422 u32 pin_reg; 423 unsigned long flags; 424 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 425 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 426 427 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 428 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 429 pin_reg |= BIT(INTERRUPT_MASK_OFF); 430 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 431 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 432 } 433 434 static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 435 { 436 u32 pin_reg; 437 unsigned long flags; 438 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 439 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 440 u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3); 441 int err; 442 443 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 444 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 445 446 if (on) 447 pin_reg |= wake_mask; 448 else 449 pin_reg &= ~wake_mask; 450 451 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 452 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 453 454 if (on) 455 err = enable_irq_wake(gpio_dev->irq); 456 else 457 err = disable_irq_wake(gpio_dev->irq); 458 459 if (err) 460 dev_err(&gpio_dev->pdev->dev, "failed to %s wake-up interrupt\n", 461 on ? "enable" : "disable"); 462 463 return 0; 464 } 465 466 static void amd_gpio_irq_eoi(struct irq_data *d) 467 { 468 u32 reg; 469 unsigned long flags; 470 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 471 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 472 473 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 474 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 475 reg |= EOI_MASK; 476 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 477 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 478 } 479 480 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) 481 { 482 int ret = 0; 483 u32 pin_reg, pin_reg_irq_en, mask; 484 unsigned long flags; 485 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 486 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 487 488 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 489 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 490 491 switch (type & IRQ_TYPE_SENSE_MASK) { 492 case IRQ_TYPE_EDGE_RISING: 493 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 494 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 495 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 496 irq_set_handler_locked(d, handle_edge_irq); 497 break; 498 499 case IRQ_TYPE_EDGE_FALLING: 500 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 501 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 502 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 503 irq_set_handler_locked(d, handle_edge_irq); 504 break; 505 506 case IRQ_TYPE_EDGE_BOTH: 507 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 508 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 509 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; 510 irq_set_handler_locked(d, handle_edge_irq); 511 break; 512 513 case IRQ_TYPE_LEVEL_HIGH: 514 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 515 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 516 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 517 irq_set_handler_locked(d, handle_level_irq); 518 break; 519 520 case IRQ_TYPE_LEVEL_LOW: 521 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 522 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 523 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 524 irq_set_handler_locked(d, handle_level_irq); 525 break; 526 527 case IRQ_TYPE_NONE: 528 break; 529 530 default: 531 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); 532 ret = -EINVAL; 533 } 534 535 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; 536 /* 537 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the 538 * debounce registers of any GPIO will block wake/interrupt status 539 * generation for *all* GPIOs for a length of time that depends on 540 * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the 541 * INTERRUPT_ENABLE bit will read as 0. 542 * 543 * We temporarily enable irq for the GPIO whose configuration is 544 * changing, and then wait for it to read back as 1 to know when 545 * debounce has settled and then disable the irq again. 546 * We do this polling with the spinlock held to ensure other GPIO 547 * access routines do not read an incorrect value for the irq enable 548 * bit of other GPIOs. We keep the GPIO masked while polling to avoid 549 * spurious irqs, and disable the irq again after polling. 550 */ 551 mask = BIT(INTERRUPT_ENABLE_OFF); 552 pin_reg_irq_en = pin_reg; 553 pin_reg_irq_en |= mask; 554 pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF); 555 writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4); 556 while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask) 557 continue; 558 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 559 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 560 561 return ret; 562 } 563 564 static void amd_irq_ack(struct irq_data *d) 565 { 566 /* 567 * based on HW design,there is no need to ack HW 568 * before handle current irq. But this routine is 569 * necessary for handle_edge_irq 570 */ 571 } 572 573 static const struct irq_chip amd_gpio_irqchip = { 574 .name = "amd_gpio", 575 .irq_ack = amd_irq_ack, 576 .irq_enable = amd_gpio_irq_enable, 577 .irq_disable = amd_gpio_irq_disable, 578 .irq_mask = amd_gpio_irq_mask, 579 .irq_unmask = amd_gpio_irq_unmask, 580 .irq_set_wake = amd_gpio_irq_set_wake, 581 .irq_eoi = amd_gpio_irq_eoi, 582 .irq_set_type = amd_gpio_irq_set_type, 583 /* 584 * We need to set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND so that a wake event 585 * also generates an IRQ. We need the IRQ so the irq_handler can clear 586 * the wake event. Otherwise the wake event will never clear and 587 * prevent the system from suspending. 588 */ 589 .flags = IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND | IRQCHIP_IMMUTABLE, 590 GPIOCHIP_IRQ_RESOURCE_HELPERS, 591 }; 592 593 #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF)) 594 595 static bool do_amd_gpio_irq_handler(int irq, void *dev_id) 596 { 597 struct amd_gpio *gpio_dev = dev_id; 598 struct gpio_chip *gc = &gpio_dev->gc; 599 unsigned int i, irqnr; 600 unsigned long flags; 601 u32 __iomem *regs; 602 bool ret = false; 603 u32 regval; 604 u64 status, mask; 605 606 /* Read the wake status */ 607 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 608 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); 609 status <<= 32; 610 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0); 611 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 612 613 /* Bit 0-45 contain the relevant status bits */ 614 status &= (1ULL << 46) - 1; 615 regs = gpio_dev->base; 616 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) { 617 if (!(status & mask)) 618 continue; 619 status &= ~mask; 620 621 /* Each status bit covers four pins */ 622 for (i = 0; i < 4; i++) { 623 regval = readl(regs + i); 624 625 if (regval & PIN_IRQ_PENDING) 626 pm_pr_dbg("GPIO %d is active: 0x%x", 627 irqnr + i, regval); 628 629 /* caused wake on resume context for shared IRQ */ 630 if (irq < 0 && (regval & BIT(WAKE_STS_OFF))) 631 return true; 632 633 if (!(regval & PIN_IRQ_PENDING) || 634 !(regval & BIT(INTERRUPT_MASK_OFF))) 635 continue; 636 generic_handle_domain_irq_safe(gc->irq.domain, irqnr + i); 637 638 /* Clear interrupt. 639 * We must read the pin register again, in case the 640 * value was changed while executing 641 * generic_handle_domain_irq() above. 642 * If the line is not an irq, disable it in order to 643 * avoid a system hang caused by an interrupt storm. 644 */ 645 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 646 regval = readl(regs + i); 647 if (!gpiochip_line_is_irq(gc, irqnr + i)) { 648 regval &= ~BIT(INTERRUPT_MASK_OFF); 649 dev_dbg(&gpio_dev->pdev->dev, 650 "Disabling spurious GPIO IRQ %d\n", 651 irqnr + i); 652 } else { 653 ret = true; 654 } 655 writel(regval, regs + i); 656 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 657 } 658 } 659 /* did not cause wake on resume context for shared IRQ */ 660 if (irq < 0) 661 return false; 662 663 /* Signal EOI to the GPIO unit */ 664 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 665 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 666 regval |= EOI_MASK; 667 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG); 668 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 669 670 return ret; 671 } 672 673 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id) 674 { 675 return IRQ_RETVAL(do_amd_gpio_irq_handler(irq, dev_id)); 676 } 677 678 static bool __maybe_unused amd_gpio_check_wake(void *dev_id) 679 { 680 return do_amd_gpio_irq_handler(-1, dev_id); 681 } 682 683 static int amd_get_groups_count(struct pinctrl_dev *pctldev) 684 { 685 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 686 687 return gpio_dev->ngroups; 688 } 689 690 static const char *amd_get_group_name(struct pinctrl_dev *pctldev, 691 unsigned group) 692 { 693 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 694 695 return gpio_dev->groups[group].name; 696 } 697 698 static int amd_get_group_pins(struct pinctrl_dev *pctldev, 699 unsigned group, 700 const unsigned **pins, 701 unsigned *num_pins) 702 { 703 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 704 705 *pins = gpio_dev->groups[group].pins; 706 *num_pins = gpio_dev->groups[group].npins; 707 return 0; 708 } 709 710 static const struct pinctrl_ops amd_pinctrl_ops = { 711 .get_groups_count = amd_get_groups_count, 712 .get_group_name = amd_get_group_name, 713 .get_group_pins = amd_get_group_pins, 714 #ifdef CONFIG_OF 715 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 716 .dt_free_map = pinctrl_utils_free_map, 717 #endif 718 }; 719 720 static int amd_pinconf_get(struct pinctrl_dev *pctldev, 721 unsigned int pin, 722 unsigned long *config) 723 { 724 u32 pin_reg; 725 unsigned arg; 726 unsigned long flags; 727 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 728 enum pin_config_param param = pinconf_to_config_param(*config); 729 730 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 731 pin_reg = readl(gpio_dev->base + pin*4); 732 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 733 switch (param) { 734 case PIN_CONFIG_INPUT_DEBOUNCE: 735 arg = pin_reg & DB_TMR_OUT_MASK; 736 break; 737 738 case PIN_CONFIG_BIAS_PULL_DOWN: 739 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); 740 break; 741 742 case PIN_CONFIG_BIAS_PULL_UP: 743 arg = (pin_reg >> PULL_UP_ENABLE_OFF) & BIT(0); 744 break; 745 746 case PIN_CONFIG_DRIVE_STRENGTH: 747 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; 748 break; 749 750 default: 751 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n", 752 param); 753 return -ENOTSUPP; 754 } 755 756 *config = pinconf_to_config_packed(param, arg); 757 758 return 0; 759 } 760 761 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 762 unsigned long *configs, unsigned int num_configs) 763 { 764 int i; 765 u32 arg; 766 int ret = 0; 767 u32 pin_reg; 768 unsigned long flags; 769 enum pin_config_param param; 770 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 771 772 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 773 for (i = 0; i < num_configs; i++) { 774 param = pinconf_to_config_param(configs[i]); 775 arg = pinconf_to_config_argument(configs[i]); 776 pin_reg = readl(gpio_dev->base + pin*4); 777 778 switch (param) { 779 case PIN_CONFIG_INPUT_DEBOUNCE: 780 ret = amd_gpio_set_debounce(gpio_dev, pin, arg); 781 goto out_unlock; 782 783 case PIN_CONFIG_BIAS_PULL_DOWN: 784 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); 785 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; 786 break; 787 788 case PIN_CONFIG_BIAS_PULL_UP: 789 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); 790 pin_reg |= (arg & BIT(0)) << PULL_UP_ENABLE_OFF; 791 break; 792 793 case PIN_CONFIG_DRIVE_STRENGTH: 794 pin_reg &= ~(DRV_STRENGTH_SEL_MASK 795 << DRV_STRENGTH_SEL_OFF); 796 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) 797 << DRV_STRENGTH_SEL_OFF; 798 break; 799 800 default: 801 dev_err(&gpio_dev->pdev->dev, 802 "Invalid config param %04x\n", param); 803 ret = -ENOTSUPP; 804 } 805 806 writel(pin_reg, gpio_dev->base + pin*4); 807 } 808 out_unlock: 809 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 810 811 return ret; 812 } 813 814 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, 815 unsigned int group, 816 unsigned long *config) 817 { 818 const unsigned *pins; 819 unsigned npins; 820 int ret; 821 822 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 823 if (ret) 824 return ret; 825 826 if (amd_pinconf_get(pctldev, pins[0], config)) 827 return -ENOTSUPP; 828 829 return 0; 830 } 831 832 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, 833 unsigned group, unsigned long *configs, 834 unsigned num_configs) 835 { 836 const unsigned *pins; 837 unsigned npins; 838 int i, ret; 839 840 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 841 if (ret) 842 return ret; 843 for (i = 0; i < npins; i++) { 844 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) 845 return -ENOTSUPP; 846 } 847 return 0; 848 } 849 850 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned int pin, 851 unsigned long config) 852 { 853 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 854 855 return amd_pinconf_set(gpio_dev->pctrl, pin, &config, 1); 856 } 857 858 static const struct pinconf_ops amd_pinconf_ops = { 859 .pin_config_get = amd_pinconf_get, 860 .pin_config_set = amd_pinconf_set, 861 .pin_config_group_get = amd_pinconf_group_get, 862 .pin_config_group_set = amd_pinconf_group_set, 863 }; 864 865 #ifdef CONFIG_PM_SLEEP 866 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) 867 { 868 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 869 870 if (!pd) 871 return false; 872 873 /* 874 * Only restore the pin if it is actually in use by the kernel (or 875 * by userspace). 876 */ 877 if (pd->mux_owner || pd->gpio_owner || 878 gpiochip_line_is_irq(&gpio_dev->gc, pin)) 879 return true; 880 881 return false; 882 } 883 884 static int amd_gpio_suspend(struct device *dev) 885 { 886 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 887 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 888 unsigned long flags; 889 int i; 890 891 for (i = 0; i < desc->npins; i++) { 892 int pin = desc->pins[i].number; 893 894 if (!amd_gpio_should_save(gpio_dev, pin)) 895 continue; 896 897 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 898 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING; 899 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 900 } 901 902 return 0; 903 } 904 905 static int amd_gpio_resume(struct device *dev) 906 { 907 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 908 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 909 unsigned long flags; 910 int i; 911 912 for (i = 0; i < desc->npins; i++) { 913 int pin = desc->pins[i].number; 914 915 if (!amd_gpio_should_save(gpio_dev, pin)) 916 continue; 917 918 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 919 gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING; 920 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin * 4); 921 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 922 } 923 924 return 0; 925 } 926 927 static const struct dev_pm_ops amd_gpio_pm_ops = { 928 SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend, 929 amd_gpio_resume) 930 }; 931 #endif 932 933 static int amd_get_functions_count(struct pinctrl_dev *pctldev) 934 { 935 return ARRAY_SIZE(pmx_functions); 936 } 937 938 static const char *amd_get_fname(struct pinctrl_dev *pctrldev, unsigned int selector) 939 { 940 return pmx_functions[selector].name; 941 } 942 943 static int amd_get_groups(struct pinctrl_dev *pctrldev, unsigned int selector, 944 const char * const **groups, 945 unsigned int * const num_groups) 946 { 947 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev); 948 949 if (!gpio_dev->iomux_base) { 950 dev_err(&gpio_dev->pdev->dev, "iomux function %d group not supported\n", selector); 951 return -EINVAL; 952 } 953 954 *groups = pmx_functions[selector].groups; 955 *num_groups = pmx_functions[selector].ngroups; 956 return 0; 957 } 958 959 static int amd_set_mux(struct pinctrl_dev *pctrldev, unsigned int function, unsigned int group) 960 { 961 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev); 962 struct device *dev = &gpio_dev->pdev->dev; 963 struct pin_desc *pd; 964 int ind, index; 965 966 if (!gpio_dev->iomux_base) 967 return -EINVAL; 968 969 for (index = 0; index < NSELECTS; index++) { 970 if (strcmp(gpio_dev->groups[group].name, pmx_functions[function].groups[index])) 971 continue; 972 973 if (readb(gpio_dev->iomux_base + pmx_functions[function].index) == 974 FUNCTION_INVALID) { 975 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n", 976 pmx_functions[function].index); 977 return -EINVAL; 978 } 979 980 writeb(index, gpio_dev->iomux_base + pmx_functions[function].index); 981 982 if (index != (readb(gpio_dev->iomux_base + pmx_functions[function].index) & 983 FUNCTION_MASK)) { 984 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n", 985 pmx_functions[function].index); 986 return -EINVAL; 987 } 988 989 for (ind = 0; ind < gpio_dev->groups[group].npins; ind++) { 990 if (strncmp(gpio_dev->groups[group].name, "IMX_F", strlen("IMX_F"))) 991 continue; 992 993 pd = pin_desc_get(gpio_dev->pctrl, gpio_dev->groups[group].pins[ind]); 994 pd->mux_owner = gpio_dev->groups[group].name; 995 } 996 break; 997 } 998 999 return 0; 1000 } 1001 1002 static const struct pinmux_ops amd_pmxops = { 1003 .get_functions_count = amd_get_functions_count, 1004 .get_function_name = amd_get_fname, 1005 .get_function_groups = amd_get_groups, 1006 .set_mux = amd_set_mux, 1007 }; 1008 1009 static struct pinctrl_desc amd_pinctrl_desc = { 1010 .pins = kerncz_pins, 1011 .npins = ARRAY_SIZE(kerncz_pins), 1012 .pctlops = &amd_pinctrl_ops, 1013 .pmxops = &amd_pmxops, 1014 .confops = &amd_pinconf_ops, 1015 .owner = THIS_MODULE, 1016 }; 1017 1018 static void amd_get_iomux_res(struct amd_gpio *gpio_dev) 1019 { 1020 struct pinctrl_desc *desc = &amd_pinctrl_desc; 1021 struct device *dev = &gpio_dev->pdev->dev; 1022 int index; 1023 1024 index = device_property_match_string(dev, "pinctrl-resource-names", "iomux"); 1025 if (index < 0) { 1026 dev_dbg(dev, "iomux not supported\n"); 1027 goto out_no_pinmux; 1028 } 1029 1030 gpio_dev->iomux_base = devm_platform_ioremap_resource(gpio_dev->pdev, index); 1031 if (IS_ERR(gpio_dev->iomux_base)) { 1032 dev_dbg(dev, "iomux not supported %d io resource\n", index); 1033 goto out_no_pinmux; 1034 } 1035 1036 return; 1037 1038 out_no_pinmux: 1039 desc->pmxops = NULL; 1040 } 1041 1042 static int amd_gpio_probe(struct platform_device *pdev) 1043 { 1044 int ret = 0; 1045 struct resource *res; 1046 struct amd_gpio *gpio_dev; 1047 struct gpio_irq_chip *girq; 1048 1049 gpio_dev = devm_kzalloc(&pdev->dev, 1050 sizeof(struct amd_gpio), GFP_KERNEL); 1051 if (!gpio_dev) 1052 return -ENOMEM; 1053 1054 raw_spin_lock_init(&gpio_dev->lock); 1055 1056 gpio_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1057 if (IS_ERR(gpio_dev->base)) { 1058 dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); 1059 return PTR_ERR(gpio_dev->base); 1060 } 1061 1062 gpio_dev->irq = platform_get_irq(pdev, 0); 1063 if (gpio_dev->irq < 0) 1064 return gpio_dev->irq; 1065 1066 #ifdef CONFIG_PM_SLEEP 1067 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins, 1068 sizeof(*gpio_dev->saved_regs), 1069 GFP_KERNEL); 1070 if (!gpio_dev->saved_regs) 1071 return -ENOMEM; 1072 #endif 1073 1074 gpio_dev->pdev = pdev; 1075 gpio_dev->gc.get_direction = amd_gpio_get_direction; 1076 gpio_dev->gc.direction_input = amd_gpio_direction_input; 1077 gpio_dev->gc.direction_output = amd_gpio_direction_output; 1078 gpio_dev->gc.get = amd_gpio_get_value; 1079 gpio_dev->gc.set = amd_gpio_set_value; 1080 gpio_dev->gc.set_config = amd_gpio_set_config; 1081 gpio_dev->gc.dbg_show = amd_gpio_dbg_show; 1082 1083 gpio_dev->gc.base = -1; 1084 gpio_dev->gc.label = pdev->name; 1085 gpio_dev->gc.owner = THIS_MODULE; 1086 gpio_dev->gc.parent = &pdev->dev; 1087 gpio_dev->gc.ngpio = resource_size(res) / 4; 1088 1089 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64; 1090 gpio_dev->groups = kerncz_groups; 1091 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); 1092 1093 amd_pinctrl_desc.name = dev_name(&pdev->dev); 1094 amd_get_iomux_res(gpio_dev); 1095 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, 1096 gpio_dev); 1097 if (IS_ERR(gpio_dev->pctrl)) { 1098 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 1099 return PTR_ERR(gpio_dev->pctrl); 1100 } 1101 1102 girq = &gpio_dev->gc.irq; 1103 gpio_irq_chip_set_chip(girq, &amd_gpio_irqchip); 1104 /* This will let us handle the parent IRQ in the driver */ 1105 girq->parent_handler = NULL; 1106 girq->num_parents = 0; 1107 girq->parents = NULL; 1108 girq->default_type = IRQ_TYPE_NONE; 1109 girq->handler = handle_simple_irq; 1110 1111 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); 1112 if (ret) 1113 return ret; 1114 1115 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), 1116 0, 0, gpio_dev->gc.ngpio); 1117 if (ret) { 1118 dev_err(&pdev->dev, "Failed to add pin range\n"); 1119 goto out2; 1120 } 1121 1122 ret = devm_request_irq(&pdev->dev, gpio_dev->irq, amd_gpio_irq_handler, 1123 IRQF_SHARED, KBUILD_MODNAME, gpio_dev); 1124 if (ret) 1125 goto out2; 1126 1127 platform_set_drvdata(pdev, gpio_dev); 1128 acpi_register_wakeup_handler(gpio_dev->irq, amd_gpio_check_wake, gpio_dev); 1129 1130 dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); 1131 return ret; 1132 1133 out2: 1134 gpiochip_remove(&gpio_dev->gc); 1135 1136 return ret; 1137 } 1138 1139 static int amd_gpio_remove(struct platform_device *pdev) 1140 { 1141 struct amd_gpio *gpio_dev; 1142 1143 gpio_dev = platform_get_drvdata(pdev); 1144 1145 gpiochip_remove(&gpio_dev->gc); 1146 acpi_unregister_wakeup_handler(amd_gpio_check_wake, gpio_dev); 1147 1148 return 0; 1149 } 1150 1151 #ifdef CONFIG_ACPI 1152 static const struct acpi_device_id amd_gpio_acpi_match[] = { 1153 { "AMD0030", 0 }, 1154 { "AMDI0030", 0}, 1155 { "AMDI0031", 0}, 1156 { }, 1157 }; 1158 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); 1159 #endif 1160 1161 static struct platform_driver amd_gpio_driver = { 1162 .driver = { 1163 .name = "amd_gpio", 1164 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), 1165 #ifdef CONFIG_PM_SLEEP 1166 .pm = &amd_gpio_pm_ops, 1167 #endif 1168 }, 1169 .probe = amd_gpio_probe, 1170 .remove = amd_gpio_remove, 1171 }; 1172 1173 module_platform_driver(amd_gpio_driver); 1174 1175 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); 1176 MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); 1177