1dbad75ddSKen Xue /* 2dbad75ddSKen Xue * GPIO driver for AMD 3dbad75ddSKen Xue * 4dbad75ddSKen Xue * Copyright (c) 2014,2015 AMD Corporation. 5dbad75ddSKen Xue * Authors: Ken Xue <Ken.Xue@amd.com> 6dbad75ddSKen Xue * Wu, Jeff <Jeff.Wu@amd.com> 7dbad75ddSKen Xue * 8dbad75ddSKen Xue * This program is free software; you can redistribute it and/or modify it 9dbad75ddSKen Xue * under the terms and conditions of the GNU General Public License, 10dbad75ddSKen Xue * version 2, as published by the Free Software Foundation. 11add7bfceSShyam Sundar S K * 12add7bfceSShyam Sundar S K * Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com> 13add7bfceSShyam Sundar S K * Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 14add7bfceSShyam Sundar S K * 15dbad75ddSKen Xue */ 16dbad75ddSKen Xue 17dbad75ddSKen Xue #include <linux/err.h> 18dbad75ddSKen Xue #include <linux/bug.h> 19dbad75ddSKen Xue #include <linux/kernel.h> 20dbad75ddSKen Xue #include <linux/module.h> 21dbad75ddSKen Xue #include <linux/spinlock.h> 22dbad75ddSKen Xue #include <linux/compiler.h> 23dbad75ddSKen Xue #include <linux/types.h> 24dbad75ddSKen Xue #include <linux/errno.h> 25dbad75ddSKen Xue #include <linux/log2.h> 26dbad75ddSKen Xue #include <linux/io.h> 27dbad75ddSKen Xue #include <linux/gpio.h> 28dbad75ddSKen Xue #include <linux/slab.h> 29dbad75ddSKen Xue #include <linux/platform_device.h> 30dbad75ddSKen Xue #include <linux/mutex.h> 31dbad75ddSKen Xue #include <linux/acpi.h> 32dbad75ddSKen Xue #include <linux/seq_file.h> 33dbad75ddSKen Xue #include <linux/interrupt.h> 34dbad75ddSKen Xue #include <linux/list.h> 35dbad75ddSKen Xue #include <linux/bitops.h> 36dbad75ddSKen Xue #include <linux/pinctrl/pinconf.h> 37dbad75ddSKen Xue #include <linux/pinctrl/pinconf-generic.h> 38dbad75ddSKen Xue 3979d2c8beSDaniel Drake #include "core.h" 40dbad75ddSKen Xue #include "pinctrl-utils.h" 41dbad75ddSKen Xue #include "pinctrl-amd.h" 42dbad75ddSKen Xue 43dbad75ddSKen Xue static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 44dbad75ddSKen Xue { 45dbad75ddSKen Xue unsigned long flags; 46dbad75ddSKen Xue u32 pin_reg; 4704d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 48dbad75ddSKen Xue 49229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 50dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 51dbad75ddSKen Xue pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); 52dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4); 53229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 54dbad75ddSKen Xue 55dbad75ddSKen Xue return 0; 56dbad75ddSKen Xue } 57dbad75ddSKen Xue 58dbad75ddSKen Xue static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 59dbad75ddSKen Xue int value) 60dbad75ddSKen Xue { 61dbad75ddSKen Xue u32 pin_reg; 62dbad75ddSKen Xue unsigned long flags; 6304d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 64dbad75ddSKen Xue 65229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 66dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 67dbad75ddSKen Xue pin_reg |= BIT(OUTPUT_ENABLE_OFF); 68dbad75ddSKen Xue if (value) 69dbad75ddSKen Xue pin_reg |= BIT(OUTPUT_VALUE_OFF); 70dbad75ddSKen Xue else 71dbad75ddSKen Xue pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 72dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4); 73229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 74dbad75ddSKen Xue 75dbad75ddSKen Xue return 0; 76dbad75ddSKen Xue } 77dbad75ddSKen Xue 78dbad75ddSKen Xue static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) 79dbad75ddSKen Xue { 80dbad75ddSKen Xue u32 pin_reg; 81dbad75ddSKen Xue unsigned long flags; 8204d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 83dbad75ddSKen Xue 84229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 85dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 86229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 87dbad75ddSKen Xue 88dbad75ddSKen Xue return !!(pin_reg & BIT(PIN_STS_OFF)); 89dbad75ddSKen Xue } 90dbad75ddSKen Xue 91dbad75ddSKen Xue static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) 92dbad75ddSKen Xue { 93dbad75ddSKen Xue u32 pin_reg; 94dbad75ddSKen Xue unsigned long flags; 9504d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 96dbad75ddSKen Xue 97229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 98dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 99dbad75ddSKen Xue if (value) 100dbad75ddSKen Xue pin_reg |= BIT(OUTPUT_VALUE_OFF); 101dbad75ddSKen Xue else 102dbad75ddSKen Xue pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 103dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4); 104229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 105dbad75ddSKen Xue } 106dbad75ddSKen Xue 107dbad75ddSKen Xue static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, 108dbad75ddSKen Xue unsigned debounce) 109dbad75ddSKen Xue { 110dbad75ddSKen Xue u32 time; 11125a853d0SKen Xue u32 pin_reg; 11225a853d0SKen Xue int ret = 0; 113dbad75ddSKen Xue unsigned long flags; 11404d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 115dbad75ddSKen Xue 116229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 117dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 118dbad75ddSKen Xue 119dbad75ddSKen Xue if (debounce) { 120dbad75ddSKen Xue pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 121dbad75ddSKen Xue pin_reg &= ~DB_TMR_OUT_MASK; 122dbad75ddSKen Xue /* 123dbad75ddSKen Xue Debounce Debounce Timer Max 124dbad75ddSKen Xue TmrLarge TmrOutUnit Unit Debounce 125dbad75ddSKen Xue Time 126dbad75ddSKen Xue 0 0 61 usec (2 RtcClk) 976 usec 127dbad75ddSKen Xue 0 1 244 usec (8 RtcClk) 3.9 msec 128dbad75ddSKen Xue 1 0 15.6 msec (512 RtcClk) 250 msec 129dbad75ddSKen Xue 1 1 62.5 msec (2048 RtcClk) 1 sec 130dbad75ddSKen Xue */ 131dbad75ddSKen Xue 132dbad75ddSKen Xue if (debounce < 61) { 133dbad75ddSKen Xue pin_reg |= 1; 134dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 135dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 136dbad75ddSKen Xue } else if (debounce < 976) { 137dbad75ddSKen Xue time = debounce / 61; 138dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK; 139dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 140dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 141dbad75ddSKen Xue } else if (debounce < 3900) { 142dbad75ddSKen Xue time = debounce / 244; 143dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK; 144dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 145dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 146dbad75ddSKen Xue } else if (debounce < 250000) { 147dbad75ddSKen Xue time = debounce / 15600; 148dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK; 149dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 150dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_LARGE_OFF); 151dbad75ddSKen Xue } else if (debounce < 1000000) { 152dbad75ddSKen Xue time = debounce / 62500; 153dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK; 154dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 155dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_LARGE_OFF); 156dbad75ddSKen Xue } else { 157dbad75ddSKen Xue pin_reg &= ~DB_CNTRl_MASK; 15825a853d0SKen Xue ret = -EINVAL; 159dbad75ddSKen Xue } 160dbad75ddSKen Xue } else { 161dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 162dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 163dbad75ddSKen Xue pin_reg &= ~DB_TMR_OUT_MASK; 164dbad75ddSKen Xue pin_reg &= ~DB_CNTRl_MASK; 165dbad75ddSKen Xue } 166dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4); 167229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 168dbad75ddSKen Xue 16925a853d0SKen Xue return ret; 170dbad75ddSKen Xue } 171dbad75ddSKen Xue 1722956b5d9SMika Westerberg static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset, 1732956b5d9SMika Westerberg unsigned long config) 1742956b5d9SMika Westerberg { 1752956b5d9SMika Westerberg u32 debounce; 1762956b5d9SMika Westerberg 1772956b5d9SMika Westerberg if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 1782956b5d9SMika Westerberg return -ENOTSUPP; 1792956b5d9SMika Westerberg 1802956b5d9SMika Westerberg debounce = pinconf_to_config_argument(config); 1812956b5d9SMika Westerberg return amd_gpio_set_debounce(gc, offset, debounce); 1822956b5d9SMika Westerberg } 1832956b5d9SMika Westerberg 184dbad75ddSKen Xue #ifdef CONFIG_DEBUG_FS 185dbad75ddSKen Xue static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) 186dbad75ddSKen Xue { 187dbad75ddSKen Xue u32 pin_reg; 188dbad75ddSKen Xue unsigned long flags; 189dbad75ddSKen Xue unsigned int bank, i, pin_num; 19004d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 191dbad75ddSKen Xue 192dbad75ddSKen Xue char *level_trig; 193dbad75ddSKen Xue char *active_level; 194dbad75ddSKen Xue char *interrupt_enable; 195dbad75ddSKen Xue char *interrupt_mask; 196dbad75ddSKen Xue char *wake_cntrl0; 197dbad75ddSKen Xue char *wake_cntrl1; 198dbad75ddSKen Xue char *wake_cntrl2; 199dbad75ddSKen Xue char *pin_sts; 200dbad75ddSKen Xue char *pull_up_sel; 201dbad75ddSKen Xue char *pull_up_enable; 202dbad75ddSKen Xue char *pull_down_enable; 203dbad75ddSKen Xue char *output_value; 204dbad75ddSKen Xue char *output_enable; 205dbad75ddSKen Xue 2063bfd4430SShah, Nehal-bakulchandra for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { 207dbad75ddSKen Xue seq_printf(s, "GPIO bank%d\t", bank); 208dbad75ddSKen Xue 209dbad75ddSKen Xue switch (bank) { 210dbad75ddSKen Xue case 0: 211dbad75ddSKen Xue i = 0; 212dbad75ddSKen Xue pin_num = AMD_GPIO_PINS_BANK0; 213dbad75ddSKen Xue break; 214dbad75ddSKen Xue case 1: 215dbad75ddSKen Xue i = 64; 216dbad75ddSKen Xue pin_num = AMD_GPIO_PINS_BANK1 + i; 217dbad75ddSKen Xue break; 218dbad75ddSKen Xue case 2: 219dbad75ddSKen Xue i = 128; 220dbad75ddSKen Xue pin_num = AMD_GPIO_PINS_BANK2 + i; 221dbad75ddSKen Xue break; 2223bfd4430SShah, Nehal-bakulchandra case 3: 2233bfd4430SShah, Nehal-bakulchandra i = 192; 2243bfd4430SShah, Nehal-bakulchandra pin_num = AMD_GPIO_PINS_BANK3 + i; 2253bfd4430SShah, Nehal-bakulchandra break; 2266ac4c1adSLinus Walleij default: 2276ac4c1adSLinus Walleij /* Illegal bank number, ignore */ 2286ac4c1adSLinus Walleij continue; 229dbad75ddSKen Xue } 230dbad75ddSKen Xue for (; i < pin_num; i++) { 231dbad75ddSKen Xue seq_printf(s, "pin%d\t", i); 232229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 233dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + i * 4); 234229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 235dbad75ddSKen Xue 236dbad75ddSKen Xue if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { 237dbad75ddSKen Xue interrupt_enable = "interrupt is enabled|"; 238dbad75ddSKen Xue 2393775dac1SDan Carpenter if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) && 2403775dac1SDan Carpenter !(pin_reg & BIT(ACTIVE_LEVEL_OFF + 1))) 241dbad75ddSKen Xue active_level = "Active low|"; 2423775dac1SDan Carpenter else if (pin_reg & BIT(ACTIVE_LEVEL_OFF) && 2433775dac1SDan Carpenter !(pin_reg & BIT(ACTIVE_LEVEL_OFF + 1))) 244dbad75ddSKen Xue active_level = "Active high|"; 2453775dac1SDan Carpenter else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) && 2463775dac1SDan Carpenter pin_reg & BIT(ACTIVE_LEVEL_OFF + 1)) 247dbad75ddSKen Xue active_level = "Active on both|"; 248dbad75ddSKen Xue else 2490a95160eSMasanari Iida active_level = "Unknown Active level|"; 250dbad75ddSKen Xue 251dbad75ddSKen Xue if (pin_reg & BIT(LEVEL_TRIG_OFF)) 252dbad75ddSKen Xue level_trig = "Level trigger|"; 253dbad75ddSKen Xue else 254dbad75ddSKen Xue level_trig = "Edge trigger|"; 255dbad75ddSKen Xue 256dbad75ddSKen Xue } else { 257dbad75ddSKen Xue interrupt_enable = 258dbad75ddSKen Xue "interrupt is disabled|"; 259dbad75ddSKen Xue active_level = " "; 260dbad75ddSKen Xue level_trig = " "; 261dbad75ddSKen Xue } 262dbad75ddSKen Xue 263dbad75ddSKen Xue if (pin_reg & BIT(INTERRUPT_MASK_OFF)) 264dbad75ddSKen Xue interrupt_mask = 265dbad75ddSKen Xue "interrupt is unmasked|"; 266dbad75ddSKen Xue else 267dbad75ddSKen Xue interrupt_mask = 268dbad75ddSKen Xue "interrupt is masked|"; 269dbad75ddSKen Xue 2703bfd4430SShah, Nehal-bakulchandra if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) 271dbad75ddSKen Xue wake_cntrl0 = "enable wakeup in S0i3 state|"; 272dbad75ddSKen Xue else 273dbad75ddSKen Xue wake_cntrl0 = "disable wakeup in S0i3 state|"; 274dbad75ddSKen Xue 2753bfd4430SShah, Nehal-bakulchandra if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) 276dbad75ddSKen Xue wake_cntrl1 = "enable wakeup in S3 state|"; 277dbad75ddSKen Xue else 278dbad75ddSKen Xue wake_cntrl1 = "disable wakeup in S3 state|"; 279dbad75ddSKen Xue 2803bfd4430SShah, Nehal-bakulchandra if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) 281dbad75ddSKen Xue wake_cntrl2 = "enable wakeup in S4/S5 state|"; 282dbad75ddSKen Xue else 283dbad75ddSKen Xue wake_cntrl2 = "disable wakeup in S4/S5 state|"; 284dbad75ddSKen Xue 285dbad75ddSKen Xue if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { 286dbad75ddSKen Xue pull_up_enable = "pull-up is enabled|"; 287dbad75ddSKen Xue if (pin_reg & BIT(PULL_UP_SEL_OFF)) 288dbad75ddSKen Xue pull_up_sel = "8k pull-up|"; 289dbad75ddSKen Xue else 290dbad75ddSKen Xue pull_up_sel = "4k pull-up|"; 291dbad75ddSKen Xue } else { 292dbad75ddSKen Xue pull_up_enable = "pull-up is disabled|"; 293dbad75ddSKen Xue pull_up_sel = " "; 294dbad75ddSKen Xue } 295dbad75ddSKen Xue 296dbad75ddSKen Xue if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) 297dbad75ddSKen Xue pull_down_enable = "pull-down is enabled|"; 298dbad75ddSKen Xue else 299dbad75ddSKen Xue pull_down_enable = "Pull-down is disabled|"; 300dbad75ddSKen Xue 301dbad75ddSKen Xue if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { 302dbad75ddSKen Xue pin_sts = " "; 303dbad75ddSKen Xue output_enable = "output is enabled|"; 304dbad75ddSKen Xue if (pin_reg & BIT(OUTPUT_VALUE_OFF)) 305dbad75ddSKen Xue output_value = "output is high|"; 306dbad75ddSKen Xue else 307dbad75ddSKen Xue output_value = "output is low|"; 308dbad75ddSKen Xue } else { 309dbad75ddSKen Xue output_enable = "output is disabled|"; 310dbad75ddSKen Xue output_value = " "; 311dbad75ddSKen Xue 312dbad75ddSKen Xue if (pin_reg & BIT(PIN_STS_OFF)) 313dbad75ddSKen Xue pin_sts = "input is high|"; 314dbad75ddSKen Xue else 315dbad75ddSKen Xue pin_sts = "input is low|"; 316dbad75ddSKen Xue } 317dbad75ddSKen Xue 318dbad75ddSKen Xue seq_printf(s, "%s %s %s %s %s %s\n" 319dbad75ddSKen Xue " %s %s %s %s %s %s %s 0x%x\n", 320dbad75ddSKen Xue level_trig, active_level, interrupt_enable, 321dbad75ddSKen Xue interrupt_mask, wake_cntrl0, wake_cntrl1, 322dbad75ddSKen Xue wake_cntrl2, pin_sts, pull_up_sel, 323dbad75ddSKen Xue pull_up_enable, pull_down_enable, 324dbad75ddSKen Xue output_value, output_enable, pin_reg); 325dbad75ddSKen Xue } 326dbad75ddSKen Xue } 327dbad75ddSKen Xue } 328dbad75ddSKen Xue #else 329dbad75ddSKen Xue #define amd_gpio_dbg_show NULL 330dbad75ddSKen Xue #endif 331dbad75ddSKen Xue 332dbad75ddSKen Xue static void amd_gpio_irq_enable(struct irq_data *d) 333dbad75ddSKen Xue { 334dbad75ddSKen Xue u32 pin_reg; 335dbad75ddSKen Xue unsigned long flags; 336dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 33704d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 338dbad75ddSKen Xue 339229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 340dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 341dbad75ddSKen Xue pin_reg |= BIT(INTERRUPT_ENABLE_OFF); 342dbad75ddSKen Xue pin_reg |= BIT(INTERRUPT_MASK_OFF); 343dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 344229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 345dbad75ddSKen Xue } 346dbad75ddSKen Xue 347dbad75ddSKen Xue static void amd_gpio_irq_disable(struct irq_data *d) 348dbad75ddSKen Xue { 349dbad75ddSKen Xue u32 pin_reg; 350dbad75ddSKen Xue unsigned long flags; 351dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 35204d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 353dbad75ddSKen Xue 354229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 355dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 356dbad75ddSKen Xue pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); 357dbad75ddSKen Xue pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 358dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 359229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 360dbad75ddSKen Xue } 361dbad75ddSKen Xue 362dbad75ddSKen Xue static void amd_gpio_irq_mask(struct irq_data *d) 363dbad75ddSKen Xue { 364dbad75ddSKen Xue u32 pin_reg; 365dbad75ddSKen Xue unsigned long flags; 366dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 36704d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 368dbad75ddSKen Xue 369229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 370dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 371dbad75ddSKen Xue pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 372dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 373229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 374dbad75ddSKen Xue } 375dbad75ddSKen Xue 376dbad75ddSKen Xue static void amd_gpio_irq_unmask(struct irq_data *d) 377dbad75ddSKen Xue { 378dbad75ddSKen Xue u32 pin_reg; 379dbad75ddSKen Xue unsigned long flags; 380dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 38104d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 382dbad75ddSKen Xue 383229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 384dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 385dbad75ddSKen Xue pin_reg |= BIT(INTERRUPT_MASK_OFF); 386dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 387229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 388dbad75ddSKen Xue } 389dbad75ddSKen Xue 390dbad75ddSKen Xue static void amd_gpio_irq_eoi(struct irq_data *d) 391dbad75ddSKen Xue { 392dbad75ddSKen Xue u32 reg; 393dbad75ddSKen Xue unsigned long flags; 394dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 39504d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 396dbad75ddSKen Xue 397229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 398dbad75ddSKen Xue reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 399dbad75ddSKen Xue reg |= EOI_MASK; 400dbad75ddSKen Xue writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 401229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 402dbad75ddSKen Xue } 403dbad75ddSKen Xue 404dbad75ddSKen Xue static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) 405dbad75ddSKen Xue { 406dbad75ddSKen Xue int ret = 0; 407dbad75ddSKen Xue u32 pin_reg; 4082983f296SShyam Sundar S K unsigned long flags, irq_flags; 409dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 41004d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 411dbad75ddSKen Xue 412229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 413dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 414dbad75ddSKen Xue 4152983f296SShyam Sundar S K /* Ignore the settings coming from the client and 4162983f296SShyam Sundar S K * read the values from the ACPI tables 4172983f296SShyam Sundar S K * while setting the trigger type 418499c7196SAgrawal, Nitesh-kumar */ 419499c7196SAgrawal, Nitesh-kumar 4202983f296SShyam Sundar S K irq_flags = irq_get_trigger_type(d->irq); 4212983f296SShyam Sundar S K if (irq_flags != IRQ_TYPE_NONE) 4222983f296SShyam Sundar S K type = irq_flags; 423499c7196SAgrawal, Nitesh-kumar 424dbad75ddSKen Xue switch (type & IRQ_TYPE_SENSE_MASK) { 425dbad75ddSKen Xue case IRQ_TYPE_EDGE_RISING: 426dbad75ddSKen Xue pin_reg &= ~BIT(LEVEL_TRIG_OFF); 427dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 428dbad75ddSKen Xue pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 429dbad75ddSKen Xue pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 4309d829314SThomas Gleixner irq_set_handler_locked(d, handle_edge_irq); 431dbad75ddSKen Xue break; 432dbad75ddSKen Xue 433dbad75ddSKen Xue case IRQ_TYPE_EDGE_FALLING: 434dbad75ddSKen Xue pin_reg &= ~BIT(LEVEL_TRIG_OFF); 435dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 436dbad75ddSKen Xue pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 437dbad75ddSKen Xue pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 4389d829314SThomas Gleixner irq_set_handler_locked(d, handle_edge_irq); 439dbad75ddSKen Xue break; 440dbad75ddSKen Xue 441dbad75ddSKen Xue case IRQ_TYPE_EDGE_BOTH: 442dbad75ddSKen Xue pin_reg &= ~BIT(LEVEL_TRIG_OFF); 443dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 444dbad75ddSKen Xue pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; 445dbad75ddSKen Xue pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 4469d829314SThomas Gleixner irq_set_handler_locked(d, handle_edge_irq); 447dbad75ddSKen Xue break; 448dbad75ddSKen Xue 449dbad75ddSKen Xue case IRQ_TYPE_LEVEL_HIGH: 450dbad75ddSKen Xue pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 451dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 452dbad75ddSKen Xue pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 453dbad75ddSKen Xue pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 454dbad75ddSKen Xue pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF; 4559d829314SThomas Gleixner irq_set_handler_locked(d, handle_level_irq); 456dbad75ddSKen Xue break; 457dbad75ddSKen Xue 458dbad75ddSKen Xue case IRQ_TYPE_LEVEL_LOW: 459dbad75ddSKen Xue pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 460dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 461dbad75ddSKen Xue pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 462dbad75ddSKen Xue pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 463dbad75ddSKen Xue pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF; 4649d829314SThomas Gleixner irq_set_handler_locked(d, handle_level_irq); 465dbad75ddSKen Xue break; 466dbad75ddSKen Xue 467dbad75ddSKen Xue case IRQ_TYPE_NONE: 468dbad75ddSKen Xue break; 469dbad75ddSKen Xue 470dbad75ddSKen Xue default: 471dbad75ddSKen Xue dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); 472dbad75ddSKen Xue ret = -EINVAL; 473dbad75ddSKen Xue } 474dbad75ddSKen Xue 475dbad75ddSKen Xue pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; 476dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 477229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 478dbad75ddSKen Xue 479dbad75ddSKen Xue return ret; 480dbad75ddSKen Xue } 481dbad75ddSKen Xue 482dbad75ddSKen Xue static void amd_irq_ack(struct irq_data *d) 483dbad75ddSKen Xue { 484dbad75ddSKen Xue /* 485dbad75ddSKen Xue * based on HW design,there is no need to ack HW 486dbad75ddSKen Xue * before handle current irq. But this routine is 487dbad75ddSKen Xue * necessary for handle_edge_irq 488dbad75ddSKen Xue */ 489dbad75ddSKen Xue } 490dbad75ddSKen Xue 491dbad75ddSKen Xue static struct irq_chip amd_gpio_irqchip = { 492dbad75ddSKen Xue .name = "amd_gpio", 493dbad75ddSKen Xue .irq_ack = amd_irq_ack, 494dbad75ddSKen Xue .irq_enable = amd_gpio_irq_enable, 495dbad75ddSKen Xue .irq_disable = amd_gpio_irq_disable, 496dbad75ddSKen Xue .irq_mask = amd_gpio_irq_mask, 497dbad75ddSKen Xue .irq_unmask = amd_gpio_irq_unmask, 498dbad75ddSKen Xue .irq_eoi = amd_gpio_irq_eoi, 499dbad75ddSKen Xue .irq_set_type = amd_gpio_irq_set_type, 5003bfd4430SShah, Nehal-bakulchandra .flags = IRQCHIP_SKIP_SET_WAKE, 501dbad75ddSKen Xue }; 502dbad75ddSKen Xue 503ba714a9cSThomas Gleixner #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF)) 504ba714a9cSThomas Gleixner 505ba714a9cSThomas Gleixner static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id) 506dbad75ddSKen Xue { 507ba714a9cSThomas Gleixner struct amd_gpio *gpio_dev = dev_id; 508ba714a9cSThomas Gleixner struct gpio_chip *gc = &gpio_dev->gc; 509ba714a9cSThomas Gleixner irqreturn_t ret = IRQ_NONE; 510ba714a9cSThomas Gleixner unsigned int i, irqnr; 511dbad75ddSKen Xue unsigned long flags; 512ba714a9cSThomas Gleixner u32 *regs, regval; 513ba714a9cSThomas Gleixner u64 status, mask; 514dbad75ddSKen Xue 515ba714a9cSThomas Gleixner /* Read the wake status */ 516229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 517ba714a9cSThomas Gleixner status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); 518ba714a9cSThomas Gleixner status <<= 32; 519ba714a9cSThomas Gleixner status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0); 520229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 521dbad75ddSKen Xue 522ba714a9cSThomas Gleixner /* Bit 0-45 contain the relevant status bits */ 523ba714a9cSThomas Gleixner status &= (1ULL << 46) - 1; 524ba714a9cSThomas Gleixner regs = gpio_dev->base; 525ba714a9cSThomas Gleixner for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) { 526ba714a9cSThomas Gleixner if (!(status & mask)) 527ba714a9cSThomas Gleixner continue; 528ba714a9cSThomas Gleixner status &= ~mask; 529ba714a9cSThomas Gleixner 530ba714a9cSThomas Gleixner /* Each status bit covers four pins */ 531dbad75ddSKen Xue for (i = 0; i < 4; i++) { 532ba714a9cSThomas Gleixner regval = readl(regs + i); 533ba714a9cSThomas Gleixner if (!(regval & PIN_IRQ_PENDING)) 534ba714a9cSThomas Gleixner continue; 535f0fbe7bcSThierry Reding irq = irq_find_mapping(gc->irq.domain, irqnr + i); 536dbad75ddSKen Xue generic_handle_irq(irq); 537ba714a9cSThomas Gleixner /* Clear interrupt */ 538ba714a9cSThomas Gleixner writel(regval, regs + i); 539ba714a9cSThomas Gleixner ret = IRQ_HANDLED; 540dbad75ddSKen Xue } 541dbad75ddSKen Xue } 542dbad75ddSKen Xue 543ba714a9cSThomas Gleixner /* Signal EOI to the GPIO unit */ 544229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 545ba714a9cSThomas Gleixner regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 546ba714a9cSThomas Gleixner regval |= EOI_MASK; 547ba714a9cSThomas Gleixner writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG); 548229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 549dbad75ddSKen Xue 550ba714a9cSThomas Gleixner return ret; 551dbad75ddSKen Xue } 552dbad75ddSKen Xue 553dbad75ddSKen Xue static int amd_get_groups_count(struct pinctrl_dev *pctldev) 554dbad75ddSKen Xue { 555dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 556dbad75ddSKen Xue 557dbad75ddSKen Xue return gpio_dev->ngroups; 558dbad75ddSKen Xue } 559dbad75ddSKen Xue 560dbad75ddSKen Xue static const char *amd_get_group_name(struct pinctrl_dev *pctldev, 561dbad75ddSKen Xue unsigned group) 562dbad75ddSKen Xue { 563dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 564dbad75ddSKen Xue 565dbad75ddSKen Xue return gpio_dev->groups[group].name; 566dbad75ddSKen Xue } 567dbad75ddSKen Xue 568dbad75ddSKen Xue static int amd_get_group_pins(struct pinctrl_dev *pctldev, 569dbad75ddSKen Xue unsigned group, 570dbad75ddSKen Xue const unsigned **pins, 571dbad75ddSKen Xue unsigned *num_pins) 572dbad75ddSKen Xue { 573dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 574dbad75ddSKen Xue 575dbad75ddSKen Xue *pins = gpio_dev->groups[group].pins; 576dbad75ddSKen Xue *num_pins = gpio_dev->groups[group].npins; 577dbad75ddSKen Xue return 0; 578dbad75ddSKen Xue } 579dbad75ddSKen Xue 580dbad75ddSKen Xue static const struct pinctrl_ops amd_pinctrl_ops = { 581dbad75ddSKen Xue .get_groups_count = amd_get_groups_count, 582dbad75ddSKen Xue .get_group_name = amd_get_group_name, 583dbad75ddSKen Xue .get_group_pins = amd_get_group_pins, 584dbad75ddSKen Xue #ifdef CONFIG_OF 585dbad75ddSKen Xue .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 586d32f7fd3SIrina Tirdea .dt_free_map = pinctrl_utils_free_map, 587dbad75ddSKen Xue #endif 588dbad75ddSKen Xue }; 589dbad75ddSKen Xue 590dbad75ddSKen Xue static int amd_pinconf_get(struct pinctrl_dev *pctldev, 591dbad75ddSKen Xue unsigned int pin, 592dbad75ddSKen Xue unsigned long *config) 593dbad75ddSKen Xue { 594dbad75ddSKen Xue u32 pin_reg; 595dbad75ddSKen Xue unsigned arg; 596dbad75ddSKen Xue unsigned long flags; 597dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 598dbad75ddSKen Xue enum pin_config_param param = pinconf_to_config_param(*config); 599dbad75ddSKen Xue 600229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 601dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + pin*4); 602229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 603dbad75ddSKen Xue switch (param) { 604dbad75ddSKen Xue case PIN_CONFIG_INPUT_DEBOUNCE: 605dbad75ddSKen Xue arg = pin_reg & DB_TMR_OUT_MASK; 606dbad75ddSKen Xue break; 607dbad75ddSKen Xue 608dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_DOWN: 609dbad75ddSKen Xue arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); 610dbad75ddSKen Xue break; 611dbad75ddSKen Xue 612dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_UP: 613dbad75ddSKen Xue arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); 614dbad75ddSKen Xue break; 615dbad75ddSKen Xue 616dbad75ddSKen Xue case PIN_CONFIG_DRIVE_STRENGTH: 617dbad75ddSKen Xue arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; 618dbad75ddSKen Xue break; 619dbad75ddSKen Xue 620dbad75ddSKen Xue default: 621dbad75ddSKen Xue dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n", 622dbad75ddSKen Xue param); 623dbad75ddSKen Xue return -ENOTSUPP; 624dbad75ddSKen Xue } 625dbad75ddSKen Xue 626dbad75ddSKen Xue *config = pinconf_to_config_packed(param, arg); 627dbad75ddSKen Xue 628dbad75ddSKen Xue return 0; 629dbad75ddSKen Xue } 630dbad75ddSKen Xue 631dbad75ddSKen Xue static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 632dbad75ddSKen Xue unsigned long *configs, unsigned num_configs) 633dbad75ddSKen Xue { 634dbad75ddSKen Xue int i; 635dbad75ddSKen Xue u32 arg; 63625a853d0SKen Xue int ret = 0; 63725a853d0SKen Xue u32 pin_reg; 638dbad75ddSKen Xue unsigned long flags; 639dbad75ddSKen Xue enum pin_config_param param; 640dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 641dbad75ddSKen Xue 642229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 643dbad75ddSKen Xue for (i = 0; i < num_configs; i++) { 644dbad75ddSKen Xue param = pinconf_to_config_param(configs[i]); 645dbad75ddSKen Xue arg = pinconf_to_config_argument(configs[i]); 646dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + pin*4); 647dbad75ddSKen Xue 648dbad75ddSKen Xue switch (param) { 649dbad75ddSKen Xue case PIN_CONFIG_INPUT_DEBOUNCE: 650dbad75ddSKen Xue pin_reg &= ~DB_TMR_OUT_MASK; 651dbad75ddSKen Xue pin_reg |= arg & DB_TMR_OUT_MASK; 652dbad75ddSKen Xue break; 653dbad75ddSKen Xue 654dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_DOWN: 655dbad75ddSKen Xue pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); 656dbad75ddSKen Xue pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; 657dbad75ddSKen Xue break; 658dbad75ddSKen Xue 659dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_UP: 660dbad75ddSKen Xue pin_reg &= ~BIT(PULL_UP_SEL_OFF); 661dbad75ddSKen Xue pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; 662dbad75ddSKen Xue pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); 663dbad75ddSKen Xue pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; 664dbad75ddSKen Xue break; 665dbad75ddSKen Xue 666dbad75ddSKen Xue case PIN_CONFIG_DRIVE_STRENGTH: 667dbad75ddSKen Xue pin_reg &= ~(DRV_STRENGTH_SEL_MASK 668dbad75ddSKen Xue << DRV_STRENGTH_SEL_OFF); 669dbad75ddSKen Xue pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) 670dbad75ddSKen Xue << DRV_STRENGTH_SEL_OFF; 671dbad75ddSKen Xue break; 672dbad75ddSKen Xue 673dbad75ddSKen Xue default: 674dbad75ddSKen Xue dev_err(&gpio_dev->pdev->dev, 675dbad75ddSKen Xue "Invalid config param %04x\n", param); 67625a853d0SKen Xue ret = -ENOTSUPP; 677dbad75ddSKen Xue } 678dbad75ddSKen Xue 679dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + pin*4); 680dbad75ddSKen Xue } 681229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 682dbad75ddSKen Xue 68325a853d0SKen Xue return ret; 684dbad75ddSKen Xue } 685dbad75ddSKen Xue 686dbad75ddSKen Xue static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, 687dbad75ddSKen Xue unsigned int group, 688dbad75ddSKen Xue unsigned long *config) 689dbad75ddSKen Xue { 690dbad75ddSKen Xue const unsigned *pins; 691dbad75ddSKen Xue unsigned npins; 692dbad75ddSKen Xue int ret; 693dbad75ddSKen Xue 694dbad75ddSKen Xue ret = amd_get_group_pins(pctldev, group, &pins, &npins); 695dbad75ddSKen Xue if (ret) 696dbad75ddSKen Xue return ret; 697dbad75ddSKen Xue 698dbad75ddSKen Xue if (amd_pinconf_get(pctldev, pins[0], config)) 699dbad75ddSKen Xue return -ENOTSUPP; 700dbad75ddSKen Xue 701dbad75ddSKen Xue return 0; 702dbad75ddSKen Xue } 703dbad75ddSKen Xue 704dbad75ddSKen Xue static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, 705dbad75ddSKen Xue unsigned group, unsigned long *configs, 706dbad75ddSKen Xue unsigned num_configs) 707dbad75ddSKen Xue { 708dbad75ddSKen Xue const unsigned *pins; 709dbad75ddSKen Xue unsigned npins; 710dbad75ddSKen Xue int i, ret; 711dbad75ddSKen Xue 712dbad75ddSKen Xue ret = amd_get_group_pins(pctldev, group, &pins, &npins); 713dbad75ddSKen Xue if (ret) 714dbad75ddSKen Xue return ret; 715dbad75ddSKen Xue for (i = 0; i < npins; i++) { 716dbad75ddSKen Xue if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) 717dbad75ddSKen Xue return -ENOTSUPP; 718dbad75ddSKen Xue } 719dbad75ddSKen Xue return 0; 720dbad75ddSKen Xue } 721dbad75ddSKen Xue 722dbad75ddSKen Xue static const struct pinconf_ops amd_pinconf_ops = { 723dbad75ddSKen Xue .pin_config_get = amd_pinconf_get, 724dbad75ddSKen Xue .pin_config_set = amd_pinconf_set, 725dbad75ddSKen Xue .pin_config_group_get = amd_pinconf_group_get, 726dbad75ddSKen Xue .pin_config_group_set = amd_pinconf_group_set, 727dbad75ddSKen Xue }; 728dbad75ddSKen Xue 72979d2c8beSDaniel Drake #ifdef CONFIG_PM_SLEEP 73079d2c8beSDaniel Drake static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) 73179d2c8beSDaniel Drake { 73279d2c8beSDaniel Drake const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 73379d2c8beSDaniel Drake 73479d2c8beSDaniel Drake if (!pd) 73579d2c8beSDaniel Drake return false; 73679d2c8beSDaniel Drake 73779d2c8beSDaniel Drake /* 73879d2c8beSDaniel Drake * Only restore the pin if it is actually in use by the kernel (or 73979d2c8beSDaniel Drake * by userspace). 74079d2c8beSDaniel Drake */ 74179d2c8beSDaniel Drake if (pd->mux_owner || pd->gpio_owner || 74279d2c8beSDaniel Drake gpiochip_line_is_irq(&gpio_dev->gc, pin)) 74379d2c8beSDaniel Drake return true; 74479d2c8beSDaniel Drake 74579d2c8beSDaniel Drake return false; 74679d2c8beSDaniel Drake } 74779d2c8beSDaniel Drake 74879d2c8beSDaniel Drake int amd_gpio_suspend(struct device *dev) 74979d2c8beSDaniel Drake { 75079d2c8beSDaniel Drake struct platform_device *pdev = to_platform_device(dev); 75179d2c8beSDaniel Drake struct amd_gpio *gpio_dev = platform_get_drvdata(pdev); 75279d2c8beSDaniel Drake struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 75379d2c8beSDaniel Drake int i; 75479d2c8beSDaniel Drake 75579d2c8beSDaniel Drake for (i = 0; i < desc->npins; i++) { 75679d2c8beSDaniel Drake int pin = desc->pins[i].number; 75779d2c8beSDaniel Drake 75879d2c8beSDaniel Drake if (!amd_gpio_should_save(gpio_dev, pin)) 75979d2c8beSDaniel Drake continue; 76079d2c8beSDaniel Drake 76179d2c8beSDaniel Drake gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin*4); 76279d2c8beSDaniel Drake } 76379d2c8beSDaniel Drake 76479d2c8beSDaniel Drake return 0; 76579d2c8beSDaniel Drake } 76679d2c8beSDaniel Drake 76779d2c8beSDaniel Drake int amd_gpio_resume(struct device *dev) 76879d2c8beSDaniel Drake { 76979d2c8beSDaniel Drake struct platform_device *pdev = to_platform_device(dev); 77079d2c8beSDaniel Drake struct amd_gpio *gpio_dev = platform_get_drvdata(pdev); 77179d2c8beSDaniel Drake struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 77279d2c8beSDaniel Drake int i; 77379d2c8beSDaniel Drake 77479d2c8beSDaniel Drake for (i = 0; i < desc->npins; i++) { 77579d2c8beSDaniel Drake int pin = desc->pins[i].number; 77679d2c8beSDaniel Drake 77779d2c8beSDaniel Drake if (!amd_gpio_should_save(gpio_dev, pin)) 77879d2c8beSDaniel Drake continue; 77979d2c8beSDaniel Drake 78079d2c8beSDaniel Drake writel(gpio_dev->saved_regs[i], gpio_dev->base + pin*4); 78179d2c8beSDaniel Drake } 78279d2c8beSDaniel Drake 78379d2c8beSDaniel Drake return 0; 78479d2c8beSDaniel Drake } 78579d2c8beSDaniel Drake 78679d2c8beSDaniel Drake static const struct dev_pm_ops amd_gpio_pm_ops = { 78779d2c8beSDaniel Drake SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend, 78879d2c8beSDaniel Drake amd_gpio_resume) 78979d2c8beSDaniel Drake }; 79079d2c8beSDaniel Drake #endif 79179d2c8beSDaniel Drake 792dbad75ddSKen Xue static struct pinctrl_desc amd_pinctrl_desc = { 793dbad75ddSKen Xue .pins = kerncz_pins, 794dbad75ddSKen Xue .npins = ARRAY_SIZE(kerncz_pins), 795dbad75ddSKen Xue .pctlops = &amd_pinctrl_ops, 796dbad75ddSKen Xue .confops = &amd_pinconf_ops, 797dbad75ddSKen Xue .owner = THIS_MODULE, 798dbad75ddSKen Xue }; 799dbad75ddSKen Xue 800dbad75ddSKen Xue static int amd_gpio_probe(struct platform_device *pdev) 801dbad75ddSKen Xue { 802dbad75ddSKen Xue int ret = 0; 80325a853d0SKen Xue int irq_base; 804dbad75ddSKen Xue struct resource *res; 805dbad75ddSKen Xue struct amd_gpio *gpio_dev; 806dbad75ddSKen Xue 807dbad75ddSKen Xue gpio_dev = devm_kzalloc(&pdev->dev, 808dbad75ddSKen Xue sizeof(struct amd_gpio), GFP_KERNEL); 809dbad75ddSKen Xue if (!gpio_dev) 810dbad75ddSKen Xue return -ENOMEM; 811dbad75ddSKen Xue 812229710feSJulia Cartwright raw_spin_lock_init(&gpio_dev->lock); 813dbad75ddSKen Xue 814dbad75ddSKen Xue res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 815dbad75ddSKen Xue if (!res) { 816dbad75ddSKen Xue dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); 817dbad75ddSKen Xue return -EINVAL; 818dbad75ddSKen Xue } 819dbad75ddSKen Xue 820dbad75ddSKen Xue gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start, 821dbad75ddSKen Xue resource_size(res)); 822424a6c60SWei Yongjun if (!gpio_dev->base) 823424a6c60SWei Yongjun return -ENOMEM; 824dbad75ddSKen Xue 825dbad75ddSKen Xue irq_base = platform_get_irq(pdev, 0); 826dbad75ddSKen Xue if (irq_base < 0) { 8272e6424abSGustavo A. R. Silva dev_err(&pdev->dev, "Failed to get gpio IRQ: %d\n", irq_base); 8282e6424abSGustavo A. R. Silva return irq_base; 829dbad75ddSKen Xue } 830dbad75ddSKen Xue 83179d2c8beSDaniel Drake #ifdef CONFIG_PM_SLEEP 83279d2c8beSDaniel Drake gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins, 83379d2c8beSDaniel Drake sizeof(*gpio_dev->saved_regs), 83479d2c8beSDaniel Drake GFP_KERNEL); 83579d2c8beSDaniel Drake if (!gpio_dev->saved_regs) 83679d2c8beSDaniel Drake return -ENOMEM; 83779d2c8beSDaniel Drake #endif 83879d2c8beSDaniel Drake 839dbad75ddSKen Xue gpio_dev->pdev = pdev; 840dbad75ddSKen Xue gpio_dev->gc.direction_input = amd_gpio_direction_input; 841dbad75ddSKen Xue gpio_dev->gc.direction_output = amd_gpio_direction_output; 842dbad75ddSKen Xue gpio_dev->gc.get = amd_gpio_get_value; 843dbad75ddSKen Xue gpio_dev->gc.set = amd_gpio_set_value; 8442956b5d9SMika Westerberg gpio_dev->gc.set_config = amd_gpio_set_config; 845dbad75ddSKen Xue gpio_dev->gc.dbg_show = amd_gpio_dbg_show; 846dbad75ddSKen Xue 8473bfd4430SShah, Nehal-bakulchandra gpio_dev->gc.base = -1; 848dbad75ddSKen Xue gpio_dev->gc.label = pdev->name; 849dbad75ddSKen Xue gpio_dev->gc.owner = THIS_MODULE; 85058383c78SLinus Walleij gpio_dev->gc.parent = &pdev->dev; 8513bfd4430SShah, Nehal-bakulchandra gpio_dev->gc.ngpio = resource_size(res) / 4; 852dbad75ddSKen Xue #if defined(CONFIG_OF_GPIO) 853dbad75ddSKen Xue gpio_dev->gc.of_node = pdev->dev.of_node; 854dbad75ddSKen Xue #endif 855dbad75ddSKen Xue 8563bfd4430SShah, Nehal-bakulchandra gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64; 857dbad75ddSKen Xue gpio_dev->groups = kerncz_groups; 858dbad75ddSKen Xue gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); 859dbad75ddSKen Xue 860dbad75ddSKen Xue amd_pinctrl_desc.name = dev_name(&pdev->dev); 861251e22abSLaxman Dewangan gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, 862251e22abSLaxman Dewangan gpio_dev); 863323de9efSMasahiro Yamada if (IS_ERR(gpio_dev->pctrl)) { 864dbad75ddSKen Xue dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 865323de9efSMasahiro Yamada return PTR_ERR(gpio_dev->pctrl); 866dbad75ddSKen Xue } 867dbad75ddSKen Xue 86804d36723SLinus Walleij ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); 869dbad75ddSKen Xue if (ret) 870251e22abSLaxman Dewangan return ret; 871dbad75ddSKen Xue 872dbad75ddSKen Xue ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), 8733bfd4430SShah, Nehal-bakulchandra 0, 0, gpio_dev->gc.ngpio); 874dbad75ddSKen Xue if (ret) { 875dbad75ddSKen Xue dev_err(&pdev->dev, "Failed to add pin range\n"); 876dbad75ddSKen Xue goto out2; 877dbad75ddSKen Xue } 878dbad75ddSKen Xue 879dbad75ddSKen Xue ret = gpiochip_irqchip_add(&gpio_dev->gc, 880dbad75ddSKen Xue &amd_gpio_irqchip, 881dbad75ddSKen Xue 0, 882dbad75ddSKen Xue handle_simple_irq, 883dbad75ddSKen Xue IRQ_TYPE_NONE); 884dbad75ddSKen Xue if (ret) { 885dbad75ddSKen Xue dev_err(&pdev->dev, "could not add irqchip\n"); 886dbad75ddSKen Xue ret = -ENODEV; 887dbad75ddSKen Xue goto out2; 888dbad75ddSKen Xue } 889dbad75ddSKen Xue 890ba714a9cSThomas Gleixner ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, 0, 891ba714a9cSThomas Gleixner KBUILD_MODNAME, gpio_dev); 892ba714a9cSThomas Gleixner if (ret) 893ba714a9cSThomas Gleixner goto out2; 894ba714a9cSThomas Gleixner 895dbad75ddSKen Xue platform_set_drvdata(pdev, gpio_dev); 896dbad75ddSKen Xue 897dbad75ddSKen Xue dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); 898dbad75ddSKen Xue return ret; 899dbad75ddSKen Xue 900dbad75ddSKen Xue out2: 901dbad75ddSKen Xue gpiochip_remove(&gpio_dev->gc); 902dbad75ddSKen Xue 903dbad75ddSKen Xue return ret; 904dbad75ddSKen Xue } 905dbad75ddSKen Xue 906dbad75ddSKen Xue static int amd_gpio_remove(struct platform_device *pdev) 907dbad75ddSKen Xue { 908dbad75ddSKen Xue struct amd_gpio *gpio_dev; 909dbad75ddSKen Xue 910dbad75ddSKen Xue gpio_dev = platform_get_drvdata(pdev); 911dbad75ddSKen Xue 912dbad75ddSKen Xue gpiochip_remove(&gpio_dev->gc); 913dbad75ddSKen Xue 914dbad75ddSKen Xue return 0; 915dbad75ddSKen Xue } 916dbad75ddSKen Xue 917dbad75ddSKen Xue static const struct acpi_device_id amd_gpio_acpi_match[] = { 918dbad75ddSKen Xue { "AMD0030", 0 }, 91942a44402SWang Hongcheng { "AMDI0030", 0}, 920dbad75ddSKen Xue { }, 921dbad75ddSKen Xue }; 922dbad75ddSKen Xue MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); 923dbad75ddSKen Xue 924dbad75ddSKen Xue static struct platform_driver amd_gpio_driver = { 925dbad75ddSKen Xue .driver = { 926dbad75ddSKen Xue .name = "amd_gpio", 927dbad75ddSKen Xue .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), 92879d2c8beSDaniel Drake #ifdef CONFIG_PM_SLEEP 92979d2c8beSDaniel Drake .pm = &amd_gpio_pm_ops, 93079d2c8beSDaniel Drake #endif 931dbad75ddSKen Xue }, 932dbad75ddSKen Xue .probe = amd_gpio_probe, 933dbad75ddSKen Xue .remove = amd_gpio_remove, 934dbad75ddSKen Xue }; 935dbad75ddSKen Xue 936dbad75ddSKen Xue module_platform_driver(amd_gpio_driver); 937dbad75ddSKen Xue 938dbad75ddSKen Xue MODULE_LICENSE("GPL v2"); 939dbad75ddSKen Xue MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); 940dbad75ddSKen Xue MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); 941