1dbad75ddSKen Xue /* 2dbad75ddSKen Xue * GPIO driver for AMD 3dbad75ddSKen Xue * 4dbad75ddSKen Xue * Copyright (c) 2014,2015 AMD Corporation. 5dbad75ddSKen Xue * Authors: Ken Xue <Ken.Xue@amd.com> 6dbad75ddSKen Xue * Wu, Jeff <Jeff.Wu@amd.com> 7dbad75ddSKen Xue * 8dbad75ddSKen Xue * This program is free software; you can redistribute it and/or modify it 9dbad75ddSKen Xue * under the terms and conditions of the GNU General Public License, 10dbad75ddSKen Xue * version 2, as published by the Free Software Foundation. 11dbad75ddSKen Xue */ 12dbad75ddSKen Xue 13dbad75ddSKen Xue #include <linux/err.h> 14dbad75ddSKen Xue #include <linux/bug.h> 15dbad75ddSKen Xue #include <linux/kernel.h> 16dbad75ddSKen Xue #include <linux/module.h> 17dbad75ddSKen Xue #include <linux/spinlock.h> 18dbad75ddSKen Xue #include <linux/compiler.h> 19dbad75ddSKen Xue #include <linux/types.h> 20dbad75ddSKen Xue #include <linux/errno.h> 21dbad75ddSKen Xue #include <linux/log2.h> 22dbad75ddSKen Xue #include <linux/io.h> 23dbad75ddSKen Xue #include <linux/gpio.h> 24dbad75ddSKen Xue #include <linux/slab.h> 25dbad75ddSKen Xue #include <linux/platform_device.h> 26dbad75ddSKen Xue #include <linux/mutex.h> 27dbad75ddSKen Xue #include <linux/acpi.h> 28dbad75ddSKen Xue #include <linux/seq_file.h> 29dbad75ddSKen Xue #include <linux/interrupt.h> 30dbad75ddSKen Xue #include <linux/list.h> 31dbad75ddSKen Xue #include <linux/bitops.h> 32dbad75ddSKen Xue #include <linux/pinctrl/pinconf.h> 33dbad75ddSKen Xue #include <linux/pinctrl/pinconf-generic.h> 34dbad75ddSKen Xue 35dbad75ddSKen Xue #include "pinctrl-utils.h" 36dbad75ddSKen Xue #include "pinctrl-amd.h" 37dbad75ddSKen Xue 38dbad75ddSKen Xue static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 39dbad75ddSKen Xue { 40dbad75ddSKen Xue unsigned long flags; 41dbad75ddSKen Xue u32 pin_reg; 4204d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 43dbad75ddSKen Xue 44dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 45dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 46dbad75ddSKen Xue /* 47dbad75ddSKen Xue * Suppose BIOS or Bootloader sets specific debounce for the 48dbad75ddSKen Xue * GPIO. if not, set debounce to be 2.75ms and remove glitch. 49dbad75ddSKen Xue */ 50dbad75ddSKen Xue if ((pin_reg & DB_TMR_OUT_MASK) == 0) { 51dbad75ddSKen Xue pin_reg |= 0xf; 52dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 53dbad75ddSKen Xue pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 54dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 55dbad75ddSKen Xue } 56dbad75ddSKen Xue 57dbad75ddSKen Xue pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); 58dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4); 59dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 60dbad75ddSKen Xue 61dbad75ddSKen Xue return 0; 62dbad75ddSKen Xue } 63dbad75ddSKen Xue 64dbad75ddSKen Xue static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 65dbad75ddSKen Xue int value) 66dbad75ddSKen Xue { 67dbad75ddSKen Xue u32 pin_reg; 68dbad75ddSKen Xue unsigned long flags; 6904d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 70dbad75ddSKen Xue 71dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 72dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 73dbad75ddSKen Xue pin_reg |= BIT(OUTPUT_ENABLE_OFF); 74dbad75ddSKen Xue if (value) 75dbad75ddSKen Xue pin_reg |= BIT(OUTPUT_VALUE_OFF); 76dbad75ddSKen Xue else 77dbad75ddSKen Xue pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 78dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4); 79dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 80dbad75ddSKen Xue 81dbad75ddSKen Xue return 0; 82dbad75ddSKen Xue } 83dbad75ddSKen Xue 84dbad75ddSKen Xue static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) 85dbad75ddSKen Xue { 86dbad75ddSKen Xue u32 pin_reg; 87dbad75ddSKen Xue unsigned long flags; 8804d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 89dbad75ddSKen Xue 90dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 91dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 92dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 93dbad75ddSKen Xue 94dbad75ddSKen Xue return !!(pin_reg & BIT(PIN_STS_OFF)); 95dbad75ddSKen Xue } 96dbad75ddSKen Xue 97dbad75ddSKen Xue static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) 98dbad75ddSKen Xue { 99dbad75ddSKen Xue u32 pin_reg; 100dbad75ddSKen Xue unsigned long flags; 10104d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 102dbad75ddSKen Xue 103dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 104dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 105dbad75ddSKen Xue if (value) 106dbad75ddSKen Xue pin_reg |= BIT(OUTPUT_VALUE_OFF); 107dbad75ddSKen Xue else 108dbad75ddSKen Xue pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 109dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4); 110dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 111dbad75ddSKen Xue } 112dbad75ddSKen Xue 113dbad75ddSKen Xue static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, 114dbad75ddSKen Xue unsigned debounce) 115dbad75ddSKen Xue { 116dbad75ddSKen Xue u32 time; 11725a853d0SKen Xue u32 pin_reg; 11825a853d0SKen Xue int ret = 0; 119dbad75ddSKen Xue unsigned long flags; 12004d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 121dbad75ddSKen Xue 122dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 123dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 124dbad75ddSKen Xue 125dbad75ddSKen Xue if (debounce) { 126dbad75ddSKen Xue pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 127dbad75ddSKen Xue pin_reg &= ~DB_TMR_OUT_MASK; 128dbad75ddSKen Xue /* 129dbad75ddSKen Xue Debounce Debounce Timer Max 130dbad75ddSKen Xue TmrLarge TmrOutUnit Unit Debounce 131dbad75ddSKen Xue Time 132dbad75ddSKen Xue 0 0 61 usec (2 RtcClk) 976 usec 133dbad75ddSKen Xue 0 1 244 usec (8 RtcClk) 3.9 msec 134dbad75ddSKen Xue 1 0 15.6 msec (512 RtcClk) 250 msec 135dbad75ddSKen Xue 1 1 62.5 msec (2048 RtcClk) 1 sec 136dbad75ddSKen Xue */ 137dbad75ddSKen Xue 138dbad75ddSKen Xue if (debounce < 61) { 139dbad75ddSKen Xue pin_reg |= 1; 140dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 141dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 142dbad75ddSKen Xue } else if (debounce < 976) { 143dbad75ddSKen Xue time = debounce / 61; 144dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK; 145dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 146dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 147dbad75ddSKen Xue } else if (debounce < 3900) { 148dbad75ddSKen Xue time = debounce / 244; 149dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK; 150dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 151dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 152dbad75ddSKen Xue } else if (debounce < 250000) { 153dbad75ddSKen Xue time = debounce / 15600; 154dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK; 155dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 156dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_LARGE_OFF); 157dbad75ddSKen Xue } else if (debounce < 1000000) { 158dbad75ddSKen Xue time = debounce / 62500; 159dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK; 160dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 161dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_LARGE_OFF); 162dbad75ddSKen Xue } else { 163dbad75ddSKen Xue pin_reg &= ~DB_CNTRl_MASK; 16425a853d0SKen Xue ret = -EINVAL; 165dbad75ddSKen Xue } 166dbad75ddSKen Xue } else { 167dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 168dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 169dbad75ddSKen Xue pin_reg &= ~DB_TMR_OUT_MASK; 170dbad75ddSKen Xue pin_reg &= ~DB_CNTRl_MASK; 171dbad75ddSKen Xue } 172dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4); 173dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 174dbad75ddSKen Xue 17525a853d0SKen Xue return ret; 176dbad75ddSKen Xue } 177dbad75ddSKen Xue 178dbad75ddSKen Xue #ifdef CONFIG_DEBUG_FS 179dbad75ddSKen Xue static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) 180dbad75ddSKen Xue { 181dbad75ddSKen Xue u32 pin_reg; 182dbad75ddSKen Xue unsigned long flags; 183dbad75ddSKen Xue unsigned int bank, i, pin_num; 18404d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 185dbad75ddSKen Xue 186dbad75ddSKen Xue char *level_trig; 187dbad75ddSKen Xue char *active_level; 188dbad75ddSKen Xue char *interrupt_enable; 189dbad75ddSKen Xue char *interrupt_mask; 190dbad75ddSKen Xue char *wake_cntrl0; 191dbad75ddSKen Xue char *wake_cntrl1; 192dbad75ddSKen Xue char *wake_cntrl2; 193dbad75ddSKen Xue char *pin_sts; 194dbad75ddSKen Xue char *pull_up_sel; 195dbad75ddSKen Xue char *pull_up_enable; 196dbad75ddSKen Xue char *pull_down_enable; 197dbad75ddSKen Xue char *output_value; 198dbad75ddSKen Xue char *output_enable; 199dbad75ddSKen Xue 200dbad75ddSKen Xue for (bank = 0; bank < AMD_GPIO_TOTAL_BANKS; bank++) { 201dbad75ddSKen Xue seq_printf(s, "GPIO bank%d\t", bank); 202dbad75ddSKen Xue 203dbad75ddSKen Xue switch (bank) { 204dbad75ddSKen Xue case 0: 205dbad75ddSKen Xue i = 0; 206dbad75ddSKen Xue pin_num = AMD_GPIO_PINS_BANK0; 207dbad75ddSKen Xue break; 208dbad75ddSKen Xue case 1: 209dbad75ddSKen Xue i = 64; 210dbad75ddSKen Xue pin_num = AMD_GPIO_PINS_BANK1 + i; 211dbad75ddSKen Xue break; 212dbad75ddSKen Xue case 2: 213dbad75ddSKen Xue i = 128; 214dbad75ddSKen Xue pin_num = AMD_GPIO_PINS_BANK2 + i; 215dbad75ddSKen Xue break; 216dbad75ddSKen Xue } 217dbad75ddSKen Xue 218dbad75ddSKen Xue for (; i < pin_num; i++) { 219dbad75ddSKen Xue seq_printf(s, "pin%d\t", i); 220dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 221dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + i * 4); 222dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 223dbad75ddSKen Xue 224dbad75ddSKen Xue if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { 225dbad75ddSKen Xue interrupt_enable = "interrupt is enabled|"; 226dbad75ddSKen Xue 227dbad75ddSKen Xue if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) 228dbad75ddSKen Xue && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1))) 229dbad75ddSKen Xue active_level = "Active low|"; 230dbad75ddSKen Xue else if (pin_reg & BIT(ACTIVE_LEVEL_OFF) 231dbad75ddSKen Xue && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1))) 232dbad75ddSKen Xue active_level = "Active high|"; 233dbad75ddSKen Xue else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) 234dbad75ddSKen Xue && pin_reg & BIT(ACTIVE_LEVEL_OFF+1)) 235dbad75ddSKen Xue active_level = "Active on both|"; 236dbad75ddSKen Xue else 237dbad75ddSKen Xue active_level = "Unknow Active level|"; 238dbad75ddSKen Xue 239dbad75ddSKen Xue if (pin_reg & BIT(LEVEL_TRIG_OFF)) 240dbad75ddSKen Xue level_trig = "Level trigger|"; 241dbad75ddSKen Xue else 242dbad75ddSKen Xue level_trig = "Edge trigger|"; 243dbad75ddSKen Xue 244dbad75ddSKen Xue } else { 245dbad75ddSKen Xue interrupt_enable = 246dbad75ddSKen Xue "interrupt is disabled|"; 247dbad75ddSKen Xue active_level = " "; 248dbad75ddSKen Xue level_trig = " "; 249dbad75ddSKen Xue } 250dbad75ddSKen Xue 251dbad75ddSKen Xue if (pin_reg & BIT(INTERRUPT_MASK_OFF)) 252dbad75ddSKen Xue interrupt_mask = 253dbad75ddSKen Xue "interrupt is unmasked|"; 254dbad75ddSKen Xue else 255dbad75ddSKen Xue interrupt_mask = 256dbad75ddSKen Xue "interrupt is masked|"; 257dbad75ddSKen Xue 258dbad75ddSKen Xue if (pin_reg & BIT(WAKE_CNTRL_OFF)) 259dbad75ddSKen Xue wake_cntrl0 = "enable wakeup in S0i3 state|"; 260dbad75ddSKen Xue else 261dbad75ddSKen Xue wake_cntrl0 = "disable wakeup in S0i3 state|"; 262dbad75ddSKen Xue 263dbad75ddSKen Xue if (pin_reg & BIT(WAKE_CNTRL_OFF)) 264dbad75ddSKen Xue wake_cntrl1 = "enable wakeup in S3 state|"; 265dbad75ddSKen Xue else 266dbad75ddSKen Xue wake_cntrl1 = "disable wakeup in S3 state|"; 267dbad75ddSKen Xue 268dbad75ddSKen Xue if (pin_reg & BIT(WAKE_CNTRL_OFF)) 269dbad75ddSKen Xue wake_cntrl2 = "enable wakeup in S4/S5 state|"; 270dbad75ddSKen Xue else 271dbad75ddSKen Xue wake_cntrl2 = "disable wakeup in S4/S5 state|"; 272dbad75ddSKen Xue 273dbad75ddSKen Xue if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { 274dbad75ddSKen Xue pull_up_enable = "pull-up is enabled|"; 275dbad75ddSKen Xue if (pin_reg & BIT(PULL_UP_SEL_OFF)) 276dbad75ddSKen Xue pull_up_sel = "8k pull-up|"; 277dbad75ddSKen Xue else 278dbad75ddSKen Xue pull_up_sel = "4k pull-up|"; 279dbad75ddSKen Xue } else { 280dbad75ddSKen Xue pull_up_enable = "pull-up is disabled|"; 281dbad75ddSKen Xue pull_up_sel = " "; 282dbad75ddSKen Xue } 283dbad75ddSKen Xue 284dbad75ddSKen Xue if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) 285dbad75ddSKen Xue pull_down_enable = "pull-down is enabled|"; 286dbad75ddSKen Xue else 287dbad75ddSKen Xue pull_down_enable = "Pull-down is disabled|"; 288dbad75ddSKen Xue 289dbad75ddSKen Xue if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { 290dbad75ddSKen Xue pin_sts = " "; 291dbad75ddSKen Xue output_enable = "output is enabled|"; 292dbad75ddSKen Xue if (pin_reg & BIT(OUTPUT_VALUE_OFF)) 293dbad75ddSKen Xue output_value = "output is high|"; 294dbad75ddSKen Xue else 295dbad75ddSKen Xue output_value = "output is low|"; 296dbad75ddSKen Xue } else { 297dbad75ddSKen Xue output_enable = "output is disabled|"; 298dbad75ddSKen Xue output_value = " "; 299dbad75ddSKen Xue 300dbad75ddSKen Xue if (pin_reg & BIT(PIN_STS_OFF)) 301dbad75ddSKen Xue pin_sts = "input is high|"; 302dbad75ddSKen Xue else 303dbad75ddSKen Xue pin_sts = "input is low|"; 304dbad75ddSKen Xue } 305dbad75ddSKen Xue 306dbad75ddSKen Xue seq_printf(s, "%s %s %s %s %s %s\n" 307dbad75ddSKen Xue " %s %s %s %s %s %s %s 0x%x\n", 308dbad75ddSKen Xue level_trig, active_level, interrupt_enable, 309dbad75ddSKen Xue interrupt_mask, wake_cntrl0, wake_cntrl1, 310dbad75ddSKen Xue wake_cntrl2, pin_sts, pull_up_sel, 311dbad75ddSKen Xue pull_up_enable, pull_down_enable, 312dbad75ddSKen Xue output_value, output_enable, pin_reg); 313dbad75ddSKen Xue } 314dbad75ddSKen Xue } 315dbad75ddSKen Xue } 316dbad75ddSKen Xue #else 317dbad75ddSKen Xue #define amd_gpio_dbg_show NULL 318dbad75ddSKen Xue #endif 319dbad75ddSKen Xue 320dbad75ddSKen Xue static void amd_gpio_irq_enable(struct irq_data *d) 321dbad75ddSKen Xue { 322dbad75ddSKen Xue u32 pin_reg; 323dbad75ddSKen Xue unsigned long flags; 324dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 32504d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 326dbad75ddSKen Xue 327dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 328dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 329dbad75ddSKen Xue /* 330dbad75ddSKen Xue Suppose BIOS or Bootloader sets specific debounce for the 331dbad75ddSKen Xue GPIO. if not, set debounce to be 2.75ms. 332dbad75ddSKen Xue */ 333dbad75ddSKen Xue if ((pin_reg & DB_TMR_OUT_MASK) == 0) { 334dbad75ddSKen Xue pin_reg |= 0xf; 335dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 336dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 337dbad75ddSKen Xue } 338dbad75ddSKen Xue pin_reg |= BIT(INTERRUPT_ENABLE_OFF); 339dbad75ddSKen Xue pin_reg |= BIT(INTERRUPT_MASK_OFF); 340dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 341dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 342dbad75ddSKen Xue } 343dbad75ddSKen Xue 344dbad75ddSKen Xue static void amd_gpio_irq_disable(struct irq_data *d) 345dbad75ddSKen Xue { 346dbad75ddSKen Xue u32 pin_reg; 347dbad75ddSKen Xue unsigned long flags; 348dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 34904d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 350dbad75ddSKen Xue 351dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 352dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 353dbad75ddSKen Xue pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); 354dbad75ddSKen Xue pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 355dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 356dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 357dbad75ddSKen Xue } 358dbad75ddSKen Xue 359dbad75ddSKen Xue static void amd_gpio_irq_mask(struct irq_data *d) 360dbad75ddSKen Xue { 361dbad75ddSKen Xue u32 pin_reg; 362dbad75ddSKen Xue unsigned long flags; 363dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 36404d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 365dbad75ddSKen Xue 366dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 367dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 368dbad75ddSKen Xue pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 369dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 370dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 371dbad75ddSKen Xue } 372dbad75ddSKen Xue 373dbad75ddSKen Xue static void amd_gpio_irq_unmask(struct irq_data *d) 374dbad75ddSKen Xue { 375dbad75ddSKen Xue u32 pin_reg; 376dbad75ddSKen Xue unsigned long flags; 377dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 37804d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 379dbad75ddSKen Xue 380dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 381dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 382dbad75ddSKen Xue pin_reg |= BIT(INTERRUPT_MASK_OFF); 383dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 384dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 385dbad75ddSKen Xue } 386dbad75ddSKen Xue 387dbad75ddSKen Xue static void amd_gpio_irq_eoi(struct irq_data *d) 388dbad75ddSKen Xue { 389dbad75ddSKen Xue u32 reg; 390dbad75ddSKen Xue unsigned long flags; 391dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 39204d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 393dbad75ddSKen Xue 394dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 395dbad75ddSKen Xue reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 396dbad75ddSKen Xue reg |= EOI_MASK; 397dbad75ddSKen Xue writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 398dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 399dbad75ddSKen Xue } 400dbad75ddSKen Xue 401dbad75ddSKen Xue static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) 402dbad75ddSKen Xue { 403dbad75ddSKen Xue int ret = 0; 404dbad75ddSKen Xue u32 pin_reg; 405dbad75ddSKen Xue unsigned long flags; 406e084448bSAgrawal, Nitesh-kumar bool level_trig; 407499c7196SAgrawal, Nitesh-kumar u32 active_level; 408dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 40904d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 410dbad75ddSKen Xue 411dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 412dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 413dbad75ddSKen Xue 414499c7196SAgrawal, Nitesh-kumar /* 415499c7196SAgrawal, Nitesh-kumar * When level_trig is set EDGE and active_level is set HIGH in BIOS 416499c7196SAgrawal, Nitesh-kumar * default settings, ignore incoming settings from client and use 417499c7196SAgrawal, Nitesh-kumar * BIOS settings to configure GPIO register. 418499c7196SAgrawal, Nitesh-kumar */ 419e084448bSAgrawal, Nitesh-kumar level_trig = !(pin_reg & (LEVEL_TRIGGER << LEVEL_TRIG_OFF)); 420499c7196SAgrawal, Nitesh-kumar active_level = pin_reg & (ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 421499c7196SAgrawal, Nitesh-kumar 422e084448bSAgrawal, Nitesh-kumar if(level_trig && 423e084448bSAgrawal, Nitesh-kumar ((active_level >> ACTIVE_LEVEL_OFF) == ACTIVE_HIGH)) 424499c7196SAgrawal, Nitesh-kumar type = IRQ_TYPE_EDGE_FALLING; 425499c7196SAgrawal, Nitesh-kumar 426dbad75ddSKen Xue switch (type & IRQ_TYPE_SENSE_MASK) { 427dbad75ddSKen Xue case IRQ_TYPE_EDGE_RISING: 428dbad75ddSKen Xue pin_reg &= ~BIT(LEVEL_TRIG_OFF); 429dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 430dbad75ddSKen Xue pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 431dbad75ddSKen Xue pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 4329d829314SThomas Gleixner irq_set_handler_locked(d, handle_edge_irq); 433dbad75ddSKen Xue break; 434dbad75ddSKen Xue 435dbad75ddSKen Xue case IRQ_TYPE_EDGE_FALLING: 436dbad75ddSKen Xue pin_reg &= ~BIT(LEVEL_TRIG_OFF); 437dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 438dbad75ddSKen Xue pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 439dbad75ddSKen Xue pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 4409d829314SThomas Gleixner irq_set_handler_locked(d, handle_edge_irq); 441dbad75ddSKen Xue break; 442dbad75ddSKen Xue 443dbad75ddSKen Xue case IRQ_TYPE_EDGE_BOTH: 444dbad75ddSKen Xue pin_reg &= ~BIT(LEVEL_TRIG_OFF); 445dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 446dbad75ddSKen Xue pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; 447dbad75ddSKen Xue pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 4489d829314SThomas Gleixner irq_set_handler_locked(d, handle_edge_irq); 449dbad75ddSKen Xue break; 450dbad75ddSKen Xue 451dbad75ddSKen Xue case IRQ_TYPE_LEVEL_HIGH: 452dbad75ddSKen Xue pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 453dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 454dbad75ddSKen Xue pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 455dbad75ddSKen Xue pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 456dbad75ddSKen Xue pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF; 4579d829314SThomas Gleixner irq_set_handler_locked(d, handle_level_irq); 458dbad75ddSKen Xue break; 459dbad75ddSKen Xue 460dbad75ddSKen Xue case IRQ_TYPE_LEVEL_LOW: 461dbad75ddSKen Xue pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 462dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 463dbad75ddSKen Xue pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 464dbad75ddSKen Xue pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 465dbad75ddSKen Xue pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF; 4669d829314SThomas Gleixner irq_set_handler_locked(d, handle_level_irq); 467dbad75ddSKen Xue break; 468dbad75ddSKen Xue 469dbad75ddSKen Xue case IRQ_TYPE_NONE: 470dbad75ddSKen Xue break; 471dbad75ddSKen Xue 472dbad75ddSKen Xue default: 473dbad75ddSKen Xue dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); 474dbad75ddSKen Xue ret = -EINVAL; 475dbad75ddSKen Xue } 476dbad75ddSKen Xue 477dbad75ddSKen Xue pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; 478dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 479dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 480dbad75ddSKen Xue 481dbad75ddSKen Xue return ret; 482dbad75ddSKen Xue } 483dbad75ddSKen Xue 484dbad75ddSKen Xue static void amd_irq_ack(struct irq_data *d) 485dbad75ddSKen Xue { 486dbad75ddSKen Xue /* 487dbad75ddSKen Xue * based on HW design,there is no need to ack HW 488dbad75ddSKen Xue * before handle current irq. But this routine is 489dbad75ddSKen Xue * necessary for handle_edge_irq 490dbad75ddSKen Xue */ 491dbad75ddSKen Xue } 492dbad75ddSKen Xue 493dbad75ddSKen Xue static struct irq_chip amd_gpio_irqchip = { 494dbad75ddSKen Xue .name = "amd_gpio", 495dbad75ddSKen Xue .irq_ack = amd_irq_ack, 496dbad75ddSKen Xue .irq_enable = amd_gpio_irq_enable, 497dbad75ddSKen Xue .irq_disable = amd_gpio_irq_disable, 498dbad75ddSKen Xue .irq_mask = amd_gpio_irq_mask, 499dbad75ddSKen Xue .irq_unmask = amd_gpio_irq_unmask, 500dbad75ddSKen Xue .irq_eoi = amd_gpio_irq_eoi, 501dbad75ddSKen Xue .irq_set_type = amd_gpio_irq_set_type, 502dbad75ddSKen Xue }; 503dbad75ddSKen Xue 504bd0b9ac4SThomas Gleixner static void amd_gpio_irq_handler(struct irq_desc *desc) 505dbad75ddSKen Xue { 506dbad75ddSKen Xue u32 i; 507dbad75ddSKen Xue u32 off; 508dbad75ddSKen Xue u32 reg; 509dbad75ddSKen Xue u32 pin_reg; 510dbad75ddSKen Xue u64 reg64; 511dbad75ddSKen Xue int handled = 0; 512bd0b9ac4SThomas Gleixner unsigned int irq; 513dbad75ddSKen Xue unsigned long flags; 5145663bb27SJiang Liu struct irq_chip *chip = irq_desc_get_chip(desc); 515dbad75ddSKen Xue struct gpio_chip *gc = irq_desc_get_handler_data(desc); 51604d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 517dbad75ddSKen Xue 518dbad75ddSKen Xue chained_irq_enter(chip, desc); 519dbad75ddSKen Xue /*enable GPIO interrupt again*/ 520dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 521dbad75ddSKen Xue reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); 522dbad75ddSKen Xue reg64 = reg; 523dbad75ddSKen Xue reg64 = reg64 << 32; 524dbad75ddSKen Xue 525dbad75ddSKen Xue reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG0); 526dbad75ddSKen Xue reg64 |= reg; 527dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 528dbad75ddSKen Xue 529dbad75ddSKen Xue /* 530dbad75ddSKen Xue * first 46 bits indicates interrupt status. 531dbad75ddSKen Xue * one bit represents four interrupt sources. 532dbad75ddSKen Xue */ 533dbad75ddSKen Xue for (off = 0; off < 46 ; off++) { 534dbad75ddSKen Xue if (reg64 & BIT(off)) { 535dbad75ddSKen Xue for (i = 0; i < 4; i++) { 536dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + 537dbad75ddSKen Xue (off * 4 + i) * 4); 538dbad75ddSKen Xue if ((pin_reg & BIT(INTERRUPT_STS_OFF)) || 539dbad75ddSKen Xue (pin_reg & BIT(WAKE_STS_OFF))) { 540dbad75ddSKen Xue irq = irq_find_mapping(gc->irqdomain, 541dbad75ddSKen Xue off * 4 + i); 542dbad75ddSKen Xue generic_handle_irq(irq); 543dbad75ddSKen Xue writel(pin_reg, 544dbad75ddSKen Xue gpio_dev->base 545dbad75ddSKen Xue + (off * 4 + i) * 4); 546dbad75ddSKen Xue handled++; 547dbad75ddSKen Xue } 548dbad75ddSKen Xue } 549dbad75ddSKen Xue } 550dbad75ddSKen Xue } 551dbad75ddSKen Xue 552dbad75ddSKen Xue if (handled == 0) 553bd0b9ac4SThomas Gleixner handle_bad_irq(desc); 554dbad75ddSKen Xue 555dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 556dbad75ddSKen Xue reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 557dbad75ddSKen Xue reg |= EOI_MASK; 558dbad75ddSKen Xue writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 559dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 560dbad75ddSKen Xue 561dbad75ddSKen Xue chained_irq_exit(chip, desc); 562dbad75ddSKen Xue } 563dbad75ddSKen Xue 564dbad75ddSKen Xue static int amd_get_groups_count(struct pinctrl_dev *pctldev) 565dbad75ddSKen Xue { 566dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 567dbad75ddSKen Xue 568dbad75ddSKen Xue return gpio_dev->ngroups; 569dbad75ddSKen Xue } 570dbad75ddSKen Xue 571dbad75ddSKen Xue static const char *amd_get_group_name(struct pinctrl_dev *pctldev, 572dbad75ddSKen Xue unsigned group) 573dbad75ddSKen Xue { 574dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 575dbad75ddSKen Xue 576dbad75ddSKen Xue return gpio_dev->groups[group].name; 577dbad75ddSKen Xue } 578dbad75ddSKen Xue 579dbad75ddSKen Xue static int amd_get_group_pins(struct pinctrl_dev *pctldev, 580dbad75ddSKen Xue unsigned group, 581dbad75ddSKen Xue const unsigned **pins, 582dbad75ddSKen Xue unsigned *num_pins) 583dbad75ddSKen Xue { 584dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 585dbad75ddSKen Xue 586dbad75ddSKen Xue *pins = gpio_dev->groups[group].pins; 587dbad75ddSKen Xue *num_pins = gpio_dev->groups[group].npins; 588dbad75ddSKen Xue return 0; 589dbad75ddSKen Xue } 590dbad75ddSKen Xue 591dbad75ddSKen Xue static const struct pinctrl_ops amd_pinctrl_ops = { 592dbad75ddSKen Xue .get_groups_count = amd_get_groups_count, 593dbad75ddSKen Xue .get_group_name = amd_get_group_name, 594dbad75ddSKen Xue .get_group_pins = amd_get_group_pins, 595dbad75ddSKen Xue #ifdef CONFIG_OF 596dbad75ddSKen Xue .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 597d32f7fd3SIrina Tirdea .dt_free_map = pinctrl_utils_free_map, 598dbad75ddSKen Xue #endif 599dbad75ddSKen Xue }; 600dbad75ddSKen Xue 601dbad75ddSKen Xue static int amd_pinconf_get(struct pinctrl_dev *pctldev, 602dbad75ddSKen Xue unsigned int pin, 603dbad75ddSKen Xue unsigned long *config) 604dbad75ddSKen Xue { 605dbad75ddSKen Xue u32 pin_reg; 606dbad75ddSKen Xue unsigned arg; 607dbad75ddSKen Xue unsigned long flags; 608dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 609dbad75ddSKen Xue enum pin_config_param param = pinconf_to_config_param(*config); 610dbad75ddSKen Xue 611dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 612dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + pin*4); 613dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 614dbad75ddSKen Xue switch (param) { 615dbad75ddSKen Xue case PIN_CONFIG_INPUT_DEBOUNCE: 616dbad75ddSKen Xue arg = pin_reg & DB_TMR_OUT_MASK; 617dbad75ddSKen Xue break; 618dbad75ddSKen Xue 619dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_DOWN: 620dbad75ddSKen Xue arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); 621dbad75ddSKen Xue break; 622dbad75ddSKen Xue 623dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_UP: 624dbad75ddSKen Xue arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); 625dbad75ddSKen Xue break; 626dbad75ddSKen Xue 627dbad75ddSKen Xue case PIN_CONFIG_DRIVE_STRENGTH: 628dbad75ddSKen Xue arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; 629dbad75ddSKen Xue break; 630dbad75ddSKen Xue 631dbad75ddSKen Xue default: 632dbad75ddSKen Xue dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n", 633dbad75ddSKen Xue param); 634dbad75ddSKen Xue return -ENOTSUPP; 635dbad75ddSKen Xue } 636dbad75ddSKen Xue 637dbad75ddSKen Xue *config = pinconf_to_config_packed(param, arg); 638dbad75ddSKen Xue 639dbad75ddSKen Xue return 0; 640dbad75ddSKen Xue } 641dbad75ddSKen Xue 642dbad75ddSKen Xue static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 643dbad75ddSKen Xue unsigned long *configs, unsigned num_configs) 644dbad75ddSKen Xue { 645dbad75ddSKen Xue int i; 646dbad75ddSKen Xue u32 arg; 64725a853d0SKen Xue int ret = 0; 64825a853d0SKen Xue u32 pin_reg; 649dbad75ddSKen Xue unsigned long flags; 650dbad75ddSKen Xue enum pin_config_param param; 651dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 652dbad75ddSKen Xue 653dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 654dbad75ddSKen Xue for (i = 0; i < num_configs; i++) { 655dbad75ddSKen Xue param = pinconf_to_config_param(configs[i]); 656dbad75ddSKen Xue arg = pinconf_to_config_argument(configs[i]); 657dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + pin*4); 658dbad75ddSKen Xue 659dbad75ddSKen Xue switch (param) { 660dbad75ddSKen Xue case PIN_CONFIG_INPUT_DEBOUNCE: 661dbad75ddSKen Xue pin_reg &= ~DB_TMR_OUT_MASK; 662dbad75ddSKen Xue pin_reg |= arg & DB_TMR_OUT_MASK; 663dbad75ddSKen Xue break; 664dbad75ddSKen Xue 665dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_DOWN: 666dbad75ddSKen Xue pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); 667dbad75ddSKen Xue pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; 668dbad75ddSKen Xue break; 669dbad75ddSKen Xue 670dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_UP: 671dbad75ddSKen Xue pin_reg &= ~BIT(PULL_UP_SEL_OFF); 672dbad75ddSKen Xue pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; 673dbad75ddSKen Xue pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); 674dbad75ddSKen Xue pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; 675dbad75ddSKen Xue break; 676dbad75ddSKen Xue 677dbad75ddSKen Xue case PIN_CONFIG_DRIVE_STRENGTH: 678dbad75ddSKen Xue pin_reg &= ~(DRV_STRENGTH_SEL_MASK 679dbad75ddSKen Xue << DRV_STRENGTH_SEL_OFF); 680dbad75ddSKen Xue pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) 681dbad75ddSKen Xue << DRV_STRENGTH_SEL_OFF; 682dbad75ddSKen Xue break; 683dbad75ddSKen Xue 684dbad75ddSKen Xue default: 685dbad75ddSKen Xue dev_err(&gpio_dev->pdev->dev, 686dbad75ddSKen Xue "Invalid config param %04x\n", param); 68725a853d0SKen Xue ret = -ENOTSUPP; 688dbad75ddSKen Xue } 689dbad75ddSKen Xue 690dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + pin*4); 691dbad75ddSKen Xue } 692dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 693dbad75ddSKen Xue 69425a853d0SKen Xue return ret; 695dbad75ddSKen Xue } 696dbad75ddSKen Xue 697dbad75ddSKen Xue static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, 698dbad75ddSKen Xue unsigned int group, 699dbad75ddSKen Xue unsigned long *config) 700dbad75ddSKen Xue { 701dbad75ddSKen Xue const unsigned *pins; 702dbad75ddSKen Xue unsigned npins; 703dbad75ddSKen Xue int ret; 704dbad75ddSKen Xue 705dbad75ddSKen Xue ret = amd_get_group_pins(pctldev, group, &pins, &npins); 706dbad75ddSKen Xue if (ret) 707dbad75ddSKen Xue return ret; 708dbad75ddSKen Xue 709dbad75ddSKen Xue if (amd_pinconf_get(pctldev, pins[0], config)) 710dbad75ddSKen Xue return -ENOTSUPP; 711dbad75ddSKen Xue 712dbad75ddSKen Xue return 0; 713dbad75ddSKen Xue } 714dbad75ddSKen Xue 715dbad75ddSKen Xue static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, 716dbad75ddSKen Xue unsigned group, unsigned long *configs, 717dbad75ddSKen Xue unsigned num_configs) 718dbad75ddSKen Xue { 719dbad75ddSKen Xue const unsigned *pins; 720dbad75ddSKen Xue unsigned npins; 721dbad75ddSKen Xue int i, ret; 722dbad75ddSKen Xue 723dbad75ddSKen Xue ret = amd_get_group_pins(pctldev, group, &pins, &npins); 724dbad75ddSKen Xue if (ret) 725dbad75ddSKen Xue return ret; 726dbad75ddSKen Xue for (i = 0; i < npins; i++) { 727dbad75ddSKen Xue if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) 728dbad75ddSKen Xue return -ENOTSUPP; 729dbad75ddSKen Xue } 730dbad75ddSKen Xue return 0; 731dbad75ddSKen Xue } 732dbad75ddSKen Xue 733dbad75ddSKen Xue static const struct pinconf_ops amd_pinconf_ops = { 734dbad75ddSKen Xue .pin_config_get = amd_pinconf_get, 735dbad75ddSKen Xue .pin_config_set = amd_pinconf_set, 736dbad75ddSKen Xue .pin_config_group_get = amd_pinconf_group_get, 737dbad75ddSKen Xue .pin_config_group_set = amd_pinconf_group_set, 738dbad75ddSKen Xue }; 739dbad75ddSKen Xue 740dbad75ddSKen Xue static struct pinctrl_desc amd_pinctrl_desc = { 741dbad75ddSKen Xue .pins = kerncz_pins, 742dbad75ddSKen Xue .npins = ARRAY_SIZE(kerncz_pins), 743dbad75ddSKen Xue .pctlops = &amd_pinctrl_ops, 744dbad75ddSKen Xue .confops = &amd_pinconf_ops, 745dbad75ddSKen Xue .owner = THIS_MODULE, 746dbad75ddSKen Xue }; 747dbad75ddSKen Xue 748dbad75ddSKen Xue static int amd_gpio_probe(struct platform_device *pdev) 749dbad75ddSKen Xue { 750dbad75ddSKen Xue int ret = 0; 75125a853d0SKen Xue int irq_base; 752dbad75ddSKen Xue struct resource *res; 753dbad75ddSKen Xue struct amd_gpio *gpio_dev; 754dbad75ddSKen Xue 755dbad75ddSKen Xue gpio_dev = devm_kzalloc(&pdev->dev, 756dbad75ddSKen Xue sizeof(struct amd_gpio), GFP_KERNEL); 757dbad75ddSKen Xue if (!gpio_dev) 758dbad75ddSKen Xue return -ENOMEM; 759dbad75ddSKen Xue 760dbad75ddSKen Xue spin_lock_init(&gpio_dev->lock); 761dbad75ddSKen Xue 762dbad75ddSKen Xue res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 763dbad75ddSKen Xue if (!res) { 764dbad75ddSKen Xue dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); 765dbad75ddSKen Xue return -EINVAL; 766dbad75ddSKen Xue } 767dbad75ddSKen Xue 768dbad75ddSKen Xue gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start, 769dbad75ddSKen Xue resource_size(res)); 770424a6c60SWei Yongjun if (!gpio_dev->base) 771424a6c60SWei Yongjun return -ENOMEM; 772dbad75ddSKen Xue 773dbad75ddSKen Xue irq_base = platform_get_irq(pdev, 0); 774dbad75ddSKen Xue if (irq_base < 0) { 775dbad75ddSKen Xue dev_err(&pdev->dev, "Failed to get gpio IRQ.\n"); 776dbad75ddSKen Xue return -EINVAL; 777dbad75ddSKen Xue } 778dbad75ddSKen Xue 779dbad75ddSKen Xue gpio_dev->pdev = pdev; 780dbad75ddSKen Xue gpio_dev->gc.direction_input = amd_gpio_direction_input; 781dbad75ddSKen Xue gpio_dev->gc.direction_output = amd_gpio_direction_output; 782dbad75ddSKen Xue gpio_dev->gc.get = amd_gpio_get_value; 783dbad75ddSKen Xue gpio_dev->gc.set = amd_gpio_set_value; 784dbad75ddSKen Xue gpio_dev->gc.set_debounce = amd_gpio_set_debounce; 785dbad75ddSKen Xue gpio_dev->gc.dbg_show = amd_gpio_dbg_show; 786dbad75ddSKen Xue 787dbad75ddSKen Xue gpio_dev->gc.base = 0; 788dbad75ddSKen Xue gpio_dev->gc.label = pdev->name; 789dbad75ddSKen Xue gpio_dev->gc.owner = THIS_MODULE; 79058383c78SLinus Walleij gpio_dev->gc.parent = &pdev->dev; 791dbad75ddSKen Xue gpio_dev->gc.ngpio = TOTAL_NUMBER_OF_PINS; 792dbad75ddSKen Xue #if defined(CONFIG_OF_GPIO) 793dbad75ddSKen Xue gpio_dev->gc.of_node = pdev->dev.of_node; 794dbad75ddSKen Xue #endif 795dbad75ddSKen Xue 796dbad75ddSKen Xue gpio_dev->groups = kerncz_groups; 797dbad75ddSKen Xue gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); 798dbad75ddSKen Xue 799dbad75ddSKen Xue amd_pinctrl_desc.name = dev_name(&pdev->dev); 800251e22abSLaxman Dewangan gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, 801251e22abSLaxman Dewangan gpio_dev); 802323de9efSMasahiro Yamada if (IS_ERR(gpio_dev->pctrl)) { 803dbad75ddSKen Xue dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 804323de9efSMasahiro Yamada return PTR_ERR(gpio_dev->pctrl); 805dbad75ddSKen Xue } 806dbad75ddSKen Xue 80704d36723SLinus Walleij ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); 808dbad75ddSKen Xue if (ret) 809251e22abSLaxman Dewangan return ret; 810dbad75ddSKen Xue 811dbad75ddSKen Xue ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), 812dbad75ddSKen Xue 0, 0, TOTAL_NUMBER_OF_PINS); 813dbad75ddSKen Xue if (ret) { 814dbad75ddSKen Xue dev_err(&pdev->dev, "Failed to add pin range\n"); 815dbad75ddSKen Xue goto out2; 816dbad75ddSKen Xue } 817dbad75ddSKen Xue 818dbad75ddSKen Xue ret = gpiochip_irqchip_add(&gpio_dev->gc, 819dbad75ddSKen Xue &amd_gpio_irqchip, 820dbad75ddSKen Xue 0, 821dbad75ddSKen Xue handle_simple_irq, 822dbad75ddSKen Xue IRQ_TYPE_NONE); 823dbad75ddSKen Xue if (ret) { 824dbad75ddSKen Xue dev_err(&pdev->dev, "could not add irqchip\n"); 825dbad75ddSKen Xue ret = -ENODEV; 826dbad75ddSKen Xue goto out2; 827dbad75ddSKen Xue } 828dbad75ddSKen Xue 829dbad75ddSKen Xue gpiochip_set_chained_irqchip(&gpio_dev->gc, 830dbad75ddSKen Xue &amd_gpio_irqchip, 831dbad75ddSKen Xue irq_base, 832dbad75ddSKen Xue amd_gpio_irq_handler); 833dbad75ddSKen Xue 834dbad75ddSKen Xue platform_set_drvdata(pdev, gpio_dev); 835dbad75ddSKen Xue 836dbad75ddSKen Xue dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); 837dbad75ddSKen Xue return ret; 838dbad75ddSKen Xue 839dbad75ddSKen Xue out2: 840dbad75ddSKen Xue gpiochip_remove(&gpio_dev->gc); 841dbad75ddSKen Xue 842dbad75ddSKen Xue return ret; 843dbad75ddSKen Xue } 844dbad75ddSKen Xue 845dbad75ddSKen Xue static int amd_gpio_remove(struct platform_device *pdev) 846dbad75ddSKen Xue { 847dbad75ddSKen Xue struct amd_gpio *gpio_dev; 848dbad75ddSKen Xue 849dbad75ddSKen Xue gpio_dev = platform_get_drvdata(pdev); 850dbad75ddSKen Xue 851dbad75ddSKen Xue gpiochip_remove(&gpio_dev->gc); 852dbad75ddSKen Xue 853dbad75ddSKen Xue return 0; 854dbad75ddSKen Xue } 855dbad75ddSKen Xue 856dbad75ddSKen Xue static const struct acpi_device_id amd_gpio_acpi_match[] = { 857dbad75ddSKen Xue { "AMD0030", 0 }, 85842a44402SWang Hongcheng { "AMDI0030", 0}, 859dbad75ddSKen Xue { }, 860dbad75ddSKen Xue }; 861dbad75ddSKen Xue MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); 862dbad75ddSKen Xue 863dbad75ddSKen Xue static struct platform_driver amd_gpio_driver = { 864dbad75ddSKen Xue .driver = { 865dbad75ddSKen Xue .name = "amd_gpio", 866dbad75ddSKen Xue .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), 867dbad75ddSKen Xue }, 868dbad75ddSKen Xue .probe = amd_gpio_probe, 869dbad75ddSKen Xue .remove = amd_gpio_remove, 870dbad75ddSKen Xue }; 871dbad75ddSKen Xue 872dbad75ddSKen Xue module_platform_driver(amd_gpio_driver); 873dbad75ddSKen Xue 874dbad75ddSKen Xue MODULE_LICENSE("GPL v2"); 875dbad75ddSKen Xue MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); 876dbad75ddSKen Xue MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); 877