175a6faf6SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2dbad75ddSKen Xue /* 3dbad75ddSKen Xue * GPIO driver for AMD 4dbad75ddSKen Xue * 5dbad75ddSKen Xue * Copyright (c) 2014,2015 AMD Corporation. 6dbad75ddSKen Xue * Authors: Ken Xue <Ken.Xue@amd.com> 7dbad75ddSKen Xue * Wu, Jeff <Jeff.Wu@amd.com> 8dbad75ddSKen Xue * 9add7bfceSShyam Sundar S K * Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com> 10add7bfceSShyam Sundar S K * Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 11dbad75ddSKen Xue */ 12dbad75ddSKen Xue 13dbad75ddSKen Xue #include <linux/err.h> 14dbad75ddSKen Xue #include <linux/bug.h> 15dbad75ddSKen Xue #include <linux/kernel.h> 16dbad75ddSKen Xue #include <linux/module.h> 17dbad75ddSKen Xue #include <linux/spinlock.h> 18dbad75ddSKen Xue #include <linux/compiler.h> 19dbad75ddSKen Xue #include <linux/types.h> 20dbad75ddSKen Xue #include <linux/errno.h> 21dbad75ddSKen Xue #include <linux/log2.h> 22dbad75ddSKen Xue #include <linux/io.h> 231c5fb66aSLinus Walleij #include <linux/gpio/driver.h> 24dbad75ddSKen Xue #include <linux/slab.h> 25dbad75ddSKen Xue #include <linux/platform_device.h> 26dbad75ddSKen Xue #include <linux/mutex.h> 27dbad75ddSKen Xue #include <linux/acpi.h> 28dbad75ddSKen Xue #include <linux/seq_file.h> 29dbad75ddSKen Xue #include <linux/interrupt.h> 30dbad75ddSKen Xue #include <linux/list.h> 31dbad75ddSKen Xue #include <linux/bitops.h> 32dbad75ddSKen Xue #include <linux/pinctrl/pinconf.h> 33dbad75ddSKen Xue #include <linux/pinctrl/pinconf-generic.h> 3472440158SBasavaraj Natikar #include <linux/pinctrl/pinmux.h> 35dbad75ddSKen Xue 3679d2c8beSDaniel Drake #include "core.h" 37dbad75ddSKen Xue #include "pinctrl-utils.h" 38dbad75ddSKen Xue #include "pinctrl-amd.h" 39dbad75ddSKen Xue 4012b10f47SDaniel Kurtz static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset) 4112b10f47SDaniel Kurtz { 4212b10f47SDaniel Kurtz unsigned long flags; 4312b10f47SDaniel Kurtz u32 pin_reg; 4412b10f47SDaniel Kurtz struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 4512b10f47SDaniel Kurtz 4612b10f47SDaniel Kurtz raw_spin_lock_irqsave(&gpio_dev->lock, flags); 4712b10f47SDaniel Kurtz pin_reg = readl(gpio_dev->base + offset * 4); 4812b10f47SDaniel Kurtz raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 4912b10f47SDaniel Kurtz 503c827873SMatti Vaittinen if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) 513c827873SMatti Vaittinen return GPIO_LINE_DIRECTION_OUT; 523c827873SMatti Vaittinen 533c827873SMatti Vaittinen return GPIO_LINE_DIRECTION_IN; 5412b10f47SDaniel Kurtz } 5512b10f47SDaniel Kurtz 56dbad75ddSKen Xue static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 57dbad75ddSKen Xue { 58dbad75ddSKen Xue unsigned long flags; 59dbad75ddSKen Xue u32 pin_reg; 6004d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 61dbad75ddSKen Xue 62229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 63dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 64dbad75ddSKen Xue pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); 65dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4); 66229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 67dbad75ddSKen Xue 68dbad75ddSKen Xue return 0; 69dbad75ddSKen Xue } 70dbad75ddSKen Xue 71dbad75ddSKen Xue static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 72dbad75ddSKen Xue int value) 73dbad75ddSKen Xue { 74dbad75ddSKen Xue u32 pin_reg; 75dbad75ddSKen Xue unsigned long flags; 7604d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 77dbad75ddSKen Xue 78229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 79dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 80dbad75ddSKen Xue pin_reg |= BIT(OUTPUT_ENABLE_OFF); 81dbad75ddSKen Xue if (value) 82dbad75ddSKen Xue pin_reg |= BIT(OUTPUT_VALUE_OFF); 83dbad75ddSKen Xue else 84dbad75ddSKen Xue pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 85dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4); 86229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 87dbad75ddSKen Xue 88dbad75ddSKen Xue return 0; 89dbad75ddSKen Xue } 90dbad75ddSKen Xue 91dbad75ddSKen Xue static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) 92dbad75ddSKen Xue { 93dbad75ddSKen Xue u32 pin_reg; 94dbad75ddSKen Xue unsigned long flags; 9504d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 96dbad75ddSKen Xue 97229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 98dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 99229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 100dbad75ddSKen Xue 101dbad75ddSKen Xue return !!(pin_reg & BIT(PIN_STS_OFF)); 102dbad75ddSKen Xue } 103dbad75ddSKen Xue 104dbad75ddSKen Xue static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) 105dbad75ddSKen Xue { 106dbad75ddSKen Xue u32 pin_reg; 107dbad75ddSKen Xue unsigned long flags; 10804d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 109dbad75ddSKen Xue 110229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 111dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 112dbad75ddSKen Xue if (value) 113dbad75ddSKen Xue pin_reg |= BIT(OUTPUT_VALUE_OFF); 114dbad75ddSKen Xue else 115dbad75ddSKen Xue pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 116dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4); 117229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 118dbad75ddSKen Xue } 119dbad75ddSKen Xue 120dbad75ddSKen Xue static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, 121dbad75ddSKen Xue unsigned debounce) 122dbad75ddSKen Xue { 123dbad75ddSKen Xue u32 time; 12425a853d0SKen Xue u32 pin_reg; 12525a853d0SKen Xue int ret = 0; 126dbad75ddSKen Xue unsigned long flags; 12704d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 128dbad75ddSKen Xue 129229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 130dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 131dbad75ddSKen Xue 132dbad75ddSKen Xue if (debounce) { 133dbad75ddSKen Xue pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 134dbad75ddSKen Xue pin_reg &= ~DB_TMR_OUT_MASK; 135dbad75ddSKen Xue /* 136dbad75ddSKen Xue Debounce Debounce Timer Max 137dbad75ddSKen Xue TmrLarge TmrOutUnit Unit Debounce 138dbad75ddSKen Xue Time 139dbad75ddSKen Xue 0 0 61 usec (2 RtcClk) 976 usec 140dbad75ddSKen Xue 0 1 244 usec (8 RtcClk) 3.9 msec 141dbad75ddSKen Xue 1 0 15.6 msec (512 RtcClk) 250 msec 142dbad75ddSKen Xue 1 1 62.5 msec (2048 RtcClk) 1 sec 143dbad75ddSKen Xue */ 144dbad75ddSKen Xue 145dbad75ddSKen Xue if (debounce < 61) { 146dbad75ddSKen Xue pin_reg |= 1; 147dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 148dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 149dbad75ddSKen Xue } else if (debounce < 976) { 150dbad75ddSKen Xue time = debounce / 61; 151dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK; 152dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 153dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 154dbad75ddSKen Xue } else if (debounce < 3900) { 155dbad75ddSKen Xue time = debounce / 244; 156dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK; 157dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 158dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 159dbad75ddSKen Xue } else if (debounce < 250000) { 160c64a6a0dSCoiby Xu time = debounce / 15625; 161dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK; 162dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 163dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_LARGE_OFF); 164dbad75ddSKen Xue } else if (debounce < 1000000) { 165dbad75ddSKen Xue time = debounce / 62500; 166dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK; 167dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 168dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_LARGE_OFF); 169dbad75ddSKen Xue } else { 17006abe829SCoiby Xu pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 17125a853d0SKen Xue ret = -EINVAL; 172dbad75ddSKen Xue } 173dbad75ddSKen Xue } else { 174dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 175dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 176dbad75ddSKen Xue pin_reg &= ~DB_TMR_OUT_MASK; 17706abe829SCoiby Xu pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 178dbad75ddSKen Xue } 179dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4); 180229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 181dbad75ddSKen Xue 18225a853d0SKen Xue return ret; 183dbad75ddSKen Xue } 184dbad75ddSKen Xue 1852956b5d9SMika Westerberg static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset, 1862956b5d9SMika Westerberg unsigned long config) 1872956b5d9SMika Westerberg { 1882956b5d9SMika Westerberg u32 debounce; 1892956b5d9SMika Westerberg 1902956b5d9SMika Westerberg if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 1912956b5d9SMika Westerberg return -ENOTSUPP; 1922956b5d9SMika Westerberg 1932956b5d9SMika Westerberg debounce = pinconf_to_config_argument(config); 1942956b5d9SMika Westerberg return amd_gpio_set_debounce(gc, offset, debounce); 1952956b5d9SMika Westerberg } 1962956b5d9SMika Westerberg 197dbad75ddSKen Xue #ifdef CONFIG_DEBUG_FS 198dbad75ddSKen Xue static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) 199dbad75ddSKen Xue { 200dbad75ddSKen Xue u32 pin_reg; 20139cc1d33SCoiby Xu u32 db_cntrl; 202dbad75ddSKen Xue unsigned long flags; 203dbad75ddSKen Xue unsigned int bank, i, pin_num; 20404d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 205dbad75ddSKen Xue 20639cc1d33SCoiby Xu bool tmr_out_unit; 20739cc1d33SCoiby Xu unsigned int time; 20839cc1d33SCoiby Xu unsigned int unit; 20939cc1d33SCoiby Xu bool tmr_large; 21039cc1d33SCoiby Xu 211dbad75ddSKen Xue char *level_trig; 212dbad75ddSKen Xue char *active_level; 213dbad75ddSKen Xue char *interrupt_enable; 214dbad75ddSKen Xue char *interrupt_mask; 215dbad75ddSKen Xue char *wake_cntrl0; 216dbad75ddSKen Xue char *wake_cntrl1; 217dbad75ddSKen Xue char *wake_cntrl2; 218dbad75ddSKen Xue char *pin_sts; 219dbad75ddSKen Xue char *pull_up_sel; 220dbad75ddSKen Xue char *pull_up_enable; 221dbad75ddSKen Xue char *pull_down_enable; 222dbad75ddSKen Xue char *output_value; 223dbad75ddSKen Xue char *output_enable; 22439cc1d33SCoiby Xu char debounce_value[40]; 22539cc1d33SCoiby Xu char *debounce_enable; 226dbad75ddSKen Xue 2273bfd4430SShah, Nehal-bakulchandra for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { 228dbad75ddSKen Xue seq_printf(s, "GPIO bank%d\t", bank); 229dbad75ddSKen Xue 230dbad75ddSKen Xue switch (bank) { 231dbad75ddSKen Xue case 0: 232dbad75ddSKen Xue i = 0; 233dbad75ddSKen Xue pin_num = AMD_GPIO_PINS_BANK0; 234dbad75ddSKen Xue break; 235dbad75ddSKen Xue case 1: 236dbad75ddSKen Xue i = 64; 237dbad75ddSKen Xue pin_num = AMD_GPIO_PINS_BANK1 + i; 238dbad75ddSKen Xue break; 239dbad75ddSKen Xue case 2: 240dbad75ddSKen Xue i = 128; 241dbad75ddSKen Xue pin_num = AMD_GPIO_PINS_BANK2 + i; 242dbad75ddSKen Xue break; 2433bfd4430SShah, Nehal-bakulchandra case 3: 2443bfd4430SShah, Nehal-bakulchandra i = 192; 2453bfd4430SShah, Nehal-bakulchandra pin_num = AMD_GPIO_PINS_BANK3 + i; 2463bfd4430SShah, Nehal-bakulchandra break; 2476ac4c1adSLinus Walleij default: 2486ac4c1adSLinus Walleij /* Illegal bank number, ignore */ 2496ac4c1adSLinus Walleij continue; 250dbad75ddSKen Xue } 251dbad75ddSKen Xue for (; i < pin_num; i++) { 252dbad75ddSKen Xue seq_printf(s, "pin%d\t", i); 253229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 254dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + i * 4); 255229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 256dbad75ddSKen Xue 257dbad75ddSKen Xue if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { 2581766e4b7SDaniel Kurtz u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) & 2591766e4b7SDaniel Kurtz ACTIVE_LEVEL_MASK; 260dbad75ddSKen Xue interrupt_enable = "interrupt is enabled|"; 261dbad75ddSKen Xue 2621766e4b7SDaniel Kurtz if (level == ACTIVE_LEVEL_HIGH) 263dbad75ddSKen Xue active_level = "Active high|"; 2641766e4b7SDaniel Kurtz else if (level == ACTIVE_LEVEL_LOW) 2651766e4b7SDaniel Kurtz active_level = "Active low|"; 2661766e4b7SDaniel Kurtz else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) && 2671766e4b7SDaniel Kurtz level == ACTIVE_LEVEL_BOTH) 268dbad75ddSKen Xue active_level = "Active on both|"; 269dbad75ddSKen Xue else 2700a95160eSMasanari Iida active_level = "Unknown Active level|"; 271dbad75ddSKen Xue 272dbad75ddSKen Xue if (pin_reg & BIT(LEVEL_TRIG_OFF)) 273dbad75ddSKen Xue level_trig = "Level trigger|"; 274dbad75ddSKen Xue else 275dbad75ddSKen Xue level_trig = "Edge trigger|"; 276dbad75ddSKen Xue 277dbad75ddSKen Xue } else { 278dbad75ddSKen Xue interrupt_enable = 279dbad75ddSKen Xue "interrupt is disabled|"; 280dbad75ddSKen Xue active_level = " "; 281dbad75ddSKen Xue level_trig = " "; 282dbad75ddSKen Xue } 283dbad75ddSKen Xue 284dbad75ddSKen Xue if (pin_reg & BIT(INTERRUPT_MASK_OFF)) 285dbad75ddSKen Xue interrupt_mask = 286dbad75ddSKen Xue "interrupt is unmasked|"; 287dbad75ddSKen Xue else 288dbad75ddSKen Xue interrupt_mask = 289dbad75ddSKen Xue "interrupt is masked|"; 290dbad75ddSKen Xue 2913bfd4430SShah, Nehal-bakulchandra if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) 292dbad75ddSKen Xue wake_cntrl0 = "enable wakeup in S0i3 state|"; 293dbad75ddSKen Xue else 294dbad75ddSKen Xue wake_cntrl0 = "disable wakeup in S0i3 state|"; 295dbad75ddSKen Xue 2963bfd4430SShah, Nehal-bakulchandra if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) 297dbad75ddSKen Xue wake_cntrl1 = "enable wakeup in S3 state|"; 298dbad75ddSKen Xue else 299dbad75ddSKen Xue wake_cntrl1 = "disable wakeup in S3 state|"; 300dbad75ddSKen Xue 3013bfd4430SShah, Nehal-bakulchandra if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) 302dbad75ddSKen Xue wake_cntrl2 = "enable wakeup in S4/S5 state|"; 303dbad75ddSKen Xue else 304dbad75ddSKen Xue wake_cntrl2 = "disable wakeup in S4/S5 state|"; 305dbad75ddSKen Xue 306dbad75ddSKen Xue if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { 307dbad75ddSKen Xue pull_up_enable = "pull-up is enabled|"; 308dbad75ddSKen Xue if (pin_reg & BIT(PULL_UP_SEL_OFF)) 309dbad75ddSKen Xue pull_up_sel = "8k pull-up|"; 310dbad75ddSKen Xue else 311dbad75ddSKen Xue pull_up_sel = "4k pull-up|"; 312dbad75ddSKen Xue } else { 313dbad75ddSKen Xue pull_up_enable = "pull-up is disabled|"; 314dbad75ddSKen Xue pull_up_sel = " "; 315dbad75ddSKen Xue } 316dbad75ddSKen Xue 317dbad75ddSKen Xue if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) 318dbad75ddSKen Xue pull_down_enable = "pull-down is enabled|"; 319dbad75ddSKen Xue else 320dbad75ddSKen Xue pull_down_enable = "Pull-down is disabled|"; 321dbad75ddSKen Xue 322dbad75ddSKen Xue if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { 323dbad75ddSKen Xue pin_sts = " "; 324dbad75ddSKen Xue output_enable = "output is enabled|"; 325dbad75ddSKen Xue if (pin_reg & BIT(OUTPUT_VALUE_OFF)) 326dbad75ddSKen Xue output_value = "output is high|"; 327dbad75ddSKen Xue else 328dbad75ddSKen Xue output_value = "output is low|"; 329dbad75ddSKen Xue } else { 330dbad75ddSKen Xue output_enable = "output is disabled|"; 331dbad75ddSKen Xue output_value = " "; 332dbad75ddSKen Xue 333dbad75ddSKen Xue if (pin_reg & BIT(PIN_STS_OFF)) 334dbad75ddSKen Xue pin_sts = "input is high|"; 335dbad75ddSKen Xue else 336dbad75ddSKen Xue pin_sts = "input is low|"; 337dbad75ddSKen Xue } 338dbad75ddSKen Xue 33939cc1d33SCoiby Xu db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg; 34039cc1d33SCoiby Xu if (db_cntrl) { 34139cc1d33SCoiby Xu tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF); 34239cc1d33SCoiby Xu tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF); 34339cc1d33SCoiby Xu time = pin_reg & DB_TMR_OUT_MASK; 34439cc1d33SCoiby Xu if (tmr_large) { 34539cc1d33SCoiby Xu if (tmr_out_unit) 34639cc1d33SCoiby Xu unit = 62500; 34739cc1d33SCoiby Xu else 34839cc1d33SCoiby Xu unit = 15625; 34939cc1d33SCoiby Xu } else { 35039cc1d33SCoiby Xu if (tmr_out_unit) 35139cc1d33SCoiby Xu unit = 244; 35239cc1d33SCoiby Xu else 35339cc1d33SCoiby Xu unit = 61; 35439cc1d33SCoiby Xu } 35539cc1d33SCoiby Xu if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl) 35639cc1d33SCoiby Xu debounce_enable = "debouncing filter (high and low) enabled|"; 35739cc1d33SCoiby Xu else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl) 35839cc1d33SCoiby Xu debounce_enable = "debouncing filter (low) enabled|"; 35939cc1d33SCoiby Xu else 36039cc1d33SCoiby Xu debounce_enable = "debouncing filter (high) enabled|"; 36139cc1d33SCoiby Xu 36239cc1d33SCoiby Xu snprintf(debounce_value, sizeof(debounce_value), 36339cc1d33SCoiby Xu "debouncing timeout is %u (us)|", time * unit); 36439cc1d33SCoiby Xu } else { 36539cc1d33SCoiby Xu debounce_enable = "debouncing filter disabled|"; 36639cc1d33SCoiby Xu snprintf(debounce_value, sizeof(debounce_value), " "); 36739cc1d33SCoiby Xu } 36839cc1d33SCoiby Xu 369dbad75ddSKen Xue seq_printf(s, "%s %s %s %s %s %s\n" 37039cc1d33SCoiby Xu " %s %s %s %s %s %s %s %s %s 0x%x\n", 371dbad75ddSKen Xue level_trig, active_level, interrupt_enable, 372dbad75ddSKen Xue interrupt_mask, wake_cntrl0, wake_cntrl1, 373dbad75ddSKen Xue wake_cntrl2, pin_sts, pull_up_sel, 374dbad75ddSKen Xue pull_up_enable, pull_down_enable, 37539cc1d33SCoiby Xu output_value, output_enable, 37639cc1d33SCoiby Xu debounce_enable, debounce_value, pin_reg); 377dbad75ddSKen Xue } 378dbad75ddSKen Xue } 379dbad75ddSKen Xue } 380dbad75ddSKen Xue #else 381dbad75ddSKen Xue #define amd_gpio_dbg_show NULL 382dbad75ddSKen Xue #endif 383dbad75ddSKen Xue 384dbad75ddSKen Xue static void amd_gpio_irq_enable(struct irq_data *d) 385dbad75ddSKen Xue { 386dbad75ddSKen Xue u32 pin_reg; 387dbad75ddSKen Xue unsigned long flags; 388dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 38904d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 390dbad75ddSKen Xue 3916173e56fSMarc Zyngier gpiochip_enable_irq(gc, d->hwirq); 3926173e56fSMarc Zyngier 393229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 394dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 395dbad75ddSKen Xue pin_reg |= BIT(INTERRUPT_ENABLE_OFF); 396dbad75ddSKen Xue pin_reg |= BIT(INTERRUPT_MASK_OFF); 397dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 398229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 399dbad75ddSKen Xue } 400dbad75ddSKen Xue 401dbad75ddSKen Xue static void amd_gpio_irq_disable(struct irq_data *d) 402dbad75ddSKen Xue { 403dbad75ddSKen Xue u32 pin_reg; 404dbad75ddSKen Xue unsigned long flags; 405dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 40604d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 407dbad75ddSKen Xue 408229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 409dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 410dbad75ddSKen Xue pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); 411dbad75ddSKen Xue pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 412dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 413229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 4146173e56fSMarc Zyngier 4156173e56fSMarc Zyngier gpiochip_disable_irq(gc, d->hwirq); 416dbad75ddSKen Xue } 417dbad75ddSKen Xue 418dbad75ddSKen Xue static void amd_gpio_irq_mask(struct irq_data *d) 419dbad75ddSKen Xue { 420dbad75ddSKen Xue u32 pin_reg; 421dbad75ddSKen Xue unsigned long flags; 422dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 42304d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 424dbad75ddSKen Xue 425229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 426dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 427dbad75ddSKen Xue pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 428dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 429229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 430dbad75ddSKen Xue } 431dbad75ddSKen Xue 432dbad75ddSKen Xue static void amd_gpio_irq_unmask(struct irq_data *d) 433dbad75ddSKen Xue { 434dbad75ddSKen Xue u32 pin_reg; 435dbad75ddSKen Xue unsigned long flags; 436dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 43704d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 438dbad75ddSKen Xue 439229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 440dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 441dbad75ddSKen Xue pin_reg |= BIT(INTERRUPT_MASK_OFF); 442dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 443229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 444dbad75ddSKen Xue } 445dbad75ddSKen Xue 446d62bd5ceSRaul E Rangel static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 447d62bd5ceSRaul E Rangel { 448d62bd5ceSRaul E Rangel u32 pin_reg; 449d62bd5ceSRaul E Rangel unsigned long flags; 450d62bd5ceSRaul E Rangel struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 451d62bd5ceSRaul E Rangel struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 452c4b68e51SMario Limonciello u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3); 453acd47b9fSBasavaraj Natikar int err; 454d62bd5ceSRaul E Rangel 455d62bd5ceSRaul E Rangel raw_spin_lock_irqsave(&gpio_dev->lock, flags); 456d62bd5ceSRaul E Rangel pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 457d62bd5ceSRaul E Rangel 458d62bd5ceSRaul E Rangel if (on) 459d62bd5ceSRaul E Rangel pin_reg |= wake_mask; 460d62bd5ceSRaul E Rangel else 461d62bd5ceSRaul E Rangel pin_reg &= ~wake_mask; 462d62bd5ceSRaul E Rangel 463d62bd5ceSRaul E Rangel writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 464d62bd5ceSRaul E Rangel raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 465d62bd5ceSRaul E Rangel 466acd47b9fSBasavaraj Natikar if (on) 467acd47b9fSBasavaraj Natikar err = enable_irq_wake(gpio_dev->irq); 468acd47b9fSBasavaraj Natikar else 469acd47b9fSBasavaraj Natikar err = disable_irq_wake(gpio_dev->irq); 470acd47b9fSBasavaraj Natikar 471acd47b9fSBasavaraj Natikar if (err) 472acd47b9fSBasavaraj Natikar dev_err(&gpio_dev->pdev->dev, "failed to %s wake-up interrupt\n", 473acd47b9fSBasavaraj Natikar on ? "enable" : "disable"); 474acd47b9fSBasavaraj Natikar 475d62bd5ceSRaul E Rangel return 0; 476d62bd5ceSRaul E Rangel } 477d62bd5ceSRaul E Rangel 478dbad75ddSKen Xue static void amd_gpio_irq_eoi(struct irq_data *d) 479dbad75ddSKen Xue { 480dbad75ddSKen Xue u32 reg; 481dbad75ddSKen Xue unsigned long flags; 482dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 48304d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 484dbad75ddSKen Xue 485229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 486dbad75ddSKen Xue reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 487dbad75ddSKen Xue reg |= EOI_MASK; 488dbad75ddSKen Xue writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 489229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 490dbad75ddSKen Xue } 491dbad75ddSKen Xue 492dbad75ddSKen Xue static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) 493dbad75ddSKen Xue { 494dbad75ddSKen Xue int ret = 0; 495b85bfa24SDaniel Kurtz u32 pin_reg, pin_reg_irq_en, mask; 4965f4962ddSFurquan Shaikh unsigned long flags; 497dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 49804d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 499dbad75ddSKen Xue 500229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 501dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 502dbad75ddSKen Xue 503dbad75ddSKen Xue switch (type & IRQ_TYPE_SENSE_MASK) { 504dbad75ddSKen Xue case IRQ_TYPE_EDGE_RISING: 505dbad75ddSKen Xue pin_reg &= ~BIT(LEVEL_TRIG_OFF); 506dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 507dbad75ddSKen Xue pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 5089d829314SThomas Gleixner irq_set_handler_locked(d, handle_edge_irq); 509dbad75ddSKen Xue break; 510dbad75ddSKen Xue 511dbad75ddSKen Xue case IRQ_TYPE_EDGE_FALLING: 512dbad75ddSKen Xue pin_reg &= ~BIT(LEVEL_TRIG_OFF); 513dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 514dbad75ddSKen Xue pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 5159d829314SThomas Gleixner irq_set_handler_locked(d, handle_edge_irq); 516dbad75ddSKen Xue break; 517dbad75ddSKen Xue 518dbad75ddSKen Xue case IRQ_TYPE_EDGE_BOTH: 519dbad75ddSKen Xue pin_reg &= ~BIT(LEVEL_TRIG_OFF); 520dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 521dbad75ddSKen Xue pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; 5229d829314SThomas Gleixner irq_set_handler_locked(d, handle_edge_irq); 523dbad75ddSKen Xue break; 524dbad75ddSKen Xue 525dbad75ddSKen Xue case IRQ_TYPE_LEVEL_HIGH: 526dbad75ddSKen Xue pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 527dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 528dbad75ddSKen Xue pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 5299d829314SThomas Gleixner irq_set_handler_locked(d, handle_level_irq); 530dbad75ddSKen Xue break; 531dbad75ddSKen Xue 532dbad75ddSKen Xue case IRQ_TYPE_LEVEL_LOW: 533dbad75ddSKen Xue pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 534dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 535dbad75ddSKen Xue pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 5369d829314SThomas Gleixner irq_set_handler_locked(d, handle_level_irq); 537dbad75ddSKen Xue break; 538dbad75ddSKen Xue 539dbad75ddSKen Xue case IRQ_TYPE_NONE: 540dbad75ddSKen Xue break; 541dbad75ddSKen Xue 542dbad75ddSKen Xue default: 543dbad75ddSKen Xue dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); 544dbad75ddSKen Xue ret = -EINVAL; 545dbad75ddSKen Xue } 546dbad75ddSKen Xue 547dbad75ddSKen Xue pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; 548b85bfa24SDaniel Kurtz /* 549b85bfa24SDaniel Kurtz * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the 550b85bfa24SDaniel Kurtz * debounce registers of any GPIO will block wake/interrupt status 55148c67f1fSMatteo Croce * generation for *all* GPIOs for a length of time that depends on 552b85bfa24SDaniel Kurtz * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the 553b85bfa24SDaniel Kurtz * INTERRUPT_ENABLE bit will read as 0. 554b85bfa24SDaniel Kurtz * 555b85bfa24SDaniel Kurtz * We temporarily enable irq for the GPIO whose configuration is 556b85bfa24SDaniel Kurtz * changing, and then wait for it to read back as 1 to know when 557b85bfa24SDaniel Kurtz * debounce has settled and then disable the irq again. 558b85bfa24SDaniel Kurtz * We do this polling with the spinlock held to ensure other GPIO 559b85bfa24SDaniel Kurtz * access routines do not read an incorrect value for the irq enable 560b85bfa24SDaniel Kurtz * bit of other GPIOs. We keep the GPIO masked while polling to avoid 561b85bfa24SDaniel Kurtz * spurious irqs, and disable the irq again after polling. 562b85bfa24SDaniel Kurtz */ 563b85bfa24SDaniel Kurtz mask = BIT(INTERRUPT_ENABLE_OFF); 564b85bfa24SDaniel Kurtz pin_reg_irq_en = pin_reg; 565b85bfa24SDaniel Kurtz pin_reg_irq_en |= mask; 566b85bfa24SDaniel Kurtz pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF); 567b85bfa24SDaniel Kurtz writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4); 568b85bfa24SDaniel Kurtz while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask) 569b85bfa24SDaniel Kurtz continue; 570dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 571229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 572dbad75ddSKen Xue 573dbad75ddSKen Xue return ret; 574dbad75ddSKen Xue } 575dbad75ddSKen Xue 576dbad75ddSKen Xue static void amd_irq_ack(struct irq_data *d) 577dbad75ddSKen Xue { 578dbad75ddSKen Xue /* 579dbad75ddSKen Xue * based on HW design,there is no need to ack HW 580dbad75ddSKen Xue * before handle current irq. But this routine is 581dbad75ddSKen Xue * necessary for handle_edge_irq 582dbad75ddSKen Xue */ 583dbad75ddSKen Xue } 584dbad75ddSKen Xue 5856173e56fSMarc Zyngier static const struct irq_chip amd_gpio_irqchip = { 586dbad75ddSKen Xue .name = "amd_gpio", 587dbad75ddSKen Xue .irq_ack = amd_irq_ack, 588dbad75ddSKen Xue .irq_enable = amd_gpio_irq_enable, 589dbad75ddSKen Xue .irq_disable = amd_gpio_irq_disable, 590dbad75ddSKen Xue .irq_mask = amd_gpio_irq_mask, 591dbad75ddSKen Xue .irq_unmask = amd_gpio_irq_unmask, 592d62bd5ceSRaul E Rangel .irq_set_wake = amd_gpio_irq_set_wake, 593dbad75ddSKen Xue .irq_eoi = amd_gpio_irq_eoi, 594dbad75ddSKen Xue .irq_set_type = amd_gpio_irq_set_type, 595d62bd5ceSRaul E Rangel /* 596d62bd5ceSRaul E Rangel * We need to set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND so that a wake event 597d62bd5ceSRaul E Rangel * also generates an IRQ. We need the IRQ so the irq_handler can clear 598d62bd5ceSRaul E Rangel * the wake event. Otherwise the wake event will never clear and 599d62bd5ceSRaul E Rangel * prevent the system from suspending. 600d62bd5ceSRaul E Rangel */ 6016173e56fSMarc Zyngier .flags = IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND | IRQCHIP_IMMUTABLE, 6026173e56fSMarc Zyngier GPIOCHIP_IRQ_RESOURCE_HELPERS, 603dbad75ddSKen Xue }; 604dbad75ddSKen Xue 605ba714a9cSThomas Gleixner #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF)) 606ba714a9cSThomas Gleixner 6072d54067fSMario Limonciello static bool do_amd_gpio_irq_handler(int irq, void *dev_id) 608dbad75ddSKen Xue { 609ba714a9cSThomas Gleixner struct amd_gpio *gpio_dev = dev_id; 610ba714a9cSThomas Gleixner struct gpio_chip *gc = &gpio_dev->gc; 611ba714a9cSThomas Gleixner unsigned int i, irqnr; 612dbad75ddSKen Xue unsigned long flags; 61310ff58aaSBen Dooks (Codethink) u32 __iomem *regs; 6142d54067fSMario Limonciello bool ret = false; 61510ff58aaSBen Dooks (Codethink) u32 regval; 616ba714a9cSThomas Gleixner u64 status, mask; 617dbad75ddSKen Xue 618ba714a9cSThomas Gleixner /* Read the wake status */ 619229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 620ba714a9cSThomas Gleixner status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); 621ba714a9cSThomas Gleixner status <<= 32; 622ba714a9cSThomas Gleixner status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0); 623229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 624dbad75ddSKen Xue 625ba714a9cSThomas Gleixner /* Bit 0-45 contain the relevant status bits */ 626ba714a9cSThomas Gleixner status &= (1ULL << 46) - 1; 627ba714a9cSThomas Gleixner regs = gpio_dev->base; 628ba714a9cSThomas Gleixner for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) { 629ba714a9cSThomas Gleixner if (!(status & mask)) 630ba714a9cSThomas Gleixner continue; 631ba714a9cSThomas Gleixner status &= ~mask; 632ba714a9cSThomas Gleixner 633ba714a9cSThomas Gleixner /* Each status bit covers four pins */ 634dbad75ddSKen Xue for (i = 0; i < 4; i++) { 635ba714a9cSThomas Gleixner regval = readl(regs + i); 6362d54067fSMario Limonciello /* caused wake on resume context for shared IRQ */ 6372d54067fSMario Limonciello if (irq < 0 && (regval & BIT(WAKE_STS_OFF))) { 6382d54067fSMario Limonciello dev_dbg(&gpio_dev->pdev->dev, 6392d54067fSMario Limonciello "Waking due to GPIO %d: 0x%x", 6402d54067fSMario Limonciello irqnr + i, regval); 6412d54067fSMario Limonciello return true; 6422d54067fSMario Limonciello } 6432d54067fSMario Limonciello 6448bbed1eeSDaniel Kurtz if (!(regval & PIN_IRQ_PENDING) || 6458bbed1eeSDaniel Kurtz !(regval & BIT(INTERRUPT_MASK_OFF))) 646ba714a9cSThomas Gleixner continue; 647a9cb09b7SMarc Zyngier generic_handle_domain_irq(gc->irq.domain, irqnr + i); 6486afb1026SDaniel Drake 6496afb1026SDaniel Drake /* Clear interrupt. 6506afb1026SDaniel Drake * We must read the pin register again, in case the 6516afb1026SDaniel Drake * value was changed while executing 652a9cb09b7SMarc Zyngier * generic_handle_domain_irq() above. 653d21b8adbSDaniel Drake * If we didn't find a mapping for the interrupt, 654d21b8adbSDaniel Drake * disable it in order to avoid a system hang caused 655d21b8adbSDaniel Drake * by an interrupt storm. 6566afb1026SDaniel Drake */ 6576afb1026SDaniel Drake raw_spin_lock_irqsave(&gpio_dev->lock, flags); 6586afb1026SDaniel Drake regval = readl(regs + i); 659d21b8adbSDaniel Drake if (irq == 0) { 660d21b8adbSDaniel Drake regval &= ~BIT(INTERRUPT_ENABLE_OFF); 661d21b8adbSDaniel Drake dev_dbg(&gpio_dev->pdev->dev, 662d21b8adbSDaniel Drake "Disabling spurious GPIO IRQ %d\n", 663d21b8adbSDaniel Drake irqnr + i); 664d21b8adbSDaniel Drake } 665ba714a9cSThomas Gleixner writel(regval, regs + i); 6666afb1026SDaniel Drake raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 6672d54067fSMario Limonciello ret = true; 668dbad75ddSKen Xue } 669dbad75ddSKen Xue } 6702d54067fSMario Limonciello /* did not cause wake on resume context for shared IRQ */ 6712d54067fSMario Limonciello if (irq < 0) 6722d54067fSMario Limonciello return false; 673dbad75ddSKen Xue 674ba714a9cSThomas Gleixner /* Signal EOI to the GPIO unit */ 675229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 676ba714a9cSThomas Gleixner regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 677ba714a9cSThomas Gleixner regval |= EOI_MASK; 678ba714a9cSThomas Gleixner writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG); 679229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 680dbad75ddSKen Xue 681ba714a9cSThomas Gleixner return ret; 682dbad75ddSKen Xue } 683dbad75ddSKen Xue 6842d54067fSMario Limonciello static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id) 6852d54067fSMario Limonciello { 6862d54067fSMario Limonciello return IRQ_RETVAL(do_amd_gpio_irq_handler(irq, dev_id)); 6872d54067fSMario Limonciello } 6882d54067fSMario Limonciello 6892d54067fSMario Limonciello static bool __maybe_unused amd_gpio_check_wake(void *dev_id) 6902d54067fSMario Limonciello { 6912d54067fSMario Limonciello return do_amd_gpio_irq_handler(-1, dev_id); 6922d54067fSMario Limonciello } 6932d54067fSMario Limonciello 694dbad75ddSKen Xue static int amd_get_groups_count(struct pinctrl_dev *pctldev) 695dbad75ddSKen Xue { 696dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 697dbad75ddSKen Xue 698dbad75ddSKen Xue return gpio_dev->ngroups; 699dbad75ddSKen Xue } 700dbad75ddSKen Xue 701dbad75ddSKen Xue static const char *amd_get_group_name(struct pinctrl_dev *pctldev, 702dbad75ddSKen Xue unsigned group) 703dbad75ddSKen Xue { 704dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 705dbad75ddSKen Xue 706dbad75ddSKen Xue return gpio_dev->groups[group].name; 707dbad75ddSKen Xue } 708dbad75ddSKen Xue 709dbad75ddSKen Xue static int amd_get_group_pins(struct pinctrl_dev *pctldev, 710dbad75ddSKen Xue unsigned group, 711dbad75ddSKen Xue const unsigned **pins, 712dbad75ddSKen Xue unsigned *num_pins) 713dbad75ddSKen Xue { 714dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 715dbad75ddSKen Xue 716dbad75ddSKen Xue *pins = gpio_dev->groups[group].pins; 717dbad75ddSKen Xue *num_pins = gpio_dev->groups[group].npins; 718dbad75ddSKen Xue return 0; 719dbad75ddSKen Xue } 720dbad75ddSKen Xue 721dbad75ddSKen Xue static const struct pinctrl_ops amd_pinctrl_ops = { 722dbad75ddSKen Xue .get_groups_count = amd_get_groups_count, 723dbad75ddSKen Xue .get_group_name = amd_get_group_name, 724dbad75ddSKen Xue .get_group_pins = amd_get_group_pins, 725dbad75ddSKen Xue #ifdef CONFIG_OF 726dbad75ddSKen Xue .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 727d32f7fd3SIrina Tirdea .dt_free_map = pinctrl_utils_free_map, 728dbad75ddSKen Xue #endif 729dbad75ddSKen Xue }; 730dbad75ddSKen Xue 731dbad75ddSKen Xue static int amd_pinconf_get(struct pinctrl_dev *pctldev, 732dbad75ddSKen Xue unsigned int pin, 733dbad75ddSKen Xue unsigned long *config) 734dbad75ddSKen Xue { 735dbad75ddSKen Xue u32 pin_reg; 736dbad75ddSKen Xue unsigned arg; 737dbad75ddSKen Xue unsigned long flags; 738dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 739dbad75ddSKen Xue enum pin_config_param param = pinconf_to_config_param(*config); 740dbad75ddSKen Xue 741229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 742dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + pin*4); 743229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 744dbad75ddSKen Xue switch (param) { 745dbad75ddSKen Xue case PIN_CONFIG_INPUT_DEBOUNCE: 746dbad75ddSKen Xue arg = pin_reg & DB_TMR_OUT_MASK; 747dbad75ddSKen Xue break; 748dbad75ddSKen Xue 749dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_DOWN: 750dbad75ddSKen Xue arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); 751dbad75ddSKen Xue break; 752dbad75ddSKen Xue 753dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_UP: 754dbad75ddSKen Xue arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); 755dbad75ddSKen Xue break; 756dbad75ddSKen Xue 757dbad75ddSKen Xue case PIN_CONFIG_DRIVE_STRENGTH: 758dbad75ddSKen Xue arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; 759dbad75ddSKen Xue break; 760dbad75ddSKen Xue 761dbad75ddSKen Xue default: 762dbad75ddSKen Xue dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n", 763dbad75ddSKen Xue param); 764dbad75ddSKen Xue return -ENOTSUPP; 765dbad75ddSKen Xue } 766dbad75ddSKen Xue 767dbad75ddSKen Xue *config = pinconf_to_config_packed(param, arg); 768dbad75ddSKen Xue 769dbad75ddSKen Xue return 0; 770dbad75ddSKen Xue } 771dbad75ddSKen Xue 772dbad75ddSKen Xue static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 773dbad75ddSKen Xue unsigned long *configs, unsigned num_configs) 774dbad75ddSKen Xue { 775dbad75ddSKen Xue int i; 776dbad75ddSKen Xue u32 arg; 77725a853d0SKen Xue int ret = 0; 77825a853d0SKen Xue u32 pin_reg; 779dbad75ddSKen Xue unsigned long flags; 780dbad75ddSKen Xue enum pin_config_param param; 781dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 782dbad75ddSKen Xue 783229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 784dbad75ddSKen Xue for (i = 0; i < num_configs; i++) { 785dbad75ddSKen Xue param = pinconf_to_config_param(configs[i]); 786dbad75ddSKen Xue arg = pinconf_to_config_argument(configs[i]); 787dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + pin*4); 788dbad75ddSKen Xue 789dbad75ddSKen Xue switch (param) { 790dbad75ddSKen Xue case PIN_CONFIG_INPUT_DEBOUNCE: 791dbad75ddSKen Xue pin_reg &= ~DB_TMR_OUT_MASK; 792dbad75ddSKen Xue pin_reg |= arg & DB_TMR_OUT_MASK; 793dbad75ddSKen Xue break; 794dbad75ddSKen Xue 795dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_DOWN: 796dbad75ddSKen Xue pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); 797dbad75ddSKen Xue pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; 798dbad75ddSKen Xue break; 799dbad75ddSKen Xue 800dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_UP: 801dbad75ddSKen Xue pin_reg &= ~BIT(PULL_UP_SEL_OFF); 802dbad75ddSKen Xue pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; 803dbad75ddSKen Xue pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); 804dbad75ddSKen Xue pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; 805dbad75ddSKen Xue break; 806dbad75ddSKen Xue 807dbad75ddSKen Xue case PIN_CONFIG_DRIVE_STRENGTH: 808dbad75ddSKen Xue pin_reg &= ~(DRV_STRENGTH_SEL_MASK 809dbad75ddSKen Xue << DRV_STRENGTH_SEL_OFF); 810dbad75ddSKen Xue pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) 811dbad75ddSKen Xue << DRV_STRENGTH_SEL_OFF; 812dbad75ddSKen Xue break; 813dbad75ddSKen Xue 814dbad75ddSKen Xue default: 815dbad75ddSKen Xue dev_err(&gpio_dev->pdev->dev, 816dbad75ddSKen Xue "Invalid config param %04x\n", param); 81725a853d0SKen Xue ret = -ENOTSUPP; 818dbad75ddSKen Xue } 819dbad75ddSKen Xue 820dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + pin*4); 821dbad75ddSKen Xue } 822229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 823dbad75ddSKen Xue 82425a853d0SKen Xue return ret; 825dbad75ddSKen Xue } 826dbad75ddSKen Xue 827dbad75ddSKen Xue static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, 828dbad75ddSKen Xue unsigned int group, 829dbad75ddSKen Xue unsigned long *config) 830dbad75ddSKen Xue { 831dbad75ddSKen Xue const unsigned *pins; 832dbad75ddSKen Xue unsigned npins; 833dbad75ddSKen Xue int ret; 834dbad75ddSKen Xue 835dbad75ddSKen Xue ret = amd_get_group_pins(pctldev, group, &pins, &npins); 836dbad75ddSKen Xue if (ret) 837dbad75ddSKen Xue return ret; 838dbad75ddSKen Xue 839dbad75ddSKen Xue if (amd_pinconf_get(pctldev, pins[0], config)) 840dbad75ddSKen Xue return -ENOTSUPP; 841dbad75ddSKen Xue 842dbad75ddSKen Xue return 0; 843dbad75ddSKen Xue } 844dbad75ddSKen Xue 845dbad75ddSKen Xue static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, 846dbad75ddSKen Xue unsigned group, unsigned long *configs, 847dbad75ddSKen Xue unsigned num_configs) 848dbad75ddSKen Xue { 849dbad75ddSKen Xue const unsigned *pins; 850dbad75ddSKen Xue unsigned npins; 851dbad75ddSKen Xue int i, ret; 852dbad75ddSKen Xue 853dbad75ddSKen Xue ret = amd_get_group_pins(pctldev, group, &pins, &npins); 854dbad75ddSKen Xue if (ret) 855dbad75ddSKen Xue return ret; 856dbad75ddSKen Xue for (i = 0; i < npins; i++) { 857dbad75ddSKen Xue if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) 858dbad75ddSKen Xue return -ENOTSUPP; 859dbad75ddSKen Xue } 860dbad75ddSKen Xue return 0; 861dbad75ddSKen Xue } 862dbad75ddSKen Xue 863dbad75ddSKen Xue static const struct pinconf_ops amd_pinconf_ops = { 864dbad75ddSKen Xue .pin_config_get = amd_pinconf_get, 865dbad75ddSKen Xue .pin_config_set = amd_pinconf_set, 866dbad75ddSKen Xue .pin_config_group_get = amd_pinconf_group_get, 867dbad75ddSKen Xue .pin_config_group_set = amd_pinconf_group_set, 868dbad75ddSKen Xue }; 869dbad75ddSKen Xue 8704e5a04beSSachi King static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) 8714e5a04beSSachi King { 8724e5a04beSSachi King struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 8734e5a04beSSachi King unsigned long flags; 8744e5a04beSSachi King u32 pin_reg, mask; 8754e5a04beSSachi King int i; 8764e5a04beSSachi King 8774e5a04beSSachi King mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) | 8784e5a04beSSachi King BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) | 8794e5a04beSSachi King BIT(WAKE_CNTRL_OFF_S4); 8804e5a04beSSachi King 8814e5a04beSSachi King for (i = 0; i < desc->npins; i++) { 8824e5a04beSSachi King int pin = desc->pins[i].number; 8834e5a04beSSachi King const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 8844e5a04beSSachi King 8854e5a04beSSachi King if (!pd) 8864e5a04beSSachi King continue; 8874e5a04beSSachi King 8884e5a04beSSachi King raw_spin_lock_irqsave(&gpio_dev->lock, flags); 8894e5a04beSSachi King 8904e5a04beSSachi King pin_reg = readl(gpio_dev->base + i * 4); 8914e5a04beSSachi King pin_reg &= ~mask; 8924e5a04beSSachi King writel(pin_reg, gpio_dev->base + i * 4); 8934e5a04beSSachi King 8944e5a04beSSachi King raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 8954e5a04beSSachi King } 8964e5a04beSSachi King } 8974e5a04beSSachi King 89879d2c8beSDaniel Drake #ifdef CONFIG_PM_SLEEP 89979d2c8beSDaniel Drake static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) 90079d2c8beSDaniel Drake { 90179d2c8beSDaniel Drake const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 90279d2c8beSDaniel Drake 90379d2c8beSDaniel Drake if (!pd) 90479d2c8beSDaniel Drake return false; 90579d2c8beSDaniel Drake 90679d2c8beSDaniel Drake /* 90779d2c8beSDaniel Drake * Only restore the pin if it is actually in use by the kernel (or 90879d2c8beSDaniel Drake * by userspace). 90979d2c8beSDaniel Drake */ 91079d2c8beSDaniel Drake if (pd->mux_owner || pd->gpio_owner || 91179d2c8beSDaniel Drake gpiochip_line_is_irq(&gpio_dev->gc, pin)) 91279d2c8beSDaniel Drake return true; 91379d2c8beSDaniel Drake 91479d2c8beSDaniel Drake return false; 91579d2c8beSDaniel Drake } 91679d2c8beSDaniel Drake 9172d71dfa2SColin Ian King static int amd_gpio_suspend(struct device *dev) 91879d2c8beSDaniel Drake { 9199f540c3eSWolfram Sang struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 92079d2c8beSDaniel Drake struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 921*b8c824a8SBasavaraj Natikar unsigned long flags; 92279d2c8beSDaniel Drake int i; 92379d2c8beSDaniel Drake 92479d2c8beSDaniel Drake for (i = 0; i < desc->npins; i++) { 92579d2c8beSDaniel Drake int pin = desc->pins[i].number; 92679d2c8beSDaniel Drake 92779d2c8beSDaniel Drake if (!amd_gpio_should_save(gpio_dev, pin)) 92879d2c8beSDaniel Drake continue; 92979d2c8beSDaniel Drake 930*b8c824a8SBasavaraj Natikar raw_spin_lock_irqsave(&gpio_dev->lock, flags); 931*b8c824a8SBasavaraj Natikar gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING; 932*b8c824a8SBasavaraj Natikar raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 93379d2c8beSDaniel Drake } 93479d2c8beSDaniel Drake 93579d2c8beSDaniel Drake return 0; 93679d2c8beSDaniel Drake } 93779d2c8beSDaniel Drake 9382d71dfa2SColin Ian King static int amd_gpio_resume(struct device *dev) 93979d2c8beSDaniel Drake { 9409f540c3eSWolfram Sang struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 94179d2c8beSDaniel Drake struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 942*b8c824a8SBasavaraj Natikar unsigned long flags; 94379d2c8beSDaniel Drake int i; 94479d2c8beSDaniel Drake 94579d2c8beSDaniel Drake for (i = 0; i < desc->npins; i++) { 94679d2c8beSDaniel Drake int pin = desc->pins[i].number; 94779d2c8beSDaniel Drake 94879d2c8beSDaniel Drake if (!amd_gpio_should_save(gpio_dev, pin)) 94979d2c8beSDaniel Drake continue; 95079d2c8beSDaniel Drake 951*b8c824a8SBasavaraj Natikar raw_spin_lock_irqsave(&gpio_dev->lock, flags); 952*b8c824a8SBasavaraj Natikar gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING; 95379d2c8beSDaniel Drake writel(gpio_dev->saved_regs[i], gpio_dev->base + pin * 4); 954*b8c824a8SBasavaraj Natikar raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 95579d2c8beSDaniel Drake } 95679d2c8beSDaniel Drake 95779d2c8beSDaniel Drake return 0; 95879d2c8beSDaniel Drake } 95979d2c8beSDaniel Drake 96079d2c8beSDaniel Drake static const struct dev_pm_ops amd_gpio_pm_ops = { 96179d2c8beSDaniel Drake SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend, 96279d2c8beSDaniel Drake amd_gpio_resume) 96379d2c8beSDaniel Drake }; 96479d2c8beSDaniel Drake #endif 96579d2c8beSDaniel Drake 96672440158SBasavaraj Natikar static int amd_get_functions_count(struct pinctrl_dev *pctldev) 96772440158SBasavaraj Natikar { 96872440158SBasavaraj Natikar return ARRAY_SIZE(pmx_functions); 96972440158SBasavaraj Natikar } 97072440158SBasavaraj Natikar 97172440158SBasavaraj Natikar static const char *amd_get_fname(struct pinctrl_dev *pctrldev, unsigned int selector) 97272440158SBasavaraj Natikar { 97372440158SBasavaraj Natikar return pmx_functions[selector].name; 97472440158SBasavaraj Natikar } 97572440158SBasavaraj Natikar 97672440158SBasavaraj Natikar static int amd_get_groups(struct pinctrl_dev *pctrldev, unsigned int selector, 97772440158SBasavaraj Natikar const char * const **groups, 97872440158SBasavaraj Natikar unsigned int * const num_groups) 97972440158SBasavaraj Natikar { 98072440158SBasavaraj Natikar struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev); 98172440158SBasavaraj Natikar 98272440158SBasavaraj Natikar if (!gpio_dev->iomux_base) { 98372440158SBasavaraj Natikar dev_err(&gpio_dev->pdev->dev, "iomux function %d group not supported\n", selector); 98472440158SBasavaraj Natikar return -EINVAL; 98572440158SBasavaraj Natikar } 98672440158SBasavaraj Natikar 98772440158SBasavaraj Natikar *groups = pmx_functions[selector].groups; 98872440158SBasavaraj Natikar *num_groups = pmx_functions[selector].ngroups; 98972440158SBasavaraj Natikar return 0; 99072440158SBasavaraj Natikar } 99172440158SBasavaraj Natikar 99272440158SBasavaraj Natikar static int amd_set_mux(struct pinctrl_dev *pctrldev, unsigned int function, unsigned int group) 99372440158SBasavaraj Natikar { 99472440158SBasavaraj Natikar struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev); 99572440158SBasavaraj Natikar struct device *dev = &gpio_dev->pdev->dev; 99672440158SBasavaraj Natikar struct pin_desc *pd; 99772440158SBasavaraj Natikar int ind, index; 99872440158SBasavaraj Natikar 99972440158SBasavaraj Natikar if (!gpio_dev->iomux_base) 100072440158SBasavaraj Natikar return -EINVAL; 100172440158SBasavaraj Natikar 100272440158SBasavaraj Natikar for (index = 0; index < NSELECTS; index++) { 100372440158SBasavaraj Natikar if (strcmp(gpio_dev->groups[group].name, pmx_functions[function].groups[index])) 100472440158SBasavaraj Natikar continue; 100572440158SBasavaraj Natikar 100672440158SBasavaraj Natikar if (readb(gpio_dev->iomux_base + pmx_functions[function].index) == 100772440158SBasavaraj Natikar FUNCTION_INVALID) { 100872440158SBasavaraj Natikar dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n", 100972440158SBasavaraj Natikar pmx_functions[function].index); 101072440158SBasavaraj Natikar return -EINVAL; 101172440158SBasavaraj Natikar } 101272440158SBasavaraj Natikar 101372440158SBasavaraj Natikar writeb(index, gpio_dev->iomux_base + pmx_functions[function].index); 101472440158SBasavaraj Natikar 101572440158SBasavaraj Natikar if (index != (readb(gpio_dev->iomux_base + pmx_functions[function].index) & 101672440158SBasavaraj Natikar FUNCTION_MASK)) { 101772440158SBasavaraj Natikar dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n", 101872440158SBasavaraj Natikar pmx_functions[function].index); 101972440158SBasavaraj Natikar return -EINVAL; 102072440158SBasavaraj Natikar } 102172440158SBasavaraj Natikar 102272440158SBasavaraj Natikar for (ind = 0; ind < gpio_dev->groups[group].npins; ind++) { 102372440158SBasavaraj Natikar if (strncmp(gpio_dev->groups[group].name, "IMX_F", strlen("IMX_F"))) 102472440158SBasavaraj Natikar continue; 102572440158SBasavaraj Natikar 102672440158SBasavaraj Natikar pd = pin_desc_get(gpio_dev->pctrl, gpio_dev->groups[group].pins[ind]); 102772440158SBasavaraj Natikar pd->mux_owner = gpio_dev->groups[group].name; 102872440158SBasavaraj Natikar } 102972440158SBasavaraj Natikar break; 103072440158SBasavaraj Natikar } 103172440158SBasavaraj Natikar 103272440158SBasavaraj Natikar return 0; 103372440158SBasavaraj Natikar } 103472440158SBasavaraj Natikar 103572440158SBasavaraj Natikar static const struct pinmux_ops amd_pmxops = { 103672440158SBasavaraj Natikar .get_functions_count = amd_get_functions_count, 103772440158SBasavaraj Natikar .get_function_name = amd_get_fname, 103872440158SBasavaraj Natikar .get_function_groups = amd_get_groups, 103972440158SBasavaraj Natikar .set_mux = amd_set_mux, 104072440158SBasavaraj Natikar }; 104172440158SBasavaraj Natikar 1042dbad75ddSKen Xue static struct pinctrl_desc amd_pinctrl_desc = { 1043dbad75ddSKen Xue .pins = kerncz_pins, 1044dbad75ddSKen Xue .npins = ARRAY_SIZE(kerncz_pins), 1045dbad75ddSKen Xue .pctlops = &amd_pinctrl_ops, 104672440158SBasavaraj Natikar .pmxops = &amd_pmxops, 1047dbad75ddSKen Xue .confops = &amd_pinconf_ops, 1048dbad75ddSKen Xue .owner = THIS_MODULE, 1049dbad75ddSKen Xue }; 1050dbad75ddSKen Xue 105179bb5c7fSBasavaraj Natikar static void amd_get_iomux_res(struct amd_gpio *gpio_dev) 105279bb5c7fSBasavaraj Natikar { 105379bb5c7fSBasavaraj Natikar struct pinctrl_desc *desc = &amd_pinctrl_desc; 105479bb5c7fSBasavaraj Natikar struct device *dev = &gpio_dev->pdev->dev; 105579bb5c7fSBasavaraj Natikar int index; 105679bb5c7fSBasavaraj Natikar 105779bb5c7fSBasavaraj Natikar index = device_property_match_string(dev, "pinctrl-resource-names", "iomux"); 105879bb5c7fSBasavaraj Natikar if (index < 0) { 105979bb5c7fSBasavaraj Natikar dev_warn(dev, "failed to get iomux index\n"); 106079bb5c7fSBasavaraj Natikar goto out_no_pinmux; 106179bb5c7fSBasavaraj Natikar } 106279bb5c7fSBasavaraj Natikar 106379bb5c7fSBasavaraj Natikar gpio_dev->iomux_base = devm_platform_ioremap_resource(gpio_dev->pdev, index); 106479bb5c7fSBasavaraj Natikar if (IS_ERR(gpio_dev->iomux_base)) { 106579bb5c7fSBasavaraj Natikar dev_warn(dev, "Failed to get iomux %d io resource\n", index); 106679bb5c7fSBasavaraj Natikar goto out_no_pinmux; 106779bb5c7fSBasavaraj Natikar } 106879bb5c7fSBasavaraj Natikar 106979bb5c7fSBasavaraj Natikar return; 107079bb5c7fSBasavaraj Natikar 107179bb5c7fSBasavaraj Natikar out_no_pinmux: 107279bb5c7fSBasavaraj Natikar desc->pmxops = NULL; 107379bb5c7fSBasavaraj Natikar } 107479bb5c7fSBasavaraj Natikar 1075dbad75ddSKen Xue static int amd_gpio_probe(struct platform_device *pdev) 1076dbad75ddSKen Xue { 1077dbad75ddSKen Xue int ret = 0; 1078dbad75ddSKen Xue struct resource *res; 1079dbad75ddSKen Xue struct amd_gpio *gpio_dev; 1080e81376ebSLinus Walleij struct gpio_irq_chip *girq; 1081dbad75ddSKen Xue 1082dbad75ddSKen Xue gpio_dev = devm_kzalloc(&pdev->dev, 1083dbad75ddSKen Xue sizeof(struct amd_gpio), GFP_KERNEL); 1084dbad75ddSKen Xue if (!gpio_dev) 1085dbad75ddSKen Xue return -ENOMEM; 1086dbad75ddSKen Xue 1087229710feSJulia Cartwright raw_spin_lock_init(&gpio_dev->lock); 1088dbad75ddSKen Xue 108921793d22SBasavaraj Natikar gpio_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 109021793d22SBasavaraj Natikar if (IS_ERR(gpio_dev->base)) { 1091dbad75ddSKen Xue dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); 109221793d22SBasavaraj Natikar return PTR_ERR(gpio_dev->base); 1093dbad75ddSKen Xue } 1094dbad75ddSKen Xue 10957e6f8d6fSBasavaraj Natikar gpio_dev->irq = platform_get_irq(pdev, 0); 10967e6f8d6fSBasavaraj Natikar if (gpio_dev->irq < 0) 10977e6f8d6fSBasavaraj Natikar return gpio_dev->irq; 1098dbad75ddSKen Xue 109979d2c8beSDaniel Drake #ifdef CONFIG_PM_SLEEP 110079d2c8beSDaniel Drake gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins, 110179d2c8beSDaniel Drake sizeof(*gpio_dev->saved_regs), 110279d2c8beSDaniel Drake GFP_KERNEL); 110379d2c8beSDaniel Drake if (!gpio_dev->saved_regs) 110479d2c8beSDaniel Drake return -ENOMEM; 110579d2c8beSDaniel Drake #endif 110679d2c8beSDaniel Drake 1107dbad75ddSKen Xue gpio_dev->pdev = pdev; 110812b10f47SDaniel Kurtz gpio_dev->gc.get_direction = amd_gpio_get_direction; 1109dbad75ddSKen Xue gpio_dev->gc.direction_input = amd_gpio_direction_input; 1110dbad75ddSKen Xue gpio_dev->gc.direction_output = amd_gpio_direction_output; 1111dbad75ddSKen Xue gpio_dev->gc.get = amd_gpio_get_value; 1112dbad75ddSKen Xue gpio_dev->gc.set = amd_gpio_set_value; 11132956b5d9SMika Westerberg gpio_dev->gc.set_config = amd_gpio_set_config; 1114dbad75ddSKen Xue gpio_dev->gc.dbg_show = amd_gpio_dbg_show; 1115dbad75ddSKen Xue 11163bfd4430SShah, Nehal-bakulchandra gpio_dev->gc.base = -1; 1117dbad75ddSKen Xue gpio_dev->gc.label = pdev->name; 1118dbad75ddSKen Xue gpio_dev->gc.owner = THIS_MODULE; 111958383c78SLinus Walleij gpio_dev->gc.parent = &pdev->dev; 11203bfd4430SShah, Nehal-bakulchandra gpio_dev->gc.ngpio = resource_size(res) / 4; 1121dbad75ddSKen Xue 11223bfd4430SShah, Nehal-bakulchandra gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64; 1123dbad75ddSKen Xue gpio_dev->groups = kerncz_groups; 1124dbad75ddSKen Xue gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); 1125dbad75ddSKen Xue 1126dbad75ddSKen Xue amd_pinctrl_desc.name = dev_name(&pdev->dev); 112779bb5c7fSBasavaraj Natikar amd_get_iomux_res(gpio_dev); 1128251e22abSLaxman Dewangan gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, 1129251e22abSLaxman Dewangan gpio_dev); 1130323de9efSMasahiro Yamada if (IS_ERR(gpio_dev->pctrl)) { 1131dbad75ddSKen Xue dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 1132323de9efSMasahiro Yamada return PTR_ERR(gpio_dev->pctrl); 1133dbad75ddSKen Xue } 1134dbad75ddSKen Xue 11354e5a04beSSachi King /* Disable and mask interrupts */ 11364e5a04beSSachi King amd_gpio_irq_init(gpio_dev); 11374e5a04beSSachi King 1138e81376ebSLinus Walleij girq = &gpio_dev->gc.irq; 11396173e56fSMarc Zyngier gpio_irq_chip_set_chip(girq, &amd_gpio_irqchip); 1140e81376ebSLinus Walleij /* This will let us handle the parent IRQ in the driver */ 1141e81376ebSLinus Walleij girq->parent_handler = NULL; 1142e81376ebSLinus Walleij girq->num_parents = 0; 1143e81376ebSLinus Walleij girq->parents = NULL; 1144e81376ebSLinus Walleij girq->default_type = IRQ_TYPE_NONE; 1145e81376ebSLinus Walleij girq->handler = handle_simple_irq; 1146e81376ebSLinus Walleij 114704d36723SLinus Walleij ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); 1148dbad75ddSKen Xue if (ret) 1149251e22abSLaxman Dewangan return ret; 1150dbad75ddSKen Xue 1151dbad75ddSKen Xue ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), 11523bfd4430SShah, Nehal-bakulchandra 0, 0, gpio_dev->gc.ngpio); 1153dbad75ddSKen Xue if (ret) { 1154dbad75ddSKen Xue dev_err(&pdev->dev, "Failed to add pin range\n"); 1155dbad75ddSKen Xue goto out2; 1156dbad75ddSKen Xue } 1157dbad75ddSKen Xue 11587e6f8d6fSBasavaraj Natikar ret = devm_request_irq(&pdev->dev, gpio_dev->irq, amd_gpio_irq_handler, 1159279ffafaSSandeep Singh IRQF_SHARED, KBUILD_MODNAME, gpio_dev); 1160ba714a9cSThomas Gleixner if (ret) 1161ba714a9cSThomas Gleixner goto out2; 1162ba714a9cSThomas Gleixner 1163dbad75ddSKen Xue platform_set_drvdata(pdev, gpio_dev); 11642d54067fSMario Limonciello acpi_register_wakeup_handler(gpio_dev->irq, amd_gpio_check_wake, gpio_dev); 1165dbad75ddSKen Xue 1166dbad75ddSKen Xue dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); 1167dbad75ddSKen Xue return ret; 1168dbad75ddSKen Xue 1169dbad75ddSKen Xue out2: 1170dbad75ddSKen Xue gpiochip_remove(&gpio_dev->gc); 1171dbad75ddSKen Xue 1172dbad75ddSKen Xue return ret; 1173dbad75ddSKen Xue } 1174dbad75ddSKen Xue 1175dbad75ddSKen Xue static int amd_gpio_remove(struct platform_device *pdev) 1176dbad75ddSKen Xue { 1177dbad75ddSKen Xue struct amd_gpio *gpio_dev; 1178dbad75ddSKen Xue 1179dbad75ddSKen Xue gpio_dev = platform_get_drvdata(pdev); 1180dbad75ddSKen Xue 1181dbad75ddSKen Xue gpiochip_remove(&gpio_dev->gc); 11822d54067fSMario Limonciello acpi_unregister_wakeup_handler(amd_gpio_check_wake, gpio_dev); 1183dbad75ddSKen Xue 1184dbad75ddSKen Xue return 0; 1185dbad75ddSKen Xue } 1186dbad75ddSKen Xue 1187de4334f7SLee Jones #ifdef CONFIG_ACPI 1188dbad75ddSKen Xue static const struct acpi_device_id amd_gpio_acpi_match[] = { 1189dbad75ddSKen Xue { "AMD0030", 0 }, 119042a44402SWang Hongcheng { "AMDI0030", 0}, 11911ca46d3eSMaximilian Luz { "AMDI0031", 0}, 1192dbad75ddSKen Xue { }, 1193dbad75ddSKen Xue }; 1194dbad75ddSKen Xue MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); 1195de4334f7SLee Jones #endif 1196dbad75ddSKen Xue 1197dbad75ddSKen Xue static struct platform_driver amd_gpio_driver = { 1198dbad75ddSKen Xue .driver = { 1199dbad75ddSKen Xue .name = "amd_gpio", 1200dbad75ddSKen Xue .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), 120179d2c8beSDaniel Drake #ifdef CONFIG_PM_SLEEP 120279d2c8beSDaniel Drake .pm = &amd_gpio_pm_ops, 120379d2c8beSDaniel Drake #endif 1204dbad75ddSKen Xue }, 1205dbad75ddSKen Xue .probe = amd_gpio_probe, 1206dbad75ddSKen Xue .remove = amd_gpio_remove, 1207dbad75ddSKen Xue }; 1208dbad75ddSKen Xue 1209dbad75ddSKen Xue module_platform_driver(amd_gpio_driver); 1210dbad75ddSKen Xue 1211dbad75ddSKen Xue MODULE_LICENSE("GPL v2"); 1212dbad75ddSKen Xue MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); 1213dbad75ddSKen Xue MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); 1214