175a6faf6SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2dbad75ddSKen Xue /* 3dbad75ddSKen Xue * GPIO driver for AMD 4dbad75ddSKen Xue * 5dbad75ddSKen Xue * Copyright (c) 2014,2015 AMD Corporation. 6dbad75ddSKen Xue * Authors: Ken Xue <Ken.Xue@amd.com> 7dbad75ddSKen Xue * Wu, Jeff <Jeff.Wu@amd.com> 8dbad75ddSKen Xue * 9add7bfceSShyam Sundar S K * Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com> 10add7bfceSShyam Sundar S K * Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 11dbad75ddSKen Xue */ 12dbad75ddSKen Xue 13dbad75ddSKen Xue #include <linux/err.h> 14dbad75ddSKen Xue #include <linux/bug.h> 15dbad75ddSKen Xue #include <linux/kernel.h> 16dbad75ddSKen Xue #include <linux/module.h> 17dbad75ddSKen Xue #include <linux/spinlock.h> 18dbad75ddSKen Xue #include <linux/compiler.h> 19dbad75ddSKen Xue #include <linux/types.h> 20dbad75ddSKen Xue #include <linux/errno.h> 21dbad75ddSKen Xue #include <linux/log2.h> 22dbad75ddSKen Xue #include <linux/io.h> 231c5fb66aSLinus Walleij #include <linux/gpio/driver.h> 24dbad75ddSKen Xue #include <linux/slab.h> 25dbad75ddSKen Xue #include <linux/platform_device.h> 26dbad75ddSKen Xue #include <linux/mutex.h> 27dbad75ddSKen Xue #include <linux/acpi.h> 28dbad75ddSKen Xue #include <linux/seq_file.h> 29dbad75ddSKen Xue #include <linux/interrupt.h> 30dbad75ddSKen Xue #include <linux/list.h> 31dbad75ddSKen Xue #include <linux/bitops.h> 32dbad75ddSKen Xue #include <linux/pinctrl/pinconf.h> 33dbad75ddSKen Xue #include <linux/pinctrl/pinconf-generic.h> 34dbad75ddSKen Xue 3579d2c8beSDaniel Drake #include "core.h" 36dbad75ddSKen Xue #include "pinctrl-utils.h" 37dbad75ddSKen Xue #include "pinctrl-amd.h" 38dbad75ddSKen Xue 3912b10f47SDaniel Kurtz static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset) 4012b10f47SDaniel Kurtz { 4112b10f47SDaniel Kurtz unsigned long flags; 4212b10f47SDaniel Kurtz u32 pin_reg; 4312b10f47SDaniel Kurtz struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 4412b10f47SDaniel Kurtz 4512b10f47SDaniel Kurtz raw_spin_lock_irqsave(&gpio_dev->lock, flags); 4612b10f47SDaniel Kurtz pin_reg = readl(gpio_dev->base + offset * 4); 4712b10f47SDaniel Kurtz raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 4812b10f47SDaniel Kurtz 493c827873SMatti Vaittinen if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) 503c827873SMatti Vaittinen return GPIO_LINE_DIRECTION_OUT; 513c827873SMatti Vaittinen 523c827873SMatti Vaittinen return GPIO_LINE_DIRECTION_IN; 5312b10f47SDaniel Kurtz } 5412b10f47SDaniel Kurtz 55dbad75ddSKen Xue static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 56dbad75ddSKen Xue { 57dbad75ddSKen Xue unsigned long flags; 58dbad75ddSKen Xue u32 pin_reg; 5904d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 60dbad75ddSKen Xue 61229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 62dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 63dbad75ddSKen Xue pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); 64dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4); 65229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 66dbad75ddSKen Xue 67dbad75ddSKen Xue return 0; 68dbad75ddSKen Xue } 69dbad75ddSKen Xue 70dbad75ddSKen Xue static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 71dbad75ddSKen Xue int value) 72dbad75ddSKen Xue { 73dbad75ddSKen Xue u32 pin_reg; 74dbad75ddSKen Xue unsigned long flags; 7504d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 76dbad75ddSKen Xue 77229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 78dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 79dbad75ddSKen Xue pin_reg |= BIT(OUTPUT_ENABLE_OFF); 80dbad75ddSKen Xue if (value) 81dbad75ddSKen Xue pin_reg |= BIT(OUTPUT_VALUE_OFF); 82dbad75ddSKen Xue else 83dbad75ddSKen Xue pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 84dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4); 85229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 86dbad75ddSKen Xue 87dbad75ddSKen Xue return 0; 88dbad75ddSKen Xue } 89dbad75ddSKen Xue 90dbad75ddSKen Xue static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) 91dbad75ddSKen Xue { 92dbad75ddSKen Xue u32 pin_reg; 93dbad75ddSKen Xue unsigned long flags; 9404d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 95dbad75ddSKen Xue 96229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 97dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 98229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 99dbad75ddSKen Xue 100dbad75ddSKen Xue return !!(pin_reg & BIT(PIN_STS_OFF)); 101dbad75ddSKen Xue } 102dbad75ddSKen Xue 103dbad75ddSKen Xue static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) 104dbad75ddSKen Xue { 105dbad75ddSKen Xue u32 pin_reg; 106dbad75ddSKen Xue unsigned long flags; 10704d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 108dbad75ddSKen Xue 109229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 110dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 111dbad75ddSKen Xue if (value) 112dbad75ddSKen Xue pin_reg |= BIT(OUTPUT_VALUE_OFF); 113dbad75ddSKen Xue else 114dbad75ddSKen Xue pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 115dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4); 116229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 117dbad75ddSKen Xue } 118dbad75ddSKen Xue 119dbad75ddSKen Xue static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, 120dbad75ddSKen Xue unsigned debounce) 121dbad75ddSKen Xue { 122dbad75ddSKen Xue u32 time; 12325a853d0SKen Xue u32 pin_reg; 12425a853d0SKen Xue int ret = 0; 125dbad75ddSKen Xue unsigned long flags; 12604d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 127dbad75ddSKen Xue 128229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 129dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 130dbad75ddSKen Xue 131dbad75ddSKen Xue if (debounce) { 132dbad75ddSKen Xue pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 133dbad75ddSKen Xue pin_reg &= ~DB_TMR_OUT_MASK; 134dbad75ddSKen Xue /* 135dbad75ddSKen Xue Debounce Debounce Timer Max 136dbad75ddSKen Xue TmrLarge TmrOutUnit Unit Debounce 137dbad75ddSKen Xue Time 138dbad75ddSKen Xue 0 0 61 usec (2 RtcClk) 976 usec 139dbad75ddSKen Xue 0 1 244 usec (8 RtcClk) 3.9 msec 140dbad75ddSKen Xue 1 0 15.6 msec (512 RtcClk) 250 msec 141dbad75ddSKen Xue 1 1 62.5 msec (2048 RtcClk) 1 sec 142dbad75ddSKen Xue */ 143dbad75ddSKen Xue 144dbad75ddSKen Xue if (debounce < 61) { 145dbad75ddSKen Xue pin_reg |= 1; 146dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 147dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 148dbad75ddSKen Xue } else if (debounce < 976) { 149dbad75ddSKen Xue time = debounce / 61; 150dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK; 151dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 152dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 153dbad75ddSKen Xue } else if (debounce < 3900) { 154dbad75ddSKen Xue time = debounce / 244; 155dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK; 156dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 157dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 158dbad75ddSKen Xue } else if (debounce < 250000) { 159c64a6a0dSCoiby Xu time = debounce / 15625; 160dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK; 161dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 162dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_LARGE_OFF); 163dbad75ddSKen Xue } else if (debounce < 1000000) { 164dbad75ddSKen Xue time = debounce / 62500; 165dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK; 166dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 167dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_LARGE_OFF); 168dbad75ddSKen Xue } else { 16906abe829SCoiby Xu pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 17025a853d0SKen Xue ret = -EINVAL; 171dbad75ddSKen Xue } 172dbad75ddSKen Xue } else { 173dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 174dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 175dbad75ddSKen Xue pin_reg &= ~DB_TMR_OUT_MASK; 17606abe829SCoiby Xu pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 177dbad75ddSKen Xue } 178dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4); 179229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 180dbad75ddSKen Xue 18125a853d0SKen Xue return ret; 182dbad75ddSKen Xue } 183dbad75ddSKen Xue 1842956b5d9SMika Westerberg static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset, 1852956b5d9SMika Westerberg unsigned long config) 1862956b5d9SMika Westerberg { 1872956b5d9SMika Westerberg u32 debounce; 1882956b5d9SMika Westerberg 1892956b5d9SMika Westerberg if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 1902956b5d9SMika Westerberg return -ENOTSUPP; 1912956b5d9SMika Westerberg 1922956b5d9SMika Westerberg debounce = pinconf_to_config_argument(config); 1932956b5d9SMika Westerberg return amd_gpio_set_debounce(gc, offset, debounce); 1942956b5d9SMika Westerberg } 1952956b5d9SMika Westerberg 196dbad75ddSKen Xue #ifdef CONFIG_DEBUG_FS 197dbad75ddSKen Xue static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) 198dbad75ddSKen Xue { 199dbad75ddSKen Xue u32 pin_reg; 20039cc1d33SCoiby Xu u32 db_cntrl; 201dbad75ddSKen Xue unsigned long flags; 202dbad75ddSKen Xue unsigned int bank, i, pin_num; 20304d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 204dbad75ddSKen Xue 20539cc1d33SCoiby Xu bool tmr_out_unit; 20639cc1d33SCoiby Xu unsigned int time; 20739cc1d33SCoiby Xu unsigned int unit; 20839cc1d33SCoiby Xu bool tmr_large; 20939cc1d33SCoiby Xu 210dbad75ddSKen Xue char *level_trig; 211dbad75ddSKen Xue char *active_level; 212dbad75ddSKen Xue char *interrupt_enable; 213dbad75ddSKen Xue char *interrupt_mask; 214dbad75ddSKen Xue char *wake_cntrl0; 215dbad75ddSKen Xue char *wake_cntrl1; 216dbad75ddSKen Xue char *wake_cntrl2; 217dbad75ddSKen Xue char *pin_sts; 218dbad75ddSKen Xue char *pull_up_sel; 219dbad75ddSKen Xue char *pull_up_enable; 220dbad75ddSKen Xue char *pull_down_enable; 221dbad75ddSKen Xue char *output_value; 222dbad75ddSKen Xue char *output_enable; 22339cc1d33SCoiby Xu char debounce_value[40]; 22439cc1d33SCoiby Xu char *debounce_enable; 225dbad75ddSKen Xue 2263bfd4430SShah, Nehal-bakulchandra for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { 227dbad75ddSKen Xue seq_printf(s, "GPIO bank%d\t", bank); 228dbad75ddSKen Xue 229dbad75ddSKen Xue switch (bank) { 230dbad75ddSKen Xue case 0: 231dbad75ddSKen Xue i = 0; 232dbad75ddSKen Xue pin_num = AMD_GPIO_PINS_BANK0; 233dbad75ddSKen Xue break; 234dbad75ddSKen Xue case 1: 235dbad75ddSKen Xue i = 64; 236dbad75ddSKen Xue pin_num = AMD_GPIO_PINS_BANK1 + i; 237dbad75ddSKen Xue break; 238dbad75ddSKen Xue case 2: 239dbad75ddSKen Xue i = 128; 240dbad75ddSKen Xue pin_num = AMD_GPIO_PINS_BANK2 + i; 241dbad75ddSKen Xue break; 2423bfd4430SShah, Nehal-bakulchandra case 3: 2433bfd4430SShah, Nehal-bakulchandra i = 192; 2443bfd4430SShah, Nehal-bakulchandra pin_num = AMD_GPIO_PINS_BANK3 + i; 2453bfd4430SShah, Nehal-bakulchandra break; 2466ac4c1adSLinus Walleij default: 2476ac4c1adSLinus Walleij /* Illegal bank number, ignore */ 2486ac4c1adSLinus Walleij continue; 249dbad75ddSKen Xue } 250dbad75ddSKen Xue for (; i < pin_num; i++) { 251dbad75ddSKen Xue seq_printf(s, "pin%d\t", i); 252229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 253dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + i * 4); 254229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 255dbad75ddSKen Xue 256dbad75ddSKen Xue if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { 2571766e4b7SDaniel Kurtz u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) & 2581766e4b7SDaniel Kurtz ACTIVE_LEVEL_MASK; 259dbad75ddSKen Xue interrupt_enable = "interrupt is enabled|"; 260dbad75ddSKen Xue 2611766e4b7SDaniel Kurtz if (level == ACTIVE_LEVEL_HIGH) 262dbad75ddSKen Xue active_level = "Active high|"; 2631766e4b7SDaniel Kurtz else if (level == ACTIVE_LEVEL_LOW) 2641766e4b7SDaniel Kurtz active_level = "Active low|"; 2651766e4b7SDaniel Kurtz else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) && 2661766e4b7SDaniel Kurtz level == ACTIVE_LEVEL_BOTH) 267dbad75ddSKen Xue active_level = "Active on both|"; 268dbad75ddSKen Xue else 2690a95160eSMasanari Iida active_level = "Unknown Active level|"; 270dbad75ddSKen Xue 271dbad75ddSKen Xue if (pin_reg & BIT(LEVEL_TRIG_OFF)) 272dbad75ddSKen Xue level_trig = "Level trigger|"; 273dbad75ddSKen Xue else 274dbad75ddSKen Xue level_trig = "Edge trigger|"; 275dbad75ddSKen Xue 276dbad75ddSKen Xue } else { 277dbad75ddSKen Xue interrupt_enable = 278dbad75ddSKen Xue "interrupt is disabled|"; 279dbad75ddSKen Xue active_level = " "; 280dbad75ddSKen Xue level_trig = " "; 281dbad75ddSKen Xue } 282dbad75ddSKen Xue 283dbad75ddSKen Xue if (pin_reg & BIT(INTERRUPT_MASK_OFF)) 284dbad75ddSKen Xue interrupt_mask = 285dbad75ddSKen Xue "interrupt is unmasked|"; 286dbad75ddSKen Xue else 287dbad75ddSKen Xue interrupt_mask = 288dbad75ddSKen Xue "interrupt is masked|"; 289dbad75ddSKen Xue 2903bfd4430SShah, Nehal-bakulchandra if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) 291dbad75ddSKen Xue wake_cntrl0 = "enable wakeup in S0i3 state|"; 292dbad75ddSKen Xue else 293dbad75ddSKen Xue wake_cntrl0 = "disable wakeup in S0i3 state|"; 294dbad75ddSKen Xue 2953bfd4430SShah, Nehal-bakulchandra if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) 296dbad75ddSKen Xue wake_cntrl1 = "enable wakeup in S3 state|"; 297dbad75ddSKen Xue else 298dbad75ddSKen Xue wake_cntrl1 = "disable wakeup in S3 state|"; 299dbad75ddSKen Xue 3003bfd4430SShah, Nehal-bakulchandra if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) 301dbad75ddSKen Xue wake_cntrl2 = "enable wakeup in S4/S5 state|"; 302dbad75ddSKen Xue else 303dbad75ddSKen Xue wake_cntrl2 = "disable wakeup in S4/S5 state|"; 304dbad75ddSKen Xue 305dbad75ddSKen Xue if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { 306dbad75ddSKen Xue pull_up_enable = "pull-up is enabled|"; 307dbad75ddSKen Xue if (pin_reg & BIT(PULL_UP_SEL_OFF)) 308dbad75ddSKen Xue pull_up_sel = "8k pull-up|"; 309dbad75ddSKen Xue else 310dbad75ddSKen Xue pull_up_sel = "4k pull-up|"; 311dbad75ddSKen Xue } else { 312dbad75ddSKen Xue pull_up_enable = "pull-up is disabled|"; 313dbad75ddSKen Xue pull_up_sel = " "; 314dbad75ddSKen Xue } 315dbad75ddSKen Xue 316dbad75ddSKen Xue if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) 317dbad75ddSKen Xue pull_down_enable = "pull-down is enabled|"; 318dbad75ddSKen Xue else 319dbad75ddSKen Xue pull_down_enable = "Pull-down is disabled|"; 320dbad75ddSKen Xue 321dbad75ddSKen Xue if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { 322dbad75ddSKen Xue pin_sts = " "; 323dbad75ddSKen Xue output_enable = "output is enabled|"; 324dbad75ddSKen Xue if (pin_reg & BIT(OUTPUT_VALUE_OFF)) 325dbad75ddSKen Xue output_value = "output is high|"; 326dbad75ddSKen Xue else 327dbad75ddSKen Xue output_value = "output is low|"; 328dbad75ddSKen Xue } else { 329dbad75ddSKen Xue output_enable = "output is disabled|"; 330dbad75ddSKen Xue output_value = " "; 331dbad75ddSKen Xue 332dbad75ddSKen Xue if (pin_reg & BIT(PIN_STS_OFF)) 333dbad75ddSKen Xue pin_sts = "input is high|"; 334dbad75ddSKen Xue else 335dbad75ddSKen Xue pin_sts = "input is low|"; 336dbad75ddSKen Xue } 337dbad75ddSKen Xue 33839cc1d33SCoiby Xu db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg; 33939cc1d33SCoiby Xu if (db_cntrl) { 34039cc1d33SCoiby Xu tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF); 34139cc1d33SCoiby Xu tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF); 34239cc1d33SCoiby Xu time = pin_reg & DB_TMR_OUT_MASK; 34339cc1d33SCoiby Xu if (tmr_large) { 34439cc1d33SCoiby Xu if (tmr_out_unit) 34539cc1d33SCoiby Xu unit = 62500; 34639cc1d33SCoiby Xu else 34739cc1d33SCoiby Xu unit = 15625; 34839cc1d33SCoiby Xu } else { 34939cc1d33SCoiby Xu if (tmr_out_unit) 35039cc1d33SCoiby Xu unit = 244; 35139cc1d33SCoiby Xu else 35239cc1d33SCoiby Xu unit = 61; 35339cc1d33SCoiby Xu } 35439cc1d33SCoiby Xu if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl) 35539cc1d33SCoiby Xu debounce_enable = "debouncing filter (high and low) enabled|"; 35639cc1d33SCoiby Xu else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl) 35739cc1d33SCoiby Xu debounce_enable = "debouncing filter (low) enabled|"; 35839cc1d33SCoiby Xu else 35939cc1d33SCoiby Xu debounce_enable = "debouncing filter (high) enabled|"; 36039cc1d33SCoiby Xu 36139cc1d33SCoiby Xu snprintf(debounce_value, sizeof(debounce_value), 36239cc1d33SCoiby Xu "debouncing timeout is %u (us)|", time * unit); 36339cc1d33SCoiby Xu } else { 36439cc1d33SCoiby Xu debounce_enable = "debouncing filter disabled|"; 36539cc1d33SCoiby Xu snprintf(debounce_value, sizeof(debounce_value), " "); 36639cc1d33SCoiby Xu } 36739cc1d33SCoiby Xu 368dbad75ddSKen Xue seq_printf(s, "%s %s %s %s %s %s\n" 36939cc1d33SCoiby Xu " %s %s %s %s %s %s %s %s %s 0x%x\n", 370dbad75ddSKen Xue level_trig, active_level, interrupt_enable, 371dbad75ddSKen Xue interrupt_mask, wake_cntrl0, wake_cntrl1, 372dbad75ddSKen Xue wake_cntrl2, pin_sts, pull_up_sel, 373dbad75ddSKen Xue pull_up_enable, pull_down_enable, 37439cc1d33SCoiby Xu output_value, output_enable, 37539cc1d33SCoiby Xu debounce_enable, debounce_value, pin_reg); 376dbad75ddSKen Xue } 377dbad75ddSKen Xue } 378dbad75ddSKen Xue } 379dbad75ddSKen Xue #else 380dbad75ddSKen Xue #define amd_gpio_dbg_show NULL 381dbad75ddSKen Xue #endif 382dbad75ddSKen Xue 383dbad75ddSKen Xue static void amd_gpio_irq_enable(struct irq_data *d) 384dbad75ddSKen Xue { 385dbad75ddSKen Xue u32 pin_reg; 386dbad75ddSKen Xue unsigned long flags; 387dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 38804d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 389dbad75ddSKen Xue 3906173e56fSMarc Zyngier gpiochip_enable_irq(gc, d->hwirq); 3916173e56fSMarc Zyngier 392229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 393dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 394dbad75ddSKen Xue pin_reg |= BIT(INTERRUPT_ENABLE_OFF); 395dbad75ddSKen Xue pin_reg |= BIT(INTERRUPT_MASK_OFF); 396dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 397229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 398dbad75ddSKen Xue } 399dbad75ddSKen Xue 400dbad75ddSKen Xue static void amd_gpio_irq_disable(struct irq_data *d) 401dbad75ddSKen Xue { 402dbad75ddSKen Xue u32 pin_reg; 403dbad75ddSKen Xue unsigned long flags; 404dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 40504d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 406dbad75ddSKen Xue 407229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 408dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 409dbad75ddSKen Xue pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); 410dbad75ddSKen Xue pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 411dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 412229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 4136173e56fSMarc Zyngier 4146173e56fSMarc Zyngier gpiochip_disable_irq(gc, d->hwirq); 415dbad75ddSKen Xue } 416dbad75ddSKen Xue 417dbad75ddSKen Xue static void amd_gpio_irq_mask(struct irq_data *d) 418dbad75ddSKen Xue { 419dbad75ddSKen Xue u32 pin_reg; 420dbad75ddSKen Xue unsigned long flags; 421dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 42204d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 423dbad75ddSKen Xue 424229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 425dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 426dbad75ddSKen Xue pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 427dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 428229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 429dbad75ddSKen Xue } 430dbad75ddSKen Xue 431dbad75ddSKen Xue static void amd_gpio_irq_unmask(struct irq_data *d) 432dbad75ddSKen Xue { 433dbad75ddSKen Xue u32 pin_reg; 434dbad75ddSKen Xue unsigned long flags; 435dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 43604d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 437dbad75ddSKen Xue 438229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 439dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 440dbad75ddSKen Xue pin_reg |= BIT(INTERRUPT_MASK_OFF); 441dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 442229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 443dbad75ddSKen Xue } 444dbad75ddSKen Xue 445d62bd5ceSRaul E Rangel static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 446d62bd5ceSRaul E Rangel { 447d62bd5ceSRaul E Rangel u32 pin_reg; 448d62bd5ceSRaul E Rangel unsigned long flags; 449d62bd5ceSRaul E Rangel struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 450d62bd5ceSRaul E Rangel struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 451c4b68e51SMario Limonciello u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3); 452acd47b9fSBasavaraj Natikar int err; 453d62bd5ceSRaul E Rangel 454d62bd5ceSRaul E Rangel raw_spin_lock_irqsave(&gpio_dev->lock, flags); 455d62bd5ceSRaul E Rangel pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 456d62bd5ceSRaul E Rangel 457d62bd5ceSRaul E Rangel if (on) 458d62bd5ceSRaul E Rangel pin_reg |= wake_mask; 459d62bd5ceSRaul E Rangel else 460d62bd5ceSRaul E Rangel pin_reg &= ~wake_mask; 461d62bd5ceSRaul E Rangel 462d62bd5ceSRaul E Rangel writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 463d62bd5ceSRaul E Rangel raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 464d62bd5ceSRaul E Rangel 465acd47b9fSBasavaraj Natikar if (on) 466acd47b9fSBasavaraj Natikar err = enable_irq_wake(gpio_dev->irq); 467acd47b9fSBasavaraj Natikar else 468acd47b9fSBasavaraj Natikar err = disable_irq_wake(gpio_dev->irq); 469acd47b9fSBasavaraj Natikar 470acd47b9fSBasavaraj Natikar if (err) 471acd47b9fSBasavaraj Natikar dev_err(&gpio_dev->pdev->dev, "failed to %s wake-up interrupt\n", 472acd47b9fSBasavaraj Natikar on ? "enable" : "disable"); 473acd47b9fSBasavaraj Natikar 474d62bd5ceSRaul E Rangel return 0; 475d62bd5ceSRaul E Rangel } 476d62bd5ceSRaul E Rangel 477dbad75ddSKen Xue static void amd_gpio_irq_eoi(struct irq_data *d) 478dbad75ddSKen Xue { 479dbad75ddSKen Xue u32 reg; 480dbad75ddSKen Xue unsigned long flags; 481dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 48204d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 483dbad75ddSKen Xue 484229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 485dbad75ddSKen Xue reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 486dbad75ddSKen Xue reg |= EOI_MASK; 487dbad75ddSKen Xue writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 488229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 489dbad75ddSKen Xue } 490dbad75ddSKen Xue 491dbad75ddSKen Xue static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) 492dbad75ddSKen Xue { 493dbad75ddSKen Xue int ret = 0; 494b85bfa24SDaniel Kurtz u32 pin_reg, pin_reg_irq_en, mask; 4955f4962ddSFurquan Shaikh unsigned long flags; 496dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 49704d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 498dbad75ddSKen Xue 499229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 500dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 501dbad75ddSKen Xue 502dbad75ddSKen Xue switch (type & IRQ_TYPE_SENSE_MASK) { 503dbad75ddSKen Xue case IRQ_TYPE_EDGE_RISING: 504dbad75ddSKen Xue pin_reg &= ~BIT(LEVEL_TRIG_OFF); 505dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 506dbad75ddSKen Xue pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 5079d829314SThomas Gleixner irq_set_handler_locked(d, handle_edge_irq); 508dbad75ddSKen Xue break; 509dbad75ddSKen Xue 510dbad75ddSKen Xue case IRQ_TYPE_EDGE_FALLING: 511dbad75ddSKen Xue pin_reg &= ~BIT(LEVEL_TRIG_OFF); 512dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 513dbad75ddSKen Xue pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 5149d829314SThomas Gleixner irq_set_handler_locked(d, handle_edge_irq); 515dbad75ddSKen Xue break; 516dbad75ddSKen Xue 517dbad75ddSKen Xue case IRQ_TYPE_EDGE_BOTH: 518dbad75ddSKen Xue pin_reg &= ~BIT(LEVEL_TRIG_OFF); 519dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 520dbad75ddSKen Xue pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; 5219d829314SThomas Gleixner irq_set_handler_locked(d, handle_edge_irq); 522dbad75ddSKen Xue break; 523dbad75ddSKen Xue 524dbad75ddSKen Xue case IRQ_TYPE_LEVEL_HIGH: 525dbad75ddSKen Xue pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 526dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 527dbad75ddSKen Xue pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 5289d829314SThomas Gleixner irq_set_handler_locked(d, handle_level_irq); 529dbad75ddSKen Xue break; 530dbad75ddSKen Xue 531dbad75ddSKen Xue case IRQ_TYPE_LEVEL_LOW: 532dbad75ddSKen Xue pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 533dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 534dbad75ddSKen Xue pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 5359d829314SThomas Gleixner irq_set_handler_locked(d, handle_level_irq); 536dbad75ddSKen Xue break; 537dbad75ddSKen Xue 538dbad75ddSKen Xue case IRQ_TYPE_NONE: 539dbad75ddSKen Xue break; 540dbad75ddSKen Xue 541dbad75ddSKen Xue default: 542dbad75ddSKen Xue dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); 543dbad75ddSKen Xue ret = -EINVAL; 544dbad75ddSKen Xue } 545dbad75ddSKen Xue 546dbad75ddSKen Xue pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; 547b85bfa24SDaniel Kurtz /* 548b85bfa24SDaniel Kurtz * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the 549b85bfa24SDaniel Kurtz * debounce registers of any GPIO will block wake/interrupt status 55048c67f1fSMatteo Croce * generation for *all* GPIOs for a length of time that depends on 551b85bfa24SDaniel Kurtz * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the 552b85bfa24SDaniel Kurtz * INTERRUPT_ENABLE bit will read as 0. 553b85bfa24SDaniel Kurtz * 554b85bfa24SDaniel Kurtz * We temporarily enable irq for the GPIO whose configuration is 555b85bfa24SDaniel Kurtz * changing, and then wait for it to read back as 1 to know when 556b85bfa24SDaniel Kurtz * debounce has settled and then disable the irq again. 557b85bfa24SDaniel Kurtz * We do this polling with the spinlock held to ensure other GPIO 558b85bfa24SDaniel Kurtz * access routines do not read an incorrect value for the irq enable 559b85bfa24SDaniel Kurtz * bit of other GPIOs. We keep the GPIO masked while polling to avoid 560b85bfa24SDaniel Kurtz * spurious irqs, and disable the irq again after polling. 561b85bfa24SDaniel Kurtz */ 562b85bfa24SDaniel Kurtz mask = BIT(INTERRUPT_ENABLE_OFF); 563b85bfa24SDaniel Kurtz pin_reg_irq_en = pin_reg; 564b85bfa24SDaniel Kurtz pin_reg_irq_en |= mask; 565b85bfa24SDaniel Kurtz pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF); 566b85bfa24SDaniel Kurtz writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4); 567b85bfa24SDaniel Kurtz while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask) 568b85bfa24SDaniel Kurtz continue; 569dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 570229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 571dbad75ddSKen Xue 572dbad75ddSKen Xue return ret; 573dbad75ddSKen Xue } 574dbad75ddSKen Xue 575dbad75ddSKen Xue static void amd_irq_ack(struct irq_data *d) 576dbad75ddSKen Xue { 577dbad75ddSKen Xue /* 578dbad75ddSKen Xue * based on HW design,there is no need to ack HW 579dbad75ddSKen Xue * before handle current irq. But this routine is 580dbad75ddSKen Xue * necessary for handle_edge_irq 581dbad75ddSKen Xue */ 582dbad75ddSKen Xue } 583dbad75ddSKen Xue 5846173e56fSMarc Zyngier static const struct irq_chip amd_gpio_irqchip = { 585dbad75ddSKen Xue .name = "amd_gpio", 586dbad75ddSKen Xue .irq_ack = amd_irq_ack, 587dbad75ddSKen Xue .irq_enable = amd_gpio_irq_enable, 588dbad75ddSKen Xue .irq_disable = amd_gpio_irq_disable, 589dbad75ddSKen Xue .irq_mask = amd_gpio_irq_mask, 590dbad75ddSKen Xue .irq_unmask = amd_gpio_irq_unmask, 591d62bd5ceSRaul E Rangel .irq_set_wake = amd_gpio_irq_set_wake, 592dbad75ddSKen Xue .irq_eoi = amd_gpio_irq_eoi, 593dbad75ddSKen Xue .irq_set_type = amd_gpio_irq_set_type, 594d62bd5ceSRaul E Rangel /* 595d62bd5ceSRaul E Rangel * We need to set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND so that a wake event 596d62bd5ceSRaul E Rangel * also generates an IRQ. We need the IRQ so the irq_handler can clear 597d62bd5ceSRaul E Rangel * the wake event. Otherwise the wake event will never clear and 598d62bd5ceSRaul E Rangel * prevent the system from suspending. 599d62bd5ceSRaul E Rangel */ 6006173e56fSMarc Zyngier .flags = IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND | IRQCHIP_IMMUTABLE, 6016173e56fSMarc Zyngier GPIOCHIP_IRQ_RESOURCE_HELPERS, 602dbad75ddSKen Xue }; 603dbad75ddSKen Xue 604ba714a9cSThomas Gleixner #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF)) 605ba714a9cSThomas Gleixner 6062d54067fSMario Limonciello static bool do_amd_gpio_irq_handler(int irq, void *dev_id) 607dbad75ddSKen Xue { 608ba714a9cSThomas Gleixner struct amd_gpio *gpio_dev = dev_id; 609ba714a9cSThomas Gleixner struct gpio_chip *gc = &gpio_dev->gc; 610ba714a9cSThomas Gleixner unsigned int i, irqnr; 611dbad75ddSKen Xue unsigned long flags; 61210ff58aaSBen Dooks (Codethink) u32 __iomem *regs; 6132d54067fSMario Limonciello bool ret = false; 61410ff58aaSBen Dooks (Codethink) u32 regval; 615ba714a9cSThomas Gleixner u64 status, mask; 616dbad75ddSKen Xue 617ba714a9cSThomas Gleixner /* Read the wake status */ 618229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 619ba714a9cSThomas Gleixner status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); 620ba714a9cSThomas Gleixner status <<= 32; 621ba714a9cSThomas Gleixner status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0); 622229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 623dbad75ddSKen Xue 624ba714a9cSThomas Gleixner /* Bit 0-45 contain the relevant status bits */ 625ba714a9cSThomas Gleixner status &= (1ULL << 46) - 1; 626ba714a9cSThomas Gleixner regs = gpio_dev->base; 627ba714a9cSThomas Gleixner for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) { 628ba714a9cSThomas Gleixner if (!(status & mask)) 629ba714a9cSThomas Gleixner continue; 630ba714a9cSThomas Gleixner status &= ~mask; 631ba714a9cSThomas Gleixner 632ba714a9cSThomas Gleixner /* Each status bit covers four pins */ 633dbad75ddSKen Xue for (i = 0; i < 4; i++) { 634ba714a9cSThomas Gleixner regval = readl(regs + i); 6352d54067fSMario Limonciello /* caused wake on resume context for shared IRQ */ 6362d54067fSMario Limonciello if (irq < 0 && (regval & BIT(WAKE_STS_OFF))) { 6372d54067fSMario Limonciello dev_dbg(&gpio_dev->pdev->dev, 6382d54067fSMario Limonciello "Waking due to GPIO %d: 0x%x", 6392d54067fSMario Limonciello irqnr + i, regval); 6402d54067fSMario Limonciello return true; 6412d54067fSMario Limonciello } 6422d54067fSMario Limonciello 6438bbed1eeSDaniel Kurtz if (!(regval & PIN_IRQ_PENDING) || 6448bbed1eeSDaniel Kurtz !(regval & BIT(INTERRUPT_MASK_OFF))) 645ba714a9cSThomas Gleixner continue; 646a9cb09b7SMarc Zyngier generic_handle_domain_irq(gc->irq.domain, irqnr + i); 6476afb1026SDaniel Drake 6486afb1026SDaniel Drake /* Clear interrupt. 6496afb1026SDaniel Drake * We must read the pin register again, in case the 6506afb1026SDaniel Drake * value was changed while executing 651a9cb09b7SMarc Zyngier * generic_handle_domain_irq() above. 652d21b8adbSDaniel Drake * If we didn't find a mapping for the interrupt, 653d21b8adbSDaniel Drake * disable it in order to avoid a system hang caused 654d21b8adbSDaniel Drake * by an interrupt storm. 6556afb1026SDaniel Drake */ 6566afb1026SDaniel Drake raw_spin_lock_irqsave(&gpio_dev->lock, flags); 6576afb1026SDaniel Drake regval = readl(regs + i); 658d21b8adbSDaniel Drake if (irq == 0) { 659d21b8adbSDaniel Drake regval &= ~BIT(INTERRUPT_ENABLE_OFF); 660d21b8adbSDaniel Drake dev_dbg(&gpio_dev->pdev->dev, 661d21b8adbSDaniel Drake "Disabling spurious GPIO IRQ %d\n", 662d21b8adbSDaniel Drake irqnr + i); 663d21b8adbSDaniel Drake } 664ba714a9cSThomas Gleixner writel(regval, regs + i); 6656afb1026SDaniel Drake raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 6662d54067fSMario Limonciello ret = true; 667dbad75ddSKen Xue } 668dbad75ddSKen Xue } 6692d54067fSMario Limonciello /* did not cause wake on resume context for shared IRQ */ 6702d54067fSMario Limonciello if (irq < 0) 6712d54067fSMario Limonciello return false; 672dbad75ddSKen Xue 673ba714a9cSThomas Gleixner /* Signal EOI to the GPIO unit */ 674229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 675ba714a9cSThomas Gleixner regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 676ba714a9cSThomas Gleixner regval |= EOI_MASK; 677ba714a9cSThomas Gleixner writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG); 678229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 679dbad75ddSKen Xue 680ba714a9cSThomas Gleixner return ret; 681dbad75ddSKen Xue } 682dbad75ddSKen Xue 6832d54067fSMario Limonciello static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id) 6842d54067fSMario Limonciello { 6852d54067fSMario Limonciello return IRQ_RETVAL(do_amd_gpio_irq_handler(irq, dev_id)); 6862d54067fSMario Limonciello } 6872d54067fSMario Limonciello 6882d54067fSMario Limonciello static bool __maybe_unused amd_gpio_check_wake(void *dev_id) 6892d54067fSMario Limonciello { 6902d54067fSMario Limonciello return do_amd_gpio_irq_handler(-1, dev_id); 6912d54067fSMario Limonciello } 6922d54067fSMario Limonciello 693dbad75ddSKen Xue static int amd_get_groups_count(struct pinctrl_dev *pctldev) 694dbad75ddSKen Xue { 695dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 696dbad75ddSKen Xue 697dbad75ddSKen Xue return gpio_dev->ngroups; 698dbad75ddSKen Xue } 699dbad75ddSKen Xue 700dbad75ddSKen Xue static const char *amd_get_group_name(struct pinctrl_dev *pctldev, 701dbad75ddSKen Xue unsigned group) 702dbad75ddSKen Xue { 703dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 704dbad75ddSKen Xue 705dbad75ddSKen Xue return gpio_dev->groups[group].name; 706dbad75ddSKen Xue } 707dbad75ddSKen Xue 708dbad75ddSKen Xue static int amd_get_group_pins(struct pinctrl_dev *pctldev, 709dbad75ddSKen Xue unsigned group, 710dbad75ddSKen Xue const unsigned **pins, 711dbad75ddSKen Xue unsigned *num_pins) 712dbad75ddSKen Xue { 713dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 714dbad75ddSKen Xue 715dbad75ddSKen Xue *pins = gpio_dev->groups[group].pins; 716dbad75ddSKen Xue *num_pins = gpio_dev->groups[group].npins; 717dbad75ddSKen Xue return 0; 718dbad75ddSKen Xue } 719dbad75ddSKen Xue 720dbad75ddSKen Xue static const struct pinctrl_ops amd_pinctrl_ops = { 721dbad75ddSKen Xue .get_groups_count = amd_get_groups_count, 722dbad75ddSKen Xue .get_group_name = amd_get_group_name, 723dbad75ddSKen Xue .get_group_pins = amd_get_group_pins, 724dbad75ddSKen Xue #ifdef CONFIG_OF 725dbad75ddSKen Xue .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 726d32f7fd3SIrina Tirdea .dt_free_map = pinctrl_utils_free_map, 727dbad75ddSKen Xue #endif 728dbad75ddSKen Xue }; 729dbad75ddSKen Xue 730dbad75ddSKen Xue static int amd_pinconf_get(struct pinctrl_dev *pctldev, 731dbad75ddSKen Xue unsigned int pin, 732dbad75ddSKen Xue unsigned long *config) 733dbad75ddSKen Xue { 734dbad75ddSKen Xue u32 pin_reg; 735dbad75ddSKen Xue unsigned arg; 736dbad75ddSKen Xue unsigned long flags; 737dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 738dbad75ddSKen Xue enum pin_config_param param = pinconf_to_config_param(*config); 739dbad75ddSKen Xue 740229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 741dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + pin*4); 742229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 743dbad75ddSKen Xue switch (param) { 744dbad75ddSKen Xue case PIN_CONFIG_INPUT_DEBOUNCE: 745dbad75ddSKen Xue arg = pin_reg & DB_TMR_OUT_MASK; 746dbad75ddSKen Xue break; 747dbad75ddSKen Xue 748dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_DOWN: 749dbad75ddSKen Xue arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); 750dbad75ddSKen Xue break; 751dbad75ddSKen Xue 752dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_UP: 753dbad75ddSKen Xue arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); 754dbad75ddSKen Xue break; 755dbad75ddSKen Xue 756dbad75ddSKen Xue case PIN_CONFIG_DRIVE_STRENGTH: 757dbad75ddSKen Xue arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; 758dbad75ddSKen Xue break; 759dbad75ddSKen Xue 760dbad75ddSKen Xue default: 761dbad75ddSKen Xue dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n", 762dbad75ddSKen Xue param); 763dbad75ddSKen Xue return -ENOTSUPP; 764dbad75ddSKen Xue } 765dbad75ddSKen Xue 766dbad75ddSKen Xue *config = pinconf_to_config_packed(param, arg); 767dbad75ddSKen Xue 768dbad75ddSKen Xue return 0; 769dbad75ddSKen Xue } 770dbad75ddSKen Xue 771dbad75ddSKen Xue static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 772dbad75ddSKen Xue unsigned long *configs, unsigned num_configs) 773dbad75ddSKen Xue { 774dbad75ddSKen Xue int i; 775dbad75ddSKen Xue u32 arg; 77625a853d0SKen Xue int ret = 0; 77725a853d0SKen Xue u32 pin_reg; 778dbad75ddSKen Xue unsigned long flags; 779dbad75ddSKen Xue enum pin_config_param param; 780dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 781dbad75ddSKen Xue 782229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 783dbad75ddSKen Xue for (i = 0; i < num_configs; i++) { 784dbad75ddSKen Xue param = pinconf_to_config_param(configs[i]); 785dbad75ddSKen Xue arg = pinconf_to_config_argument(configs[i]); 786dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + pin*4); 787dbad75ddSKen Xue 788dbad75ddSKen Xue switch (param) { 789dbad75ddSKen Xue case PIN_CONFIG_INPUT_DEBOUNCE: 790dbad75ddSKen Xue pin_reg &= ~DB_TMR_OUT_MASK; 791dbad75ddSKen Xue pin_reg |= arg & DB_TMR_OUT_MASK; 792dbad75ddSKen Xue break; 793dbad75ddSKen Xue 794dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_DOWN: 795dbad75ddSKen Xue pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); 796dbad75ddSKen Xue pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; 797dbad75ddSKen Xue break; 798dbad75ddSKen Xue 799dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_UP: 800dbad75ddSKen Xue pin_reg &= ~BIT(PULL_UP_SEL_OFF); 801dbad75ddSKen Xue pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; 802dbad75ddSKen Xue pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); 803dbad75ddSKen Xue pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; 804dbad75ddSKen Xue break; 805dbad75ddSKen Xue 806dbad75ddSKen Xue case PIN_CONFIG_DRIVE_STRENGTH: 807dbad75ddSKen Xue pin_reg &= ~(DRV_STRENGTH_SEL_MASK 808dbad75ddSKen Xue << DRV_STRENGTH_SEL_OFF); 809dbad75ddSKen Xue pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) 810dbad75ddSKen Xue << DRV_STRENGTH_SEL_OFF; 811dbad75ddSKen Xue break; 812dbad75ddSKen Xue 813dbad75ddSKen Xue default: 814dbad75ddSKen Xue dev_err(&gpio_dev->pdev->dev, 815dbad75ddSKen Xue "Invalid config param %04x\n", param); 81625a853d0SKen Xue ret = -ENOTSUPP; 817dbad75ddSKen Xue } 818dbad75ddSKen Xue 819dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + pin*4); 820dbad75ddSKen Xue } 821229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 822dbad75ddSKen Xue 82325a853d0SKen Xue return ret; 824dbad75ddSKen Xue } 825dbad75ddSKen Xue 826dbad75ddSKen Xue static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, 827dbad75ddSKen Xue unsigned int group, 828dbad75ddSKen Xue unsigned long *config) 829dbad75ddSKen Xue { 830dbad75ddSKen Xue const unsigned *pins; 831dbad75ddSKen Xue unsigned npins; 832dbad75ddSKen Xue int ret; 833dbad75ddSKen Xue 834dbad75ddSKen Xue ret = amd_get_group_pins(pctldev, group, &pins, &npins); 835dbad75ddSKen Xue if (ret) 836dbad75ddSKen Xue return ret; 837dbad75ddSKen Xue 838dbad75ddSKen Xue if (amd_pinconf_get(pctldev, pins[0], config)) 839dbad75ddSKen Xue return -ENOTSUPP; 840dbad75ddSKen Xue 841dbad75ddSKen Xue return 0; 842dbad75ddSKen Xue } 843dbad75ddSKen Xue 844dbad75ddSKen Xue static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, 845dbad75ddSKen Xue unsigned group, unsigned long *configs, 846dbad75ddSKen Xue unsigned num_configs) 847dbad75ddSKen Xue { 848dbad75ddSKen Xue const unsigned *pins; 849dbad75ddSKen Xue unsigned npins; 850dbad75ddSKen Xue int i, ret; 851dbad75ddSKen Xue 852dbad75ddSKen Xue ret = amd_get_group_pins(pctldev, group, &pins, &npins); 853dbad75ddSKen Xue if (ret) 854dbad75ddSKen Xue return ret; 855dbad75ddSKen Xue for (i = 0; i < npins; i++) { 856dbad75ddSKen Xue if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) 857dbad75ddSKen Xue return -ENOTSUPP; 858dbad75ddSKen Xue } 859dbad75ddSKen Xue return 0; 860dbad75ddSKen Xue } 861dbad75ddSKen Xue 862dbad75ddSKen Xue static const struct pinconf_ops amd_pinconf_ops = { 863dbad75ddSKen Xue .pin_config_get = amd_pinconf_get, 864dbad75ddSKen Xue .pin_config_set = amd_pinconf_set, 865dbad75ddSKen Xue .pin_config_group_get = amd_pinconf_group_get, 866dbad75ddSKen Xue .pin_config_group_set = amd_pinconf_group_set, 867dbad75ddSKen Xue }; 868dbad75ddSKen Xue 8694e5a04beSSachi King static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) 8704e5a04beSSachi King { 8714e5a04beSSachi King struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 8724e5a04beSSachi King unsigned long flags; 8734e5a04beSSachi King u32 pin_reg, mask; 8744e5a04beSSachi King int i; 8754e5a04beSSachi King 8764e5a04beSSachi King mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) | 8774e5a04beSSachi King BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) | 8784e5a04beSSachi King BIT(WAKE_CNTRL_OFF_S4); 8794e5a04beSSachi King 8804e5a04beSSachi King for (i = 0; i < desc->npins; i++) { 8814e5a04beSSachi King int pin = desc->pins[i].number; 8824e5a04beSSachi King const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 8834e5a04beSSachi King 8844e5a04beSSachi King if (!pd) 8854e5a04beSSachi King continue; 8864e5a04beSSachi King 8874e5a04beSSachi King raw_spin_lock_irqsave(&gpio_dev->lock, flags); 8884e5a04beSSachi King 8894e5a04beSSachi King pin_reg = readl(gpio_dev->base + i * 4); 8904e5a04beSSachi King pin_reg &= ~mask; 8914e5a04beSSachi King writel(pin_reg, gpio_dev->base + i * 4); 8924e5a04beSSachi King 8934e5a04beSSachi King raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 8944e5a04beSSachi King } 8954e5a04beSSachi King } 8964e5a04beSSachi King 89779d2c8beSDaniel Drake #ifdef CONFIG_PM_SLEEP 89879d2c8beSDaniel Drake static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) 89979d2c8beSDaniel Drake { 90079d2c8beSDaniel Drake const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 90179d2c8beSDaniel Drake 90279d2c8beSDaniel Drake if (!pd) 90379d2c8beSDaniel Drake return false; 90479d2c8beSDaniel Drake 90579d2c8beSDaniel Drake /* 90679d2c8beSDaniel Drake * Only restore the pin if it is actually in use by the kernel (or 90779d2c8beSDaniel Drake * by userspace). 90879d2c8beSDaniel Drake */ 90979d2c8beSDaniel Drake if (pd->mux_owner || pd->gpio_owner || 91079d2c8beSDaniel Drake gpiochip_line_is_irq(&gpio_dev->gc, pin)) 91179d2c8beSDaniel Drake return true; 91279d2c8beSDaniel Drake 91379d2c8beSDaniel Drake return false; 91479d2c8beSDaniel Drake } 91579d2c8beSDaniel Drake 9162d71dfa2SColin Ian King static int amd_gpio_suspend(struct device *dev) 91779d2c8beSDaniel Drake { 9189f540c3eSWolfram Sang struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 91979d2c8beSDaniel Drake struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 92079d2c8beSDaniel Drake int i; 92179d2c8beSDaniel Drake 92279d2c8beSDaniel Drake for (i = 0; i < desc->npins; i++) { 92379d2c8beSDaniel Drake int pin = desc->pins[i].number; 92479d2c8beSDaniel Drake 92579d2c8beSDaniel Drake if (!amd_gpio_should_save(gpio_dev, pin)) 92679d2c8beSDaniel Drake continue; 92779d2c8beSDaniel Drake 92879d2c8beSDaniel Drake gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin*4); 92979d2c8beSDaniel Drake } 93079d2c8beSDaniel Drake 93179d2c8beSDaniel Drake return 0; 93279d2c8beSDaniel Drake } 93379d2c8beSDaniel Drake 9342d71dfa2SColin Ian King static int amd_gpio_resume(struct device *dev) 93579d2c8beSDaniel Drake { 9369f540c3eSWolfram Sang struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 93779d2c8beSDaniel Drake struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 93879d2c8beSDaniel Drake int i; 93979d2c8beSDaniel Drake 94079d2c8beSDaniel Drake for (i = 0; i < desc->npins; i++) { 94179d2c8beSDaniel Drake int pin = desc->pins[i].number; 94279d2c8beSDaniel Drake 94379d2c8beSDaniel Drake if (!amd_gpio_should_save(gpio_dev, pin)) 94479d2c8beSDaniel Drake continue; 94579d2c8beSDaniel Drake 94679d2c8beSDaniel Drake writel(gpio_dev->saved_regs[i], gpio_dev->base + pin*4); 94779d2c8beSDaniel Drake } 94879d2c8beSDaniel Drake 94979d2c8beSDaniel Drake return 0; 95079d2c8beSDaniel Drake } 95179d2c8beSDaniel Drake 95279d2c8beSDaniel Drake static const struct dev_pm_ops amd_gpio_pm_ops = { 95379d2c8beSDaniel Drake SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend, 95479d2c8beSDaniel Drake amd_gpio_resume) 95579d2c8beSDaniel Drake }; 95679d2c8beSDaniel Drake #endif 95779d2c8beSDaniel Drake 958dbad75ddSKen Xue static struct pinctrl_desc amd_pinctrl_desc = { 959dbad75ddSKen Xue .pins = kerncz_pins, 960dbad75ddSKen Xue .npins = ARRAY_SIZE(kerncz_pins), 961dbad75ddSKen Xue .pctlops = &amd_pinctrl_ops, 962dbad75ddSKen Xue .confops = &amd_pinconf_ops, 963dbad75ddSKen Xue .owner = THIS_MODULE, 964dbad75ddSKen Xue }; 965dbad75ddSKen Xue 966*79bb5c7fSBasavaraj Natikar static void amd_get_iomux_res(struct amd_gpio *gpio_dev) 967*79bb5c7fSBasavaraj Natikar { 968*79bb5c7fSBasavaraj Natikar struct pinctrl_desc *desc = &amd_pinctrl_desc; 969*79bb5c7fSBasavaraj Natikar struct device *dev = &gpio_dev->pdev->dev; 970*79bb5c7fSBasavaraj Natikar int index; 971*79bb5c7fSBasavaraj Natikar 972*79bb5c7fSBasavaraj Natikar index = device_property_match_string(dev, "pinctrl-resource-names", "iomux"); 973*79bb5c7fSBasavaraj Natikar if (index < 0) { 974*79bb5c7fSBasavaraj Natikar dev_warn(dev, "failed to get iomux index\n"); 975*79bb5c7fSBasavaraj Natikar goto out_no_pinmux; 976*79bb5c7fSBasavaraj Natikar } 977*79bb5c7fSBasavaraj Natikar 978*79bb5c7fSBasavaraj Natikar gpio_dev->iomux_base = devm_platform_ioremap_resource(gpio_dev->pdev, index); 979*79bb5c7fSBasavaraj Natikar if (IS_ERR(gpio_dev->iomux_base)) { 980*79bb5c7fSBasavaraj Natikar dev_warn(dev, "Failed to get iomux %d io resource\n", index); 981*79bb5c7fSBasavaraj Natikar goto out_no_pinmux; 982*79bb5c7fSBasavaraj Natikar } 983*79bb5c7fSBasavaraj Natikar 984*79bb5c7fSBasavaraj Natikar return; 985*79bb5c7fSBasavaraj Natikar 986*79bb5c7fSBasavaraj Natikar out_no_pinmux: 987*79bb5c7fSBasavaraj Natikar desc->pmxops = NULL; 988*79bb5c7fSBasavaraj Natikar } 989*79bb5c7fSBasavaraj Natikar 990dbad75ddSKen Xue static int amd_gpio_probe(struct platform_device *pdev) 991dbad75ddSKen Xue { 992dbad75ddSKen Xue int ret = 0; 993dbad75ddSKen Xue struct resource *res; 994dbad75ddSKen Xue struct amd_gpio *gpio_dev; 995e81376ebSLinus Walleij struct gpio_irq_chip *girq; 996dbad75ddSKen Xue 997dbad75ddSKen Xue gpio_dev = devm_kzalloc(&pdev->dev, 998dbad75ddSKen Xue sizeof(struct amd_gpio), GFP_KERNEL); 999dbad75ddSKen Xue if (!gpio_dev) 1000dbad75ddSKen Xue return -ENOMEM; 1001dbad75ddSKen Xue 1002229710feSJulia Cartwright raw_spin_lock_init(&gpio_dev->lock); 1003dbad75ddSKen Xue 1004dbad75ddSKen Xue res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1005dbad75ddSKen Xue if (!res) { 1006dbad75ddSKen Xue dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); 1007dbad75ddSKen Xue return -EINVAL; 1008dbad75ddSKen Xue } 1009dbad75ddSKen Xue 10104bdc0d67SChristoph Hellwig gpio_dev->base = devm_ioremap(&pdev->dev, res->start, 1011dbad75ddSKen Xue resource_size(res)); 1012424a6c60SWei Yongjun if (!gpio_dev->base) 1013424a6c60SWei Yongjun return -ENOMEM; 1014dbad75ddSKen Xue 10157e6f8d6fSBasavaraj Natikar gpio_dev->irq = platform_get_irq(pdev, 0); 10167e6f8d6fSBasavaraj Natikar if (gpio_dev->irq < 0) 10177e6f8d6fSBasavaraj Natikar return gpio_dev->irq; 1018dbad75ddSKen Xue 101979d2c8beSDaniel Drake #ifdef CONFIG_PM_SLEEP 102079d2c8beSDaniel Drake gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins, 102179d2c8beSDaniel Drake sizeof(*gpio_dev->saved_regs), 102279d2c8beSDaniel Drake GFP_KERNEL); 102379d2c8beSDaniel Drake if (!gpio_dev->saved_regs) 102479d2c8beSDaniel Drake return -ENOMEM; 102579d2c8beSDaniel Drake #endif 102679d2c8beSDaniel Drake 1027dbad75ddSKen Xue gpio_dev->pdev = pdev; 102812b10f47SDaniel Kurtz gpio_dev->gc.get_direction = amd_gpio_get_direction; 1029dbad75ddSKen Xue gpio_dev->gc.direction_input = amd_gpio_direction_input; 1030dbad75ddSKen Xue gpio_dev->gc.direction_output = amd_gpio_direction_output; 1031dbad75ddSKen Xue gpio_dev->gc.get = amd_gpio_get_value; 1032dbad75ddSKen Xue gpio_dev->gc.set = amd_gpio_set_value; 10332956b5d9SMika Westerberg gpio_dev->gc.set_config = amd_gpio_set_config; 1034dbad75ddSKen Xue gpio_dev->gc.dbg_show = amd_gpio_dbg_show; 1035dbad75ddSKen Xue 10363bfd4430SShah, Nehal-bakulchandra gpio_dev->gc.base = -1; 1037dbad75ddSKen Xue gpio_dev->gc.label = pdev->name; 1038dbad75ddSKen Xue gpio_dev->gc.owner = THIS_MODULE; 103958383c78SLinus Walleij gpio_dev->gc.parent = &pdev->dev; 10403bfd4430SShah, Nehal-bakulchandra gpio_dev->gc.ngpio = resource_size(res) / 4; 1041dbad75ddSKen Xue 10423bfd4430SShah, Nehal-bakulchandra gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64; 1043dbad75ddSKen Xue gpio_dev->groups = kerncz_groups; 1044dbad75ddSKen Xue gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); 1045dbad75ddSKen Xue 1046dbad75ddSKen Xue amd_pinctrl_desc.name = dev_name(&pdev->dev); 1047*79bb5c7fSBasavaraj Natikar amd_get_iomux_res(gpio_dev); 1048251e22abSLaxman Dewangan gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, 1049251e22abSLaxman Dewangan gpio_dev); 1050323de9efSMasahiro Yamada if (IS_ERR(gpio_dev->pctrl)) { 1051dbad75ddSKen Xue dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 1052323de9efSMasahiro Yamada return PTR_ERR(gpio_dev->pctrl); 1053dbad75ddSKen Xue } 1054dbad75ddSKen Xue 10554e5a04beSSachi King /* Disable and mask interrupts */ 10564e5a04beSSachi King amd_gpio_irq_init(gpio_dev); 10574e5a04beSSachi King 1058e81376ebSLinus Walleij girq = &gpio_dev->gc.irq; 10596173e56fSMarc Zyngier gpio_irq_chip_set_chip(girq, &amd_gpio_irqchip); 1060e81376ebSLinus Walleij /* This will let us handle the parent IRQ in the driver */ 1061e81376ebSLinus Walleij girq->parent_handler = NULL; 1062e81376ebSLinus Walleij girq->num_parents = 0; 1063e81376ebSLinus Walleij girq->parents = NULL; 1064e81376ebSLinus Walleij girq->default_type = IRQ_TYPE_NONE; 1065e81376ebSLinus Walleij girq->handler = handle_simple_irq; 1066e81376ebSLinus Walleij 106704d36723SLinus Walleij ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); 1068dbad75ddSKen Xue if (ret) 1069251e22abSLaxman Dewangan return ret; 1070dbad75ddSKen Xue 1071dbad75ddSKen Xue ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), 10723bfd4430SShah, Nehal-bakulchandra 0, 0, gpio_dev->gc.ngpio); 1073dbad75ddSKen Xue if (ret) { 1074dbad75ddSKen Xue dev_err(&pdev->dev, "Failed to add pin range\n"); 1075dbad75ddSKen Xue goto out2; 1076dbad75ddSKen Xue } 1077dbad75ddSKen Xue 10787e6f8d6fSBasavaraj Natikar ret = devm_request_irq(&pdev->dev, gpio_dev->irq, amd_gpio_irq_handler, 1079279ffafaSSandeep Singh IRQF_SHARED, KBUILD_MODNAME, gpio_dev); 1080ba714a9cSThomas Gleixner if (ret) 1081ba714a9cSThomas Gleixner goto out2; 1082ba714a9cSThomas Gleixner 1083dbad75ddSKen Xue platform_set_drvdata(pdev, gpio_dev); 10842d54067fSMario Limonciello acpi_register_wakeup_handler(gpio_dev->irq, amd_gpio_check_wake, gpio_dev); 1085dbad75ddSKen Xue 1086dbad75ddSKen Xue dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); 1087dbad75ddSKen Xue return ret; 1088dbad75ddSKen Xue 1089dbad75ddSKen Xue out2: 1090dbad75ddSKen Xue gpiochip_remove(&gpio_dev->gc); 1091dbad75ddSKen Xue 1092dbad75ddSKen Xue return ret; 1093dbad75ddSKen Xue } 1094dbad75ddSKen Xue 1095dbad75ddSKen Xue static int amd_gpio_remove(struct platform_device *pdev) 1096dbad75ddSKen Xue { 1097dbad75ddSKen Xue struct amd_gpio *gpio_dev; 1098dbad75ddSKen Xue 1099dbad75ddSKen Xue gpio_dev = platform_get_drvdata(pdev); 1100dbad75ddSKen Xue 1101dbad75ddSKen Xue gpiochip_remove(&gpio_dev->gc); 11022d54067fSMario Limonciello acpi_unregister_wakeup_handler(amd_gpio_check_wake, gpio_dev); 1103dbad75ddSKen Xue 1104dbad75ddSKen Xue return 0; 1105dbad75ddSKen Xue } 1106dbad75ddSKen Xue 1107de4334f7SLee Jones #ifdef CONFIG_ACPI 1108dbad75ddSKen Xue static const struct acpi_device_id amd_gpio_acpi_match[] = { 1109dbad75ddSKen Xue { "AMD0030", 0 }, 111042a44402SWang Hongcheng { "AMDI0030", 0}, 11111ca46d3eSMaximilian Luz { "AMDI0031", 0}, 1112dbad75ddSKen Xue { }, 1113dbad75ddSKen Xue }; 1114dbad75ddSKen Xue MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); 1115de4334f7SLee Jones #endif 1116dbad75ddSKen Xue 1117dbad75ddSKen Xue static struct platform_driver amd_gpio_driver = { 1118dbad75ddSKen Xue .driver = { 1119dbad75ddSKen Xue .name = "amd_gpio", 1120dbad75ddSKen Xue .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), 112179d2c8beSDaniel Drake #ifdef CONFIG_PM_SLEEP 112279d2c8beSDaniel Drake .pm = &amd_gpio_pm_ops, 112379d2c8beSDaniel Drake #endif 1124dbad75ddSKen Xue }, 1125dbad75ddSKen Xue .probe = amd_gpio_probe, 1126dbad75ddSKen Xue .remove = amd_gpio_remove, 1127dbad75ddSKen Xue }; 1128dbad75ddSKen Xue 1129dbad75ddSKen Xue module_platform_driver(amd_gpio_driver); 1130dbad75ddSKen Xue 1131dbad75ddSKen Xue MODULE_LICENSE("GPL v2"); 1132dbad75ddSKen Xue MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); 1133dbad75ddSKen Xue MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); 1134