1dbad75ddSKen Xue /* 2dbad75ddSKen Xue * GPIO driver for AMD 3dbad75ddSKen Xue * 4dbad75ddSKen Xue * Copyright (c) 2014,2015 AMD Corporation. 5dbad75ddSKen Xue * Authors: Ken Xue <Ken.Xue@amd.com> 6dbad75ddSKen Xue * Wu, Jeff <Jeff.Wu@amd.com> 7dbad75ddSKen Xue * 8dbad75ddSKen Xue * This program is free software; you can redistribute it and/or modify it 9dbad75ddSKen Xue * under the terms and conditions of the GNU General Public License, 10dbad75ddSKen Xue * version 2, as published by the Free Software Foundation. 11add7bfceSShyam Sundar S K * 12add7bfceSShyam Sundar S K * Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com> 13add7bfceSShyam Sundar S K * Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 14add7bfceSShyam Sundar S K * 15dbad75ddSKen Xue */ 16dbad75ddSKen Xue 17dbad75ddSKen Xue #include <linux/err.h> 18dbad75ddSKen Xue #include <linux/bug.h> 19dbad75ddSKen Xue #include <linux/kernel.h> 20dbad75ddSKen Xue #include <linux/module.h> 21dbad75ddSKen Xue #include <linux/spinlock.h> 22dbad75ddSKen Xue #include <linux/compiler.h> 23dbad75ddSKen Xue #include <linux/types.h> 24dbad75ddSKen Xue #include <linux/errno.h> 25dbad75ddSKen Xue #include <linux/log2.h> 26dbad75ddSKen Xue #include <linux/io.h> 27dbad75ddSKen Xue #include <linux/gpio.h> 28dbad75ddSKen Xue #include <linux/slab.h> 29dbad75ddSKen Xue #include <linux/platform_device.h> 30dbad75ddSKen Xue #include <linux/mutex.h> 31dbad75ddSKen Xue #include <linux/acpi.h> 32dbad75ddSKen Xue #include <linux/seq_file.h> 33dbad75ddSKen Xue #include <linux/interrupt.h> 34dbad75ddSKen Xue #include <linux/list.h> 35dbad75ddSKen Xue #include <linux/bitops.h> 36dbad75ddSKen Xue #include <linux/pinctrl/pinconf.h> 37dbad75ddSKen Xue #include <linux/pinctrl/pinconf-generic.h> 38dbad75ddSKen Xue 3979d2c8beSDaniel Drake #include "core.h" 40dbad75ddSKen Xue #include "pinctrl-utils.h" 41dbad75ddSKen Xue #include "pinctrl-amd.h" 42dbad75ddSKen Xue 4312b10f47SDaniel Kurtz static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset) 4412b10f47SDaniel Kurtz { 4512b10f47SDaniel Kurtz unsigned long flags; 4612b10f47SDaniel Kurtz u32 pin_reg; 4712b10f47SDaniel Kurtz struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 4812b10f47SDaniel Kurtz 4912b10f47SDaniel Kurtz raw_spin_lock_irqsave(&gpio_dev->lock, flags); 5012b10f47SDaniel Kurtz pin_reg = readl(gpio_dev->base + offset * 4); 5112b10f47SDaniel Kurtz raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 5212b10f47SDaniel Kurtz 5312b10f47SDaniel Kurtz return !(pin_reg & BIT(OUTPUT_ENABLE_OFF)); 5412b10f47SDaniel Kurtz } 5512b10f47SDaniel Kurtz 56dbad75ddSKen Xue static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 57dbad75ddSKen Xue { 58dbad75ddSKen Xue unsigned long flags; 59dbad75ddSKen Xue u32 pin_reg; 6004d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 61dbad75ddSKen Xue 62229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 63dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 64dbad75ddSKen Xue pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); 65dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4); 66229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 67dbad75ddSKen Xue 68dbad75ddSKen Xue return 0; 69dbad75ddSKen Xue } 70dbad75ddSKen Xue 71dbad75ddSKen Xue static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 72dbad75ddSKen Xue int value) 73dbad75ddSKen Xue { 74dbad75ddSKen Xue u32 pin_reg; 75dbad75ddSKen Xue unsigned long flags; 7604d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 77dbad75ddSKen Xue 78229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 79dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 80dbad75ddSKen Xue pin_reg |= BIT(OUTPUT_ENABLE_OFF); 81dbad75ddSKen Xue if (value) 82dbad75ddSKen Xue pin_reg |= BIT(OUTPUT_VALUE_OFF); 83dbad75ddSKen Xue else 84dbad75ddSKen Xue pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 85dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4); 86229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 87dbad75ddSKen Xue 88dbad75ddSKen Xue return 0; 89dbad75ddSKen Xue } 90dbad75ddSKen Xue 91dbad75ddSKen Xue static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) 92dbad75ddSKen Xue { 93dbad75ddSKen Xue u32 pin_reg; 94dbad75ddSKen Xue unsigned long flags; 9504d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 96dbad75ddSKen Xue 97229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 98dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 99229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 100dbad75ddSKen Xue 101dbad75ddSKen Xue return !!(pin_reg & BIT(PIN_STS_OFF)); 102dbad75ddSKen Xue } 103dbad75ddSKen Xue 104dbad75ddSKen Xue static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) 105dbad75ddSKen Xue { 106dbad75ddSKen Xue u32 pin_reg; 107dbad75ddSKen Xue unsigned long flags; 10804d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 109dbad75ddSKen Xue 110229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 111dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 112dbad75ddSKen Xue if (value) 113dbad75ddSKen Xue pin_reg |= BIT(OUTPUT_VALUE_OFF); 114dbad75ddSKen Xue else 115dbad75ddSKen Xue pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 116dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4); 117229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 118dbad75ddSKen Xue } 119dbad75ddSKen Xue 120dbad75ddSKen Xue static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, 121dbad75ddSKen Xue unsigned debounce) 122dbad75ddSKen Xue { 123dbad75ddSKen Xue u32 time; 12425a853d0SKen Xue u32 pin_reg; 12525a853d0SKen Xue int ret = 0; 126dbad75ddSKen Xue unsigned long flags; 12704d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 128dbad75ddSKen Xue 129229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 130dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 131dbad75ddSKen Xue 132dbad75ddSKen Xue if (debounce) { 133dbad75ddSKen Xue pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 134dbad75ddSKen Xue pin_reg &= ~DB_TMR_OUT_MASK; 135dbad75ddSKen Xue /* 136dbad75ddSKen Xue Debounce Debounce Timer Max 137dbad75ddSKen Xue TmrLarge TmrOutUnit Unit Debounce 138dbad75ddSKen Xue Time 139dbad75ddSKen Xue 0 0 61 usec (2 RtcClk) 976 usec 140dbad75ddSKen Xue 0 1 244 usec (8 RtcClk) 3.9 msec 141dbad75ddSKen Xue 1 0 15.6 msec (512 RtcClk) 250 msec 142dbad75ddSKen Xue 1 1 62.5 msec (2048 RtcClk) 1 sec 143dbad75ddSKen Xue */ 144dbad75ddSKen Xue 145dbad75ddSKen Xue if (debounce < 61) { 146dbad75ddSKen Xue pin_reg |= 1; 147dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 148dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 149dbad75ddSKen Xue } else if (debounce < 976) { 150dbad75ddSKen Xue time = debounce / 61; 151dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK; 152dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 153dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 154dbad75ddSKen Xue } else if (debounce < 3900) { 155dbad75ddSKen Xue time = debounce / 244; 156dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK; 157dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 158dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 159dbad75ddSKen Xue } else if (debounce < 250000) { 160dbad75ddSKen Xue time = debounce / 15600; 161dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK; 162dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 163dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_LARGE_OFF); 164dbad75ddSKen Xue } else if (debounce < 1000000) { 165dbad75ddSKen Xue time = debounce / 62500; 166dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK; 167dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 168dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_LARGE_OFF); 169dbad75ddSKen Xue } else { 170dbad75ddSKen Xue pin_reg &= ~DB_CNTRl_MASK; 17125a853d0SKen Xue ret = -EINVAL; 172dbad75ddSKen Xue } 173dbad75ddSKen Xue } else { 174dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 175dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 176dbad75ddSKen Xue pin_reg &= ~DB_TMR_OUT_MASK; 177dbad75ddSKen Xue pin_reg &= ~DB_CNTRl_MASK; 178dbad75ddSKen Xue } 179dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4); 180229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 181dbad75ddSKen Xue 18225a853d0SKen Xue return ret; 183dbad75ddSKen Xue } 184dbad75ddSKen Xue 1852956b5d9SMika Westerberg static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset, 1862956b5d9SMika Westerberg unsigned long config) 1872956b5d9SMika Westerberg { 1882956b5d9SMika Westerberg u32 debounce; 1892956b5d9SMika Westerberg 1902956b5d9SMika Westerberg if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 1912956b5d9SMika Westerberg return -ENOTSUPP; 1922956b5d9SMika Westerberg 1932956b5d9SMika Westerberg debounce = pinconf_to_config_argument(config); 1942956b5d9SMika Westerberg return amd_gpio_set_debounce(gc, offset, debounce); 1952956b5d9SMika Westerberg } 1962956b5d9SMika Westerberg 197dbad75ddSKen Xue #ifdef CONFIG_DEBUG_FS 198dbad75ddSKen Xue static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) 199dbad75ddSKen Xue { 200dbad75ddSKen Xue u32 pin_reg; 201dbad75ddSKen Xue unsigned long flags; 202dbad75ddSKen Xue unsigned int bank, i, pin_num; 20304d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 204dbad75ddSKen Xue 205dbad75ddSKen Xue char *level_trig; 206dbad75ddSKen Xue char *active_level; 207dbad75ddSKen Xue char *interrupt_enable; 208dbad75ddSKen Xue char *interrupt_mask; 209dbad75ddSKen Xue char *wake_cntrl0; 210dbad75ddSKen Xue char *wake_cntrl1; 211dbad75ddSKen Xue char *wake_cntrl2; 212dbad75ddSKen Xue char *pin_sts; 213dbad75ddSKen Xue char *pull_up_sel; 214dbad75ddSKen Xue char *pull_up_enable; 215dbad75ddSKen Xue char *pull_down_enable; 216dbad75ddSKen Xue char *output_value; 217dbad75ddSKen Xue char *output_enable; 218dbad75ddSKen Xue 2193bfd4430SShah, Nehal-bakulchandra for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { 220dbad75ddSKen Xue seq_printf(s, "GPIO bank%d\t", bank); 221dbad75ddSKen Xue 222dbad75ddSKen Xue switch (bank) { 223dbad75ddSKen Xue case 0: 224dbad75ddSKen Xue i = 0; 225dbad75ddSKen Xue pin_num = AMD_GPIO_PINS_BANK0; 226dbad75ddSKen Xue break; 227dbad75ddSKen Xue case 1: 228dbad75ddSKen Xue i = 64; 229dbad75ddSKen Xue pin_num = AMD_GPIO_PINS_BANK1 + i; 230dbad75ddSKen Xue break; 231dbad75ddSKen Xue case 2: 232dbad75ddSKen Xue i = 128; 233dbad75ddSKen Xue pin_num = AMD_GPIO_PINS_BANK2 + i; 234dbad75ddSKen Xue break; 2353bfd4430SShah, Nehal-bakulchandra case 3: 2363bfd4430SShah, Nehal-bakulchandra i = 192; 2373bfd4430SShah, Nehal-bakulchandra pin_num = AMD_GPIO_PINS_BANK3 + i; 2383bfd4430SShah, Nehal-bakulchandra break; 2396ac4c1adSLinus Walleij default: 2406ac4c1adSLinus Walleij /* Illegal bank number, ignore */ 2416ac4c1adSLinus Walleij continue; 242dbad75ddSKen Xue } 243dbad75ddSKen Xue for (; i < pin_num; i++) { 244dbad75ddSKen Xue seq_printf(s, "pin%d\t", i); 245229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 246dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + i * 4); 247229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 248dbad75ddSKen Xue 249dbad75ddSKen Xue if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { 250dbad75ddSKen Xue interrupt_enable = "interrupt is enabled|"; 251dbad75ddSKen Xue 2523775dac1SDan Carpenter if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) && 2533775dac1SDan Carpenter !(pin_reg & BIT(ACTIVE_LEVEL_OFF + 1))) 254dbad75ddSKen Xue active_level = "Active low|"; 2553775dac1SDan Carpenter else if (pin_reg & BIT(ACTIVE_LEVEL_OFF) && 2563775dac1SDan Carpenter !(pin_reg & BIT(ACTIVE_LEVEL_OFF + 1))) 257dbad75ddSKen Xue active_level = "Active high|"; 2583775dac1SDan Carpenter else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) && 2593775dac1SDan Carpenter pin_reg & BIT(ACTIVE_LEVEL_OFF + 1)) 260dbad75ddSKen Xue active_level = "Active on both|"; 261dbad75ddSKen Xue else 2620a95160eSMasanari Iida active_level = "Unknown Active level|"; 263dbad75ddSKen Xue 264dbad75ddSKen Xue if (pin_reg & BIT(LEVEL_TRIG_OFF)) 265dbad75ddSKen Xue level_trig = "Level trigger|"; 266dbad75ddSKen Xue else 267dbad75ddSKen Xue level_trig = "Edge trigger|"; 268dbad75ddSKen Xue 269dbad75ddSKen Xue } else { 270dbad75ddSKen Xue interrupt_enable = 271dbad75ddSKen Xue "interrupt is disabled|"; 272dbad75ddSKen Xue active_level = " "; 273dbad75ddSKen Xue level_trig = " "; 274dbad75ddSKen Xue } 275dbad75ddSKen Xue 276dbad75ddSKen Xue if (pin_reg & BIT(INTERRUPT_MASK_OFF)) 277dbad75ddSKen Xue interrupt_mask = 278dbad75ddSKen Xue "interrupt is unmasked|"; 279dbad75ddSKen Xue else 280dbad75ddSKen Xue interrupt_mask = 281dbad75ddSKen Xue "interrupt is masked|"; 282dbad75ddSKen Xue 2833bfd4430SShah, Nehal-bakulchandra if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) 284dbad75ddSKen Xue wake_cntrl0 = "enable wakeup in S0i3 state|"; 285dbad75ddSKen Xue else 286dbad75ddSKen Xue wake_cntrl0 = "disable wakeup in S0i3 state|"; 287dbad75ddSKen Xue 2883bfd4430SShah, Nehal-bakulchandra if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) 289dbad75ddSKen Xue wake_cntrl1 = "enable wakeup in S3 state|"; 290dbad75ddSKen Xue else 291dbad75ddSKen Xue wake_cntrl1 = "disable wakeup in S3 state|"; 292dbad75ddSKen Xue 2933bfd4430SShah, Nehal-bakulchandra if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) 294dbad75ddSKen Xue wake_cntrl2 = "enable wakeup in S4/S5 state|"; 295dbad75ddSKen Xue else 296dbad75ddSKen Xue wake_cntrl2 = "disable wakeup in S4/S5 state|"; 297dbad75ddSKen Xue 298dbad75ddSKen Xue if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { 299dbad75ddSKen Xue pull_up_enable = "pull-up is enabled|"; 300dbad75ddSKen Xue if (pin_reg & BIT(PULL_UP_SEL_OFF)) 301dbad75ddSKen Xue pull_up_sel = "8k pull-up|"; 302dbad75ddSKen Xue else 303dbad75ddSKen Xue pull_up_sel = "4k pull-up|"; 304dbad75ddSKen Xue } else { 305dbad75ddSKen Xue pull_up_enable = "pull-up is disabled|"; 306dbad75ddSKen Xue pull_up_sel = " "; 307dbad75ddSKen Xue } 308dbad75ddSKen Xue 309dbad75ddSKen Xue if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) 310dbad75ddSKen Xue pull_down_enable = "pull-down is enabled|"; 311dbad75ddSKen Xue else 312dbad75ddSKen Xue pull_down_enable = "Pull-down is disabled|"; 313dbad75ddSKen Xue 314dbad75ddSKen Xue if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { 315dbad75ddSKen Xue pin_sts = " "; 316dbad75ddSKen Xue output_enable = "output is enabled|"; 317dbad75ddSKen Xue if (pin_reg & BIT(OUTPUT_VALUE_OFF)) 318dbad75ddSKen Xue output_value = "output is high|"; 319dbad75ddSKen Xue else 320dbad75ddSKen Xue output_value = "output is low|"; 321dbad75ddSKen Xue } else { 322dbad75ddSKen Xue output_enable = "output is disabled|"; 323dbad75ddSKen Xue output_value = " "; 324dbad75ddSKen Xue 325dbad75ddSKen Xue if (pin_reg & BIT(PIN_STS_OFF)) 326dbad75ddSKen Xue pin_sts = "input is high|"; 327dbad75ddSKen Xue else 328dbad75ddSKen Xue pin_sts = "input is low|"; 329dbad75ddSKen Xue } 330dbad75ddSKen Xue 331dbad75ddSKen Xue seq_printf(s, "%s %s %s %s %s %s\n" 332dbad75ddSKen Xue " %s %s %s %s %s %s %s 0x%x\n", 333dbad75ddSKen Xue level_trig, active_level, interrupt_enable, 334dbad75ddSKen Xue interrupt_mask, wake_cntrl0, wake_cntrl1, 335dbad75ddSKen Xue wake_cntrl2, pin_sts, pull_up_sel, 336dbad75ddSKen Xue pull_up_enable, pull_down_enable, 337dbad75ddSKen Xue output_value, output_enable, pin_reg); 338dbad75ddSKen Xue } 339dbad75ddSKen Xue } 340dbad75ddSKen Xue } 341dbad75ddSKen Xue #else 342dbad75ddSKen Xue #define amd_gpio_dbg_show NULL 343dbad75ddSKen Xue #endif 344dbad75ddSKen Xue 345dbad75ddSKen Xue static void amd_gpio_irq_enable(struct irq_data *d) 346dbad75ddSKen Xue { 347dbad75ddSKen Xue u32 pin_reg; 348dbad75ddSKen Xue unsigned long flags; 349dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 35004d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 3514c1de041SDaniel Kurtz u32 mask = BIT(INTERRUPT_ENABLE_OFF) | BIT(INTERRUPT_MASK_OFF); 352dbad75ddSKen Xue 353229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 354dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 355dbad75ddSKen Xue pin_reg |= BIT(INTERRUPT_ENABLE_OFF); 356dbad75ddSKen Xue pin_reg |= BIT(INTERRUPT_MASK_OFF); 357dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 3584c1de041SDaniel Kurtz /* 3594c1de041SDaniel Kurtz * When debounce logic is enabled it takes ~900 us before interrupts 3604c1de041SDaniel Kurtz * can be enabled. During this "debounce warm up" period the 3614c1de041SDaniel Kurtz * "INTERRUPT_ENABLE" bit will read as 0. Poll the bit here until it 3624c1de041SDaniel Kurtz * reads back as 1, signaling that interrupts are now enabled. 3634c1de041SDaniel Kurtz */ 3644c1de041SDaniel Kurtz while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask) 3654c1de041SDaniel Kurtz continue; 366229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 367dbad75ddSKen Xue } 368dbad75ddSKen Xue 369dbad75ddSKen Xue static void amd_gpio_irq_disable(struct irq_data *d) 370dbad75ddSKen Xue { 371dbad75ddSKen Xue u32 pin_reg; 372dbad75ddSKen Xue unsigned long flags; 373dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 37404d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 375dbad75ddSKen Xue 376229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 377dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 378dbad75ddSKen Xue pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); 379dbad75ddSKen Xue pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 380dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 381229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 382dbad75ddSKen Xue } 383dbad75ddSKen Xue 384dbad75ddSKen Xue static void amd_gpio_irq_mask(struct irq_data *d) 385dbad75ddSKen Xue { 386dbad75ddSKen Xue u32 pin_reg; 387dbad75ddSKen Xue unsigned long flags; 388dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 38904d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 390dbad75ddSKen Xue 391229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 392dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 393dbad75ddSKen Xue pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 394dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 395229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 396dbad75ddSKen Xue } 397dbad75ddSKen Xue 398dbad75ddSKen Xue static void amd_gpio_irq_unmask(struct irq_data *d) 399dbad75ddSKen Xue { 400dbad75ddSKen Xue u32 pin_reg; 401dbad75ddSKen Xue unsigned long flags; 402dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 40304d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 404dbad75ddSKen Xue 405229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 406dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 407dbad75ddSKen Xue pin_reg |= BIT(INTERRUPT_MASK_OFF); 408dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 409229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 410dbad75ddSKen Xue } 411dbad75ddSKen Xue 412dbad75ddSKen Xue static void amd_gpio_irq_eoi(struct irq_data *d) 413dbad75ddSKen Xue { 414dbad75ddSKen Xue u32 reg; 415dbad75ddSKen Xue unsigned long flags; 416dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 41704d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 418dbad75ddSKen Xue 419229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 420dbad75ddSKen Xue reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 421dbad75ddSKen Xue reg |= EOI_MASK; 422dbad75ddSKen Xue writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 423229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 424dbad75ddSKen Xue } 425dbad75ddSKen Xue 426dbad75ddSKen Xue static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) 427dbad75ddSKen Xue { 428dbad75ddSKen Xue int ret = 0; 429dbad75ddSKen Xue u32 pin_reg; 4302983f296SShyam Sundar S K unsigned long flags, irq_flags; 431dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 43204d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 433dbad75ddSKen Xue 434229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 435dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 436dbad75ddSKen Xue 4372983f296SShyam Sundar S K /* Ignore the settings coming from the client and 4382983f296SShyam Sundar S K * read the values from the ACPI tables 4392983f296SShyam Sundar S K * while setting the trigger type 440499c7196SAgrawal, Nitesh-kumar */ 441499c7196SAgrawal, Nitesh-kumar 4422983f296SShyam Sundar S K irq_flags = irq_get_trigger_type(d->irq); 4432983f296SShyam Sundar S K if (irq_flags != IRQ_TYPE_NONE) 4442983f296SShyam Sundar S K type = irq_flags; 445499c7196SAgrawal, Nitesh-kumar 446dbad75ddSKen Xue switch (type & IRQ_TYPE_SENSE_MASK) { 447dbad75ddSKen Xue case IRQ_TYPE_EDGE_RISING: 448dbad75ddSKen Xue pin_reg &= ~BIT(LEVEL_TRIG_OFF); 449dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 450dbad75ddSKen Xue pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 451dbad75ddSKen Xue pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 4529d829314SThomas Gleixner irq_set_handler_locked(d, handle_edge_irq); 453dbad75ddSKen Xue break; 454dbad75ddSKen Xue 455dbad75ddSKen Xue case IRQ_TYPE_EDGE_FALLING: 456dbad75ddSKen Xue pin_reg &= ~BIT(LEVEL_TRIG_OFF); 457dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 458dbad75ddSKen Xue pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 459dbad75ddSKen Xue pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 4609d829314SThomas Gleixner irq_set_handler_locked(d, handle_edge_irq); 461dbad75ddSKen Xue break; 462dbad75ddSKen Xue 463dbad75ddSKen Xue case IRQ_TYPE_EDGE_BOTH: 464dbad75ddSKen Xue pin_reg &= ~BIT(LEVEL_TRIG_OFF); 465dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 466dbad75ddSKen Xue pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; 467dbad75ddSKen Xue pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 4689d829314SThomas Gleixner irq_set_handler_locked(d, handle_edge_irq); 469dbad75ddSKen Xue break; 470dbad75ddSKen Xue 471dbad75ddSKen Xue case IRQ_TYPE_LEVEL_HIGH: 472dbad75ddSKen Xue pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 473dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 474dbad75ddSKen Xue pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 475dbad75ddSKen Xue pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 476dbad75ddSKen Xue pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF; 4779d829314SThomas Gleixner irq_set_handler_locked(d, handle_level_irq); 478dbad75ddSKen Xue break; 479dbad75ddSKen Xue 480dbad75ddSKen Xue case IRQ_TYPE_LEVEL_LOW: 481dbad75ddSKen Xue pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 482dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 483dbad75ddSKen Xue pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 484dbad75ddSKen Xue pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 485dbad75ddSKen Xue pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF; 4869d829314SThomas Gleixner irq_set_handler_locked(d, handle_level_irq); 487dbad75ddSKen Xue break; 488dbad75ddSKen Xue 489dbad75ddSKen Xue case IRQ_TYPE_NONE: 490dbad75ddSKen Xue break; 491dbad75ddSKen Xue 492dbad75ddSKen Xue default: 493dbad75ddSKen Xue dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); 494dbad75ddSKen Xue ret = -EINVAL; 495dbad75ddSKen Xue } 496dbad75ddSKen Xue 497dbad75ddSKen Xue pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; 498dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 499229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 500dbad75ddSKen Xue 501dbad75ddSKen Xue return ret; 502dbad75ddSKen Xue } 503dbad75ddSKen Xue 504dbad75ddSKen Xue static void amd_irq_ack(struct irq_data *d) 505dbad75ddSKen Xue { 506dbad75ddSKen Xue /* 507dbad75ddSKen Xue * based on HW design,there is no need to ack HW 508dbad75ddSKen Xue * before handle current irq. But this routine is 509dbad75ddSKen Xue * necessary for handle_edge_irq 510dbad75ddSKen Xue */ 511dbad75ddSKen Xue } 512dbad75ddSKen Xue 513dbad75ddSKen Xue static struct irq_chip amd_gpio_irqchip = { 514dbad75ddSKen Xue .name = "amd_gpio", 515dbad75ddSKen Xue .irq_ack = amd_irq_ack, 516dbad75ddSKen Xue .irq_enable = amd_gpio_irq_enable, 517dbad75ddSKen Xue .irq_disable = amd_gpio_irq_disable, 518dbad75ddSKen Xue .irq_mask = amd_gpio_irq_mask, 519dbad75ddSKen Xue .irq_unmask = amd_gpio_irq_unmask, 520dbad75ddSKen Xue .irq_eoi = amd_gpio_irq_eoi, 521dbad75ddSKen Xue .irq_set_type = amd_gpio_irq_set_type, 5223bfd4430SShah, Nehal-bakulchandra .flags = IRQCHIP_SKIP_SET_WAKE, 523dbad75ddSKen Xue }; 524dbad75ddSKen Xue 525ba714a9cSThomas Gleixner #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF)) 526ba714a9cSThomas Gleixner 527ba714a9cSThomas Gleixner static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id) 528dbad75ddSKen Xue { 529ba714a9cSThomas Gleixner struct amd_gpio *gpio_dev = dev_id; 530ba714a9cSThomas Gleixner struct gpio_chip *gc = &gpio_dev->gc; 531ba714a9cSThomas Gleixner irqreturn_t ret = IRQ_NONE; 532ba714a9cSThomas Gleixner unsigned int i, irqnr; 533dbad75ddSKen Xue unsigned long flags; 534ba714a9cSThomas Gleixner u32 *regs, regval; 535ba714a9cSThomas Gleixner u64 status, mask; 536dbad75ddSKen Xue 537ba714a9cSThomas Gleixner /* Read the wake status */ 538229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 539ba714a9cSThomas Gleixner status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); 540ba714a9cSThomas Gleixner status <<= 32; 541ba714a9cSThomas Gleixner status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0); 542229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 543dbad75ddSKen Xue 544ba714a9cSThomas Gleixner /* Bit 0-45 contain the relevant status bits */ 545ba714a9cSThomas Gleixner status &= (1ULL << 46) - 1; 546ba714a9cSThomas Gleixner regs = gpio_dev->base; 547ba714a9cSThomas Gleixner for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) { 548ba714a9cSThomas Gleixner if (!(status & mask)) 549ba714a9cSThomas Gleixner continue; 550ba714a9cSThomas Gleixner status &= ~mask; 551ba714a9cSThomas Gleixner 552ba714a9cSThomas Gleixner /* Each status bit covers four pins */ 553dbad75ddSKen Xue for (i = 0; i < 4; i++) { 554ba714a9cSThomas Gleixner regval = readl(regs + i); 555ba714a9cSThomas Gleixner if (!(regval & PIN_IRQ_PENDING)) 556ba714a9cSThomas Gleixner continue; 557f0fbe7bcSThierry Reding irq = irq_find_mapping(gc->irq.domain, irqnr + i); 558dbad75ddSKen Xue generic_handle_irq(irq); 5596afb1026SDaniel Drake 5606afb1026SDaniel Drake /* Clear interrupt. 5616afb1026SDaniel Drake * We must read the pin register again, in case the 5626afb1026SDaniel Drake * value was changed while executing 5636afb1026SDaniel Drake * generic_handle_irq() above. 5646afb1026SDaniel Drake */ 5656afb1026SDaniel Drake raw_spin_lock_irqsave(&gpio_dev->lock, flags); 5666afb1026SDaniel Drake regval = readl(regs + i); 567ba714a9cSThomas Gleixner writel(regval, regs + i); 5686afb1026SDaniel Drake raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 569ba714a9cSThomas Gleixner ret = IRQ_HANDLED; 570dbad75ddSKen Xue } 571dbad75ddSKen Xue } 572dbad75ddSKen Xue 573ba714a9cSThomas Gleixner /* Signal EOI to the GPIO unit */ 574229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 575ba714a9cSThomas Gleixner regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 576ba714a9cSThomas Gleixner regval |= EOI_MASK; 577ba714a9cSThomas Gleixner writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG); 578229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 579dbad75ddSKen Xue 580ba714a9cSThomas Gleixner return ret; 581dbad75ddSKen Xue } 582dbad75ddSKen Xue 583dbad75ddSKen Xue static int amd_get_groups_count(struct pinctrl_dev *pctldev) 584dbad75ddSKen Xue { 585dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 586dbad75ddSKen Xue 587dbad75ddSKen Xue return gpio_dev->ngroups; 588dbad75ddSKen Xue } 589dbad75ddSKen Xue 590dbad75ddSKen Xue static const char *amd_get_group_name(struct pinctrl_dev *pctldev, 591dbad75ddSKen Xue unsigned group) 592dbad75ddSKen Xue { 593dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 594dbad75ddSKen Xue 595dbad75ddSKen Xue return gpio_dev->groups[group].name; 596dbad75ddSKen Xue } 597dbad75ddSKen Xue 598dbad75ddSKen Xue static int amd_get_group_pins(struct pinctrl_dev *pctldev, 599dbad75ddSKen Xue unsigned group, 600dbad75ddSKen Xue const unsigned **pins, 601dbad75ddSKen Xue unsigned *num_pins) 602dbad75ddSKen Xue { 603dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 604dbad75ddSKen Xue 605dbad75ddSKen Xue *pins = gpio_dev->groups[group].pins; 606dbad75ddSKen Xue *num_pins = gpio_dev->groups[group].npins; 607dbad75ddSKen Xue return 0; 608dbad75ddSKen Xue } 609dbad75ddSKen Xue 610dbad75ddSKen Xue static const struct pinctrl_ops amd_pinctrl_ops = { 611dbad75ddSKen Xue .get_groups_count = amd_get_groups_count, 612dbad75ddSKen Xue .get_group_name = amd_get_group_name, 613dbad75ddSKen Xue .get_group_pins = amd_get_group_pins, 614dbad75ddSKen Xue #ifdef CONFIG_OF 615dbad75ddSKen Xue .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 616d32f7fd3SIrina Tirdea .dt_free_map = pinctrl_utils_free_map, 617dbad75ddSKen Xue #endif 618dbad75ddSKen Xue }; 619dbad75ddSKen Xue 620dbad75ddSKen Xue static int amd_pinconf_get(struct pinctrl_dev *pctldev, 621dbad75ddSKen Xue unsigned int pin, 622dbad75ddSKen Xue unsigned long *config) 623dbad75ddSKen Xue { 624dbad75ddSKen Xue u32 pin_reg; 625dbad75ddSKen Xue unsigned arg; 626dbad75ddSKen Xue unsigned long flags; 627dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 628dbad75ddSKen Xue enum pin_config_param param = pinconf_to_config_param(*config); 629dbad75ddSKen Xue 630229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 631dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + pin*4); 632229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 633dbad75ddSKen Xue switch (param) { 634dbad75ddSKen Xue case PIN_CONFIG_INPUT_DEBOUNCE: 635dbad75ddSKen Xue arg = pin_reg & DB_TMR_OUT_MASK; 636dbad75ddSKen Xue break; 637dbad75ddSKen Xue 638dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_DOWN: 639dbad75ddSKen Xue arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); 640dbad75ddSKen Xue break; 641dbad75ddSKen Xue 642dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_UP: 643dbad75ddSKen Xue arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); 644dbad75ddSKen Xue break; 645dbad75ddSKen Xue 646dbad75ddSKen Xue case PIN_CONFIG_DRIVE_STRENGTH: 647dbad75ddSKen Xue arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; 648dbad75ddSKen Xue break; 649dbad75ddSKen Xue 650dbad75ddSKen Xue default: 651dbad75ddSKen Xue dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n", 652dbad75ddSKen Xue param); 653dbad75ddSKen Xue return -ENOTSUPP; 654dbad75ddSKen Xue } 655dbad75ddSKen Xue 656dbad75ddSKen Xue *config = pinconf_to_config_packed(param, arg); 657dbad75ddSKen Xue 658dbad75ddSKen Xue return 0; 659dbad75ddSKen Xue } 660dbad75ddSKen Xue 661dbad75ddSKen Xue static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 662dbad75ddSKen Xue unsigned long *configs, unsigned num_configs) 663dbad75ddSKen Xue { 664dbad75ddSKen Xue int i; 665dbad75ddSKen Xue u32 arg; 66625a853d0SKen Xue int ret = 0; 66725a853d0SKen Xue u32 pin_reg; 668dbad75ddSKen Xue unsigned long flags; 669dbad75ddSKen Xue enum pin_config_param param; 670dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 671dbad75ddSKen Xue 672229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 673dbad75ddSKen Xue for (i = 0; i < num_configs; i++) { 674dbad75ddSKen Xue param = pinconf_to_config_param(configs[i]); 675dbad75ddSKen Xue arg = pinconf_to_config_argument(configs[i]); 676dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + pin*4); 677dbad75ddSKen Xue 678dbad75ddSKen Xue switch (param) { 679dbad75ddSKen Xue case PIN_CONFIG_INPUT_DEBOUNCE: 680dbad75ddSKen Xue pin_reg &= ~DB_TMR_OUT_MASK; 681dbad75ddSKen Xue pin_reg |= arg & DB_TMR_OUT_MASK; 682dbad75ddSKen Xue break; 683dbad75ddSKen Xue 684dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_DOWN: 685dbad75ddSKen Xue pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); 686dbad75ddSKen Xue pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; 687dbad75ddSKen Xue break; 688dbad75ddSKen Xue 689dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_UP: 690dbad75ddSKen Xue pin_reg &= ~BIT(PULL_UP_SEL_OFF); 691dbad75ddSKen Xue pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; 692dbad75ddSKen Xue pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); 693dbad75ddSKen Xue pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; 694dbad75ddSKen Xue break; 695dbad75ddSKen Xue 696dbad75ddSKen Xue case PIN_CONFIG_DRIVE_STRENGTH: 697dbad75ddSKen Xue pin_reg &= ~(DRV_STRENGTH_SEL_MASK 698dbad75ddSKen Xue << DRV_STRENGTH_SEL_OFF); 699dbad75ddSKen Xue pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) 700dbad75ddSKen Xue << DRV_STRENGTH_SEL_OFF; 701dbad75ddSKen Xue break; 702dbad75ddSKen Xue 703dbad75ddSKen Xue default: 704dbad75ddSKen Xue dev_err(&gpio_dev->pdev->dev, 705dbad75ddSKen Xue "Invalid config param %04x\n", param); 70625a853d0SKen Xue ret = -ENOTSUPP; 707dbad75ddSKen Xue } 708dbad75ddSKen Xue 709dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + pin*4); 710dbad75ddSKen Xue } 711229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 712dbad75ddSKen Xue 71325a853d0SKen Xue return ret; 714dbad75ddSKen Xue } 715dbad75ddSKen Xue 716dbad75ddSKen Xue static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, 717dbad75ddSKen Xue unsigned int group, 718dbad75ddSKen Xue unsigned long *config) 719dbad75ddSKen Xue { 720dbad75ddSKen Xue const unsigned *pins; 721dbad75ddSKen Xue unsigned npins; 722dbad75ddSKen Xue int ret; 723dbad75ddSKen Xue 724dbad75ddSKen Xue ret = amd_get_group_pins(pctldev, group, &pins, &npins); 725dbad75ddSKen Xue if (ret) 726dbad75ddSKen Xue return ret; 727dbad75ddSKen Xue 728dbad75ddSKen Xue if (amd_pinconf_get(pctldev, pins[0], config)) 729dbad75ddSKen Xue return -ENOTSUPP; 730dbad75ddSKen Xue 731dbad75ddSKen Xue return 0; 732dbad75ddSKen Xue } 733dbad75ddSKen Xue 734dbad75ddSKen Xue static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, 735dbad75ddSKen Xue unsigned group, unsigned long *configs, 736dbad75ddSKen Xue unsigned num_configs) 737dbad75ddSKen Xue { 738dbad75ddSKen Xue const unsigned *pins; 739dbad75ddSKen Xue unsigned npins; 740dbad75ddSKen Xue int i, ret; 741dbad75ddSKen Xue 742dbad75ddSKen Xue ret = amd_get_group_pins(pctldev, group, &pins, &npins); 743dbad75ddSKen Xue if (ret) 744dbad75ddSKen Xue return ret; 745dbad75ddSKen Xue for (i = 0; i < npins; i++) { 746dbad75ddSKen Xue if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) 747dbad75ddSKen Xue return -ENOTSUPP; 748dbad75ddSKen Xue } 749dbad75ddSKen Xue return 0; 750dbad75ddSKen Xue } 751dbad75ddSKen Xue 752dbad75ddSKen Xue static const struct pinconf_ops amd_pinconf_ops = { 753dbad75ddSKen Xue .pin_config_get = amd_pinconf_get, 754dbad75ddSKen Xue .pin_config_set = amd_pinconf_set, 755dbad75ddSKen Xue .pin_config_group_get = amd_pinconf_group_get, 756dbad75ddSKen Xue .pin_config_group_set = amd_pinconf_group_set, 757dbad75ddSKen Xue }; 758dbad75ddSKen Xue 75979d2c8beSDaniel Drake #ifdef CONFIG_PM_SLEEP 76079d2c8beSDaniel Drake static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) 76179d2c8beSDaniel Drake { 76279d2c8beSDaniel Drake const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 76379d2c8beSDaniel Drake 76479d2c8beSDaniel Drake if (!pd) 76579d2c8beSDaniel Drake return false; 76679d2c8beSDaniel Drake 76779d2c8beSDaniel Drake /* 76879d2c8beSDaniel Drake * Only restore the pin if it is actually in use by the kernel (or 76979d2c8beSDaniel Drake * by userspace). 77079d2c8beSDaniel Drake */ 77179d2c8beSDaniel Drake if (pd->mux_owner || pd->gpio_owner || 77279d2c8beSDaniel Drake gpiochip_line_is_irq(&gpio_dev->gc, pin)) 77379d2c8beSDaniel Drake return true; 77479d2c8beSDaniel Drake 77579d2c8beSDaniel Drake return false; 77679d2c8beSDaniel Drake } 77779d2c8beSDaniel Drake 7782d71dfa2SColin Ian King static int amd_gpio_suspend(struct device *dev) 77979d2c8beSDaniel Drake { 78079d2c8beSDaniel Drake struct platform_device *pdev = to_platform_device(dev); 78179d2c8beSDaniel Drake struct amd_gpio *gpio_dev = platform_get_drvdata(pdev); 78279d2c8beSDaniel Drake struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 78379d2c8beSDaniel Drake int i; 78479d2c8beSDaniel Drake 78579d2c8beSDaniel Drake for (i = 0; i < desc->npins; i++) { 78679d2c8beSDaniel Drake int pin = desc->pins[i].number; 78779d2c8beSDaniel Drake 78879d2c8beSDaniel Drake if (!amd_gpio_should_save(gpio_dev, pin)) 78979d2c8beSDaniel Drake continue; 79079d2c8beSDaniel Drake 79179d2c8beSDaniel Drake gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin*4); 79279d2c8beSDaniel Drake } 79379d2c8beSDaniel Drake 79479d2c8beSDaniel Drake return 0; 79579d2c8beSDaniel Drake } 79679d2c8beSDaniel Drake 7972d71dfa2SColin Ian King static int amd_gpio_resume(struct device *dev) 79879d2c8beSDaniel Drake { 79979d2c8beSDaniel Drake struct platform_device *pdev = to_platform_device(dev); 80079d2c8beSDaniel Drake struct amd_gpio *gpio_dev = platform_get_drvdata(pdev); 80179d2c8beSDaniel Drake struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 80279d2c8beSDaniel Drake int i; 80379d2c8beSDaniel Drake 80479d2c8beSDaniel Drake for (i = 0; i < desc->npins; i++) { 80579d2c8beSDaniel Drake int pin = desc->pins[i].number; 80679d2c8beSDaniel Drake 80779d2c8beSDaniel Drake if (!amd_gpio_should_save(gpio_dev, pin)) 80879d2c8beSDaniel Drake continue; 80979d2c8beSDaniel Drake 81079d2c8beSDaniel Drake writel(gpio_dev->saved_regs[i], gpio_dev->base + pin*4); 81179d2c8beSDaniel Drake } 81279d2c8beSDaniel Drake 81379d2c8beSDaniel Drake return 0; 81479d2c8beSDaniel Drake } 81579d2c8beSDaniel Drake 81679d2c8beSDaniel Drake static const struct dev_pm_ops amd_gpio_pm_ops = { 81779d2c8beSDaniel Drake SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend, 81879d2c8beSDaniel Drake amd_gpio_resume) 81979d2c8beSDaniel Drake }; 82079d2c8beSDaniel Drake #endif 82179d2c8beSDaniel Drake 822dbad75ddSKen Xue static struct pinctrl_desc amd_pinctrl_desc = { 823dbad75ddSKen Xue .pins = kerncz_pins, 824dbad75ddSKen Xue .npins = ARRAY_SIZE(kerncz_pins), 825dbad75ddSKen Xue .pctlops = &amd_pinctrl_ops, 826dbad75ddSKen Xue .confops = &amd_pinconf_ops, 827dbad75ddSKen Xue .owner = THIS_MODULE, 828dbad75ddSKen Xue }; 829dbad75ddSKen Xue 830dbad75ddSKen Xue static int amd_gpio_probe(struct platform_device *pdev) 831dbad75ddSKen Xue { 832dbad75ddSKen Xue int ret = 0; 83325a853d0SKen Xue int irq_base; 834dbad75ddSKen Xue struct resource *res; 835dbad75ddSKen Xue struct amd_gpio *gpio_dev; 836dbad75ddSKen Xue 837dbad75ddSKen Xue gpio_dev = devm_kzalloc(&pdev->dev, 838dbad75ddSKen Xue sizeof(struct amd_gpio), GFP_KERNEL); 839dbad75ddSKen Xue if (!gpio_dev) 840dbad75ddSKen Xue return -ENOMEM; 841dbad75ddSKen Xue 842229710feSJulia Cartwright raw_spin_lock_init(&gpio_dev->lock); 843dbad75ddSKen Xue 844dbad75ddSKen Xue res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 845dbad75ddSKen Xue if (!res) { 846dbad75ddSKen Xue dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); 847dbad75ddSKen Xue return -EINVAL; 848dbad75ddSKen Xue } 849dbad75ddSKen Xue 850dbad75ddSKen Xue gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start, 851dbad75ddSKen Xue resource_size(res)); 852424a6c60SWei Yongjun if (!gpio_dev->base) 853424a6c60SWei Yongjun return -ENOMEM; 854dbad75ddSKen Xue 855dbad75ddSKen Xue irq_base = platform_get_irq(pdev, 0); 856dbad75ddSKen Xue if (irq_base < 0) { 8572e6424abSGustavo A. R. Silva dev_err(&pdev->dev, "Failed to get gpio IRQ: %d\n", irq_base); 8582e6424abSGustavo A. R. Silva return irq_base; 859dbad75ddSKen Xue } 860dbad75ddSKen Xue 86179d2c8beSDaniel Drake #ifdef CONFIG_PM_SLEEP 86279d2c8beSDaniel Drake gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins, 86379d2c8beSDaniel Drake sizeof(*gpio_dev->saved_regs), 86479d2c8beSDaniel Drake GFP_KERNEL); 86579d2c8beSDaniel Drake if (!gpio_dev->saved_regs) 86679d2c8beSDaniel Drake return -ENOMEM; 86779d2c8beSDaniel Drake #endif 86879d2c8beSDaniel Drake 869dbad75ddSKen Xue gpio_dev->pdev = pdev; 87012b10f47SDaniel Kurtz gpio_dev->gc.get_direction = amd_gpio_get_direction; 871dbad75ddSKen Xue gpio_dev->gc.direction_input = amd_gpio_direction_input; 872dbad75ddSKen Xue gpio_dev->gc.direction_output = amd_gpio_direction_output; 873dbad75ddSKen Xue gpio_dev->gc.get = amd_gpio_get_value; 874dbad75ddSKen Xue gpio_dev->gc.set = amd_gpio_set_value; 8752956b5d9SMika Westerberg gpio_dev->gc.set_config = amd_gpio_set_config; 876dbad75ddSKen Xue gpio_dev->gc.dbg_show = amd_gpio_dbg_show; 877dbad75ddSKen Xue 8783bfd4430SShah, Nehal-bakulchandra gpio_dev->gc.base = -1; 879dbad75ddSKen Xue gpio_dev->gc.label = pdev->name; 880dbad75ddSKen Xue gpio_dev->gc.owner = THIS_MODULE; 88158383c78SLinus Walleij gpio_dev->gc.parent = &pdev->dev; 8823bfd4430SShah, Nehal-bakulchandra gpio_dev->gc.ngpio = resource_size(res) / 4; 883dbad75ddSKen Xue #if defined(CONFIG_OF_GPIO) 884dbad75ddSKen Xue gpio_dev->gc.of_node = pdev->dev.of_node; 885dbad75ddSKen Xue #endif 886dbad75ddSKen Xue 8873bfd4430SShah, Nehal-bakulchandra gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64; 888dbad75ddSKen Xue gpio_dev->groups = kerncz_groups; 889dbad75ddSKen Xue gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); 890dbad75ddSKen Xue 891dbad75ddSKen Xue amd_pinctrl_desc.name = dev_name(&pdev->dev); 892251e22abSLaxman Dewangan gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, 893251e22abSLaxman Dewangan gpio_dev); 894323de9efSMasahiro Yamada if (IS_ERR(gpio_dev->pctrl)) { 895dbad75ddSKen Xue dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 896323de9efSMasahiro Yamada return PTR_ERR(gpio_dev->pctrl); 897dbad75ddSKen Xue } 898dbad75ddSKen Xue 89904d36723SLinus Walleij ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); 900dbad75ddSKen Xue if (ret) 901251e22abSLaxman Dewangan return ret; 902dbad75ddSKen Xue 903dbad75ddSKen Xue ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), 9043bfd4430SShah, Nehal-bakulchandra 0, 0, gpio_dev->gc.ngpio); 905dbad75ddSKen Xue if (ret) { 906dbad75ddSKen Xue dev_err(&pdev->dev, "Failed to add pin range\n"); 907dbad75ddSKen Xue goto out2; 908dbad75ddSKen Xue } 909dbad75ddSKen Xue 910dbad75ddSKen Xue ret = gpiochip_irqchip_add(&gpio_dev->gc, 911dbad75ddSKen Xue &amd_gpio_irqchip, 912dbad75ddSKen Xue 0, 913dbad75ddSKen Xue handle_simple_irq, 914dbad75ddSKen Xue IRQ_TYPE_NONE); 915dbad75ddSKen Xue if (ret) { 916dbad75ddSKen Xue dev_err(&pdev->dev, "could not add irqchip\n"); 917dbad75ddSKen Xue ret = -ENODEV; 918dbad75ddSKen Xue goto out2; 919dbad75ddSKen Xue } 920dbad75ddSKen Xue 921ba714a9cSThomas Gleixner ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, 0, 922ba714a9cSThomas Gleixner KBUILD_MODNAME, gpio_dev); 923ba714a9cSThomas Gleixner if (ret) 924ba714a9cSThomas Gleixner goto out2; 925ba714a9cSThomas Gleixner 926dbad75ddSKen Xue platform_set_drvdata(pdev, gpio_dev); 927dbad75ddSKen Xue 928dbad75ddSKen Xue dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); 929dbad75ddSKen Xue return ret; 930dbad75ddSKen Xue 931dbad75ddSKen Xue out2: 932dbad75ddSKen Xue gpiochip_remove(&gpio_dev->gc); 933dbad75ddSKen Xue 934dbad75ddSKen Xue return ret; 935dbad75ddSKen Xue } 936dbad75ddSKen Xue 937dbad75ddSKen Xue static int amd_gpio_remove(struct platform_device *pdev) 938dbad75ddSKen Xue { 939dbad75ddSKen Xue struct amd_gpio *gpio_dev; 940dbad75ddSKen Xue 941dbad75ddSKen Xue gpio_dev = platform_get_drvdata(pdev); 942dbad75ddSKen Xue 943dbad75ddSKen Xue gpiochip_remove(&gpio_dev->gc); 944dbad75ddSKen Xue 945dbad75ddSKen Xue return 0; 946dbad75ddSKen Xue } 947dbad75ddSKen Xue 948dbad75ddSKen Xue static const struct acpi_device_id amd_gpio_acpi_match[] = { 949dbad75ddSKen Xue { "AMD0030", 0 }, 95042a44402SWang Hongcheng { "AMDI0030", 0}, 951dbad75ddSKen Xue { }, 952dbad75ddSKen Xue }; 953dbad75ddSKen Xue MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); 954dbad75ddSKen Xue 955dbad75ddSKen Xue static struct platform_driver amd_gpio_driver = { 956dbad75ddSKen Xue .driver = { 957dbad75ddSKen Xue .name = "amd_gpio", 958dbad75ddSKen Xue .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), 95979d2c8beSDaniel Drake #ifdef CONFIG_PM_SLEEP 96079d2c8beSDaniel Drake .pm = &amd_gpio_pm_ops, 96179d2c8beSDaniel Drake #endif 962dbad75ddSKen Xue }, 963dbad75ddSKen Xue .probe = amd_gpio_probe, 964dbad75ddSKen Xue .remove = amd_gpio_remove, 965dbad75ddSKen Xue }; 966dbad75ddSKen Xue 967dbad75ddSKen Xue module_platform_driver(amd_gpio_driver); 968dbad75ddSKen Xue 969dbad75ddSKen Xue MODULE_LICENSE("GPL v2"); 970dbad75ddSKen Xue MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); 971dbad75ddSKen Xue MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); 972