1dbad75ddSKen Xue /* 2dbad75ddSKen Xue * GPIO driver for AMD 3dbad75ddSKen Xue * 4dbad75ddSKen Xue * Copyright (c) 2014,2015 AMD Corporation. 5dbad75ddSKen Xue * Authors: Ken Xue <Ken.Xue@amd.com> 6dbad75ddSKen Xue * Wu, Jeff <Jeff.Wu@amd.com> 7dbad75ddSKen Xue * 8dbad75ddSKen Xue * This program is free software; you can redistribute it and/or modify it 9dbad75ddSKen Xue * under the terms and conditions of the GNU General Public License, 10dbad75ddSKen Xue * version 2, as published by the Free Software Foundation. 11dbad75ddSKen Xue */ 12dbad75ddSKen Xue 13dbad75ddSKen Xue #include <linux/err.h> 14dbad75ddSKen Xue #include <linux/bug.h> 15dbad75ddSKen Xue #include <linux/kernel.h> 16dbad75ddSKen Xue #include <linux/module.h> 17dbad75ddSKen Xue #include <linux/spinlock.h> 18dbad75ddSKen Xue #include <linux/compiler.h> 19dbad75ddSKen Xue #include <linux/types.h> 20dbad75ddSKen Xue #include <linux/errno.h> 21dbad75ddSKen Xue #include <linux/log2.h> 22dbad75ddSKen Xue #include <linux/io.h> 23dbad75ddSKen Xue #include <linux/gpio.h> 24dbad75ddSKen Xue #include <linux/slab.h> 25dbad75ddSKen Xue #include <linux/platform_device.h> 26dbad75ddSKen Xue #include <linux/mutex.h> 27dbad75ddSKen Xue #include <linux/acpi.h> 28dbad75ddSKen Xue #include <linux/seq_file.h> 29dbad75ddSKen Xue #include <linux/interrupt.h> 30dbad75ddSKen Xue #include <linux/list.h> 31dbad75ddSKen Xue #include <linux/bitops.h> 32dbad75ddSKen Xue #include <linux/pinctrl/pinconf.h> 33dbad75ddSKen Xue #include <linux/pinctrl/pinconf-generic.h> 34dbad75ddSKen Xue 35dbad75ddSKen Xue #include "pinctrl-utils.h" 36dbad75ddSKen Xue #include "pinctrl-amd.h" 37dbad75ddSKen Xue 38dbad75ddSKen Xue static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 39dbad75ddSKen Xue { 40dbad75ddSKen Xue unsigned long flags; 41dbad75ddSKen Xue u32 pin_reg; 4204d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 43dbad75ddSKen Xue 44dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 45dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 46dbad75ddSKen Xue pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); 47dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4); 48dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 49dbad75ddSKen Xue 50dbad75ddSKen Xue return 0; 51dbad75ddSKen Xue } 52dbad75ddSKen Xue 53dbad75ddSKen Xue static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 54dbad75ddSKen Xue int value) 55dbad75ddSKen Xue { 56dbad75ddSKen Xue u32 pin_reg; 57dbad75ddSKen Xue unsigned long flags; 5804d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 59dbad75ddSKen Xue 60dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 61dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 62dbad75ddSKen Xue pin_reg |= BIT(OUTPUT_ENABLE_OFF); 63dbad75ddSKen Xue if (value) 64dbad75ddSKen Xue pin_reg |= BIT(OUTPUT_VALUE_OFF); 65dbad75ddSKen Xue else 66dbad75ddSKen Xue pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 67dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4); 68dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 69dbad75ddSKen Xue 70dbad75ddSKen Xue return 0; 71dbad75ddSKen Xue } 72dbad75ddSKen Xue 73dbad75ddSKen Xue static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) 74dbad75ddSKen Xue { 75dbad75ddSKen Xue u32 pin_reg; 76dbad75ddSKen Xue unsigned long flags; 7704d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 78dbad75ddSKen Xue 79dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 80dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 81dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 82dbad75ddSKen Xue 83dbad75ddSKen Xue return !!(pin_reg & BIT(PIN_STS_OFF)); 84dbad75ddSKen Xue } 85dbad75ddSKen Xue 86dbad75ddSKen Xue static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) 87dbad75ddSKen Xue { 88dbad75ddSKen Xue u32 pin_reg; 89dbad75ddSKen Xue unsigned long flags; 9004d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 91dbad75ddSKen Xue 92dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 93dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 94dbad75ddSKen Xue if (value) 95dbad75ddSKen Xue pin_reg |= BIT(OUTPUT_VALUE_OFF); 96dbad75ddSKen Xue else 97dbad75ddSKen Xue pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 98dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4); 99dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 100dbad75ddSKen Xue } 101dbad75ddSKen Xue 102dbad75ddSKen Xue static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, 103dbad75ddSKen Xue unsigned debounce) 104dbad75ddSKen Xue { 105dbad75ddSKen Xue u32 time; 10625a853d0SKen Xue u32 pin_reg; 10725a853d0SKen Xue int ret = 0; 108dbad75ddSKen Xue unsigned long flags; 10904d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 110dbad75ddSKen Xue 111dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 112dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 113dbad75ddSKen Xue 114dbad75ddSKen Xue if (debounce) { 115dbad75ddSKen Xue pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 116dbad75ddSKen Xue pin_reg &= ~DB_TMR_OUT_MASK; 117dbad75ddSKen Xue /* 118dbad75ddSKen Xue Debounce Debounce Timer Max 119dbad75ddSKen Xue TmrLarge TmrOutUnit Unit Debounce 120dbad75ddSKen Xue Time 121dbad75ddSKen Xue 0 0 61 usec (2 RtcClk) 976 usec 122dbad75ddSKen Xue 0 1 244 usec (8 RtcClk) 3.9 msec 123dbad75ddSKen Xue 1 0 15.6 msec (512 RtcClk) 250 msec 124dbad75ddSKen Xue 1 1 62.5 msec (2048 RtcClk) 1 sec 125dbad75ddSKen Xue */ 126dbad75ddSKen Xue 127dbad75ddSKen Xue if (debounce < 61) { 128dbad75ddSKen Xue pin_reg |= 1; 129dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 130dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 131dbad75ddSKen Xue } else if (debounce < 976) { 132dbad75ddSKen Xue time = debounce / 61; 133dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK; 134dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 135dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 136dbad75ddSKen Xue } else if (debounce < 3900) { 137dbad75ddSKen Xue time = debounce / 244; 138dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK; 139dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 140dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 141dbad75ddSKen Xue } else if (debounce < 250000) { 142dbad75ddSKen Xue time = debounce / 15600; 143dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK; 144dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 145dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_LARGE_OFF); 146dbad75ddSKen Xue } else if (debounce < 1000000) { 147dbad75ddSKen Xue time = debounce / 62500; 148dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK; 149dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 150dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_LARGE_OFF); 151dbad75ddSKen Xue } else { 152dbad75ddSKen Xue pin_reg &= ~DB_CNTRl_MASK; 15325a853d0SKen Xue ret = -EINVAL; 154dbad75ddSKen Xue } 155dbad75ddSKen Xue } else { 156dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 157dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 158dbad75ddSKen Xue pin_reg &= ~DB_TMR_OUT_MASK; 159dbad75ddSKen Xue pin_reg &= ~DB_CNTRl_MASK; 160dbad75ddSKen Xue } 161dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4); 162dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 163dbad75ddSKen Xue 16425a853d0SKen Xue return ret; 165dbad75ddSKen Xue } 166dbad75ddSKen Xue 167dbad75ddSKen Xue #ifdef CONFIG_DEBUG_FS 168dbad75ddSKen Xue static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) 169dbad75ddSKen Xue { 170dbad75ddSKen Xue u32 pin_reg; 171dbad75ddSKen Xue unsigned long flags; 172dbad75ddSKen Xue unsigned int bank, i, pin_num; 17304d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 174dbad75ddSKen Xue 175dbad75ddSKen Xue char *level_trig; 176dbad75ddSKen Xue char *active_level; 177dbad75ddSKen Xue char *interrupt_enable; 178dbad75ddSKen Xue char *interrupt_mask; 179dbad75ddSKen Xue char *wake_cntrl0; 180dbad75ddSKen Xue char *wake_cntrl1; 181dbad75ddSKen Xue char *wake_cntrl2; 182dbad75ddSKen Xue char *pin_sts; 183dbad75ddSKen Xue char *pull_up_sel; 184dbad75ddSKen Xue char *pull_up_enable; 185dbad75ddSKen Xue char *pull_down_enable; 186dbad75ddSKen Xue char *output_value; 187dbad75ddSKen Xue char *output_enable; 188dbad75ddSKen Xue 1893bfd4430SShah, Nehal-bakulchandra for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { 190dbad75ddSKen Xue seq_printf(s, "GPIO bank%d\t", bank); 191dbad75ddSKen Xue 192dbad75ddSKen Xue switch (bank) { 193dbad75ddSKen Xue case 0: 194dbad75ddSKen Xue i = 0; 195dbad75ddSKen Xue pin_num = AMD_GPIO_PINS_BANK0; 196dbad75ddSKen Xue break; 197dbad75ddSKen Xue case 1: 198dbad75ddSKen Xue i = 64; 199dbad75ddSKen Xue pin_num = AMD_GPIO_PINS_BANK1 + i; 200dbad75ddSKen Xue break; 201dbad75ddSKen Xue case 2: 202dbad75ddSKen Xue i = 128; 203dbad75ddSKen Xue pin_num = AMD_GPIO_PINS_BANK2 + i; 204dbad75ddSKen Xue break; 2053bfd4430SShah, Nehal-bakulchandra case 3: 2063bfd4430SShah, Nehal-bakulchandra i = 192; 2073bfd4430SShah, Nehal-bakulchandra pin_num = AMD_GPIO_PINS_BANK3 + i; 2083bfd4430SShah, Nehal-bakulchandra break; 2096ac4c1adSLinus Walleij default: 2106ac4c1adSLinus Walleij /* Illegal bank number, ignore */ 2116ac4c1adSLinus Walleij continue; 212dbad75ddSKen Xue } 213dbad75ddSKen Xue for (; i < pin_num; i++) { 214dbad75ddSKen Xue seq_printf(s, "pin%d\t", i); 215dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 216dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + i * 4); 217dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 218dbad75ddSKen Xue 219dbad75ddSKen Xue if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { 220dbad75ddSKen Xue interrupt_enable = "interrupt is enabled|"; 221dbad75ddSKen Xue 2223775dac1SDan Carpenter if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) && 2233775dac1SDan Carpenter !(pin_reg & BIT(ACTIVE_LEVEL_OFF + 1))) 224dbad75ddSKen Xue active_level = "Active low|"; 2253775dac1SDan Carpenter else if (pin_reg & BIT(ACTIVE_LEVEL_OFF) && 2263775dac1SDan Carpenter !(pin_reg & BIT(ACTIVE_LEVEL_OFF + 1))) 227dbad75ddSKen Xue active_level = "Active high|"; 2283775dac1SDan Carpenter else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) && 2293775dac1SDan Carpenter pin_reg & BIT(ACTIVE_LEVEL_OFF + 1)) 230dbad75ddSKen Xue active_level = "Active on both|"; 231dbad75ddSKen Xue else 232dbad75ddSKen Xue active_level = "Unknow Active level|"; 233dbad75ddSKen Xue 234dbad75ddSKen Xue if (pin_reg & BIT(LEVEL_TRIG_OFF)) 235dbad75ddSKen Xue level_trig = "Level trigger|"; 236dbad75ddSKen Xue else 237dbad75ddSKen Xue level_trig = "Edge trigger|"; 238dbad75ddSKen Xue 239dbad75ddSKen Xue } else { 240dbad75ddSKen Xue interrupt_enable = 241dbad75ddSKen Xue "interrupt is disabled|"; 242dbad75ddSKen Xue active_level = " "; 243dbad75ddSKen Xue level_trig = " "; 244dbad75ddSKen Xue } 245dbad75ddSKen Xue 246dbad75ddSKen Xue if (pin_reg & BIT(INTERRUPT_MASK_OFF)) 247dbad75ddSKen Xue interrupt_mask = 248dbad75ddSKen Xue "interrupt is unmasked|"; 249dbad75ddSKen Xue else 250dbad75ddSKen Xue interrupt_mask = 251dbad75ddSKen Xue "interrupt is masked|"; 252dbad75ddSKen Xue 2533bfd4430SShah, Nehal-bakulchandra if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) 254dbad75ddSKen Xue wake_cntrl0 = "enable wakeup in S0i3 state|"; 255dbad75ddSKen Xue else 256dbad75ddSKen Xue wake_cntrl0 = "disable wakeup in S0i3 state|"; 257dbad75ddSKen Xue 2583bfd4430SShah, Nehal-bakulchandra if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) 259dbad75ddSKen Xue wake_cntrl1 = "enable wakeup in S3 state|"; 260dbad75ddSKen Xue else 261dbad75ddSKen Xue wake_cntrl1 = "disable wakeup in S3 state|"; 262dbad75ddSKen Xue 2633bfd4430SShah, Nehal-bakulchandra if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) 264dbad75ddSKen Xue wake_cntrl2 = "enable wakeup in S4/S5 state|"; 265dbad75ddSKen Xue else 266dbad75ddSKen Xue wake_cntrl2 = "disable wakeup in S4/S5 state|"; 267dbad75ddSKen Xue 268dbad75ddSKen Xue if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { 269dbad75ddSKen Xue pull_up_enable = "pull-up is enabled|"; 270dbad75ddSKen Xue if (pin_reg & BIT(PULL_UP_SEL_OFF)) 271dbad75ddSKen Xue pull_up_sel = "8k pull-up|"; 272dbad75ddSKen Xue else 273dbad75ddSKen Xue pull_up_sel = "4k pull-up|"; 274dbad75ddSKen Xue } else { 275dbad75ddSKen Xue pull_up_enable = "pull-up is disabled|"; 276dbad75ddSKen Xue pull_up_sel = " "; 277dbad75ddSKen Xue } 278dbad75ddSKen Xue 279dbad75ddSKen Xue if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) 280dbad75ddSKen Xue pull_down_enable = "pull-down is enabled|"; 281dbad75ddSKen Xue else 282dbad75ddSKen Xue pull_down_enable = "Pull-down is disabled|"; 283dbad75ddSKen Xue 284dbad75ddSKen Xue if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { 285dbad75ddSKen Xue pin_sts = " "; 286dbad75ddSKen Xue output_enable = "output is enabled|"; 287dbad75ddSKen Xue if (pin_reg & BIT(OUTPUT_VALUE_OFF)) 288dbad75ddSKen Xue output_value = "output is high|"; 289dbad75ddSKen Xue else 290dbad75ddSKen Xue output_value = "output is low|"; 291dbad75ddSKen Xue } else { 292dbad75ddSKen Xue output_enable = "output is disabled|"; 293dbad75ddSKen Xue output_value = " "; 294dbad75ddSKen Xue 295dbad75ddSKen Xue if (pin_reg & BIT(PIN_STS_OFF)) 296dbad75ddSKen Xue pin_sts = "input is high|"; 297dbad75ddSKen Xue else 298dbad75ddSKen Xue pin_sts = "input is low|"; 299dbad75ddSKen Xue } 300dbad75ddSKen Xue 301dbad75ddSKen Xue seq_printf(s, "%s %s %s %s %s %s\n" 302dbad75ddSKen Xue " %s %s %s %s %s %s %s 0x%x\n", 303dbad75ddSKen Xue level_trig, active_level, interrupt_enable, 304dbad75ddSKen Xue interrupt_mask, wake_cntrl0, wake_cntrl1, 305dbad75ddSKen Xue wake_cntrl2, pin_sts, pull_up_sel, 306dbad75ddSKen Xue pull_up_enable, pull_down_enable, 307dbad75ddSKen Xue output_value, output_enable, pin_reg); 308dbad75ddSKen Xue } 309dbad75ddSKen Xue } 310dbad75ddSKen Xue } 311dbad75ddSKen Xue #else 312dbad75ddSKen Xue #define amd_gpio_dbg_show NULL 313dbad75ddSKen Xue #endif 314dbad75ddSKen Xue 315dbad75ddSKen Xue static void amd_gpio_irq_enable(struct irq_data *d) 316dbad75ddSKen Xue { 317dbad75ddSKen Xue u32 pin_reg; 318dbad75ddSKen Xue unsigned long flags; 319dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 32004d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 321dbad75ddSKen Xue 322dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 323dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 324dbad75ddSKen Xue pin_reg |= BIT(INTERRUPT_ENABLE_OFF); 325dbad75ddSKen Xue pin_reg |= BIT(INTERRUPT_MASK_OFF); 326dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 327dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 328dbad75ddSKen Xue } 329dbad75ddSKen Xue 330dbad75ddSKen Xue static void amd_gpio_irq_disable(struct irq_data *d) 331dbad75ddSKen Xue { 332dbad75ddSKen Xue u32 pin_reg; 333dbad75ddSKen Xue unsigned long flags; 334dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 33504d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 336dbad75ddSKen Xue 337dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 338dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 339dbad75ddSKen Xue pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); 340dbad75ddSKen Xue pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 341dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 342dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 343dbad75ddSKen Xue } 344dbad75ddSKen Xue 345dbad75ddSKen Xue static void amd_gpio_irq_mask(struct irq_data *d) 346dbad75ddSKen Xue { 347dbad75ddSKen Xue u32 pin_reg; 348dbad75ddSKen Xue unsigned long flags; 349dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 35004d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 351dbad75ddSKen Xue 352dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 353dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 354dbad75ddSKen Xue pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 355dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 356dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 357dbad75ddSKen Xue } 358dbad75ddSKen Xue 359dbad75ddSKen Xue static void amd_gpio_irq_unmask(struct irq_data *d) 360dbad75ddSKen Xue { 361dbad75ddSKen Xue u32 pin_reg; 362dbad75ddSKen Xue unsigned long flags; 363dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 36404d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 365dbad75ddSKen Xue 366dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 367dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 368dbad75ddSKen Xue pin_reg |= BIT(INTERRUPT_MASK_OFF); 369dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 370dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 371dbad75ddSKen Xue } 372dbad75ddSKen Xue 373dbad75ddSKen Xue static void amd_gpio_irq_eoi(struct irq_data *d) 374dbad75ddSKen Xue { 375dbad75ddSKen Xue u32 reg; 376dbad75ddSKen Xue unsigned long flags; 377dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 37804d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 379dbad75ddSKen Xue 380dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 381dbad75ddSKen Xue reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 382dbad75ddSKen Xue reg |= EOI_MASK; 383dbad75ddSKen Xue writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 384dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 385dbad75ddSKen Xue } 386dbad75ddSKen Xue 387dbad75ddSKen Xue static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) 388dbad75ddSKen Xue { 389dbad75ddSKen Xue int ret = 0; 390dbad75ddSKen Xue u32 pin_reg; 391dbad75ddSKen Xue unsigned long flags; 392e084448bSAgrawal, Nitesh-kumar bool level_trig; 393499c7196SAgrawal, Nitesh-kumar u32 active_level; 394dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 39504d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 396dbad75ddSKen Xue 397dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 398dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 399dbad75ddSKen Xue 400499c7196SAgrawal, Nitesh-kumar /* 401499c7196SAgrawal, Nitesh-kumar * When level_trig is set EDGE and active_level is set HIGH in BIOS 402499c7196SAgrawal, Nitesh-kumar * default settings, ignore incoming settings from client and use 403499c7196SAgrawal, Nitesh-kumar * BIOS settings to configure GPIO register. 404499c7196SAgrawal, Nitesh-kumar */ 405e084448bSAgrawal, Nitesh-kumar level_trig = !(pin_reg & (LEVEL_TRIGGER << LEVEL_TRIG_OFF)); 406499c7196SAgrawal, Nitesh-kumar active_level = pin_reg & (ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 407499c7196SAgrawal, Nitesh-kumar 408e084448bSAgrawal, Nitesh-kumar if(level_trig && 409e084448bSAgrawal, Nitesh-kumar ((active_level >> ACTIVE_LEVEL_OFF) == ACTIVE_HIGH)) 410499c7196SAgrawal, Nitesh-kumar type = IRQ_TYPE_EDGE_FALLING; 411499c7196SAgrawal, Nitesh-kumar 412dbad75ddSKen Xue switch (type & IRQ_TYPE_SENSE_MASK) { 413dbad75ddSKen Xue case IRQ_TYPE_EDGE_RISING: 414dbad75ddSKen Xue pin_reg &= ~BIT(LEVEL_TRIG_OFF); 415dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 416dbad75ddSKen Xue pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 417dbad75ddSKen Xue pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 4189d829314SThomas Gleixner irq_set_handler_locked(d, handle_edge_irq); 419dbad75ddSKen Xue break; 420dbad75ddSKen Xue 421dbad75ddSKen Xue case IRQ_TYPE_EDGE_FALLING: 422dbad75ddSKen Xue pin_reg &= ~BIT(LEVEL_TRIG_OFF); 423dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 424dbad75ddSKen Xue pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 425dbad75ddSKen Xue pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 4269d829314SThomas Gleixner irq_set_handler_locked(d, handle_edge_irq); 427dbad75ddSKen Xue break; 428dbad75ddSKen Xue 429dbad75ddSKen Xue case IRQ_TYPE_EDGE_BOTH: 430dbad75ddSKen Xue pin_reg &= ~BIT(LEVEL_TRIG_OFF); 431dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 432dbad75ddSKen Xue pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; 433dbad75ddSKen Xue pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 4349d829314SThomas Gleixner irq_set_handler_locked(d, handle_edge_irq); 435dbad75ddSKen Xue break; 436dbad75ddSKen Xue 437dbad75ddSKen Xue case IRQ_TYPE_LEVEL_HIGH: 438dbad75ddSKen Xue pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 439dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 440dbad75ddSKen Xue pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 441dbad75ddSKen Xue pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 442dbad75ddSKen Xue pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF; 4439d829314SThomas Gleixner irq_set_handler_locked(d, handle_level_irq); 444dbad75ddSKen Xue break; 445dbad75ddSKen Xue 446dbad75ddSKen Xue case IRQ_TYPE_LEVEL_LOW: 447dbad75ddSKen Xue pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 448dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 449dbad75ddSKen Xue pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 450dbad75ddSKen Xue pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 451dbad75ddSKen Xue pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF; 4529d829314SThomas Gleixner irq_set_handler_locked(d, handle_level_irq); 453dbad75ddSKen Xue break; 454dbad75ddSKen Xue 455dbad75ddSKen Xue case IRQ_TYPE_NONE: 456dbad75ddSKen Xue break; 457dbad75ddSKen Xue 458dbad75ddSKen Xue default: 459dbad75ddSKen Xue dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); 460dbad75ddSKen Xue ret = -EINVAL; 461dbad75ddSKen Xue } 462dbad75ddSKen Xue 463dbad75ddSKen Xue pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; 464dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 465dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 466dbad75ddSKen Xue 467dbad75ddSKen Xue return ret; 468dbad75ddSKen Xue } 469dbad75ddSKen Xue 470dbad75ddSKen Xue static void amd_irq_ack(struct irq_data *d) 471dbad75ddSKen Xue { 472dbad75ddSKen Xue /* 473dbad75ddSKen Xue * based on HW design,there is no need to ack HW 474dbad75ddSKen Xue * before handle current irq. But this routine is 475dbad75ddSKen Xue * necessary for handle_edge_irq 476dbad75ddSKen Xue */ 477dbad75ddSKen Xue } 478dbad75ddSKen Xue 479dbad75ddSKen Xue static struct irq_chip amd_gpio_irqchip = { 480dbad75ddSKen Xue .name = "amd_gpio", 481dbad75ddSKen Xue .irq_ack = amd_irq_ack, 482dbad75ddSKen Xue .irq_enable = amd_gpio_irq_enable, 483dbad75ddSKen Xue .irq_disable = amd_gpio_irq_disable, 484dbad75ddSKen Xue .irq_mask = amd_gpio_irq_mask, 485dbad75ddSKen Xue .irq_unmask = amd_gpio_irq_unmask, 486dbad75ddSKen Xue .irq_eoi = amd_gpio_irq_eoi, 487dbad75ddSKen Xue .irq_set_type = amd_gpio_irq_set_type, 4883bfd4430SShah, Nehal-bakulchandra .flags = IRQCHIP_SKIP_SET_WAKE, 489dbad75ddSKen Xue }; 490dbad75ddSKen Xue 491bd0b9ac4SThomas Gleixner static void amd_gpio_irq_handler(struct irq_desc *desc) 492dbad75ddSKen Xue { 493dbad75ddSKen Xue u32 i; 494dbad75ddSKen Xue u32 off; 495dbad75ddSKen Xue u32 reg; 496dbad75ddSKen Xue u32 pin_reg; 497dbad75ddSKen Xue u64 reg64; 498dbad75ddSKen Xue int handled = 0; 499bd0b9ac4SThomas Gleixner unsigned int irq; 500dbad75ddSKen Xue unsigned long flags; 5015663bb27SJiang Liu struct irq_chip *chip = irq_desc_get_chip(desc); 502dbad75ddSKen Xue struct gpio_chip *gc = irq_desc_get_handler_data(desc); 50304d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 504dbad75ddSKen Xue 505dbad75ddSKen Xue chained_irq_enter(chip, desc); 506dbad75ddSKen Xue /*enable GPIO interrupt again*/ 507dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 508dbad75ddSKen Xue reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); 509dbad75ddSKen Xue reg64 = reg; 510dbad75ddSKen Xue reg64 = reg64 << 32; 511dbad75ddSKen Xue 512dbad75ddSKen Xue reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG0); 513dbad75ddSKen Xue reg64 |= reg; 514dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 515dbad75ddSKen Xue 516dbad75ddSKen Xue /* 517dbad75ddSKen Xue * first 46 bits indicates interrupt status. 518dbad75ddSKen Xue * one bit represents four interrupt sources. 519dbad75ddSKen Xue */ 520dbad75ddSKen Xue for (off = 0; off < 46 ; off++) { 521dbad75ddSKen Xue if (reg64 & BIT(off)) { 522dbad75ddSKen Xue for (i = 0; i < 4; i++) { 523dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + 524dbad75ddSKen Xue (off * 4 + i) * 4); 525dbad75ddSKen Xue if ((pin_reg & BIT(INTERRUPT_STS_OFF)) || 526dbad75ddSKen Xue (pin_reg & BIT(WAKE_STS_OFF))) { 527dbad75ddSKen Xue irq = irq_find_mapping(gc->irqdomain, 528dbad75ddSKen Xue off * 4 + i); 529dbad75ddSKen Xue generic_handle_irq(irq); 530dbad75ddSKen Xue writel(pin_reg, 531dbad75ddSKen Xue gpio_dev->base 532dbad75ddSKen Xue + (off * 4 + i) * 4); 533dbad75ddSKen Xue handled++; 534dbad75ddSKen Xue } 535dbad75ddSKen Xue } 536dbad75ddSKen Xue } 537dbad75ddSKen Xue } 538dbad75ddSKen Xue 539dbad75ddSKen Xue if (handled == 0) 540bd0b9ac4SThomas Gleixner handle_bad_irq(desc); 541dbad75ddSKen Xue 542dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 543dbad75ddSKen Xue reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 544dbad75ddSKen Xue reg |= EOI_MASK; 545dbad75ddSKen Xue writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 546dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 547dbad75ddSKen Xue 548dbad75ddSKen Xue chained_irq_exit(chip, desc); 549dbad75ddSKen Xue } 550dbad75ddSKen Xue 551dbad75ddSKen Xue static int amd_get_groups_count(struct pinctrl_dev *pctldev) 552dbad75ddSKen Xue { 553dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 554dbad75ddSKen Xue 555dbad75ddSKen Xue return gpio_dev->ngroups; 556dbad75ddSKen Xue } 557dbad75ddSKen Xue 558dbad75ddSKen Xue static const char *amd_get_group_name(struct pinctrl_dev *pctldev, 559dbad75ddSKen Xue unsigned group) 560dbad75ddSKen Xue { 561dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 562dbad75ddSKen Xue 563dbad75ddSKen Xue return gpio_dev->groups[group].name; 564dbad75ddSKen Xue } 565dbad75ddSKen Xue 566dbad75ddSKen Xue static int amd_get_group_pins(struct pinctrl_dev *pctldev, 567dbad75ddSKen Xue unsigned group, 568dbad75ddSKen Xue const unsigned **pins, 569dbad75ddSKen Xue unsigned *num_pins) 570dbad75ddSKen Xue { 571dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 572dbad75ddSKen Xue 573dbad75ddSKen Xue *pins = gpio_dev->groups[group].pins; 574dbad75ddSKen Xue *num_pins = gpio_dev->groups[group].npins; 575dbad75ddSKen Xue return 0; 576dbad75ddSKen Xue } 577dbad75ddSKen Xue 578dbad75ddSKen Xue static const struct pinctrl_ops amd_pinctrl_ops = { 579dbad75ddSKen Xue .get_groups_count = amd_get_groups_count, 580dbad75ddSKen Xue .get_group_name = amd_get_group_name, 581dbad75ddSKen Xue .get_group_pins = amd_get_group_pins, 582dbad75ddSKen Xue #ifdef CONFIG_OF 583dbad75ddSKen Xue .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 584d32f7fd3SIrina Tirdea .dt_free_map = pinctrl_utils_free_map, 585dbad75ddSKen Xue #endif 586dbad75ddSKen Xue }; 587dbad75ddSKen Xue 588dbad75ddSKen Xue static int amd_pinconf_get(struct pinctrl_dev *pctldev, 589dbad75ddSKen Xue unsigned int pin, 590dbad75ddSKen Xue unsigned long *config) 591dbad75ddSKen Xue { 592dbad75ddSKen Xue u32 pin_reg; 593dbad75ddSKen Xue unsigned arg; 594dbad75ddSKen Xue unsigned long flags; 595dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 596dbad75ddSKen Xue enum pin_config_param param = pinconf_to_config_param(*config); 597dbad75ddSKen Xue 598dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 599dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + pin*4); 600dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 601dbad75ddSKen Xue switch (param) { 602dbad75ddSKen Xue case PIN_CONFIG_INPUT_DEBOUNCE: 603dbad75ddSKen Xue arg = pin_reg & DB_TMR_OUT_MASK; 604dbad75ddSKen Xue break; 605dbad75ddSKen Xue 606dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_DOWN: 607dbad75ddSKen Xue arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); 608dbad75ddSKen Xue break; 609dbad75ddSKen Xue 610dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_UP: 611dbad75ddSKen Xue arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); 612dbad75ddSKen Xue break; 613dbad75ddSKen Xue 614dbad75ddSKen Xue case PIN_CONFIG_DRIVE_STRENGTH: 615dbad75ddSKen Xue arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; 616dbad75ddSKen Xue break; 617dbad75ddSKen Xue 618dbad75ddSKen Xue default: 619dbad75ddSKen Xue dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n", 620dbad75ddSKen Xue param); 621dbad75ddSKen Xue return -ENOTSUPP; 622dbad75ddSKen Xue } 623dbad75ddSKen Xue 624dbad75ddSKen Xue *config = pinconf_to_config_packed(param, arg); 625dbad75ddSKen Xue 626dbad75ddSKen Xue return 0; 627dbad75ddSKen Xue } 628dbad75ddSKen Xue 629dbad75ddSKen Xue static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 630dbad75ddSKen Xue unsigned long *configs, unsigned num_configs) 631dbad75ddSKen Xue { 632dbad75ddSKen Xue int i; 633dbad75ddSKen Xue u32 arg; 63425a853d0SKen Xue int ret = 0; 63525a853d0SKen Xue u32 pin_reg; 636dbad75ddSKen Xue unsigned long flags; 637dbad75ddSKen Xue enum pin_config_param param; 638dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 639dbad75ddSKen Xue 640dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 641dbad75ddSKen Xue for (i = 0; i < num_configs; i++) { 642dbad75ddSKen Xue param = pinconf_to_config_param(configs[i]); 643dbad75ddSKen Xue arg = pinconf_to_config_argument(configs[i]); 644dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + pin*4); 645dbad75ddSKen Xue 646dbad75ddSKen Xue switch (param) { 647dbad75ddSKen Xue case PIN_CONFIG_INPUT_DEBOUNCE: 648dbad75ddSKen Xue pin_reg &= ~DB_TMR_OUT_MASK; 649dbad75ddSKen Xue pin_reg |= arg & DB_TMR_OUT_MASK; 650dbad75ddSKen Xue break; 651dbad75ddSKen Xue 652dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_DOWN: 653dbad75ddSKen Xue pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); 654dbad75ddSKen Xue pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; 655dbad75ddSKen Xue break; 656dbad75ddSKen Xue 657dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_UP: 658dbad75ddSKen Xue pin_reg &= ~BIT(PULL_UP_SEL_OFF); 659dbad75ddSKen Xue pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; 660dbad75ddSKen Xue pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); 661dbad75ddSKen Xue pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; 662dbad75ddSKen Xue break; 663dbad75ddSKen Xue 664dbad75ddSKen Xue case PIN_CONFIG_DRIVE_STRENGTH: 665dbad75ddSKen Xue pin_reg &= ~(DRV_STRENGTH_SEL_MASK 666dbad75ddSKen Xue << DRV_STRENGTH_SEL_OFF); 667dbad75ddSKen Xue pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) 668dbad75ddSKen Xue << DRV_STRENGTH_SEL_OFF; 669dbad75ddSKen Xue break; 670dbad75ddSKen Xue 671dbad75ddSKen Xue default: 672dbad75ddSKen Xue dev_err(&gpio_dev->pdev->dev, 673dbad75ddSKen Xue "Invalid config param %04x\n", param); 67425a853d0SKen Xue ret = -ENOTSUPP; 675dbad75ddSKen Xue } 676dbad75ddSKen Xue 677dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + pin*4); 678dbad75ddSKen Xue } 679dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 680dbad75ddSKen Xue 68125a853d0SKen Xue return ret; 682dbad75ddSKen Xue } 683dbad75ddSKen Xue 684dbad75ddSKen Xue static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, 685dbad75ddSKen Xue unsigned int group, 686dbad75ddSKen Xue unsigned long *config) 687dbad75ddSKen Xue { 688dbad75ddSKen Xue const unsigned *pins; 689dbad75ddSKen Xue unsigned npins; 690dbad75ddSKen Xue int ret; 691dbad75ddSKen Xue 692dbad75ddSKen Xue ret = amd_get_group_pins(pctldev, group, &pins, &npins); 693dbad75ddSKen Xue if (ret) 694dbad75ddSKen Xue return ret; 695dbad75ddSKen Xue 696dbad75ddSKen Xue if (amd_pinconf_get(pctldev, pins[0], config)) 697dbad75ddSKen Xue return -ENOTSUPP; 698dbad75ddSKen Xue 699dbad75ddSKen Xue return 0; 700dbad75ddSKen Xue } 701dbad75ddSKen Xue 702dbad75ddSKen Xue static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, 703dbad75ddSKen Xue unsigned group, unsigned long *configs, 704dbad75ddSKen Xue unsigned num_configs) 705dbad75ddSKen Xue { 706dbad75ddSKen Xue const unsigned *pins; 707dbad75ddSKen Xue unsigned npins; 708dbad75ddSKen Xue int i, ret; 709dbad75ddSKen Xue 710dbad75ddSKen Xue ret = amd_get_group_pins(pctldev, group, &pins, &npins); 711dbad75ddSKen Xue if (ret) 712dbad75ddSKen Xue return ret; 713dbad75ddSKen Xue for (i = 0; i < npins; i++) { 714dbad75ddSKen Xue if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) 715dbad75ddSKen Xue return -ENOTSUPP; 716dbad75ddSKen Xue } 717dbad75ddSKen Xue return 0; 718dbad75ddSKen Xue } 719dbad75ddSKen Xue 720dbad75ddSKen Xue static const struct pinconf_ops amd_pinconf_ops = { 721dbad75ddSKen Xue .pin_config_get = amd_pinconf_get, 722dbad75ddSKen Xue .pin_config_set = amd_pinconf_set, 723dbad75ddSKen Xue .pin_config_group_get = amd_pinconf_group_get, 724dbad75ddSKen Xue .pin_config_group_set = amd_pinconf_group_set, 725dbad75ddSKen Xue }; 726dbad75ddSKen Xue 727dbad75ddSKen Xue static struct pinctrl_desc amd_pinctrl_desc = { 728dbad75ddSKen Xue .pins = kerncz_pins, 729dbad75ddSKen Xue .npins = ARRAY_SIZE(kerncz_pins), 730dbad75ddSKen Xue .pctlops = &amd_pinctrl_ops, 731dbad75ddSKen Xue .confops = &amd_pinconf_ops, 732dbad75ddSKen Xue .owner = THIS_MODULE, 733dbad75ddSKen Xue }; 734dbad75ddSKen Xue 735dbad75ddSKen Xue static int amd_gpio_probe(struct platform_device *pdev) 736dbad75ddSKen Xue { 737dbad75ddSKen Xue int ret = 0; 73825a853d0SKen Xue int irq_base; 739dbad75ddSKen Xue struct resource *res; 740dbad75ddSKen Xue struct amd_gpio *gpio_dev; 741dbad75ddSKen Xue 742dbad75ddSKen Xue gpio_dev = devm_kzalloc(&pdev->dev, 743dbad75ddSKen Xue sizeof(struct amd_gpio), GFP_KERNEL); 744dbad75ddSKen Xue if (!gpio_dev) 745dbad75ddSKen Xue return -ENOMEM; 746dbad75ddSKen Xue 747dbad75ddSKen Xue spin_lock_init(&gpio_dev->lock); 748dbad75ddSKen Xue 749dbad75ddSKen Xue res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 750dbad75ddSKen Xue if (!res) { 751dbad75ddSKen Xue dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); 752dbad75ddSKen Xue return -EINVAL; 753dbad75ddSKen Xue } 754dbad75ddSKen Xue 755dbad75ddSKen Xue gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start, 756dbad75ddSKen Xue resource_size(res)); 757424a6c60SWei Yongjun if (!gpio_dev->base) 758424a6c60SWei Yongjun return -ENOMEM; 759dbad75ddSKen Xue 760dbad75ddSKen Xue irq_base = platform_get_irq(pdev, 0); 761dbad75ddSKen Xue if (irq_base < 0) { 762dbad75ddSKen Xue dev_err(&pdev->dev, "Failed to get gpio IRQ.\n"); 763dbad75ddSKen Xue return -EINVAL; 764dbad75ddSKen Xue } 765dbad75ddSKen Xue 766dbad75ddSKen Xue gpio_dev->pdev = pdev; 767dbad75ddSKen Xue gpio_dev->gc.direction_input = amd_gpio_direction_input; 768dbad75ddSKen Xue gpio_dev->gc.direction_output = amd_gpio_direction_output; 769dbad75ddSKen Xue gpio_dev->gc.get = amd_gpio_get_value; 770dbad75ddSKen Xue gpio_dev->gc.set = amd_gpio_set_value; 771dbad75ddSKen Xue gpio_dev->gc.set_debounce = amd_gpio_set_debounce; 772dbad75ddSKen Xue gpio_dev->gc.dbg_show = amd_gpio_dbg_show; 773dbad75ddSKen Xue 7743bfd4430SShah, Nehal-bakulchandra gpio_dev->gc.base = -1; 775dbad75ddSKen Xue gpio_dev->gc.label = pdev->name; 776dbad75ddSKen Xue gpio_dev->gc.owner = THIS_MODULE; 77758383c78SLinus Walleij gpio_dev->gc.parent = &pdev->dev; 7783bfd4430SShah, Nehal-bakulchandra gpio_dev->gc.ngpio = resource_size(res) / 4; 779dbad75ddSKen Xue #if defined(CONFIG_OF_GPIO) 780dbad75ddSKen Xue gpio_dev->gc.of_node = pdev->dev.of_node; 781dbad75ddSKen Xue #endif 782dbad75ddSKen Xue 7833bfd4430SShah, Nehal-bakulchandra gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64; 784dbad75ddSKen Xue gpio_dev->groups = kerncz_groups; 785dbad75ddSKen Xue gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); 786dbad75ddSKen Xue 787dbad75ddSKen Xue amd_pinctrl_desc.name = dev_name(&pdev->dev); 788251e22abSLaxman Dewangan gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, 789251e22abSLaxman Dewangan gpio_dev); 790323de9efSMasahiro Yamada if (IS_ERR(gpio_dev->pctrl)) { 791dbad75ddSKen Xue dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 792323de9efSMasahiro Yamada return PTR_ERR(gpio_dev->pctrl); 793dbad75ddSKen Xue } 794dbad75ddSKen Xue 79504d36723SLinus Walleij ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); 796dbad75ddSKen Xue if (ret) 797251e22abSLaxman Dewangan return ret; 798dbad75ddSKen Xue 799dbad75ddSKen Xue ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), 8003bfd4430SShah, Nehal-bakulchandra 0, 0, gpio_dev->gc.ngpio); 801dbad75ddSKen Xue if (ret) { 802dbad75ddSKen Xue dev_err(&pdev->dev, "Failed to add pin range\n"); 803dbad75ddSKen Xue goto out2; 804dbad75ddSKen Xue } 805dbad75ddSKen Xue 806dbad75ddSKen Xue ret = gpiochip_irqchip_add(&gpio_dev->gc, 807dbad75ddSKen Xue &amd_gpio_irqchip, 808dbad75ddSKen Xue 0, 809dbad75ddSKen Xue handle_simple_irq, 810dbad75ddSKen Xue IRQ_TYPE_NONE); 811dbad75ddSKen Xue if (ret) { 812dbad75ddSKen Xue dev_err(&pdev->dev, "could not add irqchip\n"); 813dbad75ddSKen Xue ret = -ENODEV; 814dbad75ddSKen Xue goto out2; 815dbad75ddSKen Xue } 816dbad75ddSKen Xue 817dbad75ddSKen Xue gpiochip_set_chained_irqchip(&gpio_dev->gc, 818dbad75ddSKen Xue &amd_gpio_irqchip, 819dbad75ddSKen Xue irq_base, 820dbad75ddSKen Xue amd_gpio_irq_handler); 821dbad75ddSKen Xue platform_set_drvdata(pdev, gpio_dev); 822dbad75ddSKen Xue 823dbad75ddSKen Xue dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); 824dbad75ddSKen Xue return ret; 825dbad75ddSKen Xue 826dbad75ddSKen Xue out2: 827dbad75ddSKen Xue gpiochip_remove(&gpio_dev->gc); 828dbad75ddSKen Xue 829dbad75ddSKen Xue return ret; 830dbad75ddSKen Xue } 831dbad75ddSKen Xue 832dbad75ddSKen Xue static int amd_gpio_remove(struct platform_device *pdev) 833dbad75ddSKen Xue { 834dbad75ddSKen Xue struct amd_gpio *gpio_dev; 835dbad75ddSKen Xue 836dbad75ddSKen Xue gpio_dev = platform_get_drvdata(pdev); 837dbad75ddSKen Xue 838dbad75ddSKen Xue gpiochip_remove(&gpio_dev->gc); 8393bfd4430SShah, Nehal-bakulchandra pinctrl_unregister(gpio_dev->pctrl); 840dbad75ddSKen Xue 841dbad75ddSKen Xue return 0; 842dbad75ddSKen Xue } 843dbad75ddSKen Xue 844dbad75ddSKen Xue static const struct acpi_device_id amd_gpio_acpi_match[] = { 845dbad75ddSKen Xue { "AMD0030", 0 }, 84642a44402SWang Hongcheng { "AMDI0030", 0}, 847dbad75ddSKen Xue { }, 848dbad75ddSKen Xue }; 849dbad75ddSKen Xue MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); 850dbad75ddSKen Xue 851dbad75ddSKen Xue static struct platform_driver amd_gpio_driver = { 852dbad75ddSKen Xue .driver = { 853dbad75ddSKen Xue .name = "amd_gpio", 854dbad75ddSKen Xue .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), 855dbad75ddSKen Xue }, 856dbad75ddSKen Xue .probe = amd_gpio_probe, 857dbad75ddSKen Xue .remove = amd_gpio_remove, 858dbad75ddSKen Xue }; 859dbad75ddSKen Xue 860dbad75ddSKen Xue module_platform_driver(amd_gpio_driver); 861dbad75ddSKen Xue 862dbad75ddSKen Xue MODULE_LICENSE("GPL v2"); 863dbad75ddSKen Xue MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); 864dbad75ddSKen Xue MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); 865