1dbad75ddSKen Xue /* 2dbad75ddSKen Xue * GPIO driver for AMD 3dbad75ddSKen Xue * 4dbad75ddSKen Xue * Copyright (c) 2014,2015 AMD Corporation. 5dbad75ddSKen Xue * Authors: Ken Xue <Ken.Xue@amd.com> 6dbad75ddSKen Xue * Wu, Jeff <Jeff.Wu@amd.com> 7dbad75ddSKen Xue * 8dbad75ddSKen Xue * This program is free software; you can redistribute it and/or modify it 9dbad75ddSKen Xue * under the terms and conditions of the GNU General Public License, 10dbad75ddSKen Xue * version 2, as published by the Free Software Foundation. 11dbad75ddSKen Xue */ 12dbad75ddSKen Xue 13dbad75ddSKen Xue #include <linux/err.h> 14dbad75ddSKen Xue #include <linux/bug.h> 15dbad75ddSKen Xue #include <linux/kernel.h> 16dbad75ddSKen Xue #include <linux/module.h> 17dbad75ddSKen Xue #include <linux/spinlock.h> 18dbad75ddSKen Xue #include <linux/compiler.h> 19dbad75ddSKen Xue #include <linux/types.h> 20dbad75ddSKen Xue #include <linux/errno.h> 21dbad75ddSKen Xue #include <linux/log2.h> 22dbad75ddSKen Xue #include <linux/io.h> 23dbad75ddSKen Xue #include <linux/gpio.h> 24dbad75ddSKen Xue #include <linux/slab.h> 25dbad75ddSKen Xue #include <linux/platform_device.h> 26dbad75ddSKen Xue #include <linux/mutex.h> 27dbad75ddSKen Xue #include <linux/acpi.h> 28dbad75ddSKen Xue #include <linux/seq_file.h> 29dbad75ddSKen Xue #include <linux/interrupt.h> 30dbad75ddSKen Xue #include <linux/list.h> 31dbad75ddSKen Xue #include <linux/bitops.h> 32dbad75ddSKen Xue #include <linux/pinctrl/pinconf.h> 33dbad75ddSKen Xue #include <linux/pinctrl/pinconf-generic.h> 34dbad75ddSKen Xue 35dbad75ddSKen Xue #include "pinctrl-utils.h" 36dbad75ddSKen Xue #include "pinctrl-amd.h" 37dbad75ddSKen Xue 38dbad75ddSKen Xue static inline struct amd_gpio *to_amd_gpio(struct gpio_chip *gc) 39dbad75ddSKen Xue { 40dbad75ddSKen Xue return container_of(gc, struct amd_gpio, gc); 41dbad75ddSKen Xue } 42dbad75ddSKen Xue 43dbad75ddSKen Xue static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 44dbad75ddSKen Xue { 45dbad75ddSKen Xue unsigned long flags; 46dbad75ddSKen Xue u32 pin_reg; 47dbad75ddSKen Xue struct amd_gpio *gpio_dev = to_amd_gpio(gc); 48dbad75ddSKen Xue 49dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 50dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 51dbad75ddSKen Xue /* 52dbad75ddSKen Xue * Suppose BIOS or Bootloader sets specific debounce for the 53dbad75ddSKen Xue * GPIO. if not, set debounce to be 2.75ms and remove glitch. 54dbad75ddSKen Xue */ 55dbad75ddSKen Xue if ((pin_reg & DB_TMR_OUT_MASK) == 0) { 56dbad75ddSKen Xue pin_reg |= 0xf; 57dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 58dbad75ddSKen Xue pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 59dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 60dbad75ddSKen Xue } 61dbad75ddSKen Xue 62dbad75ddSKen Xue pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); 63dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4); 64dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 65dbad75ddSKen Xue 66dbad75ddSKen Xue return 0; 67dbad75ddSKen Xue } 68dbad75ddSKen Xue 69dbad75ddSKen Xue static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 70dbad75ddSKen Xue int value) 71dbad75ddSKen Xue { 72dbad75ddSKen Xue u32 pin_reg; 73dbad75ddSKen Xue unsigned long flags; 74dbad75ddSKen Xue struct amd_gpio *gpio_dev = to_amd_gpio(gc); 75dbad75ddSKen Xue 76dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 77dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 78dbad75ddSKen Xue pin_reg |= BIT(OUTPUT_ENABLE_OFF); 79dbad75ddSKen Xue if (value) 80dbad75ddSKen Xue pin_reg |= BIT(OUTPUT_VALUE_OFF); 81dbad75ddSKen Xue else 82dbad75ddSKen Xue pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 83dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4); 84dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 85dbad75ddSKen Xue 86dbad75ddSKen Xue return 0; 87dbad75ddSKen Xue } 88dbad75ddSKen Xue 89dbad75ddSKen Xue static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) 90dbad75ddSKen Xue { 91dbad75ddSKen Xue u32 pin_reg; 92dbad75ddSKen Xue unsigned long flags; 93dbad75ddSKen Xue struct amd_gpio *gpio_dev = to_amd_gpio(gc); 94dbad75ddSKen Xue 95dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 96dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 97dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 98dbad75ddSKen Xue 99dbad75ddSKen Xue return !!(pin_reg & BIT(PIN_STS_OFF)); 100dbad75ddSKen Xue } 101dbad75ddSKen Xue 102dbad75ddSKen Xue static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) 103dbad75ddSKen Xue { 104dbad75ddSKen Xue u32 pin_reg; 105dbad75ddSKen Xue unsigned long flags; 106dbad75ddSKen Xue struct amd_gpio *gpio_dev = to_amd_gpio(gc); 107dbad75ddSKen Xue 108dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 109dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 110dbad75ddSKen Xue if (value) 111dbad75ddSKen Xue pin_reg |= BIT(OUTPUT_VALUE_OFF); 112dbad75ddSKen Xue else 113dbad75ddSKen Xue pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 114dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4); 115dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 116dbad75ddSKen Xue } 117dbad75ddSKen Xue 118dbad75ddSKen Xue static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, 119dbad75ddSKen Xue unsigned debounce) 120dbad75ddSKen Xue { 121dbad75ddSKen Xue u32 time; 12225a853d0SKen Xue u32 pin_reg; 12325a853d0SKen Xue int ret = 0; 124dbad75ddSKen Xue unsigned long flags; 125dbad75ddSKen Xue struct amd_gpio *gpio_dev = to_amd_gpio(gc); 126dbad75ddSKen Xue 127dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 128dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 129dbad75ddSKen Xue 130dbad75ddSKen Xue if (debounce) { 131dbad75ddSKen Xue pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 132dbad75ddSKen Xue pin_reg &= ~DB_TMR_OUT_MASK; 133dbad75ddSKen Xue /* 134dbad75ddSKen Xue Debounce Debounce Timer Max 135dbad75ddSKen Xue TmrLarge TmrOutUnit Unit Debounce 136dbad75ddSKen Xue Time 137dbad75ddSKen Xue 0 0 61 usec (2 RtcClk) 976 usec 138dbad75ddSKen Xue 0 1 244 usec (8 RtcClk) 3.9 msec 139dbad75ddSKen Xue 1 0 15.6 msec (512 RtcClk) 250 msec 140dbad75ddSKen Xue 1 1 62.5 msec (2048 RtcClk) 1 sec 141dbad75ddSKen Xue */ 142dbad75ddSKen Xue 143dbad75ddSKen Xue if (debounce < 61) { 144dbad75ddSKen Xue pin_reg |= 1; 145dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 146dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 147dbad75ddSKen Xue } else if (debounce < 976) { 148dbad75ddSKen Xue time = debounce / 61; 149dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK; 150dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 151dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 152dbad75ddSKen Xue } else if (debounce < 3900) { 153dbad75ddSKen Xue time = debounce / 244; 154dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK; 155dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 156dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 157dbad75ddSKen Xue } else if (debounce < 250000) { 158dbad75ddSKen Xue time = debounce / 15600; 159dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK; 160dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 161dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_LARGE_OFF); 162dbad75ddSKen Xue } else if (debounce < 1000000) { 163dbad75ddSKen Xue time = debounce / 62500; 164dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK; 165dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 166dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_LARGE_OFF); 167dbad75ddSKen Xue } else { 168dbad75ddSKen Xue pin_reg &= ~DB_CNTRl_MASK; 16925a853d0SKen Xue ret = -EINVAL; 170dbad75ddSKen Xue } 171dbad75ddSKen Xue } else { 172dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 173dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 174dbad75ddSKen Xue pin_reg &= ~DB_TMR_OUT_MASK; 175dbad75ddSKen Xue pin_reg &= ~DB_CNTRl_MASK; 176dbad75ddSKen Xue } 177dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4); 178dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 179dbad75ddSKen Xue 18025a853d0SKen Xue return ret; 181dbad75ddSKen Xue } 182dbad75ddSKen Xue 183dbad75ddSKen Xue #ifdef CONFIG_DEBUG_FS 184dbad75ddSKen Xue static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) 185dbad75ddSKen Xue { 186dbad75ddSKen Xue u32 pin_reg; 187dbad75ddSKen Xue unsigned long flags; 188dbad75ddSKen Xue unsigned int bank, i, pin_num; 189dbad75ddSKen Xue struct amd_gpio *gpio_dev = to_amd_gpio(gc); 190dbad75ddSKen Xue 191dbad75ddSKen Xue char *level_trig; 192dbad75ddSKen Xue char *active_level; 193dbad75ddSKen Xue char *interrupt_enable; 194dbad75ddSKen Xue char *interrupt_mask; 195dbad75ddSKen Xue char *wake_cntrl0; 196dbad75ddSKen Xue char *wake_cntrl1; 197dbad75ddSKen Xue char *wake_cntrl2; 198dbad75ddSKen Xue char *pin_sts; 199dbad75ddSKen Xue char *pull_up_sel; 200dbad75ddSKen Xue char *pull_up_enable; 201dbad75ddSKen Xue char *pull_down_enable; 202dbad75ddSKen Xue char *output_value; 203dbad75ddSKen Xue char *output_enable; 204dbad75ddSKen Xue 205dbad75ddSKen Xue for (bank = 0; bank < AMD_GPIO_TOTAL_BANKS; bank++) { 206dbad75ddSKen Xue seq_printf(s, "GPIO bank%d\t", bank); 207dbad75ddSKen Xue 208dbad75ddSKen Xue switch (bank) { 209dbad75ddSKen Xue case 0: 210dbad75ddSKen Xue i = 0; 211dbad75ddSKen Xue pin_num = AMD_GPIO_PINS_BANK0; 212dbad75ddSKen Xue break; 213dbad75ddSKen Xue case 1: 214dbad75ddSKen Xue i = 64; 215dbad75ddSKen Xue pin_num = AMD_GPIO_PINS_BANK1 + i; 216dbad75ddSKen Xue break; 217dbad75ddSKen Xue case 2: 218dbad75ddSKen Xue i = 128; 219dbad75ddSKen Xue pin_num = AMD_GPIO_PINS_BANK2 + i; 220dbad75ddSKen Xue break; 221dbad75ddSKen Xue } 222dbad75ddSKen Xue 223dbad75ddSKen Xue for (; i < pin_num; i++) { 224dbad75ddSKen Xue seq_printf(s, "pin%d\t", i); 225dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 226dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + i * 4); 227dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 228dbad75ddSKen Xue 229dbad75ddSKen Xue if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { 230dbad75ddSKen Xue interrupt_enable = "interrupt is enabled|"; 231dbad75ddSKen Xue 232dbad75ddSKen Xue if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) 233dbad75ddSKen Xue && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1))) 234dbad75ddSKen Xue active_level = "Active low|"; 235dbad75ddSKen Xue else if (pin_reg & BIT(ACTIVE_LEVEL_OFF) 236dbad75ddSKen Xue && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1))) 237dbad75ddSKen Xue active_level = "Active high|"; 238dbad75ddSKen Xue else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) 239dbad75ddSKen Xue && pin_reg & BIT(ACTIVE_LEVEL_OFF+1)) 240dbad75ddSKen Xue active_level = "Active on both|"; 241dbad75ddSKen Xue else 242dbad75ddSKen Xue active_level = "Unknow Active level|"; 243dbad75ddSKen Xue 244dbad75ddSKen Xue if (pin_reg & BIT(LEVEL_TRIG_OFF)) 245dbad75ddSKen Xue level_trig = "Level trigger|"; 246dbad75ddSKen Xue else 247dbad75ddSKen Xue level_trig = "Edge trigger|"; 248dbad75ddSKen Xue 249dbad75ddSKen Xue } else { 250dbad75ddSKen Xue interrupt_enable = 251dbad75ddSKen Xue "interrupt is disabled|"; 252dbad75ddSKen Xue active_level = " "; 253dbad75ddSKen Xue level_trig = " "; 254dbad75ddSKen Xue } 255dbad75ddSKen Xue 256dbad75ddSKen Xue if (pin_reg & BIT(INTERRUPT_MASK_OFF)) 257dbad75ddSKen Xue interrupt_mask = 258dbad75ddSKen Xue "interrupt is unmasked|"; 259dbad75ddSKen Xue else 260dbad75ddSKen Xue interrupt_mask = 261dbad75ddSKen Xue "interrupt is masked|"; 262dbad75ddSKen Xue 263dbad75ddSKen Xue if (pin_reg & BIT(WAKE_CNTRL_OFF)) 264dbad75ddSKen Xue wake_cntrl0 = "enable wakeup in S0i3 state|"; 265dbad75ddSKen Xue else 266dbad75ddSKen Xue wake_cntrl0 = "disable wakeup in S0i3 state|"; 267dbad75ddSKen Xue 268dbad75ddSKen Xue if (pin_reg & BIT(WAKE_CNTRL_OFF)) 269dbad75ddSKen Xue wake_cntrl1 = "enable wakeup in S3 state|"; 270dbad75ddSKen Xue else 271dbad75ddSKen Xue wake_cntrl1 = "disable wakeup in S3 state|"; 272dbad75ddSKen Xue 273dbad75ddSKen Xue if (pin_reg & BIT(WAKE_CNTRL_OFF)) 274dbad75ddSKen Xue wake_cntrl2 = "enable wakeup in S4/S5 state|"; 275dbad75ddSKen Xue else 276dbad75ddSKen Xue wake_cntrl2 = "disable wakeup in S4/S5 state|"; 277dbad75ddSKen Xue 278dbad75ddSKen Xue if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { 279dbad75ddSKen Xue pull_up_enable = "pull-up is enabled|"; 280dbad75ddSKen Xue if (pin_reg & BIT(PULL_UP_SEL_OFF)) 281dbad75ddSKen Xue pull_up_sel = "8k pull-up|"; 282dbad75ddSKen Xue else 283dbad75ddSKen Xue pull_up_sel = "4k pull-up|"; 284dbad75ddSKen Xue } else { 285dbad75ddSKen Xue pull_up_enable = "pull-up is disabled|"; 286dbad75ddSKen Xue pull_up_sel = " "; 287dbad75ddSKen Xue } 288dbad75ddSKen Xue 289dbad75ddSKen Xue if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) 290dbad75ddSKen Xue pull_down_enable = "pull-down is enabled|"; 291dbad75ddSKen Xue else 292dbad75ddSKen Xue pull_down_enable = "Pull-down is disabled|"; 293dbad75ddSKen Xue 294dbad75ddSKen Xue if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { 295dbad75ddSKen Xue pin_sts = " "; 296dbad75ddSKen Xue output_enable = "output is enabled|"; 297dbad75ddSKen Xue if (pin_reg & BIT(OUTPUT_VALUE_OFF)) 298dbad75ddSKen Xue output_value = "output is high|"; 299dbad75ddSKen Xue else 300dbad75ddSKen Xue output_value = "output is low|"; 301dbad75ddSKen Xue } else { 302dbad75ddSKen Xue output_enable = "output is disabled|"; 303dbad75ddSKen Xue output_value = " "; 304dbad75ddSKen Xue 305dbad75ddSKen Xue if (pin_reg & BIT(PIN_STS_OFF)) 306dbad75ddSKen Xue pin_sts = "input is high|"; 307dbad75ddSKen Xue else 308dbad75ddSKen Xue pin_sts = "input is low|"; 309dbad75ddSKen Xue } 310dbad75ddSKen Xue 311dbad75ddSKen Xue seq_printf(s, "%s %s %s %s %s %s\n" 312dbad75ddSKen Xue " %s %s %s %s %s %s %s 0x%x\n", 313dbad75ddSKen Xue level_trig, active_level, interrupt_enable, 314dbad75ddSKen Xue interrupt_mask, wake_cntrl0, wake_cntrl1, 315dbad75ddSKen Xue wake_cntrl2, pin_sts, pull_up_sel, 316dbad75ddSKen Xue pull_up_enable, pull_down_enable, 317dbad75ddSKen Xue output_value, output_enable, pin_reg); 318dbad75ddSKen Xue } 319dbad75ddSKen Xue } 320dbad75ddSKen Xue } 321dbad75ddSKen Xue #else 322dbad75ddSKen Xue #define amd_gpio_dbg_show NULL 323dbad75ddSKen Xue #endif 324dbad75ddSKen Xue 325dbad75ddSKen Xue static void amd_gpio_irq_enable(struct irq_data *d) 326dbad75ddSKen Xue { 327dbad75ddSKen Xue u32 pin_reg; 328dbad75ddSKen Xue unsigned long flags; 329dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 330dbad75ddSKen Xue struct amd_gpio *gpio_dev = to_amd_gpio(gc); 331dbad75ddSKen Xue 332dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 333dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 334dbad75ddSKen Xue /* 335dbad75ddSKen Xue Suppose BIOS or Bootloader sets specific debounce for the 336dbad75ddSKen Xue GPIO. if not, set debounce to be 2.75ms. 337dbad75ddSKen Xue */ 338dbad75ddSKen Xue if ((pin_reg & DB_TMR_OUT_MASK) == 0) { 339dbad75ddSKen Xue pin_reg |= 0xf; 340dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 341dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 342dbad75ddSKen Xue } 343dbad75ddSKen Xue pin_reg |= BIT(INTERRUPT_ENABLE_OFF); 344dbad75ddSKen Xue pin_reg |= BIT(INTERRUPT_MASK_OFF); 345dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 346dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 347dbad75ddSKen Xue } 348dbad75ddSKen Xue 349dbad75ddSKen Xue static void amd_gpio_irq_disable(struct irq_data *d) 350dbad75ddSKen Xue { 351dbad75ddSKen Xue u32 pin_reg; 352dbad75ddSKen Xue unsigned long flags; 353dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 354dbad75ddSKen Xue struct amd_gpio *gpio_dev = to_amd_gpio(gc); 355dbad75ddSKen Xue 356dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 357dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 358dbad75ddSKen Xue pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); 359dbad75ddSKen Xue pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 360dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 361dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 362dbad75ddSKen Xue } 363dbad75ddSKen Xue 364dbad75ddSKen Xue static void amd_gpio_irq_mask(struct irq_data *d) 365dbad75ddSKen Xue { 366dbad75ddSKen Xue u32 pin_reg; 367dbad75ddSKen Xue unsigned long flags; 368dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 369dbad75ddSKen Xue struct amd_gpio *gpio_dev = to_amd_gpio(gc); 370dbad75ddSKen Xue 371dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 372dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 373dbad75ddSKen Xue pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 374dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 375dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 376dbad75ddSKen Xue } 377dbad75ddSKen Xue 378dbad75ddSKen Xue static void amd_gpio_irq_unmask(struct irq_data *d) 379dbad75ddSKen Xue { 380dbad75ddSKen Xue u32 pin_reg; 381dbad75ddSKen Xue unsigned long flags; 382dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 383dbad75ddSKen Xue struct amd_gpio *gpio_dev = to_amd_gpio(gc); 384dbad75ddSKen Xue 385dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 386dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 387dbad75ddSKen Xue pin_reg |= BIT(INTERRUPT_MASK_OFF); 388dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 389dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 390dbad75ddSKen Xue } 391dbad75ddSKen Xue 392dbad75ddSKen Xue static void amd_gpio_irq_eoi(struct irq_data *d) 393dbad75ddSKen Xue { 394dbad75ddSKen Xue u32 reg; 395dbad75ddSKen Xue unsigned long flags; 396dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 397dbad75ddSKen Xue struct amd_gpio *gpio_dev = to_amd_gpio(gc); 398dbad75ddSKen Xue 399dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 400dbad75ddSKen Xue reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 401dbad75ddSKen Xue reg |= EOI_MASK; 402dbad75ddSKen Xue writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 403dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 404dbad75ddSKen Xue } 405dbad75ddSKen Xue 406dbad75ddSKen Xue static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) 407dbad75ddSKen Xue { 408dbad75ddSKen Xue int ret = 0; 409dbad75ddSKen Xue u32 pin_reg; 410dbad75ddSKen Xue unsigned long flags; 411dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 412dbad75ddSKen Xue struct amd_gpio *gpio_dev = to_amd_gpio(gc); 413dbad75ddSKen Xue 414dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 415dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 416dbad75ddSKen Xue 417dbad75ddSKen Xue switch (type & IRQ_TYPE_SENSE_MASK) { 418dbad75ddSKen Xue case IRQ_TYPE_EDGE_RISING: 419dbad75ddSKen Xue pin_reg &= ~BIT(LEVEL_TRIG_OFF); 420dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 421dbad75ddSKen Xue pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 422dbad75ddSKen Xue pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 423dbad75ddSKen Xue __irq_set_handler_locked(d->irq, handle_edge_irq); 424dbad75ddSKen Xue break; 425dbad75ddSKen Xue 426dbad75ddSKen Xue case IRQ_TYPE_EDGE_FALLING: 427dbad75ddSKen Xue pin_reg &= ~BIT(LEVEL_TRIG_OFF); 428dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 429dbad75ddSKen Xue pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 430dbad75ddSKen Xue pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 431dbad75ddSKen Xue __irq_set_handler_locked(d->irq, handle_edge_irq); 432dbad75ddSKen Xue break; 433dbad75ddSKen Xue 434dbad75ddSKen Xue case IRQ_TYPE_EDGE_BOTH: 435dbad75ddSKen Xue pin_reg &= ~BIT(LEVEL_TRIG_OFF); 436dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 437dbad75ddSKen Xue pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; 438dbad75ddSKen Xue pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 439dbad75ddSKen Xue __irq_set_handler_locked(d->irq, handle_edge_irq); 440dbad75ddSKen Xue break; 441dbad75ddSKen Xue 442dbad75ddSKen Xue case IRQ_TYPE_LEVEL_HIGH: 443dbad75ddSKen Xue pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 444dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 445dbad75ddSKen Xue pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 446dbad75ddSKen Xue pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 447dbad75ddSKen Xue pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF; 448dbad75ddSKen Xue __irq_set_handler_locked(d->irq, handle_level_irq); 449dbad75ddSKen Xue break; 450dbad75ddSKen Xue 451dbad75ddSKen Xue case IRQ_TYPE_LEVEL_LOW: 452dbad75ddSKen Xue pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 453dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 454dbad75ddSKen Xue pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 455dbad75ddSKen Xue pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 456dbad75ddSKen Xue pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF; 457dbad75ddSKen Xue __irq_set_handler_locked(d->irq, handle_level_irq); 458dbad75ddSKen Xue break; 459dbad75ddSKen Xue 460dbad75ddSKen Xue case IRQ_TYPE_NONE: 461dbad75ddSKen Xue break; 462dbad75ddSKen Xue 463dbad75ddSKen Xue default: 464dbad75ddSKen Xue dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); 465dbad75ddSKen Xue ret = -EINVAL; 466dbad75ddSKen Xue } 467dbad75ddSKen Xue 468dbad75ddSKen Xue pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; 469dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 470dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 471dbad75ddSKen Xue 472dbad75ddSKen Xue return ret; 473dbad75ddSKen Xue } 474dbad75ddSKen Xue 475dbad75ddSKen Xue static void amd_irq_ack(struct irq_data *d) 476dbad75ddSKen Xue { 477dbad75ddSKen Xue /* 478dbad75ddSKen Xue * based on HW design,there is no need to ack HW 479dbad75ddSKen Xue * before handle current irq. But this routine is 480dbad75ddSKen Xue * necessary for handle_edge_irq 481dbad75ddSKen Xue */ 482dbad75ddSKen Xue } 483dbad75ddSKen Xue 484dbad75ddSKen Xue static struct irq_chip amd_gpio_irqchip = { 485dbad75ddSKen Xue .name = "amd_gpio", 486dbad75ddSKen Xue .irq_ack = amd_irq_ack, 487dbad75ddSKen Xue .irq_enable = amd_gpio_irq_enable, 488dbad75ddSKen Xue .irq_disable = amd_gpio_irq_disable, 489dbad75ddSKen Xue .irq_mask = amd_gpio_irq_mask, 490dbad75ddSKen Xue .irq_unmask = amd_gpio_irq_unmask, 491dbad75ddSKen Xue .irq_eoi = amd_gpio_irq_eoi, 492dbad75ddSKen Xue .irq_set_type = amd_gpio_irq_set_type, 493dbad75ddSKen Xue }; 494dbad75ddSKen Xue 495dbad75ddSKen Xue static void amd_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) 496dbad75ddSKen Xue { 497dbad75ddSKen Xue u32 i; 498dbad75ddSKen Xue u32 off; 499dbad75ddSKen Xue u32 reg; 500dbad75ddSKen Xue u32 pin_reg; 501dbad75ddSKen Xue u64 reg64; 502dbad75ddSKen Xue int handled = 0; 503dbad75ddSKen Xue unsigned long flags; 504dbad75ddSKen Xue struct irq_chip *chip = irq_get_chip(irq); 505dbad75ddSKen Xue struct gpio_chip *gc = irq_desc_get_handler_data(desc); 506dbad75ddSKen Xue struct amd_gpio *gpio_dev = to_amd_gpio(gc); 507dbad75ddSKen Xue 508dbad75ddSKen Xue chained_irq_enter(chip, desc); 509dbad75ddSKen Xue /*enable GPIO interrupt again*/ 510dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 511dbad75ddSKen Xue reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); 512dbad75ddSKen Xue reg64 = reg; 513dbad75ddSKen Xue reg64 = reg64 << 32; 514dbad75ddSKen Xue 515dbad75ddSKen Xue reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG0); 516dbad75ddSKen Xue reg64 |= reg; 517dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 518dbad75ddSKen Xue 519dbad75ddSKen Xue /* 520dbad75ddSKen Xue * first 46 bits indicates interrupt status. 521dbad75ddSKen Xue * one bit represents four interrupt sources. 522dbad75ddSKen Xue */ 523dbad75ddSKen Xue for (off = 0; off < 46 ; off++) { 524dbad75ddSKen Xue if (reg64 & BIT(off)) { 525dbad75ddSKen Xue for (i = 0; i < 4; i++) { 526dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + 527dbad75ddSKen Xue (off * 4 + i) * 4); 528dbad75ddSKen Xue if ((pin_reg & BIT(INTERRUPT_STS_OFF)) || 529dbad75ddSKen Xue (pin_reg & BIT(WAKE_STS_OFF))) { 530dbad75ddSKen Xue irq = irq_find_mapping(gc->irqdomain, 531dbad75ddSKen Xue off * 4 + i); 532dbad75ddSKen Xue generic_handle_irq(irq); 533dbad75ddSKen Xue writel(pin_reg, 534dbad75ddSKen Xue gpio_dev->base 535dbad75ddSKen Xue + (off * 4 + i) * 4); 536dbad75ddSKen Xue handled++; 537dbad75ddSKen Xue } 538dbad75ddSKen Xue } 539dbad75ddSKen Xue } 540dbad75ddSKen Xue } 541dbad75ddSKen Xue 542dbad75ddSKen Xue if (handled == 0) 543dbad75ddSKen Xue handle_bad_irq(irq, desc); 544dbad75ddSKen Xue 545dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 546dbad75ddSKen Xue reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 547dbad75ddSKen Xue reg |= EOI_MASK; 548dbad75ddSKen Xue writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 549dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 550dbad75ddSKen Xue 551dbad75ddSKen Xue chained_irq_exit(chip, desc); 552dbad75ddSKen Xue } 553dbad75ddSKen Xue 554dbad75ddSKen Xue static int amd_get_groups_count(struct pinctrl_dev *pctldev) 555dbad75ddSKen Xue { 556dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 557dbad75ddSKen Xue 558dbad75ddSKen Xue return gpio_dev->ngroups; 559dbad75ddSKen Xue } 560dbad75ddSKen Xue 561dbad75ddSKen Xue static const char *amd_get_group_name(struct pinctrl_dev *pctldev, 562dbad75ddSKen Xue unsigned group) 563dbad75ddSKen Xue { 564dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 565dbad75ddSKen Xue 566dbad75ddSKen Xue return gpio_dev->groups[group].name; 567dbad75ddSKen Xue } 568dbad75ddSKen Xue 569dbad75ddSKen Xue static int amd_get_group_pins(struct pinctrl_dev *pctldev, 570dbad75ddSKen Xue unsigned group, 571dbad75ddSKen Xue const unsigned **pins, 572dbad75ddSKen Xue unsigned *num_pins) 573dbad75ddSKen Xue { 574dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 575dbad75ddSKen Xue 576dbad75ddSKen Xue *pins = gpio_dev->groups[group].pins; 577dbad75ddSKen Xue *num_pins = gpio_dev->groups[group].npins; 578dbad75ddSKen Xue return 0; 579dbad75ddSKen Xue } 580dbad75ddSKen Xue 581dbad75ddSKen Xue static const struct pinctrl_ops amd_pinctrl_ops = { 582dbad75ddSKen Xue .get_groups_count = amd_get_groups_count, 583dbad75ddSKen Xue .get_group_name = amd_get_group_name, 584dbad75ddSKen Xue .get_group_pins = amd_get_group_pins, 585dbad75ddSKen Xue #ifdef CONFIG_OF 586dbad75ddSKen Xue .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 587dbad75ddSKen Xue .dt_free_map = pinctrl_utils_dt_free_map, 588dbad75ddSKen Xue #endif 589dbad75ddSKen Xue }; 590dbad75ddSKen Xue 591dbad75ddSKen Xue static int amd_pinconf_get(struct pinctrl_dev *pctldev, 592dbad75ddSKen Xue unsigned int pin, 593dbad75ddSKen Xue unsigned long *config) 594dbad75ddSKen Xue { 595dbad75ddSKen Xue u32 pin_reg; 596dbad75ddSKen Xue unsigned arg; 597dbad75ddSKen Xue unsigned long flags; 598dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 599dbad75ddSKen Xue enum pin_config_param param = pinconf_to_config_param(*config); 600dbad75ddSKen Xue 601dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 602dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + pin*4); 603dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 604dbad75ddSKen Xue switch (param) { 605dbad75ddSKen Xue case PIN_CONFIG_INPUT_DEBOUNCE: 606dbad75ddSKen Xue arg = pin_reg & DB_TMR_OUT_MASK; 607dbad75ddSKen Xue break; 608dbad75ddSKen Xue 609dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_DOWN: 610dbad75ddSKen Xue arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); 611dbad75ddSKen Xue break; 612dbad75ddSKen Xue 613dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_UP: 614dbad75ddSKen Xue arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); 615dbad75ddSKen Xue break; 616dbad75ddSKen Xue 617dbad75ddSKen Xue case PIN_CONFIG_DRIVE_STRENGTH: 618dbad75ddSKen Xue arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; 619dbad75ddSKen Xue break; 620dbad75ddSKen Xue 621dbad75ddSKen Xue default: 622dbad75ddSKen Xue dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n", 623dbad75ddSKen Xue param); 624dbad75ddSKen Xue return -ENOTSUPP; 625dbad75ddSKen Xue } 626dbad75ddSKen Xue 627dbad75ddSKen Xue *config = pinconf_to_config_packed(param, arg); 628dbad75ddSKen Xue 629dbad75ddSKen Xue return 0; 630dbad75ddSKen Xue } 631dbad75ddSKen Xue 632dbad75ddSKen Xue static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 633dbad75ddSKen Xue unsigned long *configs, unsigned num_configs) 634dbad75ddSKen Xue { 635dbad75ddSKen Xue int i; 636dbad75ddSKen Xue u32 arg; 63725a853d0SKen Xue int ret = 0; 63825a853d0SKen Xue u32 pin_reg; 639dbad75ddSKen Xue unsigned long flags; 640dbad75ddSKen Xue enum pin_config_param param; 641dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 642dbad75ddSKen Xue 643dbad75ddSKen Xue spin_lock_irqsave(&gpio_dev->lock, flags); 644dbad75ddSKen Xue for (i = 0; i < num_configs; i++) { 645dbad75ddSKen Xue param = pinconf_to_config_param(configs[i]); 646dbad75ddSKen Xue arg = pinconf_to_config_argument(configs[i]); 647dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + pin*4); 648dbad75ddSKen Xue 649dbad75ddSKen Xue switch (param) { 650dbad75ddSKen Xue case PIN_CONFIG_INPUT_DEBOUNCE: 651dbad75ddSKen Xue pin_reg &= ~DB_TMR_OUT_MASK; 652dbad75ddSKen Xue pin_reg |= arg & DB_TMR_OUT_MASK; 653dbad75ddSKen Xue break; 654dbad75ddSKen Xue 655dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_DOWN: 656dbad75ddSKen Xue pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); 657dbad75ddSKen Xue pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; 658dbad75ddSKen Xue break; 659dbad75ddSKen Xue 660dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_UP: 661dbad75ddSKen Xue pin_reg &= ~BIT(PULL_UP_SEL_OFF); 662dbad75ddSKen Xue pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; 663dbad75ddSKen Xue pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); 664dbad75ddSKen Xue pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; 665dbad75ddSKen Xue break; 666dbad75ddSKen Xue 667dbad75ddSKen Xue case PIN_CONFIG_DRIVE_STRENGTH: 668dbad75ddSKen Xue pin_reg &= ~(DRV_STRENGTH_SEL_MASK 669dbad75ddSKen Xue << DRV_STRENGTH_SEL_OFF); 670dbad75ddSKen Xue pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) 671dbad75ddSKen Xue << DRV_STRENGTH_SEL_OFF; 672dbad75ddSKen Xue break; 673dbad75ddSKen Xue 674dbad75ddSKen Xue default: 675dbad75ddSKen Xue dev_err(&gpio_dev->pdev->dev, 676dbad75ddSKen Xue "Invalid config param %04x\n", param); 67725a853d0SKen Xue ret = -ENOTSUPP; 678dbad75ddSKen Xue } 679dbad75ddSKen Xue 680dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + pin*4); 681dbad75ddSKen Xue } 682dbad75ddSKen Xue spin_unlock_irqrestore(&gpio_dev->lock, flags); 683dbad75ddSKen Xue 68425a853d0SKen Xue return ret; 685dbad75ddSKen Xue } 686dbad75ddSKen Xue 687dbad75ddSKen Xue static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, 688dbad75ddSKen Xue unsigned int group, 689dbad75ddSKen Xue unsigned long *config) 690dbad75ddSKen Xue { 691dbad75ddSKen Xue const unsigned *pins; 692dbad75ddSKen Xue unsigned npins; 693dbad75ddSKen Xue int ret; 694dbad75ddSKen Xue 695dbad75ddSKen Xue ret = amd_get_group_pins(pctldev, group, &pins, &npins); 696dbad75ddSKen Xue if (ret) 697dbad75ddSKen Xue return ret; 698dbad75ddSKen Xue 699dbad75ddSKen Xue if (amd_pinconf_get(pctldev, pins[0], config)) 700dbad75ddSKen Xue return -ENOTSUPP; 701dbad75ddSKen Xue 702dbad75ddSKen Xue return 0; 703dbad75ddSKen Xue } 704dbad75ddSKen Xue 705dbad75ddSKen Xue static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, 706dbad75ddSKen Xue unsigned group, unsigned long *configs, 707dbad75ddSKen Xue unsigned num_configs) 708dbad75ddSKen Xue { 709dbad75ddSKen Xue const unsigned *pins; 710dbad75ddSKen Xue unsigned npins; 711dbad75ddSKen Xue int i, ret; 712dbad75ddSKen Xue 713dbad75ddSKen Xue ret = amd_get_group_pins(pctldev, group, &pins, &npins); 714dbad75ddSKen Xue if (ret) 715dbad75ddSKen Xue return ret; 716dbad75ddSKen Xue for (i = 0; i < npins; i++) { 717dbad75ddSKen Xue if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) 718dbad75ddSKen Xue return -ENOTSUPP; 719dbad75ddSKen Xue } 720dbad75ddSKen Xue return 0; 721dbad75ddSKen Xue } 722dbad75ddSKen Xue 723dbad75ddSKen Xue static const struct pinconf_ops amd_pinconf_ops = { 724dbad75ddSKen Xue .pin_config_get = amd_pinconf_get, 725dbad75ddSKen Xue .pin_config_set = amd_pinconf_set, 726dbad75ddSKen Xue .pin_config_group_get = amd_pinconf_group_get, 727dbad75ddSKen Xue .pin_config_group_set = amd_pinconf_group_set, 728dbad75ddSKen Xue }; 729dbad75ddSKen Xue 730dbad75ddSKen Xue static struct pinctrl_desc amd_pinctrl_desc = { 731dbad75ddSKen Xue .pins = kerncz_pins, 732dbad75ddSKen Xue .npins = ARRAY_SIZE(kerncz_pins), 733dbad75ddSKen Xue .pctlops = &amd_pinctrl_ops, 734dbad75ddSKen Xue .confops = &amd_pinconf_ops, 735dbad75ddSKen Xue .owner = THIS_MODULE, 736dbad75ddSKen Xue }; 737dbad75ddSKen Xue 738dbad75ddSKen Xue static int amd_gpio_probe(struct platform_device *pdev) 739dbad75ddSKen Xue { 740dbad75ddSKen Xue int ret = 0; 74125a853d0SKen Xue int irq_base; 742dbad75ddSKen Xue struct resource *res; 743dbad75ddSKen Xue struct amd_gpio *gpio_dev; 744dbad75ddSKen Xue 745dbad75ddSKen Xue gpio_dev = devm_kzalloc(&pdev->dev, 746dbad75ddSKen Xue sizeof(struct amd_gpio), GFP_KERNEL); 747dbad75ddSKen Xue if (!gpio_dev) 748dbad75ddSKen Xue return -ENOMEM; 749dbad75ddSKen Xue 750dbad75ddSKen Xue spin_lock_init(&gpio_dev->lock); 751dbad75ddSKen Xue 752dbad75ddSKen Xue res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 753dbad75ddSKen Xue if (!res) { 754dbad75ddSKen Xue dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); 755dbad75ddSKen Xue return -EINVAL; 756dbad75ddSKen Xue } 757dbad75ddSKen Xue 758dbad75ddSKen Xue gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start, 759dbad75ddSKen Xue resource_size(res)); 760dbad75ddSKen Xue if (IS_ERR(gpio_dev->base)) 761dbad75ddSKen Xue return PTR_ERR(gpio_dev->base); 762dbad75ddSKen Xue 763dbad75ddSKen Xue irq_base = platform_get_irq(pdev, 0); 764dbad75ddSKen Xue if (irq_base < 0) { 765dbad75ddSKen Xue dev_err(&pdev->dev, "Failed to get gpio IRQ.\n"); 766dbad75ddSKen Xue return -EINVAL; 767dbad75ddSKen Xue } 768dbad75ddSKen Xue 769dbad75ddSKen Xue gpio_dev->pdev = pdev; 770dbad75ddSKen Xue gpio_dev->gc.direction_input = amd_gpio_direction_input; 771dbad75ddSKen Xue gpio_dev->gc.direction_output = amd_gpio_direction_output; 772dbad75ddSKen Xue gpio_dev->gc.get = amd_gpio_get_value; 773dbad75ddSKen Xue gpio_dev->gc.set = amd_gpio_set_value; 774dbad75ddSKen Xue gpio_dev->gc.set_debounce = amd_gpio_set_debounce; 775dbad75ddSKen Xue gpio_dev->gc.dbg_show = amd_gpio_dbg_show; 776dbad75ddSKen Xue 777dbad75ddSKen Xue gpio_dev->gc.base = 0; 778dbad75ddSKen Xue gpio_dev->gc.label = pdev->name; 779dbad75ddSKen Xue gpio_dev->gc.owner = THIS_MODULE; 780dbad75ddSKen Xue gpio_dev->gc.dev = &pdev->dev; 781dbad75ddSKen Xue gpio_dev->gc.ngpio = TOTAL_NUMBER_OF_PINS; 782dbad75ddSKen Xue #if defined(CONFIG_OF_GPIO) 783dbad75ddSKen Xue gpio_dev->gc.of_node = pdev->dev.of_node; 784dbad75ddSKen Xue #endif 785dbad75ddSKen Xue 786dbad75ddSKen Xue gpio_dev->groups = kerncz_groups; 787dbad75ddSKen Xue gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); 788dbad75ddSKen Xue 789dbad75ddSKen Xue amd_pinctrl_desc.name = dev_name(&pdev->dev); 790dbad75ddSKen Xue gpio_dev->pctrl = pinctrl_register(&amd_pinctrl_desc, 791dbad75ddSKen Xue &pdev->dev, gpio_dev); 792323de9efSMasahiro Yamada if (IS_ERR(gpio_dev->pctrl)) { 793dbad75ddSKen Xue dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 794323de9efSMasahiro Yamada return PTR_ERR(gpio_dev->pctrl); 795dbad75ddSKen Xue } 796dbad75ddSKen Xue 797dbad75ddSKen Xue ret = gpiochip_add(&gpio_dev->gc); 798dbad75ddSKen Xue if (ret) 799dbad75ddSKen Xue goto out1; 800dbad75ddSKen Xue 801dbad75ddSKen Xue ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), 802dbad75ddSKen Xue 0, 0, TOTAL_NUMBER_OF_PINS); 803dbad75ddSKen Xue if (ret) { 804dbad75ddSKen Xue dev_err(&pdev->dev, "Failed to add pin range\n"); 805dbad75ddSKen Xue goto out2; 806dbad75ddSKen Xue } 807dbad75ddSKen Xue 808dbad75ddSKen Xue ret = gpiochip_irqchip_add(&gpio_dev->gc, 809dbad75ddSKen Xue &amd_gpio_irqchip, 810dbad75ddSKen Xue 0, 811dbad75ddSKen Xue handle_simple_irq, 812dbad75ddSKen Xue IRQ_TYPE_NONE); 813dbad75ddSKen Xue if (ret) { 814dbad75ddSKen Xue dev_err(&pdev->dev, "could not add irqchip\n"); 815dbad75ddSKen Xue ret = -ENODEV; 816dbad75ddSKen Xue goto out2; 817dbad75ddSKen Xue } 818dbad75ddSKen Xue 819dbad75ddSKen Xue gpiochip_set_chained_irqchip(&gpio_dev->gc, 820dbad75ddSKen Xue &amd_gpio_irqchip, 821dbad75ddSKen Xue irq_base, 822dbad75ddSKen Xue amd_gpio_irq_handler); 823dbad75ddSKen Xue 824dbad75ddSKen Xue platform_set_drvdata(pdev, gpio_dev); 825dbad75ddSKen Xue 826dbad75ddSKen Xue dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); 827dbad75ddSKen Xue return ret; 828dbad75ddSKen Xue 829dbad75ddSKen Xue out2: 830dbad75ddSKen Xue gpiochip_remove(&gpio_dev->gc); 831dbad75ddSKen Xue 832dbad75ddSKen Xue out1: 833dbad75ddSKen Xue pinctrl_unregister(gpio_dev->pctrl); 834dbad75ddSKen Xue return ret; 835dbad75ddSKen Xue } 836dbad75ddSKen Xue 837dbad75ddSKen Xue static int amd_gpio_remove(struct platform_device *pdev) 838dbad75ddSKen Xue { 839dbad75ddSKen Xue struct amd_gpio *gpio_dev; 840dbad75ddSKen Xue 841dbad75ddSKen Xue gpio_dev = platform_get_drvdata(pdev); 842dbad75ddSKen Xue 843dbad75ddSKen Xue gpiochip_remove(&gpio_dev->gc); 844dbad75ddSKen Xue pinctrl_unregister(gpio_dev->pctrl); 845dbad75ddSKen Xue 846dbad75ddSKen Xue return 0; 847dbad75ddSKen Xue } 848dbad75ddSKen Xue 849dbad75ddSKen Xue static const struct acpi_device_id amd_gpio_acpi_match[] = { 850dbad75ddSKen Xue { "AMD0030", 0 }, 851dbad75ddSKen Xue { }, 852dbad75ddSKen Xue }; 853dbad75ddSKen Xue MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); 854dbad75ddSKen Xue 855dbad75ddSKen Xue static struct platform_driver amd_gpio_driver = { 856dbad75ddSKen Xue .driver = { 857dbad75ddSKen Xue .name = "amd_gpio", 858dbad75ddSKen Xue .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), 859dbad75ddSKen Xue }, 860dbad75ddSKen Xue .probe = amd_gpio_probe, 861dbad75ddSKen Xue .remove = amd_gpio_remove, 862dbad75ddSKen Xue }; 863dbad75ddSKen Xue 864dbad75ddSKen Xue module_platform_driver(amd_gpio_driver); 865dbad75ddSKen Xue 866dbad75ddSKen Xue MODULE_LICENSE("GPL v2"); 867dbad75ddSKen Xue MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); 868dbad75ddSKen Xue MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); 869