175a6faf6SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2dbad75ddSKen Xue /* 3dbad75ddSKen Xue * GPIO driver for AMD 4dbad75ddSKen Xue * 5dbad75ddSKen Xue * Copyright (c) 2014,2015 AMD Corporation. 6dbad75ddSKen Xue * Authors: Ken Xue <Ken.Xue@amd.com> 7dbad75ddSKen Xue * Wu, Jeff <Jeff.Wu@amd.com> 8dbad75ddSKen Xue * 9add7bfceSShyam Sundar S K * Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com> 10add7bfceSShyam Sundar S K * Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 11dbad75ddSKen Xue */ 12dbad75ddSKen Xue 13dbad75ddSKen Xue #include <linux/err.h> 14dbad75ddSKen Xue #include <linux/bug.h> 15dbad75ddSKen Xue #include <linux/kernel.h> 16dbad75ddSKen Xue #include <linux/module.h> 17dbad75ddSKen Xue #include <linux/spinlock.h> 18dbad75ddSKen Xue #include <linux/compiler.h> 19dbad75ddSKen Xue #include <linux/types.h> 20dbad75ddSKen Xue #include <linux/errno.h> 21dbad75ddSKen Xue #include <linux/log2.h> 22dbad75ddSKen Xue #include <linux/io.h> 231c5fb66aSLinus Walleij #include <linux/gpio/driver.h> 24dbad75ddSKen Xue #include <linux/slab.h> 25dbad75ddSKen Xue #include <linux/platform_device.h> 26dbad75ddSKen Xue #include <linux/mutex.h> 27dbad75ddSKen Xue #include <linux/acpi.h> 28dbad75ddSKen Xue #include <linux/seq_file.h> 29dbad75ddSKen Xue #include <linux/interrupt.h> 30dbad75ddSKen Xue #include <linux/list.h> 31dbad75ddSKen Xue #include <linux/bitops.h> 32dbad75ddSKen Xue #include <linux/pinctrl/pinconf.h> 33dbad75ddSKen Xue #include <linux/pinctrl/pinconf-generic.h> 34dbad75ddSKen Xue 3579d2c8beSDaniel Drake #include "core.h" 36dbad75ddSKen Xue #include "pinctrl-utils.h" 37dbad75ddSKen Xue #include "pinctrl-amd.h" 38dbad75ddSKen Xue 3912b10f47SDaniel Kurtz static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset) 4012b10f47SDaniel Kurtz { 4112b10f47SDaniel Kurtz unsigned long flags; 4212b10f47SDaniel Kurtz u32 pin_reg; 4312b10f47SDaniel Kurtz struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 4412b10f47SDaniel Kurtz 4512b10f47SDaniel Kurtz raw_spin_lock_irqsave(&gpio_dev->lock, flags); 4612b10f47SDaniel Kurtz pin_reg = readl(gpio_dev->base + offset * 4); 4712b10f47SDaniel Kurtz raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 4812b10f47SDaniel Kurtz 493c827873SMatti Vaittinen if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) 503c827873SMatti Vaittinen return GPIO_LINE_DIRECTION_OUT; 513c827873SMatti Vaittinen 523c827873SMatti Vaittinen return GPIO_LINE_DIRECTION_IN; 5312b10f47SDaniel Kurtz } 5412b10f47SDaniel Kurtz 55dbad75ddSKen Xue static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 56dbad75ddSKen Xue { 57dbad75ddSKen Xue unsigned long flags; 58dbad75ddSKen Xue u32 pin_reg; 5904d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 60dbad75ddSKen Xue 61229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 62dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 63dbad75ddSKen Xue pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); 64dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4); 65229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 66dbad75ddSKen Xue 67dbad75ddSKen Xue return 0; 68dbad75ddSKen Xue } 69dbad75ddSKen Xue 70dbad75ddSKen Xue static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 71dbad75ddSKen Xue int value) 72dbad75ddSKen Xue { 73dbad75ddSKen Xue u32 pin_reg; 74dbad75ddSKen Xue unsigned long flags; 7504d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 76dbad75ddSKen Xue 77229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 78dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 79dbad75ddSKen Xue pin_reg |= BIT(OUTPUT_ENABLE_OFF); 80dbad75ddSKen Xue if (value) 81dbad75ddSKen Xue pin_reg |= BIT(OUTPUT_VALUE_OFF); 82dbad75ddSKen Xue else 83dbad75ddSKen Xue pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 84dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4); 85229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 86dbad75ddSKen Xue 87dbad75ddSKen Xue return 0; 88dbad75ddSKen Xue } 89dbad75ddSKen Xue 90dbad75ddSKen Xue static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) 91dbad75ddSKen Xue { 92dbad75ddSKen Xue u32 pin_reg; 93dbad75ddSKen Xue unsigned long flags; 9404d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 95dbad75ddSKen Xue 96229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 97dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 98229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 99dbad75ddSKen Xue 100dbad75ddSKen Xue return !!(pin_reg & BIT(PIN_STS_OFF)); 101dbad75ddSKen Xue } 102dbad75ddSKen Xue 103dbad75ddSKen Xue static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) 104dbad75ddSKen Xue { 105dbad75ddSKen Xue u32 pin_reg; 106dbad75ddSKen Xue unsigned long flags; 10704d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 108dbad75ddSKen Xue 109229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 110dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 111dbad75ddSKen Xue if (value) 112dbad75ddSKen Xue pin_reg |= BIT(OUTPUT_VALUE_OFF); 113dbad75ddSKen Xue else 114dbad75ddSKen Xue pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 115dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4); 116229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 117dbad75ddSKen Xue } 118dbad75ddSKen Xue 119dbad75ddSKen Xue static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, 120dbad75ddSKen Xue unsigned debounce) 121dbad75ddSKen Xue { 122dbad75ddSKen Xue u32 time; 12325a853d0SKen Xue u32 pin_reg; 12425a853d0SKen Xue int ret = 0; 125dbad75ddSKen Xue unsigned long flags; 12604d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 127dbad75ddSKen Xue 128229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 129dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4); 130dbad75ddSKen Xue 131dbad75ddSKen Xue if (debounce) { 132dbad75ddSKen Xue pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 133dbad75ddSKen Xue pin_reg &= ~DB_TMR_OUT_MASK; 134dbad75ddSKen Xue /* 135dbad75ddSKen Xue Debounce Debounce Timer Max 136dbad75ddSKen Xue TmrLarge TmrOutUnit Unit Debounce 137dbad75ddSKen Xue Time 138dbad75ddSKen Xue 0 0 61 usec (2 RtcClk) 976 usec 139dbad75ddSKen Xue 0 1 244 usec (8 RtcClk) 3.9 msec 140dbad75ddSKen Xue 1 0 15.6 msec (512 RtcClk) 250 msec 141dbad75ddSKen Xue 1 1 62.5 msec (2048 RtcClk) 1 sec 142dbad75ddSKen Xue */ 143dbad75ddSKen Xue 144dbad75ddSKen Xue if (debounce < 61) { 145dbad75ddSKen Xue pin_reg |= 1; 146dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 147dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 148dbad75ddSKen Xue } else if (debounce < 976) { 149dbad75ddSKen Xue time = debounce / 61; 150dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK; 151dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 152dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 153dbad75ddSKen Xue } else if (debounce < 3900) { 154dbad75ddSKen Xue time = debounce / 244; 155dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK; 156dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 157dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 158dbad75ddSKen Xue } else if (debounce < 250000) { 159c64a6a0dSCoiby Xu time = debounce / 15625; 160dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK; 161dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 162dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_LARGE_OFF); 163dbad75ddSKen Xue } else if (debounce < 1000000) { 164dbad75ddSKen Xue time = debounce / 62500; 165dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK; 166dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 167dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_LARGE_OFF); 168dbad75ddSKen Xue } else { 16906abe829SCoiby Xu pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 17025a853d0SKen Xue ret = -EINVAL; 171dbad75ddSKen Xue } 172dbad75ddSKen Xue } else { 173dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 174dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 175dbad75ddSKen Xue pin_reg &= ~DB_TMR_OUT_MASK; 17606abe829SCoiby Xu pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 177dbad75ddSKen Xue } 178dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4); 179229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 180dbad75ddSKen Xue 18125a853d0SKen Xue return ret; 182dbad75ddSKen Xue } 183dbad75ddSKen Xue 1842956b5d9SMika Westerberg static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset, 1852956b5d9SMika Westerberg unsigned long config) 1862956b5d9SMika Westerberg { 1872956b5d9SMika Westerberg u32 debounce; 1882956b5d9SMika Westerberg 1892956b5d9SMika Westerberg if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 1902956b5d9SMika Westerberg return -ENOTSUPP; 1912956b5d9SMika Westerberg 1922956b5d9SMika Westerberg debounce = pinconf_to_config_argument(config); 1932956b5d9SMika Westerberg return amd_gpio_set_debounce(gc, offset, debounce); 1942956b5d9SMika Westerberg } 1952956b5d9SMika Westerberg 196dbad75ddSKen Xue #ifdef CONFIG_DEBUG_FS 197dbad75ddSKen Xue static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) 198dbad75ddSKen Xue { 199dbad75ddSKen Xue u32 pin_reg; 20039cc1d33SCoiby Xu u32 db_cntrl; 201dbad75ddSKen Xue unsigned long flags; 202dbad75ddSKen Xue unsigned int bank, i, pin_num; 20304d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 204dbad75ddSKen Xue 20539cc1d33SCoiby Xu bool tmr_out_unit; 20639cc1d33SCoiby Xu unsigned int time; 20739cc1d33SCoiby Xu unsigned int unit; 20839cc1d33SCoiby Xu bool tmr_large; 20939cc1d33SCoiby Xu 210dbad75ddSKen Xue char *level_trig; 211dbad75ddSKen Xue char *active_level; 212dbad75ddSKen Xue char *interrupt_enable; 213dbad75ddSKen Xue char *interrupt_mask; 214dbad75ddSKen Xue char *wake_cntrl0; 215dbad75ddSKen Xue char *wake_cntrl1; 216dbad75ddSKen Xue char *wake_cntrl2; 217dbad75ddSKen Xue char *pin_sts; 218dbad75ddSKen Xue char *pull_up_sel; 219dbad75ddSKen Xue char *pull_up_enable; 220dbad75ddSKen Xue char *pull_down_enable; 221dbad75ddSKen Xue char *output_value; 222dbad75ddSKen Xue char *output_enable; 22339cc1d33SCoiby Xu char debounce_value[40]; 22439cc1d33SCoiby Xu char *debounce_enable; 225dbad75ddSKen Xue 2263bfd4430SShah, Nehal-bakulchandra for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { 227dbad75ddSKen Xue seq_printf(s, "GPIO bank%d\t", bank); 228dbad75ddSKen Xue 229dbad75ddSKen Xue switch (bank) { 230dbad75ddSKen Xue case 0: 231dbad75ddSKen Xue i = 0; 232dbad75ddSKen Xue pin_num = AMD_GPIO_PINS_BANK0; 233dbad75ddSKen Xue break; 234dbad75ddSKen Xue case 1: 235dbad75ddSKen Xue i = 64; 236dbad75ddSKen Xue pin_num = AMD_GPIO_PINS_BANK1 + i; 237dbad75ddSKen Xue break; 238dbad75ddSKen Xue case 2: 239dbad75ddSKen Xue i = 128; 240dbad75ddSKen Xue pin_num = AMD_GPIO_PINS_BANK2 + i; 241dbad75ddSKen Xue break; 2423bfd4430SShah, Nehal-bakulchandra case 3: 2433bfd4430SShah, Nehal-bakulchandra i = 192; 2443bfd4430SShah, Nehal-bakulchandra pin_num = AMD_GPIO_PINS_BANK3 + i; 2453bfd4430SShah, Nehal-bakulchandra break; 2466ac4c1adSLinus Walleij default: 2476ac4c1adSLinus Walleij /* Illegal bank number, ignore */ 2486ac4c1adSLinus Walleij continue; 249dbad75ddSKen Xue } 250dbad75ddSKen Xue for (; i < pin_num; i++) { 251dbad75ddSKen Xue seq_printf(s, "pin%d\t", i); 252229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 253dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + i * 4); 254229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 255dbad75ddSKen Xue 256dbad75ddSKen Xue if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { 2571766e4b7SDaniel Kurtz u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) & 2581766e4b7SDaniel Kurtz ACTIVE_LEVEL_MASK; 259dbad75ddSKen Xue interrupt_enable = "interrupt is enabled|"; 260dbad75ddSKen Xue 2611766e4b7SDaniel Kurtz if (level == ACTIVE_LEVEL_HIGH) 262dbad75ddSKen Xue active_level = "Active high|"; 2631766e4b7SDaniel Kurtz else if (level == ACTIVE_LEVEL_LOW) 2641766e4b7SDaniel Kurtz active_level = "Active low|"; 2651766e4b7SDaniel Kurtz else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) && 2661766e4b7SDaniel Kurtz level == ACTIVE_LEVEL_BOTH) 267dbad75ddSKen Xue active_level = "Active on both|"; 268dbad75ddSKen Xue else 2690a95160eSMasanari Iida active_level = "Unknown Active level|"; 270dbad75ddSKen Xue 271dbad75ddSKen Xue if (pin_reg & BIT(LEVEL_TRIG_OFF)) 272dbad75ddSKen Xue level_trig = "Level trigger|"; 273dbad75ddSKen Xue else 274dbad75ddSKen Xue level_trig = "Edge trigger|"; 275dbad75ddSKen Xue 276dbad75ddSKen Xue } else { 277dbad75ddSKen Xue interrupt_enable = 278dbad75ddSKen Xue "interrupt is disabled|"; 279dbad75ddSKen Xue active_level = " "; 280dbad75ddSKen Xue level_trig = " "; 281dbad75ddSKen Xue } 282dbad75ddSKen Xue 283dbad75ddSKen Xue if (pin_reg & BIT(INTERRUPT_MASK_OFF)) 284dbad75ddSKen Xue interrupt_mask = 285dbad75ddSKen Xue "interrupt is unmasked|"; 286dbad75ddSKen Xue else 287dbad75ddSKen Xue interrupt_mask = 288dbad75ddSKen Xue "interrupt is masked|"; 289dbad75ddSKen Xue 2903bfd4430SShah, Nehal-bakulchandra if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) 291dbad75ddSKen Xue wake_cntrl0 = "enable wakeup in S0i3 state|"; 292dbad75ddSKen Xue else 293dbad75ddSKen Xue wake_cntrl0 = "disable wakeup in S0i3 state|"; 294dbad75ddSKen Xue 2953bfd4430SShah, Nehal-bakulchandra if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) 296dbad75ddSKen Xue wake_cntrl1 = "enable wakeup in S3 state|"; 297dbad75ddSKen Xue else 298dbad75ddSKen Xue wake_cntrl1 = "disable wakeup in S3 state|"; 299dbad75ddSKen Xue 3003bfd4430SShah, Nehal-bakulchandra if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) 301dbad75ddSKen Xue wake_cntrl2 = "enable wakeup in S4/S5 state|"; 302dbad75ddSKen Xue else 303dbad75ddSKen Xue wake_cntrl2 = "disable wakeup in S4/S5 state|"; 304dbad75ddSKen Xue 305dbad75ddSKen Xue if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { 306dbad75ddSKen Xue pull_up_enable = "pull-up is enabled|"; 307dbad75ddSKen Xue if (pin_reg & BIT(PULL_UP_SEL_OFF)) 308dbad75ddSKen Xue pull_up_sel = "8k pull-up|"; 309dbad75ddSKen Xue else 310dbad75ddSKen Xue pull_up_sel = "4k pull-up|"; 311dbad75ddSKen Xue } else { 312dbad75ddSKen Xue pull_up_enable = "pull-up is disabled|"; 313dbad75ddSKen Xue pull_up_sel = " "; 314dbad75ddSKen Xue } 315dbad75ddSKen Xue 316dbad75ddSKen Xue if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) 317dbad75ddSKen Xue pull_down_enable = "pull-down is enabled|"; 318dbad75ddSKen Xue else 319dbad75ddSKen Xue pull_down_enable = "Pull-down is disabled|"; 320dbad75ddSKen Xue 321dbad75ddSKen Xue if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { 322dbad75ddSKen Xue pin_sts = " "; 323dbad75ddSKen Xue output_enable = "output is enabled|"; 324dbad75ddSKen Xue if (pin_reg & BIT(OUTPUT_VALUE_OFF)) 325dbad75ddSKen Xue output_value = "output is high|"; 326dbad75ddSKen Xue else 327dbad75ddSKen Xue output_value = "output is low|"; 328dbad75ddSKen Xue } else { 329dbad75ddSKen Xue output_enable = "output is disabled|"; 330dbad75ddSKen Xue output_value = " "; 331dbad75ddSKen Xue 332dbad75ddSKen Xue if (pin_reg & BIT(PIN_STS_OFF)) 333dbad75ddSKen Xue pin_sts = "input is high|"; 334dbad75ddSKen Xue else 335dbad75ddSKen Xue pin_sts = "input is low|"; 336dbad75ddSKen Xue } 337dbad75ddSKen Xue 33839cc1d33SCoiby Xu db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg; 33939cc1d33SCoiby Xu if (db_cntrl) { 34039cc1d33SCoiby Xu tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF); 34139cc1d33SCoiby Xu tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF); 34239cc1d33SCoiby Xu time = pin_reg & DB_TMR_OUT_MASK; 34339cc1d33SCoiby Xu if (tmr_large) { 34439cc1d33SCoiby Xu if (tmr_out_unit) 34539cc1d33SCoiby Xu unit = 62500; 34639cc1d33SCoiby Xu else 34739cc1d33SCoiby Xu unit = 15625; 34839cc1d33SCoiby Xu } else { 34939cc1d33SCoiby Xu if (tmr_out_unit) 35039cc1d33SCoiby Xu unit = 244; 35139cc1d33SCoiby Xu else 35239cc1d33SCoiby Xu unit = 61; 35339cc1d33SCoiby Xu } 35439cc1d33SCoiby Xu if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl) 35539cc1d33SCoiby Xu debounce_enable = "debouncing filter (high and low) enabled|"; 35639cc1d33SCoiby Xu else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl) 35739cc1d33SCoiby Xu debounce_enable = "debouncing filter (low) enabled|"; 35839cc1d33SCoiby Xu else 35939cc1d33SCoiby Xu debounce_enable = "debouncing filter (high) enabled|"; 36039cc1d33SCoiby Xu 36139cc1d33SCoiby Xu snprintf(debounce_value, sizeof(debounce_value), 36239cc1d33SCoiby Xu "debouncing timeout is %u (us)|", time * unit); 36339cc1d33SCoiby Xu } else { 36439cc1d33SCoiby Xu debounce_enable = "debouncing filter disabled|"; 36539cc1d33SCoiby Xu snprintf(debounce_value, sizeof(debounce_value), " "); 36639cc1d33SCoiby Xu } 36739cc1d33SCoiby Xu 368dbad75ddSKen Xue seq_printf(s, "%s %s %s %s %s %s\n" 36939cc1d33SCoiby Xu " %s %s %s %s %s %s %s %s %s 0x%x\n", 370dbad75ddSKen Xue level_trig, active_level, interrupt_enable, 371dbad75ddSKen Xue interrupt_mask, wake_cntrl0, wake_cntrl1, 372dbad75ddSKen Xue wake_cntrl2, pin_sts, pull_up_sel, 373dbad75ddSKen Xue pull_up_enable, pull_down_enable, 37439cc1d33SCoiby Xu output_value, output_enable, 37539cc1d33SCoiby Xu debounce_enable, debounce_value, pin_reg); 376dbad75ddSKen Xue } 377dbad75ddSKen Xue } 378dbad75ddSKen Xue } 379dbad75ddSKen Xue #else 380dbad75ddSKen Xue #define amd_gpio_dbg_show NULL 381dbad75ddSKen Xue #endif 382dbad75ddSKen Xue 383dbad75ddSKen Xue static void amd_gpio_irq_enable(struct irq_data *d) 384dbad75ddSKen Xue { 385dbad75ddSKen Xue u32 pin_reg; 386dbad75ddSKen Xue unsigned long flags; 387dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 38804d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 389dbad75ddSKen Xue 390229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 391dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 392dbad75ddSKen Xue pin_reg |= BIT(INTERRUPT_ENABLE_OFF); 393dbad75ddSKen Xue pin_reg |= BIT(INTERRUPT_MASK_OFF); 394dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 395229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 396dbad75ddSKen Xue } 397dbad75ddSKen Xue 398dbad75ddSKen Xue static void amd_gpio_irq_disable(struct irq_data *d) 399dbad75ddSKen Xue { 400dbad75ddSKen Xue u32 pin_reg; 401dbad75ddSKen Xue unsigned long flags; 402dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 40304d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 404dbad75ddSKen Xue 405229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 406dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 407dbad75ddSKen Xue pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); 408dbad75ddSKen Xue pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 409dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 410229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 411dbad75ddSKen Xue } 412dbad75ddSKen Xue 413dbad75ddSKen Xue static void amd_gpio_irq_mask(struct irq_data *d) 414dbad75ddSKen Xue { 415dbad75ddSKen Xue u32 pin_reg; 416dbad75ddSKen Xue unsigned long flags; 417dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 41804d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 419dbad75ddSKen Xue 420229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 421dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 422dbad75ddSKen Xue pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 423dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 424229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 425dbad75ddSKen Xue } 426dbad75ddSKen Xue 427dbad75ddSKen Xue static void amd_gpio_irq_unmask(struct irq_data *d) 428dbad75ddSKen Xue { 429dbad75ddSKen Xue u32 pin_reg; 430dbad75ddSKen Xue unsigned long flags; 431dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 43204d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 433dbad75ddSKen Xue 434229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 435dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 436dbad75ddSKen Xue pin_reg |= BIT(INTERRUPT_MASK_OFF); 437dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 438229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 439dbad75ddSKen Xue } 440dbad75ddSKen Xue 441d62bd5ceSRaul E Rangel static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 442d62bd5ceSRaul E Rangel { 443d62bd5ceSRaul E Rangel u32 pin_reg; 444d62bd5ceSRaul E Rangel unsigned long flags; 445d62bd5ceSRaul E Rangel struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 446d62bd5ceSRaul E Rangel struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 447d62bd5ceSRaul E Rangel u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) | 448d62bd5ceSRaul E Rangel BIT(WAKE_CNTRL_OFF_S4); 449d62bd5ceSRaul E Rangel 450d62bd5ceSRaul E Rangel raw_spin_lock_irqsave(&gpio_dev->lock, flags); 451d62bd5ceSRaul E Rangel pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 452d62bd5ceSRaul E Rangel 453d62bd5ceSRaul E Rangel if (on) 454d62bd5ceSRaul E Rangel pin_reg |= wake_mask; 455d62bd5ceSRaul E Rangel else 456d62bd5ceSRaul E Rangel pin_reg &= ~wake_mask; 457d62bd5ceSRaul E Rangel 458d62bd5ceSRaul E Rangel writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 459d62bd5ceSRaul E Rangel raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 460d62bd5ceSRaul E Rangel 461d62bd5ceSRaul E Rangel return 0; 462d62bd5ceSRaul E Rangel } 463d62bd5ceSRaul E Rangel 464dbad75ddSKen Xue static void amd_gpio_irq_eoi(struct irq_data *d) 465dbad75ddSKen Xue { 466dbad75ddSKen Xue u32 reg; 467dbad75ddSKen Xue unsigned long flags; 468dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 46904d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 470dbad75ddSKen Xue 471229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 472dbad75ddSKen Xue reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 473dbad75ddSKen Xue reg |= EOI_MASK; 474dbad75ddSKen Xue writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 475229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 476dbad75ddSKen Xue } 477dbad75ddSKen Xue 478dbad75ddSKen Xue static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) 479dbad75ddSKen Xue { 480dbad75ddSKen Xue int ret = 0; 481b85bfa24SDaniel Kurtz u32 pin_reg, pin_reg_irq_en, mask; 4825f4962ddSFurquan Shaikh unsigned long flags; 483dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 48404d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 485dbad75ddSKen Xue 486229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 487dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 488dbad75ddSKen Xue 489dbad75ddSKen Xue switch (type & IRQ_TYPE_SENSE_MASK) { 490dbad75ddSKen Xue case IRQ_TYPE_EDGE_RISING: 491dbad75ddSKen Xue pin_reg &= ~BIT(LEVEL_TRIG_OFF); 492dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 493dbad75ddSKen Xue pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 4949d829314SThomas Gleixner irq_set_handler_locked(d, handle_edge_irq); 495dbad75ddSKen Xue break; 496dbad75ddSKen Xue 497dbad75ddSKen Xue case IRQ_TYPE_EDGE_FALLING: 498dbad75ddSKen Xue pin_reg &= ~BIT(LEVEL_TRIG_OFF); 499dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 500dbad75ddSKen Xue pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 5019d829314SThomas Gleixner irq_set_handler_locked(d, handle_edge_irq); 502dbad75ddSKen Xue break; 503dbad75ddSKen Xue 504dbad75ddSKen Xue case IRQ_TYPE_EDGE_BOTH: 505dbad75ddSKen Xue pin_reg &= ~BIT(LEVEL_TRIG_OFF); 506dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 507dbad75ddSKen Xue pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; 5089d829314SThomas Gleixner irq_set_handler_locked(d, handle_edge_irq); 509dbad75ddSKen Xue break; 510dbad75ddSKen Xue 511dbad75ddSKen Xue case IRQ_TYPE_LEVEL_HIGH: 512dbad75ddSKen Xue pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 513dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 514dbad75ddSKen Xue pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 5159d829314SThomas Gleixner irq_set_handler_locked(d, handle_level_irq); 516dbad75ddSKen Xue break; 517dbad75ddSKen Xue 518dbad75ddSKen Xue case IRQ_TYPE_LEVEL_LOW: 519dbad75ddSKen Xue pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 520dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 521dbad75ddSKen Xue pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 5229d829314SThomas Gleixner irq_set_handler_locked(d, handle_level_irq); 523dbad75ddSKen Xue break; 524dbad75ddSKen Xue 525dbad75ddSKen Xue case IRQ_TYPE_NONE: 526dbad75ddSKen Xue break; 527dbad75ddSKen Xue 528dbad75ddSKen Xue default: 529dbad75ddSKen Xue dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); 530dbad75ddSKen Xue ret = -EINVAL; 531dbad75ddSKen Xue } 532dbad75ddSKen Xue 533dbad75ddSKen Xue pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; 534b85bfa24SDaniel Kurtz /* 535b85bfa24SDaniel Kurtz * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the 536b85bfa24SDaniel Kurtz * debounce registers of any GPIO will block wake/interrupt status 53748c67f1fSMatteo Croce * generation for *all* GPIOs for a length of time that depends on 538b85bfa24SDaniel Kurtz * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the 539b85bfa24SDaniel Kurtz * INTERRUPT_ENABLE bit will read as 0. 540b85bfa24SDaniel Kurtz * 541b85bfa24SDaniel Kurtz * We temporarily enable irq for the GPIO whose configuration is 542b85bfa24SDaniel Kurtz * changing, and then wait for it to read back as 1 to know when 543b85bfa24SDaniel Kurtz * debounce has settled and then disable the irq again. 544b85bfa24SDaniel Kurtz * We do this polling with the spinlock held to ensure other GPIO 545b85bfa24SDaniel Kurtz * access routines do not read an incorrect value for the irq enable 546b85bfa24SDaniel Kurtz * bit of other GPIOs. We keep the GPIO masked while polling to avoid 547b85bfa24SDaniel Kurtz * spurious irqs, and disable the irq again after polling. 548b85bfa24SDaniel Kurtz */ 549b85bfa24SDaniel Kurtz mask = BIT(INTERRUPT_ENABLE_OFF); 550b85bfa24SDaniel Kurtz pin_reg_irq_en = pin_reg; 551b85bfa24SDaniel Kurtz pin_reg_irq_en |= mask; 552b85bfa24SDaniel Kurtz pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF); 553b85bfa24SDaniel Kurtz writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4); 554b85bfa24SDaniel Kurtz while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask) 555b85bfa24SDaniel Kurtz continue; 556dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 557229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 558dbad75ddSKen Xue 559dbad75ddSKen Xue return ret; 560dbad75ddSKen Xue } 561dbad75ddSKen Xue 562dbad75ddSKen Xue static void amd_irq_ack(struct irq_data *d) 563dbad75ddSKen Xue { 564dbad75ddSKen Xue /* 565dbad75ddSKen Xue * based on HW design,there is no need to ack HW 566dbad75ddSKen Xue * before handle current irq. But this routine is 567dbad75ddSKen Xue * necessary for handle_edge_irq 568dbad75ddSKen Xue */ 569dbad75ddSKen Xue } 570dbad75ddSKen Xue 571dbad75ddSKen Xue static struct irq_chip amd_gpio_irqchip = { 572dbad75ddSKen Xue .name = "amd_gpio", 573dbad75ddSKen Xue .irq_ack = amd_irq_ack, 574dbad75ddSKen Xue .irq_enable = amd_gpio_irq_enable, 575dbad75ddSKen Xue .irq_disable = amd_gpio_irq_disable, 576dbad75ddSKen Xue .irq_mask = amd_gpio_irq_mask, 577dbad75ddSKen Xue .irq_unmask = amd_gpio_irq_unmask, 578d62bd5ceSRaul E Rangel .irq_set_wake = amd_gpio_irq_set_wake, 579dbad75ddSKen Xue .irq_eoi = amd_gpio_irq_eoi, 580dbad75ddSKen Xue .irq_set_type = amd_gpio_irq_set_type, 581d62bd5ceSRaul E Rangel /* 582d62bd5ceSRaul E Rangel * We need to set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND so that a wake event 583d62bd5ceSRaul E Rangel * also generates an IRQ. We need the IRQ so the irq_handler can clear 584d62bd5ceSRaul E Rangel * the wake event. Otherwise the wake event will never clear and 585d62bd5ceSRaul E Rangel * prevent the system from suspending. 586d62bd5ceSRaul E Rangel */ 587d62bd5ceSRaul E Rangel .flags = IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND, 588dbad75ddSKen Xue }; 589dbad75ddSKen Xue 590ba714a9cSThomas Gleixner #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF)) 591ba714a9cSThomas Gleixner 592ba714a9cSThomas Gleixner static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id) 593dbad75ddSKen Xue { 594ba714a9cSThomas Gleixner struct amd_gpio *gpio_dev = dev_id; 595ba714a9cSThomas Gleixner struct gpio_chip *gc = &gpio_dev->gc; 596ba714a9cSThomas Gleixner irqreturn_t ret = IRQ_NONE; 597ba714a9cSThomas Gleixner unsigned int i, irqnr; 598dbad75ddSKen Xue unsigned long flags; 59910ff58aaSBen Dooks (Codethink) u32 __iomem *regs; 60010ff58aaSBen Dooks (Codethink) u32 regval; 601ba714a9cSThomas Gleixner u64 status, mask; 602dbad75ddSKen Xue 603ba714a9cSThomas Gleixner /* Read the wake status */ 604229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 605ba714a9cSThomas Gleixner status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); 606ba714a9cSThomas Gleixner status <<= 32; 607ba714a9cSThomas Gleixner status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0); 608229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 609dbad75ddSKen Xue 610ba714a9cSThomas Gleixner /* Bit 0-45 contain the relevant status bits */ 611ba714a9cSThomas Gleixner status &= (1ULL << 46) - 1; 612ba714a9cSThomas Gleixner regs = gpio_dev->base; 613ba714a9cSThomas Gleixner for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) { 614ba714a9cSThomas Gleixner if (!(status & mask)) 615ba714a9cSThomas Gleixner continue; 616ba714a9cSThomas Gleixner status &= ~mask; 617ba714a9cSThomas Gleixner 618ba714a9cSThomas Gleixner /* Each status bit covers four pins */ 619dbad75ddSKen Xue for (i = 0; i < 4; i++) { 620ba714a9cSThomas Gleixner regval = readl(regs + i); 6218bbed1eeSDaniel Kurtz if (!(regval & PIN_IRQ_PENDING) || 6228bbed1eeSDaniel Kurtz !(regval & BIT(INTERRUPT_MASK_OFF))) 623ba714a9cSThomas Gleixner continue; 624f0fbe7bcSThierry Reding irq = irq_find_mapping(gc->irq.domain, irqnr + i); 625d21b8adbSDaniel Drake if (irq != 0) 626dbad75ddSKen Xue generic_handle_irq(irq); 6276afb1026SDaniel Drake 6286afb1026SDaniel Drake /* Clear interrupt. 6296afb1026SDaniel Drake * We must read the pin register again, in case the 6306afb1026SDaniel Drake * value was changed while executing 6316afb1026SDaniel Drake * generic_handle_irq() above. 632d21b8adbSDaniel Drake * If we didn't find a mapping for the interrupt, 633d21b8adbSDaniel Drake * disable it in order to avoid a system hang caused 634d21b8adbSDaniel Drake * by an interrupt storm. 6356afb1026SDaniel Drake */ 6366afb1026SDaniel Drake raw_spin_lock_irqsave(&gpio_dev->lock, flags); 6376afb1026SDaniel Drake regval = readl(regs + i); 638d21b8adbSDaniel Drake if (irq == 0) { 639d21b8adbSDaniel Drake regval &= ~BIT(INTERRUPT_ENABLE_OFF); 640d21b8adbSDaniel Drake dev_dbg(&gpio_dev->pdev->dev, 641d21b8adbSDaniel Drake "Disabling spurious GPIO IRQ %d\n", 642d21b8adbSDaniel Drake irqnr + i); 643d21b8adbSDaniel Drake } 644ba714a9cSThomas Gleixner writel(regval, regs + i); 6456afb1026SDaniel Drake raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 646ba714a9cSThomas Gleixner ret = IRQ_HANDLED; 647dbad75ddSKen Xue } 648dbad75ddSKen Xue } 649dbad75ddSKen Xue 650ba714a9cSThomas Gleixner /* Signal EOI to the GPIO unit */ 651229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 652ba714a9cSThomas Gleixner regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 653ba714a9cSThomas Gleixner regval |= EOI_MASK; 654ba714a9cSThomas Gleixner writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG); 655229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 656dbad75ddSKen Xue 657ba714a9cSThomas Gleixner return ret; 658dbad75ddSKen Xue } 659dbad75ddSKen Xue 660dbad75ddSKen Xue static int amd_get_groups_count(struct pinctrl_dev *pctldev) 661dbad75ddSKen Xue { 662dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 663dbad75ddSKen Xue 664dbad75ddSKen Xue return gpio_dev->ngroups; 665dbad75ddSKen Xue } 666dbad75ddSKen Xue 667dbad75ddSKen Xue static const char *amd_get_group_name(struct pinctrl_dev *pctldev, 668dbad75ddSKen Xue unsigned group) 669dbad75ddSKen Xue { 670dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 671dbad75ddSKen Xue 672dbad75ddSKen Xue return gpio_dev->groups[group].name; 673dbad75ddSKen Xue } 674dbad75ddSKen Xue 675dbad75ddSKen Xue static int amd_get_group_pins(struct pinctrl_dev *pctldev, 676dbad75ddSKen Xue unsigned group, 677dbad75ddSKen Xue const unsigned **pins, 678dbad75ddSKen Xue unsigned *num_pins) 679dbad75ddSKen Xue { 680dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 681dbad75ddSKen Xue 682dbad75ddSKen Xue *pins = gpio_dev->groups[group].pins; 683dbad75ddSKen Xue *num_pins = gpio_dev->groups[group].npins; 684dbad75ddSKen Xue return 0; 685dbad75ddSKen Xue } 686dbad75ddSKen Xue 687dbad75ddSKen Xue static const struct pinctrl_ops amd_pinctrl_ops = { 688dbad75ddSKen Xue .get_groups_count = amd_get_groups_count, 689dbad75ddSKen Xue .get_group_name = amd_get_group_name, 690dbad75ddSKen Xue .get_group_pins = amd_get_group_pins, 691dbad75ddSKen Xue #ifdef CONFIG_OF 692dbad75ddSKen Xue .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 693d32f7fd3SIrina Tirdea .dt_free_map = pinctrl_utils_free_map, 694dbad75ddSKen Xue #endif 695dbad75ddSKen Xue }; 696dbad75ddSKen Xue 697dbad75ddSKen Xue static int amd_pinconf_get(struct pinctrl_dev *pctldev, 698dbad75ddSKen Xue unsigned int pin, 699dbad75ddSKen Xue unsigned long *config) 700dbad75ddSKen Xue { 701dbad75ddSKen Xue u32 pin_reg; 702dbad75ddSKen Xue unsigned arg; 703dbad75ddSKen Xue unsigned long flags; 704dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 705dbad75ddSKen Xue enum pin_config_param param = pinconf_to_config_param(*config); 706dbad75ddSKen Xue 707229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 708dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + pin*4); 709229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 710dbad75ddSKen Xue switch (param) { 711dbad75ddSKen Xue case PIN_CONFIG_INPUT_DEBOUNCE: 712dbad75ddSKen Xue arg = pin_reg & DB_TMR_OUT_MASK; 713dbad75ddSKen Xue break; 714dbad75ddSKen Xue 715dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_DOWN: 716dbad75ddSKen Xue arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); 717dbad75ddSKen Xue break; 718dbad75ddSKen Xue 719dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_UP: 720dbad75ddSKen Xue arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); 721dbad75ddSKen Xue break; 722dbad75ddSKen Xue 723dbad75ddSKen Xue case PIN_CONFIG_DRIVE_STRENGTH: 724dbad75ddSKen Xue arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; 725dbad75ddSKen Xue break; 726dbad75ddSKen Xue 727dbad75ddSKen Xue default: 728dbad75ddSKen Xue dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n", 729dbad75ddSKen Xue param); 730dbad75ddSKen Xue return -ENOTSUPP; 731dbad75ddSKen Xue } 732dbad75ddSKen Xue 733dbad75ddSKen Xue *config = pinconf_to_config_packed(param, arg); 734dbad75ddSKen Xue 735dbad75ddSKen Xue return 0; 736dbad75ddSKen Xue } 737dbad75ddSKen Xue 738dbad75ddSKen Xue static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 739dbad75ddSKen Xue unsigned long *configs, unsigned num_configs) 740dbad75ddSKen Xue { 741dbad75ddSKen Xue int i; 742dbad75ddSKen Xue u32 arg; 74325a853d0SKen Xue int ret = 0; 74425a853d0SKen Xue u32 pin_reg; 745dbad75ddSKen Xue unsigned long flags; 746dbad75ddSKen Xue enum pin_config_param param; 747dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 748dbad75ddSKen Xue 749229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags); 750dbad75ddSKen Xue for (i = 0; i < num_configs; i++) { 751dbad75ddSKen Xue param = pinconf_to_config_param(configs[i]); 752dbad75ddSKen Xue arg = pinconf_to_config_argument(configs[i]); 753dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + pin*4); 754dbad75ddSKen Xue 755dbad75ddSKen Xue switch (param) { 756dbad75ddSKen Xue case PIN_CONFIG_INPUT_DEBOUNCE: 757dbad75ddSKen Xue pin_reg &= ~DB_TMR_OUT_MASK; 758dbad75ddSKen Xue pin_reg |= arg & DB_TMR_OUT_MASK; 759dbad75ddSKen Xue break; 760dbad75ddSKen Xue 761dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_DOWN: 762dbad75ddSKen Xue pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); 763dbad75ddSKen Xue pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; 764dbad75ddSKen Xue break; 765dbad75ddSKen Xue 766dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_UP: 767dbad75ddSKen Xue pin_reg &= ~BIT(PULL_UP_SEL_OFF); 768dbad75ddSKen Xue pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; 769dbad75ddSKen Xue pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); 770dbad75ddSKen Xue pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; 771dbad75ddSKen Xue break; 772dbad75ddSKen Xue 773dbad75ddSKen Xue case PIN_CONFIG_DRIVE_STRENGTH: 774dbad75ddSKen Xue pin_reg &= ~(DRV_STRENGTH_SEL_MASK 775dbad75ddSKen Xue << DRV_STRENGTH_SEL_OFF); 776dbad75ddSKen Xue pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) 777dbad75ddSKen Xue << DRV_STRENGTH_SEL_OFF; 778dbad75ddSKen Xue break; 779dbad75ddSKen Xue 780dbad75ddSKen Xue default: 781dbad75ddSKen Xue dev_err(&gpio_dev->pdev->dev, 782dbad75ddSKen Xue "Invalid config param %04x\n", param); 78325a853d0SKen Xue ret = -ENOTSUPP; 784dbad75ddSKen Xue } 785dbad75ddSKen Xue 786dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + pin*4); 787dbad75ddSKen Xue } 788229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 789dbad75ddSKen Xue 79025a853d0SKen Xue return ret; 791dbad75ddSKen Xue } 792dbad75ddSKen Xue 793dbad75ddSKen Xue static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, 794dbad75ddSKen Xue unsigned int group, 795dbad75ddSKen Xue unsigned long *config) 796dbad75ddSKen Xue { 797dbad75ddSKen Xue const unsigned *pins; 798dbad75ddSKen Xue unsigned npins; 799dbad75ddSKen Xue int ret; 800dbad75ddSKen Xue 801dbad75ddSKen Xue ret = amd_get_group_pins(pctldev, group, &pins, &npins); 802dbad75ddSKen Xue if (ret) 803dbad75ddSKen Xue return ret; 804dbad75ddSKen Xue 805dbad75ddSKen Xue if (amd_pinconf_get(pctldev, pins[0], config)) 806dbad75ddSKen Xue return -ENOTSUPP; 807dbad75ddSKen Xue 808dbad75ddSKen Xue return 0; 809dbad75ddSKen Xue } 810dbad75ddSKen Xue 811dbad75ddSKen Xue static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, 812dbad75ddSKen Xue unsigned group, unsigned long *configs, 813dbad75ddSKen Xue unsigned num_configs) 814dbad75ddSKen Xue { 815dbad75ddSKen Xue const unsigned *pins; 816dbad75ddSKen Xue unsigned npins; 817dbad75ddSKen Xue int i, ret; 818dbad75ddSKen Xue 819dbad75ddSKen Xue ret = amd_get_group_pins(pctldev, group, &pins, &npins); 820dbad75ddSKen Xue if (ret) 821dbad75ddSKen Xue return ret; 822dbad75ddSKen Xue for (i = 0; i < npins; i++) { 823dbad75ddSKen Xue if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) 824dbad75ddSKen Xue return -ENOTSUPP; 825dbad75ddSKen Xue } 826dbad75ddSKen Xue return 0; 827dbad75ddSKen Xue } 828dbad75ddSKen Xue 829dbad75ddSKen Xue static const struct pinconf_ops amd_pinconf_ops = { 830dbad75ddSKen Xue .pin_config_get = amd_pinconf_get, 831dbad75ddSKen Xue .pin_config_set = amd_pinconf_set, 832dbad75ddSKen Xue .pin_config_group_get = amd_pinconf_group_get, 833dbad75ddSKen Xue .pin_config_group_set = amd_pinconf_group_set, 834dbad75ddSKen Xue }; 835dbad75ddSKen Xue 83679d2c8beSDaniel Drake #ifdef CONFIG_PM_SLEEP 83779d2c8beSDaniel Drake static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) 83879d2c8beSDaniel Drake { 83979d2c8beSDaniel Drake const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 84079d2c8beSDaniel Drake 84179d2c8beSDaniel Drake if (!pd) 84279d2c8beSDaniel Drake return false; 84379d2c8beSDaniel Drake 84479d2c8beSDaniel Drake /* 84579d2c8beSDaniel Drake * Only restore the pin if it is actually in use by the kernel (or 84679d2c8beSDaniel Drake * by userspace). 84779d2c8beSDaniel Drake */ 84879d2c8beSDaniel Drake if (pd->mux_owner || pd->gpio_owner || 84979d2c8beSDaniel Drake gpiochip_line_is_irq(&gpio_dev->gc, pin)) 85079d2c8beSDaniel Drake return true; 85179d2c8beSDaniel Drake 85279d2c8beSDaniel Drake return false; 85379d2c8beSDaniel Drake } 85479d2c8beSDaniel Drake 8552d71dfa2SColin Ian King static int amd_gpio_suspend(struct device *dev) 85679d2c8beSDaniel Drake { 8579f540c3eSWolfram Sang struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 85879d2c8beSDaniel Drake struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 85979d2c8beSDaniel Drake int i; 86079d2c8beSDaniel Drake 86179d2c8beSDaniel Drake for (i = 0; i < desc->npins; i++) { 86279d2c8beSDaniel Drake int pin = desc->pins[i].number; 86379d2c8beSDaniel Drake 86479d2c8beSDaniel Drake if (!amd_gpio_should_save(gpio_dev, pin)) 86579d2c8beSDaniel Drake continue; 86679d2c8beSDaniel Drake 86779d2c8beSDaniel Drake gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin*4); 86879d2c8beSDaniel Drake } 86979d2c8beSDaniel Drake 87079d2c8beSDaniel Drake return 0; 87179d2c8beSDaniel Drake } 87279d2c8beSDaniel Drake 8732d71dfa2SColin Ian King static int amd_gpio_resume(struct device *dev) 87479d2c8beSDaniel Drake { 8759f540c3eSWolfram Sang struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 87679d2c8beSDaniel Drake struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 87779d2c8beSDaniel Drake int i; 87879d2c8beSDaniel Drake 87979d2c8beSDaniel Drake for (i = 0; i < desc->npins; i++) { 88079d2c8beSDaniel Drake int pin = desc->pins[i].number; 88179d2c8beSDaniel Drake 88279d2c8beSDaniel Drake if (!amd_gpio_should_save(gpio_dev, pin)) 88379d2c8beSDaniel Drake continue; 88479d2c8beSDaniel Drake 88579d2c8beSDaniel Drake writel(gpio_dev->saved_regs[i], gpio_dev->base + pin*4); 88679d2c8beSDaniel Drake } 88779d2c8beSDaniel Drake 88879d2c8beSDaniel Drake return 0; 88979d2c8beSDaniel Drake } 89079d2c8beSDaniel Drake 89179d2c8beSDaniel Drake static const struct dev_pm_ops amd_gpio_pm_ops = { 89279d2c8beSDaniel Drake SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend, 89379d2c8beSDaniel Drake amd_gpio_resume) 89479d2c8beSDaniel Drake }; 89579d2c8beSDaniel Drake #endif 89679d2c8beSDaniel Drake 897dbad75ddSKen Xue static struct pinctrl_desc amd_pinctrl_desc = { 898dbad75ddSKen Xue .pins = kerncz_pins, 899dbad75ddSKen Xue .npins = ARRAY_SIZE(kerncz_pins), 900dbad75ddSKen Xue .pctlops = &amd_pinctrl_ops, 901dbad75ddSKen Xue .confops = &amd_pinconf_ops, 902dbad75ddSKen Xue .owner = THIS_MODULE, 903dbad75ddSKen Xue }; 904dbad75ddSKen Xue 905dbad75ddSKen Xue static int amd_gpio_probe(struct platform_device *pdev) 906dbad75ddSKen Xue { 907dbad75ddSKen Xue int ret = 0; 90825a853d0SKen Xue int irq_base; 909dbad75ddSKen Xue struct resource *res; 910dbad75ddSKen Xue struct amd_gpio *gpio_dev; 911e81376ebSLinus Walleij struct gpio_irq_chip *girq; 912dbad75ddSKen Xue 913dbad75ddSKen Xue gpio_dev = devm_kzalloc(&pdev->dev, 914dbad75ddSKen Xue sizeof(struct amd_gpio), GFP_KERNEL); 915dbad75ddSKen Xue if (!gpio_dev) 916dbad75ddSKen Xue return -ENOMEM; 917dbad75ddSKen Xue 918229710feSJulia Cartwright raw_spin_lock_init(&gpio_dev->lock); 919dbad75ddSKen Xue 920dbad75ddSKen Xue res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 921dbad75ddSKen Xue if (!res) { 922dbad75ddSKen Xue dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); 923dbad75ddSKen Xue return -EINVAL; 924dbad75ddSKen Xue } 925dbad75ddSKen Xue 9264bdc0d67SChristoph Hellwig gpio_dev->base = devm_ioremap(&pdev->dev, res->start, 927dbad75ddSKen Xue resource_size(res)); 928424a6c60SWei Yongjun if (!gpio_dev->base) 929424a6c60SWei Yongjun return -ENOMEM; 930dbad75ddSKen Xue 931dbad75ddSKen Xue irq_base = platform_get_irq(pdev, 0); 93264c4dcbfSStephen Boyd if (irq_base < 0) 9332e6424abSGustavo A. R. Silva return irq_base; 934dbad75ddSKen Xue 93579d2c8beSDaniel Drake #ifdef CONFIG_PM_SLEEP 93679d2c8beSDaniel Drake gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins, 93779d2c8beSDaniel Drake sizeof(*gpio_dev->saved_regs), 93879d2c8beSDaniel Drake GFP_KERNEL); 93979d2c8beSDaniel Drake if (!gpio_dev->saved_regs) 94079d2c8beSDaniel Drake return -ENOMEM; 94179d2c8beSDaniel Drake #endif 94279d2c8beSDaniel Drake 943dbad75ddSKen Xue gpio_dev->pdev = pdev; 94412b10f47SDaniel Kurtz gpio_dev->gc.get_direction = amd_gpio_get_direction; 945dbad75ddSKen Xue gpio_dev->gc.direction_input = amd_gpio_direction_input; 946dbad75ddSKen Xue gpio_dev->gc.direction_output = amd_gpio_direction_output; 947dbad75ddSKen Xue gpio_dev->gc.get = amd_gpio_get_value; 948dbad75ddSKen Xue gpio_dev->gc.set = amd_gpio_set_value; 9492956b5d9SMika Westerberg gpio_dev->gc.set_config = amd_gpio_set_config; 950dbad75ddSKen Xue gpio_dev->gc.dbg_show = amd_gpio_dbg_show; 951dbad75ddSKen Xue 9523bfd4430SShah, Nehal-bakulchandra gpio_dev->gc.base = -1; 953dbad75ddSKen Xue gpio_dev->gc.label = pdev->name; 954dbad75ddSKen Xue gpio_dev->gc.owner = THIS_MODULE; 95558383c78SLinus Walleij gpio_dev->gc.parent = &pdev->dev; 9563bfd4430SShah, Nehal-bakulchandra gpio_dev->gc.ngpio = resource_size(res) / 4; 957dbad75ddSKen Xue #if defined(CONFIG_OF_GPIO) 958dbad75ddSKen Xue gpio_dev->gc.of_node = pdev->dev.of_node; 959dbad75ddSKen Xue #endif 960dbad75ddSKen Xue 9613bfd4430SShah, Nehal-bakulchandra gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64; 962dbad75ddSKen Xue gpio_dev->groups = kerncz_groups; 963dbad75ddSKen Xue gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); 964dbad75ddSKen Xue 965dbad75ddSKen Xue amd_pinctrl_desc.name = dev_name(&pdev->dev); 966251e22abSLaxman Dewangan gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, 967251e22abSLaxman Dewangan gpio_dev); 968323de9efSMasahiro Yamada if (IS_ERR(gpio_dev->pctrl)) { 969dbad75ddSKen Xue dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 970323de9efSMasahiro Yamada return PTR_ERR(gpio_dev->pctrl); 971dbad75ddSKen Xue } 972dbad75ddSKen Xue 973e81376ebSLinus Walleij girq = &gpio_dev->gc.irq; 974e81376ebSLinus Walleij girq->chip = &amd_gpio_irqchip; 975e81376ebSLinus Walleij /* This will let us handle the parent IRQ in the driver */ 976e81376ebSLinus Walleij girq->parent_handler = NULL; 977e81376ebSLinus Walleij girq->num_parents = 0; 978e81376ebSLinus Walleij girq->parents = NULL; 979e81376ebSLinus Walleij girq->default_type = IRQ_TYPE_NONE; 980e81376ebSLinus Walleij girq->handler = handle_simple_irq; 981e81376ebSLinus Walleij 98204d36723SLinus Walleij ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); 983dbad75ddSKen Xue if (ret) 984251e22abSLaxman Dewangan return ret; 985dbad75ddSKen Xue 986dbad75ddSKen Xue ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), 9873bfd4430SShah, Nehal-bakulchandra 0, 0, gpio_dev->gc.ngpio); 988dbad75ddSKen Xue if (ret) { 989dbad75ddSKen Xue dev_err(&pdev->dev, "Failed to add pin range\n"); 990dbad75ddSKen Xue goto out2; 991dbad75ddSKen Xue } 992dbad75ddSKen Xue 993279ffafaSSandeep Singh ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, 994279ffafaSSandeep Singh IRQF_SHARED, KBUILD_MODNAME, gpio_dev); 995ba714a9cSThomas Gleixner if (ret) 996ba714a9cSThomas Gleixner goto out2; 997ba714a9cSThomas Gleixner 998dbad75ddSKen Xue platform_set_drvdata(pdev, gpio_dev); 999dbad75ddSKen Xue 1000dbad75ddSKen Xue dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); 1001dbad75ddSKen Xue return ret; 1002dbad75ddSKen Xue 1003dbad75ddSKen Xue out2: 1004dbad75ddSKen Xue gpiochip_remove(&gpio_dev->gc); 1005dbad75ddSKen Xue 1006dbad75ddSKen Xue return ret; 1007dbad75ddSKen Xue } 1008dbad75ddSKen Xue 1009dbad75ddSKen Xue static int amd_gpio_remove(struct platform_device *pdev) 1010dbad75ddSKen Xue { 1011dbad75ddSKen Xue struct amd_gpio *gpio_dev; 1012dbad75ddSKen Xue 1013dbad75ddSKen Xue gpio_dev = platform_get_drvdata(pdev); 1014dbad75ddSKen Xue 1015dbad75ddSKen Xue gpiochip_remove(&gpio_dev->gc); 1016dbad75ddSKen Xue 1017dbad75ddSKen Xue return 0; 1018dbad75ddSKen Xue } 1019dbad75ddSKen Xue 1020de4334f7SLee Jones #ifdef CONFIG_ACPI 1021dbad75ddSKen Xue static const struct acpi_device_id amd_gpio_acpi_match[] = { 1022dbad75ddSKen Xue { "AMD0030", 0 }, 102342a44402SWang Hongcheng { "AMDI0030", 0}, 1024*1ca46d3eSMaximilian Luz { "AMDI0031", 0}, 1025dbad75ddSKen Xue { }, 1026dbad75ddSKen Xue }; 1027dbad75ddSKen Xue MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); 1028de4334f7SLee Jones #endif 1029dbad75ddSKen Xue 1030dbad75ddSKen Xue static struct platform_driver amd_gpio_driver = { 1031dbad75ddSKen Xue .driver = { 1032dbad75ddSKen Xue .name = "amd_gpio", 1033dbad75ddSKen Xue .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), 103479d2c8beSDaniel Drake #ifdef CONFIG_PM_SLEEP 103579d2c8beSDaniel Drake .pm = &amd_gpio_pm_ops, 103679d2c8beSDaniel Drake #endif 1037dbad75ddSKen Xue }, 1038dbad75ddSKen Xue .probe = amd_gpio_probe, 1039dbad75ddSKen Xue .remove = amd_gpio_remove, 1040dbad75ddSKen Xue }; 1041dbad75ddSKen Xue 1042dbad75ddSKen Xue module_platform_driver(amd_gpio_driver); 1043dbad75ddSKen Xue 1044dbad75ddSKen Xue MODULE_LICENSE("GPL v2"); 1045dbad75ddSKen Xue MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); 1046dbad75ddSKen Xue MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); 1047