175a6faf6SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2dbad75ddSKen Xue /*
3dbad75ddSKen Xue * GPIO driver for AMD
4dbad75ddSKen Xue *
5dbad75ddSKen Xue * Copyright (c) 2014,2015 AMD Corporation.
6dbad75ddSKen Xue * Authors: Ken Xue <Ken.Xue@amd.com>
7dbad75ddSKen Xue * Wu, Jeff <Jeff.Wu@amd.com>
8dbad75ddSKen Xue *
9dbad75ddSKen Xue */
10dbad75ddSKen Xue
11dbad75ddSKen Xue #include <linux/err.h>
12dbad75ddSKen Xue #include <linux/bug.h>
13dbad75ddSKen Xue #include <linux/kernel.h>
14dbad75ddSKen Xue #include <linux/module.h>
15dbad75ddSKen Xue #include <linux/spinlock.h>
16dbad75ddSKen Xue #include <linux/compiler.h>
17dbad75ddSKen Xue #include <linux/types.h>
18dbad75ddSKen Xue #include <linux/errno.h>
19dbad75ddSKen Xue #include <linux/log2.h>
20dbad75ddSKen Xue #include <linux/io.h>
211c5fb66aSLinus Walleij #include <linux/gpio/driver.h>
22dbad75ddSKen Xue #include <linux/slab.h>
23dbad75ddSKen Xue #include <linux/platform_device.h>
24dbad75ddSKen Xue #include <linux/mutex.h>
25dbad75ddSKen Xue #include <linux/acpi.h>
26dbad75ddSKen Xue #include <linux/seq_file.h>
27dbad75ddSKen Xue #include <linux/interrupt.h>
28dbad75ddSKen Xue #include <linux/list.h>
29dbad75ddSKen Xue #include <linux/bitops.h>
30dbad75ddSKen Xue #include <linux/pinctrl/pinconf.h>
31dbad75ddSKen Xue #include <linux/pinctrl/pinconf-generic.h>
3272440158SBasavaraj Natikar #include <linux/pinctrl/pinmux.h>
33c9a23641SMario Limonciello #include <linux/suspend.h>
34dbad75ddSKen Xue
3579d2c8beSDaniel Drake #include "core.h"
36dbad75ddSKen Xue #include "pinctrl-utils.h"
37dbad75ddSKen Xue #include "pinctrl-amd.h"
38dbad75ddSKen Xue
amd_gpio_get_direction(struct gpio_chip * gc,unsigned offset)3912b10f47SDaniel Kurtz static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
4012b10f47SDaniel Kurtz {
4112b10f47SDaniel Kurtz unsigned long flags;
4212b10f47SDaniel Kurtz u32 pin_reg;
4312b10f47SDaniel Kurtz struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
4412b10f47SDaniel Kurtz
4512b10f47SDaniel Kurtz raw_spin_lock_irqsave(&gpio_dev->lock, flags);
4612b10f47SDaniel Kurtz pin_reg = readl(gpio_dev->base + offset * 4);
4712b10f47SDaniel Kurtz raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
4812b10f47SDaniel Kurtz
493c827873SMatti Vaittinen if (pin_reg & BIT(OUTPUT_ENABLE_OFF))
503c827873SMatti Vaittinen return GPIO_LINE_DIRECTION_OUT;
513c827873SMatti Vaittinen
523c827873SMatti Vaittinen return GPIO_LINE_DIRECTION_IN;
5312b10f47SDaniel Kurtz }
5412b10f47SDaniel Kurtz
amd_gpio_direction_input(struct gpio_chip * gc,unsigned offset)55dbad75ddSKen Xue static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
56dbad75ddSKen Xue {
57dbad75ddSKen Xue unsigned long flags;
58dbad75ddSKen Xue u32 pin_reg;
5904d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
60dbad75ddSKen Xue
61229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags);
62dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4);
63dbad75ddSKen Xue pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
64dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4);
65229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
66dbad75ddSKen Xue
67dbad75ddSKen Xue return 0;
68dbad75ddSKen Xue }
69dbad75ddSKen Xue
amd_gpio_direction_output(struct gpio_chip * gc,unsigned offset,int value)70dbad75ddSKen Xue static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
71dbad75ddSKen Xue int value)
72dbad75ddSKen Xue {
73dbad75ddSKen Xue u32 pin_reg;
74dbad75ddSKen Xue unsigned long flags;
7504d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
76dbad75ddSKen Xue
77229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags);
78dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4);
79dbad75ddSKen Xue pin_reg |= BIT(OUTPUT_ENABLE_OFF);
80dbad75ddSKen Xue if (value)
81dbad75ddSKen Xue pin_reg |= BIT(OUTPUT_VALUE_OFF);
82dbad75ddSKen Xue else
83dbad75ddSKen Xue pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
84dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4);
85229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
86dbad75ddSKen Xue
87dbad75ddSKen Xue return 0;
88dbad75ddSKen Xue }
89dbad75ddSKen Xue
amd_gpio_get_value(struct gpio_chip * gc,unsigned offset)90dbad75ddSKen Xue static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
91dbad75ddSKen Xue {
92dbad75ddSKen Xue u32 pin_reg;
93dbad75ddSKen Xue unsigned long flags;
9404d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
95dbad75ddSKen Xue
96229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags);
97dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4);
98229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
99dbad75ddSKen Xue
100dbad75ddSKen Xue return !!(pin_reg & BIT(PIN_STS_OFF));
101dbad75ddSKen Xue }
102dbad75ddSKen Xue
amd_gpio_set_value(struct gpio_chip * gc,unsigned offset,int value)103dbad75ddSKen Xue static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
104dbad75ddSKen Xue {
105dbad75ddSKen Xue u32 pin_reg;
106dbad75ddSKen Xue unsigned long flags;
10704d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
108dbad75ddSKen Xue
109229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags);
110dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4);
111dbad75ddSKen Xue if (value)
112dbad75ddSKen Xue pin_reg |= BIT(OUTPUT_VALUE_OFF);
113dbad75ddSKen Xue else
114dbad75ddSKen Xue pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
115dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4);
116229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
117dbad75ddSKen Xue }
118dbad75ddSKen Xue
amd_gpio_set_debounce(struct amd_gpio * gpio_dev,unsigned int offset,unsigned int debounce)119283c5ce7SMario Limonciello static int amd_gpio_set_debounce(struct amd_gpio *gpio_dev, unsigned int offset,
120283c5ce7SMario Limonciello unsigned int debounce)
121dbad75ddSKen Xue {
122dbad75ddSKen Xue u32 time;
12325a853d0SKen Xue u32 pin_reg;
12425a853d0SKen Xue int ret = 0;
125968ab926SMario Limonciello
126968ab926SMario Limonciello /* Use special handling for Pin0 debounce */
1270d5ace1aSMario Limonciello if (offset == 0) {
128968ab926SMario Limonciello pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
129968ab926SMario Limonciello if (pin_reg & INTERNAL_GPIO0_DEBOUNCE)
130968ab926SMario Limonciello debounce = 0;
1310d5ace1aSMario Limonciello }
132968ab926SMario Limonciello
133dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + offset * 4);
134dbad75ddSKen Xue
135dbad75ddSKen Xue if (debounce) {
136dbad75ddSKen Xue pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
137dbad75ddSKen Xue pin_reg &= ~DB_TMR_OUT_MASK;
138dbad75ddSKen Xue /*
139dbad75ddSKen Xue Debounce Debounce Timer Max
140dbad75ddSKen Xue TmrLarge TmrOutUnit Unit Debounce
141dbad75ddSKen Xue Time
142dbad75ddSKen Xue 0 0 61 usec (2 RtcClk) 976 usec
143dbad75ddSKen Xue 0 1 244 usec (8 RtcClk) 3.9 msec
144dbad75ddSKen Xue 1 0 15.6 msec (512 RtcClk) 250 msec
145dbad75ddSKen Xue 1 1 62.5 msec (2048 RtcClk) 1 sec
146dbad75ddSKen Xue */
147dbad75ddSKen Xue
148dbad75ddSKen Xue if (debounce < 61) {
149dbad75ddSKen Xue pin_reg |= 1;
150dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
151dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
152dbad75ddSKen Xue } else if (debounce < 976) {
153dbad75ddSKen Xue time = debounce / 61;
154dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK;
155dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
156dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
157dbad75ddSKen Xue } else if (debounce < 3900) {
158dbad75ddSKen Xue time = debounce / 244;
159dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK;
160dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
161dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
162dbad75ddSKen Xue } else if (debounce < 250000) {
163c64a6a0dSCoiby Xu time = debounce / 15625;
164dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK;
165dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
166dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_LARGE_OFF);
167dbad75ddSKen Xue } else if (debounce < 1000000) {
168dbad75ddSKen Xue time = debounce / 62500;
169dbad75ddSKen Xue pin_reg |= time & DB_TMR_OUT_MASK;
170dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
171dbad75ddSKen Xue pin_reg |= BIT(DB_TMR_LARGE_OFF);
172dbad75ddSKen Xue } else {
17306abe829SCoiby Xu pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
17425a853d0SKen Xue ret = -EINVAL;
175dbad75ddSKen Xue }
176dbad75ddSKen Xue } else {
177dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
178dbad75ddSKen Xue pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
179dbad75ddSKen Xue pin_reg &= ~DB_TMR_OUT_MASK;
18006abe829SCoiby Xu pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
181dbad75ddSKen Xue }
182dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + offset * 4);
183dbad75ddSKen Xue
18425a853d0SKen Xue return ret;
185dbad75ddSKen Xue }
186dbad75ddSKen Xue
187dbad75ddSKen Xue #ifdef CONFIG_DEBUG_FS
amd_gpio_dbg_show(struct seq_file * s,struct gpio_chip * gc)188dbad75ddSKen Xue static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
189dbad75ddSKen Xue {
190dbad75ddSKen Xue u32 pin_reg;
19139cc1d33SCoiby Xu u32 db_cntrl;
192dbad75ddSKen Xue unsigned long flags;
193dbad75ddSKen Xue unsigned int bank, i, pin_num;
19404d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
195dbad75ddSKen Xue
19639cc1d33SCoiby Xu bool tmr_out_unit;
19739cc1d33SCoiby Xu bool tmr_large;
19839cc1d33SCoiby Xu
199dbad75ddSKen Xue char *level_trig;
200dbad75ddSKen Xue char *active_level;
201dbad75ddSKen Xue char *interrupt_mask;
202dbad75ddSKen Xue char *wake_cntrl0;
203dbad75ddSKen Xue char *wake_cntrl1;
204dbad75ddSKen Xue char *wake_cntrl2;
205dbad75ddSKen Xue char *pin_sts;
206010f493dSMario Limonciello char *interrupt_sts;
207010f493dSMario Limonciello char *wake_sts;
208e8129a07SMario Limonciello char *orientation;
20939cc1d33SCoiby Xu char debounce_value[40];
21039cc1d33SCoiby Xu char *debounce_enable;
211df72b4a6SBasavaraj Natikar char *wake_cntrlz;
212dbad75ddSKen Xue
213968ab926SMario Limonciello seq_printf(s, "WAKE_INT_MASTER_REG: 0x%08x\n", readl(gpio_dev->base + WAKE_INT_MASTER_REG));
2143bfd4430SShah, Nehal-bakulchandra for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {
215e8129a07SMario Limonciello unsigned int time = 0;
216e8129a07SMario Limonciello unsigned int unit = 0;
217dbad75ddSKen Xue
218dbad75ddSKen Xue switch (bank) {
219dbad75ddSKen Xue case 0:
220dbad75ddSKen Xue i = 0;
221dbad75ddSKen Xue pin_num = AMD_GPIO_PINS_BANK0;
222dbad75ddSKen Xue break;
223dbad75ddSKen Xue case 1:
224dbad75ddSKen Xue i = 64;
225dbad75ddSKen Xue pin_num = AMD_GPIO_PINS_BANK1 + i;
226dbad75ddSKen Xue break;
227dbad75ddSKen Xue case 2:
228dbad75ddSKen Xue i = 128;
229dbad75ddSKen Xue pin_num = AMD_GPIO_PINS_BANK2 + i;
230dbad75ddSKen Xue break;
2313bfd4430SShah, Nehal-bakulchandra case 3:
2323bfd4430SShah, Nehal-bakulchandra i = 192;
2333bfd4430SShah, Nehal-bakulchandra pin_num = AMD_GPIO_PINS_BANK3 + i;
2343bfd4430SShah, Nehal-bakulchandra break;
2356ac4c1adSLinus Walleij default:
2366ac4c1adSLinus Walleij /* Illegal bank number, ignore */
2376ac4c1adSLinus Walleij continue;
238dbad75ddSKen Xue }
239e8129a07SMario Limonciello seq_printf(s, "GPIO bank%d\n", bank);
24075358cf3SMario Limonciello seq_puts(s, "gpio\t int|active|trigger|S0i3| S3|S4/S5| Z|wake|pull| orient| debounce|reg\n");
241dbad75ddSKen Xue for (; i < pin_num; i++) {
24276e55d93SMario Limonciello seq_printf(s, "#%d\t", i);
243229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags);
244dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + i * 4);
245229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
246dbad75ddSKen Xue
247dbad75ddSKen Xue if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
2481766e4b7SDaniel Kurtz u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) &
2491766e4b7SDaniel Kurtz ACTIVE_LEVEL_MASK;
250dbad75ddSKen Xue
2511766e4b7SDaniel Kurtz if (level == ACTIVE_LEVEL_HIGH)
252e8129a07SMario Limonciello active_level = "↑";
2531766e4b7SDaniel Kurtz else if (level == ACTIVE_LEVEL_LOW)
254e8129a07SMario Limonciello active_level = "↓";
2551766e4b7SDaniel Kurtz else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) &&
2561766e4b7SDaniel Kurtz level == ACTIVE_LEVEL_BOTH)
257e8129a07SMario Limonciello active_level = "b";
258dbad75ddSKen Xue else
259e8129a07SMario Limonciello active_level = "?";
260dbad75ddSKen Xue
261dbad75ddSKen Xue if (pin_reg & BIT(LEVEL_TRIG_OFF))
262e8129a07SMario Limonciello level_trig = "level";
263dbad75ddSKen Xue else
264e8129a07SMario Limonciello level_trig = " edge";
265dbad75ddSKen Xue
266dbad75ddSKen Xue if (pin_reg & BIT(INTERRUPT_MASK_OFF))
26776e55d93SMario Limonciello interrupt_mask = "";
268dbad75ddSKen Xue else
26976e55d93SMario Limonciello interrupt_mask = "";
27075358cf3SMario Limonciello
271010f493dSMario Limonciello if (pin_reg & BIT(INTERRUPT_STS_OFF))
272010f493dSMario Limonciello interrupt_sts = "";
273010f493dSMario Limonciello else
274010f493dSMario Limonciello interrupt_sts = " ";
275010f493dSMario Limonciello
276010f493dSMario Limonciello seq_printf(s, "%s %s| %s| %s|",
277010f493dSMario Limonciello interrupt_sts,
278e8129a07SMario Limonciello interrupt_mask,
279e8129a07SMario Limonciello active_level,
280e8129a07SMario Limonciello level_trig);
28175358cf3SMario Limonciello } else
28275358cf3SMario Limonciello seq_puts(s, " ∅| | |");
283dbad75ddSKen Xue
2843bfd4430SShah, Nehal-bakulchandra if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3))
28576e55d93SMario Limonciello wake_cntrl0 = "⏰";
286dbad75ddSKen Xue else
28775358cf3SMario Limonciello wake_cntrl0 = " ";
28875358cf3SMario Limonciello seq_printf(s, " %s| ", wake_cntrl0);
289dbad75ddSKen Xue
2903bfd4430SShah, Nehal-bakulchandra if (pin_reg & BIT(WAKE_CNTRL_OFF_S3))
29176e55d93SMario Limonciello wake_cntrl1 = "⏰";
292dbad75ddSKen Xue else
29375358cf3SMario Limonciello wake_cntrl1 = " ";
29475358cf3SMario Limonciello seq_printf(s, "%s|", wake_cntrl1);
295dbad75ddSKen Xue
2963bfd4430SShah, Nehal-bakulchandra if (pin_reg & BIT(WAKE_CNTRL_OFF_S4))
29776e55d93SMario Limonciello wake_cntrl2 = "⏰";
298dbad75ddSKen Xue else
29975358cf3SMario Limonciello wake_cntrl2 = " ";
30075358cf3SMario Limonciello seq_printf(s, " %s|", wake_cntrl2);
301dbad75ddSKen Xue
302df72b4a6SBasavaraj Natikar if (pin_reg & BIT(WAKECNTRL_Z_OFF))
303df72b4a6SBasavaraj Natikar wake_cntrlz = "⏰";
304df72b4a6SBasavaraj Natikar else
30575358cf3SMario Limonciello wake_cntrlz = " ";
30675358cf3SMario Limonciello seq_printf(s, "%s|", wake_cntrlz);
307df72b4a6SBasavaraj Natikar
308010f493dSMario Limonciello if (pin_reg & BIT(WAKE_STS_OFF))
309010f493dSMario Limonciello wake_sts = "";
310010f493dSMario Limonciello else
311010f493dSMario Limonciello wake_sts = " ";
312010f493dSMario Limonciello seq_printf(s, " %s|", wake_sts);
313dbad75ddSKen Xue
314e8129a07SMario Limonciello if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
3153f62312dSMario Limonciello seq_puts(s, " ↑ |");
31675358cf3SMario Limonciello } else if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) {
31775358cf3SMario Limonciello seq_puts(s, " ↓ |");
31875358cf3SMario Limonciello } else {
31975358cf3SMario Limonciello seq_puts(s, " |");
32075358cf3SMario Limonciello }
321dbad75ddSKen Xue
322dbad75ddSKen Xue if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
323e8129a07SMario Limonciello pin_sts = "output";
324dbad75ddSKen Xue if (pin_reg & BIT(OUTPUT_VALUE_OFF))
325e8129a07SMario Limonciello orientation = "↑";
326dbad75ddSKen Xue else
327e8129a07SMario Limonciello orientation = "↓";
328dbad75ddSKen Xue } else {
329e8129a07SMario Limonciello pin_sts = "input ";
330dbad75ddSKen Xue if (pin_reg & BIT(PIN_STS_OFF))
331e8129a07SMario Limonciello orientation = "↑";
332dbad75ddSKen Xue else
333e8129a07SMario Limonciello orientation = "↓";
334dbad75ddSKen Xue }
335e8129a07SMario Limonciello seq_printf(s, "%s %s|", pin_sts, orientation);
336dbad75ddSKen Xue
33739cc1d33SCoiby Xu db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg;
33839cc1d33SCoiby Xu if (db_cntrl) {
33939cc1d33SCoiby Xu tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF);
34039cc1d33SCoiby Xu tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF);
34139cc1d33SCoiby Xu time = pin_reg & DB_TMR_OUT_MASK;
34239cc1d33SCoiby Xu if (tmr_large) {
34339cc1d33SCoiby Xu if (tmr_out_unit)
34439cc1d33SCoiby Xu unit = 62500;
34539cc1d33SCoiby Xu else
34639cc1d33SCoiby Xu unit = 15625;
34739cc1d33SCoiby Xu } else {
34839cc1d33SCoiby Xu if (tmr_out_unit)
34939cc1d33SCoiby Xu unit = 244;
35039cc1d33SCoiby Xu else
35139cc1d33SCoiby Xu unit = 61;
35239cc1d33SCoiby Xu }
35339cc1d33SCoiby Xu if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl)
35475358cf3SMario Limonciello debounce_enable = "b";
35539cc1d33SCoiby Xu else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl)
35675358cf3SMario Limonciello debounce_enable = "↓";
35739cc1d33SCoiby Xu else
35875358cf3SMario Limonciello debounce_enable = "↑";
35975358cf3SMario Limonciello snprintf(debounce_value, sizeof(debounce_value), "%06u", time * unit);
36075358cf3SMario Limonciello seq_printf(s, "%s ( %sus)|", debounce_enable, debounce_value);
36139cc1d33SCoiby Xu } else {
36275358cf3SMario Limonciello seq_puts(s, " |");
36339cc1d33SCoiby Xu }
364e8129a07SMario Limonciello seq_printf(s, "0x%x\n", pin_reg);
365dbad75ddSKen Xue }
366dbad75ddSKen Xue }
367dbad75ddSKen Xue }
368dbad75ddSKen Xue #else
369dbad75ddSKen Xue #define amd_gpio_dbg_show NULL
370dbad75ddSKen Xue #endif
371dbad75ddSKen Xue
amd_gpio_irq_enable(struct irq_data * d)372dbad75ddSKen Xue static void amd_gpio_irq_enable(struct irq_data *d)
373dbad75ddSKen Xue {
374dbad75ddSKen Xue u32 pin_reg;
375dbad75ddSKen Xue unsigned long flags;
376dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
37704d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
378dbad75ddSKen Xue
3796173e56fSMarc Zyngier gpiochip_enable_irq(gc, d->hwirq);
3806173e56fSMarc Zyngier
381229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags);
382dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
383dbad75ddSKen Xue pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
384dbad75ddSKen Xue pin_reg |= BIT(INTERRUPT_MASK_OFF);
385dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
386229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
387dbad75ddSKen Xue }
388dbad75ddSKen Xue
amd_gpio_irq_disable(struct irq_data * d)389dbad75ddSKen Xue static void amd_gpio_irq_disable(struct irq_data *d)
390dbad75ddSKen Xue {
391dbad75ddSKen Xue u32 pin_reg;
392dbad75ddSKen Xue unsigned long flags;
393dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
39404d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
395dbad75ddSKen Xue
396229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags);
397dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
398dbad75ddSKen Xue pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
399dbad75ddSKen Xue pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
400dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
401229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
4026173e56fSMarc Zyngier
4036173e56fSMarc Zyngier gpiochip_disable_irq(gc, d->hwirq);
404dbad75ddSKen Xue }
405dbad75ddSKen Xue
amd_gpio_irq_mask(struct irq_data * d)406dbad75ddSKen Xue static void amd_gpio_irq_mask(struct irq_data *d)
407dbad75ddSKen Xue {
408dbad75ddSKen Xue u32 pin_reg;
409dbad75ddSKen Xue unsigned long flags;
410dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
41104d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
412dbad75ddSKen Xue
413229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags);
414dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
415dbad75ddSKen Xue pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
416dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
417229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
418dbad75ddSKen Xue }
419dbad75ddSKen Xue
amd_gpio_irq_unmask(struct irq_data * d)420dbad75ddSKen Xue static void amd_gpio_irq_unmask(struct irq_data *d)
421dbad75ddSKen Xue {
422dbad75ddSKen Xue u32 pin_reg;
423dbad75ddSKen Xue unsigned long flags;
424dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
42504d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
426dbad75ddSKen Xue
427229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags);
428dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
429dbad75ddSKen Xue pin_reg |= BIT(INTERRUPT_MASK_OFF);
430dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
431229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
432dbad75ddSKen Xue }
433dbad75ddSKen Xue
amd_gpio_irq_set_wake(struct irq_data * d,unsigned int on)434d62bd5ceSRaul E Rangel static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
435d62bd5ceSRaul E Rangel {
436d62bd5ceSRaul E Rangel u32 pin_reg;
437d62bd5ceSRaul E Rangel unsigned long flags;
438d62bd5ceSRaul E Rangel struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
439d62bd5ceSRaul E Rangel struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
440c4b68e51SMario Limonciello u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3);
441acd47b9fSBasavaraj Natikar int err;
442d62bd5ceSRaul E Rangel
443d62bd5ceSRaul E Rangel raw_spin_lock_irqsave(&gpio_dev->lock, flags);
444d62bd5ceSRaul E Rangel pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
445d62bd5ceSRaul E Rangel
446d62bd5ceSRaul E Rangel if (on)
447d62bd5ceSRaul E Rangel pin_reg |= wake_mask;
448d62bd5ceSRaul E Rangel else
449d62bd5ceSRaul E Rangel pin_reg &= ~wake_mask;
450d62bd5ceSRaul E Rangel
451d62bd5ceSRaul E Rangel writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
452d62bd5ceSRaul E Rangel raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
453d62bd5ceSRaul E Rangel
454acd47b9fSBasavaraj Natikar if (on)
455acd47b9fSBasavaraj Natikar err = enable_irq_wake(gpio_dev->irq);
456acd47b9fSBasavaraj Natikar else
457acd47b9fSBasavaraj Natikar err = disable_irq_wake(gpio_dev->irq);
458acd47b9fSBasavaraj Natikar
459acd47b9fSBasavaraj Natikar if (err)
460acd47b9fSBasavaraj Natikar dev_err(&gpio_dev->pdev->dev, "failed to %s wake-up interrupt\n",
461acd47b9fSBasavaraj Natikar on ? "enable" : "disable");
462acd47b9fSBasavaraj Natikar
463d62bd5ceSRaul E Rangel return 0;
464d62bd5ceSRaul E Rangel }
465d62bd5ceSRaul E Rangel
amd_gpio_irq_eoi(struct irq_data * d)466dbad75ddSKen Xue static void amd_gpio_irq_eoi(struct irq_data *d)
467dbad75ddSKen Xue {
468dbad75ddSKen Xue u32 reg;
469dbad75ddSKen Xue unsigned long flags;
470dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
47104d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
472dbad75ddSKen Xue
473229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags);
474dbad75ddSKen Xue reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
475dbad75ddSKen Xue reg |= EOI_MASK;
476dbad75ddSKen Xue writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
477229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
478dbad75ddSKen Xue }
479dbad75ddSKen Xue
amd_gpio_irq_set_type(struct irq_data * d,unsigned int type)480dbad75ddSKen Xue static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
481dbad75ddSKen Xue {
482dbad75ddSKen Xue int ret = 0;
483b85bfa24SDaniel Kurtz u32 pin_reg, pin_reg_irq_en, mask;
4845f4962ddSFurquan Shaikh unsigned long flags;
485dbad75ddSKen Xue struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
48604d36723SLinus Walleij struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
487dbad75ddSKen Xue
488229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags);
489dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
490dbad75ddSKen Xue
491dbad75ddSKen Xue switch (type & IRQ_TYPE_SENSE_MASK) {
492dbad75ddSKen Xue case IRQ_TYPE_EDGE_RISING:
493dbad75ddSKen Xue pin_reg &= ~BIT(LEVEL_TRIG_OFF);
494dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
495dbad75ddSKen Xue pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
4969d829314SThomas Gleixner irq_set_handler_locked(d, handle_edge_irq);
497dbad75ddSKen Xue break;
498dbad75ddSKen Xue
499dbad75ddSKen Xue case IRQ_TYPE_EDGE_FALLING:
500dbad75ddSKen Xue pin_reg &= ~BIT(LEVEL_TRIG_OFF);
501dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
502dbad75ddSKen Xue pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
5039d829314SThomas Gleixner irq_set_handler_locked(d, handle_edge_irq);
504dbad75ddSKen Xue break;
505dbad75ddSKen Xue
506dbad75ddSKen Xue case IRQ_TYPE_EDGE_BOTH:
507dbad75ddSKen Xue pin_reg &= ~BIT(LEVEL_TRIG_OFF);
508dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
509dbad75ddSKen Xue pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
5109d829314SThomas Gleixner irq_set_handler_locked(d, handle_edge_irq);
511dbad75ddSKen Xue break;
512dbad75ddSKen Xue
513dbad75ddSKen Xue case IRQ_TYPE_LEVEL_HIGH:
514dbad75ddSKen Xue pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
515dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
516dbad75ddSKen Xue pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
5179d829314SThomas Gleixner irq_set_handler_locked(d, handle_level_irq);
518dbad75ddSKen Xue break;
519dbad75ddSKen Xue
520dbad75ddSKen Xue case IRQ_TYPE_LEVEL_LOW:
521dbad75ddSKen Xue pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
522dbad75ddSKen Xue pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
523dbad75ddSKen Xue pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
5249d829314SThomas Gleixner irq_set_handler_locked(d, handle_level_irq);
525dbad75ddSKen Xue break;
526dbad75ddSKen Xue
527dbad75ddSKen Xue case IRQ_TYPE_NONE:
528dbad75ddSKen Xue break;
529dbad75ddSKen Xue
530dbad75ddSKen Xue default:
531dbad75ddSKen Xue dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
532dbad75ddSKen Xue ret = -EINVAL;
533dbad75ddSKen Xue }
534dbad75ddSKen Xue
535dbad75ddSKen Xue pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
536b85bfa24SDaniel Kurtz /*
537b85bfa24SDaniel Kurtz * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the
538b85bfa24SDaniel Kurtz * debounce registers of any GPIO will block wake/interrupt status
53948c67f1fSMatteo Croce * generation for *all* GPIOs for a length of time that depends on
540b85bfa24SDaniel Kurtz * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the
541b85bfa24SDaniel Kurtz * INTERRUPT_ENABLE bit will read as 0.
542b85bfa24SDaniel Kurtz *
543b85bfa24SDaniel Kurtz * We temporarily enable irq for the GPIO whose configuration is
544b85bfa24SDaniel Kurtz * changing, and then wait for it to read back as 1 to know when
545b85bfa24SDaniel Kurtz * debounce has settled and then disable the irq again.
546b85bfa24SDaniel Kurtz * We do this polling with the spinlock held to ensure other GPIO
547b85bfa24SDaniel Kurtz * access routines do not read an incorrect value for the irq enable
548b85bfa24SDaniel Kurtz * bit of other GPIOs. We keep the GPIO masked while polling to avoid
549b85bfa24SDaniel Kurtz * spurious irqs, and disable the irq again after polling.
550b85bfa24SDaniel Kurtz */
551b85bfa24SDaniel Kurtz mask = BIT(INTERRUPT_ENABLE_OFF);
552b85bfa24SDaniel Kurtz pin_reg_irq_en = pin_reg;
553b85bfa24SDaniel Kurtz pin_reg_irq_en |= mask;
554b85bfa24SDaniel Kurtz pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF);
555b85bfa24SDaniel Kurtz writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4);
556b85bfa24SDaniel Kurtz while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask)
557b85bfa24SDaniel Kurtz continue;
558dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
559229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
560dbad75ddSKen Xue
561dbad75ddSKen Xue return ret;
562dbad75ddSKen Xue }
563dbad75ddSKen Xue
amd_irq_ack(struct irq_data * d)564dbad75ddSKen Xue static void amd_irq_ack(struct irq_data *d)
565dbad75ddSKen Xue {
566dbad75ddSKen Xue /*
567dbad75ddSKen Xue * based on HW design,there is no need to ack HW
568dbad75ddSKen Xue * before handle current irq. But this routine is
569dbad75ddSKen Xue * necessary for handle_edge_irq
570dbad75ddSKen Xue */
571dbad75ddSKen Xue }
572dbad75ddSKen Xue
5736173e56fSMarc Zyngier static const struct irq_chip amd_gpio_irqchip = {
574dbad75ddSKen Xue .name = "amd_gpio",
575dbad75ddSKen Xue .irq_ack = amd_irq_ack,
576dbad75ddSKen Xue .irq_enable = amd_gpio_irq_enable,
577dbad75ddSKen Xue .irq_disable = amd_gpio_irq_disable,
578dbad75ddSKen Xue .irq_mask = amd_gpio_irq_mask,
579dbad75ddSKen Xue .irq_unmask = amd_gpio_irq_unmask,
580d62bd5ceSRaul E Rangel .irq_set_wake = amd_gpio_irq_set_wake,
581dbad75ddSKen Xue .irq_eoi = amd_gpio_irq_eoi,
582dbad75ddSKen Xue .irq_set_type = amd_gpio_irq_set_type,
583d62bd5ceSRaul E Rangel /*
584d62bd5ceSRaul E Rangel * We need to set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND so that a wake event
585d62bd5ceSRaul E Rangel * also generates an IRQ. We need the IRQ so the irq_handler can clear
586d62bd5ceSRaul E Rangel * the wake event. Otherwise the wake event will never clear and
587d62bd5ceSRaul E Rangel * prevent the system from suspending.
588d62bd5ceSRaul E Rangel */
5896173e56fSMarc Zyngier .flags = IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND | IRQCHIP_IMMUTABLE,
5906173e56fSMarc Zyngier GPIOCHIP_IRQ_RESOURCE_HELPERS,
591dbad75ddSKen Xue };
592dbad75ddSKen Xue
593ba714a9cSThomas Gleixner #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF))
594ba714a9cSThomas Gleixner
do_amd_gpio_irq_handler(int irq,void * dev_id)5952d54067fSMario Limonciello static bool do_amd_gpio_irq_handler(int irq, void *dev_id)
596dbad75ddSKen Xue {
597ba714a9cSThomas Gleixner struct amd_gpio *gpio_dev = dev_id;
598ba714a9cSThomas Gleixner struct gpio_chip *gc = &gpio_dev->gc;
599ba714a9cSThomas Gleixner unsigned int i, irqnr;
600dbad75ddSKen Xue unsigned long flags;
60110ff58aaSBen Dooks (Codethink) u32 __iomem *regs;
6022d54067fSMario Limonciello bool ret = false;
60310ff58aaSBen Dooks (Codethink) u32 regval;
604ba714a9cSThomas Gleixner u64 status, mask;
605dbad75ddSKen Xue
606ba714a9cSThomas Gleixner /* Read the wake status */
607229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags);
608ba714a9cSThomas Gleixner status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
609ba714a9cSThomas Gleixner status <<= 32;
610ba714a9cSThomas Gleixner status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
611229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
612dbad75ddSKen Xue
613ba714a9cSThomas Gleixner /* Bit 0-45 contain the relevant status bits */
614ba714a9cSThomas Gleixner status &= (1ULL << 46) - 1;
615ba714a9cSThomas Gleixner regs = gpio_dev->base;
616ba714a9cSThomas Gleixner for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) {
617ba714a9cSThomas Gleixner if (!(status & mask))
618ba714a9cSThomas Gleixner continue;
619ba714a9cSThomas Gleixner status &= ~mask;
620ba714a9cSThomas Gleixner
621ba714a9cSThomas Gleixner /* Each status bit covers four pins */
622dbad75ddSKen Xue for (i = 0; i < 4; i++) {
623ba714a9cSThomas Gleixner regval = readl(regs + i);
6241d66e379SMario Limonciello
6251d66e379SMario Limonciello if (regval & PIN_IRQ_PENDING)
626c9a23641SMario Limonciello pm_pr_dbg("GPIO %d is active: 0x%x",
6272d54067fSMario Limonciello irqnr + i, regval);
6281d66e379SMario Limonciello
6291d66e379SMario Limonciello /* caused wake on resume context for shared IRQ */
6301d66e379SMario Limonciello if (irq < 0 && (regval & BIT(WAKE_STS_OFF)))
6312d54067fSMario Limonciello return true;
6322d54067fSMario Limonciello
6338bbed1eeSDaniel Kurtz if (!(regval & PIN_IRQ_PENDING) ||
6348bbed1eeSDaniel Kurtz !(regval & BIT(INTERRUPT_MASK_OFF)))
635ba714a9cSThomas Gleixner continue;
636f460c701SSebastian Andrzej Siewior generic_handle_domain_irq_safe(gc->irq.domain, irqnr + i);
6376afb1026SDaniel Drake
6386afb1026SDaniel Drake /* Clear interrupt.
6396afb1026SDaniel Drake * We must read the pin register again, in case the
6406afb1026SDaniel Drake * value was changed while executing
641a9cb09b7SMarc Zyngier * generic_handle_domain_irq() above.
6420cf9e48fSKornel Dulęba * If the line is not an irq, disable it in order to
6430cf9e48fSKornel Dulęba * avoid a system hang caused by an interrupt storm.
6446afb1026SDaniel Drake */
6456afb1026SDaniel Drake raw_spin_lock_irqsave(&gpio_dev->lock, flags);
6466afb1026SDaniel Drake regval = readl(regs + i);
6470cf9e48fSKornel Dulęba if (!gpiochip_line_is_irq(gc, irqnr + i)) {
6480cf9e48fSKornel Dulęba regval &= ~BIT(INTERRUPT_MASK_OFF);
649d21b8adbSDaniel Drake dev_dbg(&gpio_dev->pdev->dev,
650d21b8adbSDaniel Drake "Disabling spurious GPIO IRQ %d\n",
651d21b8adbSDaniel Drake irqnr + i);
6520cf9e48fSKornel Dulęba } else {
6530cf9e48fSKornel Dulęba ret = true;
654d21b8adbSDaniel Drake }
655ba714a9cSThomas Gleixner writel(regval, regs + i);
6566afb1026SDaniel Drake raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
657dbad75ddSKen Xue }
658dbad75ddSKen Xue }
6592d54067fSMario Limonciello /* did not cause wake on resume context for shared IRQ */
6602d54067fSMario Limonciello if (irq < 0)
6612d54067fSMario Limonciello return false;
662dbad75ddSKen Xue
663ba714a9cSThomas Gleixner /* Signal EOI to the GPIO unit */
664229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags);
665ba714a9cSThomas Gleixner regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
666ba714a9cSThomas Gleixner regval |= EOI_MASK;
667ba714a9cSThomas Gleixner writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG);
668229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
669dbad75ddSKen Xue
670ba714a9cSThomas Gleixner return ret;
671dbad75ddSKen Xue }
672dbad75ddSKen Xue
amd_gpio_irq_handler(int irq,void * dev_id)6732d54067fSMario Limonciello static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
6742d54067fSMario Limonciello {
6752d54067fSMario Limonciello return IRQ_RETVAL(do_amd_gpio_irq_handler(irq, dev_id));
6762d54067fSMario Limonciello }
6772d54067fSMario Limonciello
amd_gpio_check_wake(void * dev_id)6782d54067fSMario Limonciello static bool __maybe_unused amd_gpio_check_wake(void *dev_id)
6792d54067fSMario Limonciello {
6802d54067fSMario Limonciello return do_amd_gpio_irq_handler(-1, dev_id);
6812d54067fSMario Limonciello }
6822d54067fSMario Limonciello
amd_get_groups_count(struct pinctrl_dev * pctldev)683dbad75ddSKen Xue static int amd_get_groups_count(struct pinctrl_dev *pctldev)
684dbad75ddSKen Xue {
685dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
686dbad75ddSKen Xue
687dbad75ddSKen Xue return gpio_dev->ngroups;
688dbad75ddSKen Xue }
689dbad75ddSKen Xue
amd_get_group_name(struct pinctrl_dev * pctldev,unsigned group)690dbad75ddSKen Xue static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
691dbad75ddSKen Xue unsigned group)
692dbad75ddSKen Xue {
693dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
694dbad75ddSKen Xue
695dbad75ddSKen Xue return gpio_dev->groups[group].name;
696dbad75ddSKen Xue }
697dbad75ddSKen Xue
amd_get_group_pins(struct pinctrl_dev * pctldev,unsigned group,const unsigned ** pins,unsigned * num_pins)698dbad75ddSKen Xue static int amd_get_group_pins(struct pinctrl_dev *pctldev,
699dbad75ddSKen Xue unsigned group,
700dbad75ddSKen Xue const unsigned **pins,
701dbad75ddSKen Xue unsigned *num_pins)
702dbad75ddSKen Xue {
703dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
704dbad75ddSKen Xue
705dbad75ddSKen Xue *pins = gpio_dev->groups[group].pins;
706dbad75ddSKen Xue *num_pins = gpio_dev->groups[group].npins;
707dbad75ddSKen Xue return 0;
708dbad75ddSKen Xue }
709dbad75ddSKen Xue
710dbad75ddSKen Xue static const struct pinctrl_ops amd_pinctrl_ops = {
711dbad75ddSKen Xue .get_groups_count = amd_get_groups_count,
712dbad75ddSKen Xue .get_group_name = amd_get_group_name,
713dbad75ddSKen Xue .get_group_pins = amd_get_group_pins,
714dbad75ddSKen Xue #ifdef CONFIG_OF
715dbad75ddSKen Xue .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
716d32f7fd3SIrina Tirdea .dt_free_map = pinctrl_utils_free_map,
717dbad75ddSKen Xue #endif
718dbad75ddSKen Xue };
719dbad75ddSKen Xue
amd_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)720dbad75ddSKen Xue static int amd_pinconf_get(struct pinctrl_dev *pctldev,
721dbad75ddSKen Xue unsigned int pin,
722dbad75ddSKen Xue unsigned long *config)
723dbad75ddSKen Xue {
724dbad75ddSKen Xue u32 pin_reg;
725dbad75ddSKen Xue unsigned arg;
726dbad75ddSKen Xue unsigned long flags;
727dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
728dbad75ddSKen Xue enum pin_config_param param = pinconf_to_config_param(*config);
729dbad75ddSKen Xue
730229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags);
731dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + pin*4);
732229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
733dbad75ddSKen Xue switch (param) {
734dbad75ddSKen Xue case PIN_CONFIG_INPUT_DEBOUNCE:
735dbad75ddSKen Xue arg = pin_reg & DB_TMR_OUT_MASK;
736dbad75ddSKen Xue break;
737dbad75ddSKen Xue
738dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_DOWN:
739dbad75ddSKen Xue arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
740dbad75ddSKen Xue break;
741dbad75ddSKen Xue
742dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_UP:
7433f62312dSMario Limonciello arg = (pin_reg >> PULL_UP_ENABLE_OFF) & BIT(0);
744dbad75ddSKen Xue break;
745dbad75ddSKen Xue
746dbad75ddSKen Xue case PIN_CONFIG_DRIVE_STRENGTH:
747dbad75ddSKen Xue arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
748dbad75ddSKen Xue break;
749dbad75ddSKen Xue
750dbad75ddSKen Xue default:
75187b549efSMario Limonciello dev_dbg(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
752dbad75ddSKen Xue param);
753dbad75ddSKen Xue return -ENOTSUPP;
754dbad75ddSKen Xue }
755dbad75ddSKen Xue
756dbad75ddSKen Xue *config = pinconf_to_config_packed(param, arg);
757dbad75ddSKen Xue
758dbad75ddSKen Xue return 0;
759dbad75ddSKen Xue }
760dbad75ddSKen Xue
amd_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)761dbad75ddSKen Xue static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
762635a750dSMario Limonciello unsigned long *configs, unsigned int num_configs)
763dbad75ddSKen Xue {
764dbad75ddSKen Xue int i;
765dbad75ddSKen Xue u32 arg;
76625a853d0SKen Xue int ret = 0;
76725a853d0SKen Xue u32 pin_reg;
768dbad75ddSKen Xue unsigned long flags;
769dbad75ddSKen Xue enum pin_config_param param;
770dbad75ddSKen Xue struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
771dbad75ddSKen Xue
772229710feSJulia Cartwright raw_spin_lock_irqsave(&gpio_dev->lock, flags);
773dbad75ddSKen Xue for (i = 0; i < num_configs; i++) {
774dbad75ddSKen Xue param = pinconf_to_config_param(configs[i]);
775dbad75ddSKen Xue arg = pinconf_to_config_argument(configs[i]);
776dbad75ddSKen Xue pin_reg = readl(gpio_dev->base + pin*4);
777dbad75ddSKen Xue
778dbad75ddSKen Xue switch (param) {
779dbad75ddSKen Xue case PIN_CONFIG_INPUT_DEBOUNCE:
780283c5ce7SMario Limonciello ret = amd_gpio_set_debounce(gpio_dev, pin, arg);
781283c5ce7SMario Limonciello goto out_unlock;
782dbad75ddSKen Xue
783dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_DOWN:
784dbad75ddSKen Xue pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
785dbad75ddSKen Xue pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
786dbad75ddSKen Xue break;
787dbad75ddSKen Xue
788dbad75ddSKen Xue case PIN_CONFIG_BIAS_PULL_UP:
789dbad75ddSKen Xue pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
7903f62312dSMario Limonciello pin_reg |= (arg & BIT(0)) << PULL_UP_ENABLE_OFF;
791dbad75ddSKen Xue break;
792dbad75ddSKen Xue
793dbad75ddSKen Xue case PIN_CONFIG_DRIVE_STRENGTH:
794dbad75ddSKen Xue pin_reg &= ~(DRV_STRENGTH_SEL_MASK
795dbad75ddSKen Xue << DRV_STRENGTH_SEL_OFF);
796dbad75ddSKen Xue pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
797dbad75ddSKen Xue << DRV_STRENGTH_SEL_OFF;
798dbad75ddSKen Xue break;
799dbad75ddSKen Xue
800dbad75ddSKen Xue default:
80187b549efSMario Limonciello dev_dbg(&gpio_dev->pdev->dev,
802dbad75ddSKen Xue "Invalid config param %04x\n", param);
80325a853d0SKen Xue ret = -ENOTSUPP;
804dbad75ddSKen Xue }
805dbad75ddSKen Xue
806dbad75ddSKen Xue writel(pin_reg, gpio_dev->base + pin*4);
807dbad75ddSKen Xue }
808283c5ce7SMario Limonciello out_unlock:
809229710feSJulia Cartwright raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
810dbad75ddSKen Xue
81125a853d0SKen Xue return ret;
812dbad75ddSKen Xue }
813dbad75ddSKen Xue
amd_pinconf_group_get(struct pinctrl_dev * pctldev,unsigned int group,unsigned long * config)814dbad75ddSKen Xue static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
815dbad75ddSKen Xue unsigned int group,
816dbad75ddSKen Xue unsigned long *config)
817dbad75ddSKen Xue {
818dbad75ddSKen Xue const unsigned *pins;
819dbad75ddSKen Xue unsigned npins;
820dbad75ddSKen Xue int ret;
821dbad75ddSKen Xue
822dbad75ddSKen Xue ret = amd_get_group_pins(pctldev, group, &pins, &npins);
823dbad75ddSKen Xue if (ret)
824dbad75ddSKen Xue return ret;
825dbad75ddSKen Xue
826dbad75ddSKen Xue if (amd_pinconf_get(pctldev, pins[0], config))
827dbad75ddSKen Xue return -ENOTSUPP;
828dbad75ddSKen Xue
829dbad75ddSKen Xue return 0;
830dbad75ddSKen Xue }
831dbad75ddSKen Xue
amd_pinconf_group_set(struct pinctrl_dev * pctldev,unsigned group,unsigned long * configs,unsigned num_configs)832dbad75ddSKen Xue static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
833dbad75ddSKen Xue unsigned group, unsigned long *configs,
834dbad75ddSKen Xue unsigned num_configs)
835dbad75ddSKen Xue {
836dbad75ddSKen Xue const unsigned *pins;
837dbad75ddSKen Xue unsigned npins;
838dbad75ddSKen Xue int i, ret;
839dbad75ddSKen Xue
840dbad75ddSKen Xue ret = amd_get_group_pins(pctldev, group, &pins, &npins);
841dbad75ddSKen Xue if (ret)
842dbad75ddSKen Xue return ret;
843dbad75ddSKen Xue for (i = 0; i < npins; i++) {
844dbad75ddSKen Xue if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
845dbad75ddSKen Xue return -ENOTSUPP;
846dbad75ddSKen Xue }
847dbad75ddSKen Xue return 0;
848dbad75ddSKen Xue }
849dbad75ddSKen Xue
amd_gpio_set_config(struct gpio_chip * gc,unsigned int pin,unsigned long config)850635a750dSMario Limonciello static int amd_gpio_set_config(struct gpio_chip *gc, unsigned int pin,
851635a750dSMario Limonciello unsigned long config)
852635a750dSMario Limonciello {
853635a750dSMario Limonciello struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
854635a750dSMario Limonciello
855635a750dSMario Limonciello return amd_pinconf_set(gpio_dev->pctrl, pin, &config, 1);
856635a750dSMario Limonciello }
857635a750dSMario Limonciello
858dbad75ddSKen Xue static const struct pinconf_ops amd_pinconf_ops = {
859dbad75ddSKen Xue .pin_config_get = amd_pinconf_get,
860dbad75ddSKen Xue .pin_config_set = amd_pinconf_set,
861dbad75ddSKen Xue .pin_config_group_get = amd_pinconf_group_get,
862dbad75ddSKen Xue .pin_config_group_set = amd_pinconf_group_set,
863dbad75ddSKen Xue };
864dbad75ddSKen Xue
amd_gpio_irq_init(struct amd_gpio * gpio_dev)8656bc3462aSMario Limonciello static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)
8666bc3462aSMario Limonciello {
8676bc3462aSMario Limonciello struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
8686bc3462aSMario Limonciello unsigned long flags;
8696bc3462aSMario Limonciello u32 pin_reg, mask;
8706bc3462aSMario Limonciello int i;
8716bc3462aSMario Limonciello
8726bc3462aSMario Limonciello mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) |
8736bc3462aSMario Limonciello BIT(WAKE_CNTRL_OFF_S4);
8746bc3462aSMario Limonciello
8756bc3462aSMario Limonciello for (i = 0; i < desc->npins; i++) {
8766bc3462aSMario Limonciello int pin = desc->pins[i].number;
8776bc3462aSMario Limonciello const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
8786bc3462aSMario Limonciello
8796bc3462aSMario Limonciello if (!pd)
8806bc3462aSMario Limonciello continue;
8816bc3462aSMario Limonciello
8826bc3462aSMario Limonciello raw_spin_lock_irqsave(&gpio_dev->lock, flags);
8836bc3462aSMario Limonciello
8846bc3462aSMario Limonciello pin_reg = readl(gpio_dev->base + pin * 4);
8856bc3462aSMario Limonciello pin_reg &= ~mask;
8866bc3462aSMario Limonciello writel(pin_reg, gpio_dev->base + pin * 4);
8876bc3462aSMario Limonciello
8886bc3462aSMario Limonciello raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
8896bc3462aSMario Limonciello }
8906bc3462aSMario Limonciello }
8916bc3462aSMario Limonciello
89279d2c8beSDaniel Drake #ifdef CONFIG_PM_SLEEP
amd_gpio_should_save(struct amd_gpio * gpio_dev,unsigned int pin)89379d2c8beSDaniel Drake static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
89479d2c8beSDaniel Drake {
89579d2c8beSDaniel Drake const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
89679d2c8beSDaniel Drake
89779d2c8beSDaniel Drake if (!pd)
89879d2c8beSDaniel Drake return false;
89979d2c8beSDaniel Drake
90079d2c8beSDaniel Drake /*
90179d2c8beSDaniel Drake * Only restore the pin if it is actually in use by the kernel (or
90279d2c8beSDaniel Drake * by userspace).
90379d2c8beSDaniel Drake */
90479d2c8beSDaniel Drake if (pd->mux_owner || pd->gpio_owner ||
90579d2c8beSDaniel Drake gpiochip_line_is_irq(&gpio_dev->gc, pin))
90679d2c8beSDaniel Drake return true;
90779d2c8beSDaniel Drake
90879d2c8beSDaniel Drake return false;
90979d2c8beSDaniel Drake }
91079d2c8beSDaniel Drake
amd_gpio_suspend(struct device * dev)9112d71dfa2SColin Ian King static int amd_gpio_suspend(struct device *dev)
91279d2c8beSDaniel Drake {
9139f540c3eSWolfram Sang struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
91479d2c8beSDaniel Drake struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
915b8c824a8SBasavaraj Natikar unsigned long flags;
91679d2c8beSDaniel Drake int i;
91779d2c8beSDaniel Drake
91879d2c8beSDaniel Drake for (i = 0; i < desc->npins; i++) {
91979d2c8beSDaniel Drake int pin = desc->pins[i].number;
92079d2c8beSDaniel Drake
92179d2c8beSDaniel Drake if (!amd_gpio_should_save(gpio_dev, pin))
92279d2c8beSDaniel Drake continue;
92379d2c8beSDaniel Drake
924b8c824a8SBasavaraj Natikar raw_spin_lock_irqsave(&gpio_dev->lock, flags);
925b8c824a8SBasavaraj Natikar gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING;
926*a2af708bSMario Limonciello
927*a2af708bSMario Limonciello /* mask any interrupts not intended to be a wake source */
928*a2af708bSMario Limonciello if (!(gpio_dev->saved_regs[i] & WAKE_SOURCE)) {
929*a2af708bSMario Limonciello writel(gpio_dev->saved_regs[i] & ~BIT(INTERRUPT_MASK_OFF),
930*a2af708bSMario Limonciello gpio_dev->base + pin * 4);
931*a2af708bSMario Limonciello pm_pr_dbg("Disabling GPIO #%d interrupt for suspend.\n",
932*a2af708bSMario Limonciello pin);
933*a2af708bSMario Limonciello }
934*a2af708bSMario Limonciello
935b8c824a8SBasavaraj Natikar raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
93679d2c8beSDaniel Drake }
93779d2c8beSDaniel Drake
93879d2c8beSDaniel Drake return 0;
93979d2c8beSDaniel Drake }
94079d2c8beSDaniel Drake
amd_gpio_resume(struct device * dev)9412d71dfa2SColin Ian King static int amd_gpio_resume(struct device *dev)
94279d2c8beSDaniel Drake {
9439f540c3eSWolfram Sang struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
94479d2c8beSDaniel Drake struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
945b8c824a8SBasavaraj Natikar unsigned long flags;
94679d2c8beSDaniel Drake int i;
94779d2c8beSDaniel Drake
94879d2c8beSDaniel Drake for (i = 0; i < desc->npins; i++) {
94979d2c8beSDaniel Drake int pin = desc->pins[i].number;
95079d2c8beSDaniel Drake
95179d2c8beSDaniel Drake if (!amd_gpio_should_save(gpio_dev, pin))
95279d2c8beSDaniel Drake continue;
95379d2c8beSDaniel Drake
954b8c824a8SBasavaraj Natikar raw_spin_lock_irqsave(&gpio_dev->lock, flags);
955b8c824a8SBasavaraj Natikar gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING;
95679d2c8beSDaniel Drake writel(gpio_dev->saved_regs[i], gpio_dev->base + pin * 4);
957b8c824a8SBasavaraj Natikar raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
95879d2c8beSDaniel Drake }
95979d2c8beSDaniel Drake
96079d2c8beSDaniel Drake return 0;
96179d2c8beSDaniel Drake }
96279d2c8beSDaniel Drake
96379d2c8beSDaniel Drake static const struct dev_pm_ops amd_gpio_pm_ops = {
96479d2c8beSDaniel Drake SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend,
96579d2c8beSDaniel Drake amd_gpio_resume)
96679d2c8beSDaniel Drake };
96779d2c8beSDaniel Drake #endif
96879d2c8beSDaniel Drake
amd_get_functions_count(struct pinctrl_dev * pctldev)96972440158SBasavaraj Natikar static int amd_get_functions_count(struct pinctrl_dev *pctldev)
97072440158SBasavaraj Natikar {
97172440158SBasavaraj Natikar return ARRAY_SIZE(pmx_functions);
97272440158SBasavaraj Natikar }
97372440158SBasavaraj Natikar
amd_get_fname(struct pinctrl_dev * pctrldev,unsigned int selector)97472440158SBasavaraj Natikar static const char *amd_get_fname(struct pinctrl_dev *pctrldev, unsigned int selector)
97572440158SBasavaraj Natikar {
97672440158SBasavaraj Natikar return pmx_functions[selector].name;
97772440158SBasavaraj Natikar }
97872440158SBasavaraj Natikar
amd_get_groups(struct pinctrl_dev * pctrldev,unsigned int selector,const char * const ** groups,unsigned int * const num_groups)97972440158SBasavaraj Natikar static int amd_get_groups(struct pinctrl_dev *pctrldev, unsigned int selector,
98072440158SBasavaraj Natikar const char * const **groups,
98172440158SBasavaraj Natikar unsigned int * const num_groups)
98272440158SBasavaraj Natikar {
98372440158SBasavaraj Natikar struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev);
98472440158SBasavaraj Natikar
98572440158SBasavaraj Natikar if (!gpio_dev->iomux_base) {
98672440158SBasavaraj Natikar dev_err(&gpio_dev->pdev->dev, "iomux function %d group not supported\n", selector);
98772440158SBasavaraj Natikar return -EINVAL;
98872440158SBasavaraj Natikar }
98972440158SBasavaraj Natikar
99072440158SBasavaraj Natikar *groups = pmx_functions[selector].groups;
99172440158SBasavaraj Natikar *num_groups = pmx_functions[selector].ngroups;
99272440158SBasavaraj Natikar return 0;
99372440158SBasavaraj Natikar }
99472440158SBasavaraj Natikar
amd_set_mux(struct pinctrl_dev * pctrldev,unsigned int function,unsigned int group)99572440158SBasavaraj Natikar static int amd_set_mux(struct pinctrl_dev *pctrldev, unsigned int function, unsigned int group)
99672440158SBasavaraj Natikar {
99772440158SBasavaraj Natikar struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev);
99872440158SBasavaraj Natikar struct device *dev = &gpio_dev->pdev->dev;
99972440158SBasavaraj Natikar struct pin_desc *pd;
100072440158SBasavaraj Natikar int ind, index;
100172440158SBasavaraj Natikar
100272440158SBasavaraj Natikar if (!gpio_dev->iomux_base)
100372440158SBasavaraj Natikar return -EINVAL;
100472440158SBasavaraj Natikar
100572440158SBasavaraj Natikar for (index = 0; index < NSELECTS; index++) {
100672440158SBasavaraj Natikar if (strcmp(gpio_dev->groups[group].name, pmx_functions[function].groups[index]))
100772440158SBasavaraj Natikar continue;
100872440158SBasavaraj Natikar
100972440158SBasavaraj Natikar if (readb(gpio_dev->iomux_base + pmx_functions[function].index) ==
101072440158SBasavaraj Natikar FUNCTION_INVALID) {
101172440158SBasavaraj Natikar dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n",
101272440158SBasavaraj Natikar pmx_functions[function].index);
101372440158SBasavaraj Natikar return -EINVAL;
101472440158SBasavaraj Natikar }
101572440158SBasavaraj Natikar
101672440158SBasavaraj Natikar writeb(index, gpio_dev->iomux_base + pmx_functions[function].index);
101772440158SBasavaraj Natikar
101872440158SBasavaraj Natikar if (index != (readb(gpio_dev->iomux_base + pmx_functions[function].index) &
101972440158SBasavaraj Natikar FUNCTION_MASK)) {
102072440158SBasavaraj Natikar dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n",
102172440158SBasavaraj Natikar pmx_functions[function].index);
102272440158SBasavaraj Natikar return -EINVAL;
102372440158SBasavaraj Natikar }
102472440158SBasavaraj Natikar
102572440158SBasavaraj Natikar for (ind = 0; ind < gpio_dev->groups[group].npins; ind++) {
102672440158SBasavaraj Natikar if (strncmp(gpio_dev->groups[group].name, "IMX_F", strlen("IMX_F")))
102772440158SBasavaraj Natikar continue;
102872440158SBasavaraj Natikar
102972440158SBasavaraj Natikar pd = pin_desc_get(gpio_dev->pctrl, gpio_dev->groups[group].pins[ind]);
103072440158SBasavaraj Natikar pd->mux_owner = gpio_dev->groups[group].name;
103172440158SBasavaraj Natikar }
103272440158SBasavaraj Natikar break;
103372440158SBasavaraj Natikar }
103472440158SBasavaraj Natikar
103572440158SBasavaraj Natikar return 0;
103672440158SBasavaraj Natikar }
103772440158SBasavaraj Natikar
103872440158SBasavaraj Natikar static const struct pinmux_ops amd_pmxops = {
103972440158SBasavaraj Natikar .get_functions_count = amd_get_functions_count,
104072440158SBasavaraj Natikar .get_function_name = amd_get_fname,
104172440158SBasavaraj Natikar .get_function_groups = amd_get_groups,
104272440158SBasavaraj Natikar .set_mux = amd_set_mux,
104372440158SBasavaraj Natikar };
104472440158SBasavaraj Natikar
1045dbad75ddSKen Xue static struct pinctrl_desc amd_pinctrl_desc = {
1046dbad75ddSKen Xue .pins = kerncz_pins,
1047dbad75ddSKen Xue .npins = ARRAY_SIZE(kerncz_pins),
1048dbad75ddSKen Xue .pctlops = &amd_pinctrl_ops,
104972440158SBasavaraj Natikar .pmxops = &amd_pmxops,
1050dbad75ddSKen Xue .confops = &amd_pinconf_ops,
1051dbad75ddSKen Xue .owner = THIS_MODULE,
1052dbad75ddSKen Xue };
1053dbad75ddSKen Xue
amd_get_iomux_res(struct amd_gpio * gpio_dev)105479bb5c7fSBasavaraj Natikar static void amd_get_iomux_res(struct amd_gpio *gpio_dev)
105579bb5c7fSBasavaraj Natikar {
105679bb5c7fSBasavaraj Natikar struct pinctrl_desc *desc = &amd_pinctrl_desc;
105779bb5c7fSBasavaraj Natikar struct device *dev = &gpio_dev->pdev->dev;
105879bb5c7fSBasavaraj Natikar int index;
105979bb5c7fSBasavaraj Natikar
106079bb5c7fSBasavaraj Natikar index = device_property_match_string(dev, "pinctrl-resource-names", "iomux");
106179bb5c7fSBasavaraj Natikar if (index < 0) {
10623160b37eSBasavaraj Natikar dev_dbg(dev, "iomux not supported\n");
106379bb5c7fSBasavaraj Natikar goto out_no_pinmux;
106479bb5c7fSBasavaraj Natikar }
106579bb5c7fSBasavaraj Natikar
106679bb5c7fSBasavaraj Natikar gpio_dev->iomux_base = devm_platform_ioremap_resource(gpio_dev->pdev, index);
106779bb5c7fSBasavaraj Natikar if (IS_ERR(gpio_dev->iomux_base)) {
10683160b37eSBasavaraj Natikar dev_dbg(dev, "iomux not supported %d io resource\n", index);
106979bb5c7fSBasavaraj Natikar goto out_no_pinmux;
107079bb5c7fSBasavaraj Natikar }
107179bb5c7fSBasavaraj Natikar
107279bb5c7fSBasavaraj Natikar return;
107379bb5c7fSBasavaraj Natikar
107479bb5c7fSBasavaraj Natikar out_no_pinmux:
107579bb5c7fSBasavaraj Natikar desc->pmxops = NULL;
107679bb5c7fSBasavaraj Natikar }
107779bb5c7fSBasavaraj Natikar
amd_gpio_probe(struct platform_device * pdev)1078dbad75ddSKen Xue static int amd_gpio_probe(struct platform_device *pdev)
1079dbad75ddSKen Xue {
1080dbad75ddSKen Xue int ret = 0;
1081dbad75ddSKen Xue struct resource *res;
1082dbad75ddSKen Xue struct amd_gpio *gpio_dev;
1083e81376ebSLinus Walleij struct gpio_irq_chip *girq;
1084dbad75ddSKen Xue
1085dbad75ddSKen Xue gpio_dev = devm_kzalloc(&pdev->dev,
1086dbad75ddSKen Xue sizeof(struct amd_gpio), GFP_KERNEL);
1087dbad75ddSKen Xue if (!gpio_dev)
1088dbad75ddSKen Xue return -ENOMEM;
1089dbad75ddSKen Xue
1090229710feSJulia Cartwright raw_spin_lock_init(&gpio_dev->lock);
1091dbad75ddSKen Xue
109221793d22SBasavaraj Natikar gpio_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
109321793d22SBasavaraj Natikar if (IS_ERR(gpio_dev->base)) {
1094dbad75ddSKen Xue dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
109521793d22SBasavaraj Natikar return PTR_ERR(gpio_dev->base);
1096dbad75ddSKen Xue }
1097dbad75ddSKen Xue
10987e6f8d6fSBasavaraj Natikar gpio_dev->irq = platform_get_irq(pdev, 0);
10997e6f8d6fSBasavaraj Natikar if (gpio_dev->irq < 0)
11007e6f8d6fSBasavaraj Natikar return gpio_dev->irq;
1101dbad75ddSKen Xue
110279d2c8beSDaniel Drake #ifdef CONFIG_PM_SLEEP
110379d2c8beSDaniel Drake gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins,
110479d2c8beSDaniel Drake sizeof(*gpio_dev->saved_regs),
110579d2c8beSDaniel Drake GFP_KERNEL);
110679d2c8beSDaniel Drake if (!gpio_dev->saved_regs)
110779d2c8beSDaniel Drake return -ENOMEM;
110879d2c8beSDaniel Drake #endif
110979d2c8beSDaniel Drake
1110dbad75ddSKen Xue gpio_dev->pdev = pdev;
111112b10f47SDaniel Kurtz gpio_dev->gc.get_direction = amd_gpio_get_direction;
1112dbad75ddSKen Xue gpio_dev->gc.direction_input = amd_gpio_direction_input;
1113dbad75ddSKen Xue gpio_dev->gc.direction_output = amd_gpio_direction_output;
1114dbad75ddSKen Xue gpio_dev->gc.get = amd_gpio_get_value;
1115dbad75ddSKen Xue gpio_dev->gc.set = amd_gpio_set_value;
11162956b5d9SMika Westerberg gpio_dev->gc.set_config = amd_gpio_set_config;
1117dbad75ddSKen Xue gpio_dev->gc.dbg_show = amd_gpio_dbg_show;
1118dbad75ddSKen Xue
11193bfd4430SShah, Nehal-bakulchandra gpio_dev->gc.base = -1;
1120dbad75ddSKen Xue gpio_dev->gc.label = pdev->name;
1121dbad75ddSKen Xue gpio_dev->gc.owner = THIS_MODULE;
112258383c78SLinus Walleij gpio_dev->gc.parent = &pdev->dev;
11233bfd4430SShah, Nehal-bakulchandra gpio_dev->gc.ngpio = resource_size(res) / 4;
1124dbad75ddSKen Xue
11253bfd4430SShah, Nehal-bakulchandra gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64;
1126dbad75ddSKen Xue gpio_dev->groups = kerncz_groups;
1127dbad75ddSKen Xue gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
1128dbad75ddSKen Xue
1129dbad75ddSKen Xue amd_pinctrl_desc.name = dev_name(&pdev->dev);
113079bb5c7fSBasavaraj Natikar amd_get_iomux_res(gpio_dev);
1131251e22abSLaxman Dewangan gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
1132251e22abSLaxman Dewangan gpio_dev);
1133323de9efSMasahiro Yamada if (IS_ERR(gpio_dev->pctrl)) {
1134dbad75ddSKen Xue dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
1135323de9efSMasahiro Yamada return PTR_ERR(gpio_dev->pctrl);
1136dbad75ddSKen Xue }
1137dbad75ddSKen Xue
11386bc3462aSMario Limonciello /* Disable and mask interrupts */
11396bc3462aSMario Limonciello amd_gpio_irq_init(gpio_dev);
11406bc3462aSMario Limonciello
1141e81376ebSLinus Walleij girq = &gpio_dev->gc.irq;
11426173e56fSMarc Zyngier gpio_irq_chip_set_chip(girq, &amd_gpio_irqchip);
1143e81376ebSLinus Walleij /* This will let us handle the parent IRQ in the driver */
1144e81376ebSLinus Walleij girq->parent_handler = NULL;
1145e81376ebSLinus Walleij girq->num_parents = 0;
1146e81376ebSLinus Walleij girq->parents = NULL;
1147e81376ebSLinus Walleij girq->default_type = IRQ_TYPE_NONE;
1148e81376ebSLinus Walleij girq->handler = handle_simple_irq;
1149e81376ebSLinus Walleij
115004d36723SLinus Walleij ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
1151dbad75ddSKen Xue if (ret)
1152251e22abSLaxman Dewangan return ret;
1153dbad75ddSKen Xue
1154dbad75ddSKen Xue ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
11553bfd4430SShah, Nehal-bakulchandra 0, 0, gpio_dev->gc.ngpio);
1156dbad75ddSKen Xue if (ret) {
1157dbad75ddSKen Xue dev_err(&pdev->dev, "Failed to add pin range\n");
1158dbad75ddSKen Xue goto out2;
1159dbad75ddSKen Xue }
1160dbad75ddSKen Xue
11617e6f8d6fSBasavaraj Natikar ret = devm_request_irq(&pdev->dev, gpio_dev->irq, amd_gpio_irq_handler,
1162279ffafaSSandeep Singh IRQF_SHARED, KBUILD_MODNAME, gpio_dev);
1163ba714a9cSThomas Gleixner if (ret)
1164ba714a9cSThomas Gleixner goto out2;
1165ba714a9cSThomas Gleixner
1166dbad75ddSKen Xue platform_set_drvdata(pdev, gpio_dev);
11672d54067fSMario Limonciello acpi_register_wakeup_handler(gpio_dev->irq, amd_gpio_check_wake, gpio_dev);
1168dbad75ddSKen Xue
1169dbad75ddSKen Xue dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
1170dbad75ddSKen Xue return ret;
1171dbad75ddSKen Xue
1172dbad75ddSKen Xue out2:
1173dbad75ddSKen Xue gpiochip_remove(&gpio_dev->gc);
1174dbad75ddSKen Xue
1175dbad75ddSKen Xue return ret;
1176dbad75ddSKen Xue }
1177dbad75ddSKen Xue
amd_gpio_remove(struct platform_device * pdev)1178dbad75ddSKen Xue static int amd_gpio_remove(struct platform_device *pdev)
1179dbad75ddSKen Xue {
1180dbad75ddSKen Xue struct amd_gpio *gpio_dev;
1181dbad75ddSKen Xue
1182dbad75ddSKen Xue gpio_dev = platform_get_drvdata(pdev);
1183dbad75ddSKen Xue
1184dbad75ddSKen Xue gpiochip_remove(&gpio_dev->gc);
11852d54067fSMario Limonciello acpi_unregister_wakeup_handler(amd_gpio_check_wake, gpio_dev);
1186dbad75ddSKen Xue
1187dbad75ddSKen Xue return 0;
1188dbad75ddSKen Xue }
1189dbad75ddSKen Xue
1190de4334f7SLee Jones #ifdef CONFIG_ACPI
1191dbad75ddSKen Xue static const struct acpi_device_id amd_gpio_acpi_match[] = {
1192dbad75ddSKen Xue { "AMD0030", 0 },
119342a44402SWang Hongcheng { "AMDI0030", 0},
11941ca46d3eSMaximilian Luz { "AMDI0031", 0},
1195dbad75ddSKen Xue { },
1196dbad75ddSKen Xue };
1197dbad75ddSKen Xue MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
1198de4334f7SLee Jones #endif
1199dbad75ddSKen Xue
1200dbad75ddSKen Xue static struct platform_driver amd_gpio_driver = {
1201dbad75ddSKen Xue .driver = {
1202dbad75ddSKen Xue .name = "amd_gpio",
1203dbad75ddSKen Xue .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
120479d2c8beSDaniel Drake #ifdef CONFIG_PM_SLEEP
120579d2c8beSDaniel Drake .pm = &amd_gpio_pm_ops,
120679d2c8beSDaniel Drake #endif
1207dbad75ddSKen Xue },
1208dbad75ddSKen Xue .probe = amd_gpio_probe,
1209dbad75ddSKen Xue .remove = amd_gpio_remove,
1210dbad75ddSKen Xue };
1211dbad75ddSKen Xue
1212dbad75ddSKen Xue module_platform_driver(amd_gpio_driver);
1213dbad75ddSKen Xue
1214dbad75ddSKen Xue MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
1215dbad75ddSKen Xue MODULE_DESCRIPTION("AMD GPIO pinctrl driver");
1216