1 /* SPDX-License-Identifier: GPL-2.0-or-later 2 * 3 * S32 pinmux core definitions 4 * 5 * Copyright 2016-2020, 2022 NXP 6 * Copyright (C) 2022 SUSE LLC 7 * Copyright 2015-2016 Freescale Semiconductor, Inc. 8 * Copyright (C) 2012 Linaro Ltd. 9 */ 10 11 #ifndef __DRIVERS_PINCTRL_S32_H 12 #define __DRIVERS_PINCTRL_S32_H 13 14 struct platform_device; 15 16 /** 17 * struct s32_pin_group - describes an S32 pin group 18 * @data: generic data describes group name, number of pins, and a pin array in 19 this group. 20 * @pin_sss: an array of source signal select configs paired with pin array. 21 */ 22 struct s32_pin_group { 23 struct pingroup data; 24 unsigned int *pin_sss; 25 }; 26 27 /** 28 * struct s32_pin_range - pin ID range for each memory region. 29 * @start: start pin ID 30 * @end: end pin ID 31 */ 32 struct s32_pin_range { 33 unsigned int start; 34 unsigned int end; 35 }; 36 37 struct s32_pinctrl_soc_info { 38 struct device *dev; 39 const struct pinctrl_pin_desc *pins; 40 unsigned int npins; 41 struct s32_pin_group *groups; 42 unsigned int ngroups; 43 struct pinfunction *functions; 44 unsigned int nfunctions; 45 unsigned int grp_index; 46 const struct s32_pin_range *mem_pin_ranges; 47 unsigned int mem_regions; 48 }; 49 50 #define S32_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin) 51 #define S32_PIN_RANGE(_start, _end) { .start = _start, .end = _end } 52 53 int s32_pinctrl_probe(struct platform_device *pdev, 54 struct s32_pinctrl_soc_info *info); 55 int s32_pinctrl_resume(struct device *dev); 56 int s32_pinctrl_suspend(struct device *dev); 57 #endif /* __DRIVERS_PINCTRL_S32_H */ 58