1 /* SPDX-License-Identifier: GPL-2.0-or-later
2  *
3  * S32 pinmux core definitions
4  *
5  * Copyright 2016-2020, 2022 NXP
6  * Copyright (C) 2022 SUSE LLC
7  * Copyright 2015-2016 Freescale Semiconductor, Inc.
8  * Copyright (C) 2012 Linaro Ltd.
9  */
10 
11 #ifndef __DRIVERS_PINCTRL_S32_H
12 #define __DRIVERS_PINCTRL_S32_H
13 
14 struct platform_device;
15 
16 /**
17  * struct s32_pin_group - describes an S32 pin group
18  * @data: generic data describes group name, number of pins, and a pin array in
19 	this group.
20  * @pin_sss: an array of source signal select configs paired with pin array.
21  */
22 struct s32_pin_group {
23 	struct pingroup data;
24 	unsigned int *pin_sss;
25 };
26 
27 /**
28  * struct s32_pin_range - pin ID range for each memory region.
29  * @start: start pin ID
30  * @end: end pin ID
31  */
32 struct s32_pin_range {
33 	unsigned int start;
34 	unsigned int end;
35 };
36 
37 struct s32_pinctrl_soc_data {
38 	const struct pinctrl_pin_desc *pins;
39 	unsigned int npins;
40 	const struct s32_pin_range *mem_pin_ranges;
41 	unsigned int mem_regions;
42 };
43 
44 struct s32_pinctrl_soc_info {
45 	struct device *dev;
46 	const struct s32_pinctrl_soc_data *soc_data;
47 	struct s32_pin_group *groups;
48 	unsigned int ngroups;
49 	struct pinfunction *functions;
50 	unsigned int nfunctions;
51 	unsigned int grp_index;
52 };
53 
54 #define S32_PINCTRL_PIN(pin)	PINCTRL_PIN(pin, #pin)
55 #define S32_PIN_RANGE(_start, _end) { .start = _start, .end = _end }
56 
57 int s32_pinctrl_probe(struct platform_device *pdev,
58 		      const struct s32_pinctrl_soc_data *soc_data);
59 int s32_pinctrl_resume(struct device *dev);
60 int s32_pinctrl_suspend(struct device *dev);
61 #endif /* __DRIVERS_PINCTRL_S32_H */
62