1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2020 Nuvoton Technology corporation.
3 
4 #include <linux/bits.h>
5 #include <linux/device.h>
6 #include <linux/gpio/driver.h>
7 #include <linux/interrupt.h>
8 #include <linux/irq.h>
9 #include <linux/mfd/syscon.h>
10 #include <linux/module.h>
11 #include <linux/debugfs.h>
12 #include <linux/seq_file.h>
13 #include <linux/mod_devicetable.h>
14 #include <linux/pinctrl/machine.h>
15 #include <linux/pinctrl/pinconf.h>
16 #include <linux/pinctrl/pinconf-generic.h>
17 #include <linux/pinctrl/pinctrl.h>
18 #include <linux/pinctrl/pinmux.h>
19 #include <linux/pinctrl/consumer.h>
20 #include <linux/platform_device.h>
21 #include <linux/property.h>
22 #include <linux/regmap.h>
23 
24 /* GCR registers */
25 #define NPCM8XX_GCR_SRCNT	0x068
26 #define NPCM8XX_GCR_FLOCKR1	0x074
27 #define NPCM8XX_GCR_DSCNT	0x078
28 #define NPCM8XX_GCR_I2CSEGSEL	0x0e0
29 #define NPCM8XX_GCR_MFSEL1	0x260
30 #define NPCM8XX_GCR_MFSEL2	0x264
31 #define NPCM8XX_GCR_MFSEL3	0x268
32 #define NPCM8XX_GCR_MFSEL4	0x26c
33 #define NPCM8XX_GCR_MFSEL5	0x270
34 #define NPCM8XX_GCR_MFSEL6	0x274
35 #define NPCM8XX_GCR_MFSEL7	0x278
36 
37 #define SRCNT_ESPI		BIT(3)
38 
39 /* GPIO registers */
40 #define NPCM8XX_GP_N_TLOCK1	0x00
41 #define NPCM8XX_GP_N_DIN	0x04
42 #define NPCM8XX_GP_N_POL	0x08
43 #define NPCM8XX_GP_N_DOUT	0x0c
44 #define NPCM8XX_GP_N_OE		0x10
45 #define NPCM8XX_GP_N_OTYP	0x14
46 #define NPCM8XX_GP_N_MP		0x18
47 #define NPCM8XX_GP_N_PU		0x1c
48 #define NPCM8XX_GP_N_PD		0x20
49 #define NPCM8XX_GP_N_DBNC	0x24
50 #define NPCM8XX_GP_N_EVTYP	0x28
51 #define NPCM8XX_GP_N_EVBE	0x2c
52 #define NPCM8XX_GP_N_OBL0	0x30
53 #define NPCM8XX_GP_N_OBL1	0x34
54 #define NPCM8XX_GP_N_OBL2	0x38
55 #define NPCM8XX_GP_N_OBL3	0x3c
56 #define NPCM8XX_GP_N_EVEN	0x40
57 #define NPCM8XX_GP_N_EVENS	0x44
58 #define NPCM8XX_GP_N_EVENC	0x48
59 #define NPCM8XX_GP_N_EVST	0x4c
60 #define NPCM8XX_GP_N_SPLCK	0x50
61 #define NPCM8XX_GP_N_MPLCK	0x54
62 #define NPCM8XX_GP_N_IEM	0x58
63 #define NPCM8XX_GP_N_OSRC	0x5c
64 #define NPCM8XX_GP_N_ODSC	0x60
65 #define NPCM8XX_GP_N_DOS	0x68
66 #define NPCM8XX_GP_N_DOC	0x6c
67 #define NPCM8XX_GP_N_OES	0x70
68 #define NPCM8XX_GP_N_OEC	0x74
69 #define NPCM8XX_GP_N_DBNCS0	0x80
70 #define NPCM8XX_GP_N_DBNCS1	0x84
71 #define NPCM8XX_GP_N_DBNCP0	0x88
72 #define NPCM8XX_GP_N_DBNCP1	0x8c
73 #define NPCM8XX_GP_N_DBNCP2	0x90
74 #define NPCM8XX_GP_N_DBNCP3	0x94
75 #define NPCM8XX_GP_N_TLOCK2	0xac
76 
77 #define NPCM8XX_GPIO_PER_BANK	32
78 #define NPCM8XX_GPIO_BANK_NUM	8
79 #define NPCM8XX_GCR_NONE	0
80 
81 #define NPCM8XX_DEBOUNCE_MAX		4
82 #define NPCM8XX_DEBOUNCE_NSEC		40
83 #define NPCM8XX_DEBOUNCE_VAL_MASK	GENMASK(23, 4)
84 #define NPCM8XX_DEBOUNCE_MAX_VAL	0xFFFFF7
85 
86 /* Structure for register banks */
87 struct debounce_time {
88 	bool	set_val[NPCM8XX_DEBOUNCE_MAX];
89 	u32	nanosec_val[NPCM8XX_DEBOUNCE_MAX];
90 };
91 
92 struct npcm8xx_gpio {
93 	struct gpio_chip	gc;
94 	void __iomem		*base;
95 	struct debounce_time	debounce;
96 	int			irqbase;
97 	int			irq;
98 	struct irq_chip		irq_chip;
99 	u32			pinctrl_id;
100 	int (*direction_input)(struct gpio_chip *chip, unsigned int offset);
101 	int (*direction_output)(struct gpio_chip *chip, unsigned int offset,
102 				int value);
103 	int (*request)(struct gpio_chip *chip, unsigned int offset);
104 	void (*free)(struct gpio_chip *chip, unsigned int offset);
105 };
106 
107 struct npcm8xx_pinctrl {
108 	struct pinctrl_dev	*pctldev;
109 	struct device		*dev;
110 	struct npcm8xx_gpio	gpio_bank[NPCM8XX_GPIO_BANK_NUM];
111 	struct irq_domain	*domain;
112 	struct regmap		*gcr_regmap;
113 	void __iomem		*regs;
114 	u32			bank_num;
115 };
116 
117 /* GPIO handling in the pinctrl driver */
118 static void npcm_gpio_set(struct gpio_chip *gc, void __iomem *reg,
119 			  unsigned int pinmask)
120 {
121 	unsigned long flags;
122 
123 	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
124 	iowrite32(ioread32(reg) | pinmask, reg);
125 	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
126 }
127 
128 static void npcm_gpio_clr(struct gpio_chip *gc, void __iomem *reg,
129 			  unsigned int pinmask)
130 {
131 	unsigned long flags;
132 
133 	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
134 	iowrite32(ioread32(reg) & ~pinmask, reg);
135 	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
136 }
137 
138 static void npcmgpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
139 {
140 	struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
141 
142 	seq_printf(s, "DIN :%.8x DOUT:%.8x IE  :%.8x OE	 :%.8x\n",
143 		   ioread32(bank->base + NPCM8XX_GP_N_DIN),
144 		   ioread32(bank->base + NPCM8XX_GP_N_DOUT),
145 		   ioread32(bank->base + NPCM8XX_GP_N_IEM),
146 		   ioread32(bank->base + NPCM8XX_GP_N_OE));
147 	seq_printf(s, "PU  :%.8x PD  :%.8x DB  :%.8x POL :%.8x\n",
148 		   ioread32(bank->base + NPCM8XX_GP_N_PU),
149 		   ioread32(bank->base + NPCM8XX_GP_N_PD),
150 		   ioread32(bank->base + NPCM8XX_GP_N_DBNC),
151 		   ioread32(bank->base + NPCM8XX_GP_N_POL));
152 	seq_printf(s, "ETYP:%.8x EVBE:%.8x EVEN:%.8x EVST:%.8x\n",
153 		   ioread32(bank->base + NPCM8XX_GP_N_EVTYP),
154 		   ioread32(bank->base + NPCM8XX_GP_N_EVBE),
155 		   ioread32(bank->base + NPCM8XX_GP_N_EVEN),
156 		   ioread32(bank->base + NPCM8XX_GP_N_EVST));
157 	seq_printf(s, "OTYP:%.8x OSRC:%.8x ODSC:%.8x\n",
158 		   ioread32(bank->base + NPCM8XX_GP_N_OTYP),
159 		   ioread32(bank->base + NPCM8XX_GP_N_OSRC),
160 		   ioread32(bank->base + NPCM8XX_GP_N_ODSC));
161 	seq_printf(s, "OBL0:%.8x OBL1:%.8x OBL2:%.8x OBL3:%.8x\n",
162 		   ioread32(bank->base + NPCM8XX_GP_N_OBL0),
163 		   ioread32(bank->base + NPCM8XX_GP_N_OBL1),
164 		   ioread32(bank->base + NPCM8XX_GP_N_OBL2),
165 		   ioread32(bank->base + NPCM8XX_GP_N_OBL3));
166 	seq_printf(s, "SLCK:%.8x MLCK:%.8x\n",
167 		   ioread32(bank->base + NPCM8XX_GP_N_SPLCK),
168 		   ioread32(bank->base + NPCM8XX_GP_N_MPLCK));
169 }
170 
171 static int npcmgpio_direction_input(struct gpio_chip *chip, unsigned int offset)
172 {
173 	struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
174 	int ret;
175 
176 	ret = pinctrl_gpio_direction_input(offset + chip->base);
177 	if (ret)
178 		return ret;
179 
180 	return bank->direction_input(chip, offset);
181 }
182 
183 static int npcmgpio_direction_output(struct gpio_chip *chip,
184 				     unsigned int offset, int value)
185 {
186 	struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
187 	int ret;
188 
189 	ret = pinctrl_gpio_direction_output(offset + chip->base);
190 	if (ret)
191 		return ret;
192 
193 	return bank->direction_output(chip, offset, value);
194 }
195 
196 static int npcmgpio_gpio_request(struct gpio_chip *chip, unsigned int offset)
197 {
198 	struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
199 	int ret;
200 
201 	ret = pinctrl_gpio_request(offset + chip->base);
202 	if (ret)
203 		return ret;
204 
205 	return bank->request(chip, offset);
206 }
207 
208 static void npcmgpio_gpio_free(struct gpio_chip *chip, unsigned int offset)
209 {
210 	pinctrl_gpio_free(offset + chip->base);
211 }
212 
213 static void npcmgpio_irq_handler(struct irq_desc *desc)
214 {
215 	unsigned long sts, en, bit;
216 	struct npcm8xx_gpio *bank;
217 	struct irq_chip *chip;
218 	struct gpio_chip *gc;
219 
220 	gc = irq_desc_get_handler_data(desc);
221 	bank = gpiochip_get_data(gc);
222 	chip = irq_desc_get_chip(desc);
223 
224 	chained_irq_enter(chip, desc);
225 	sts = ioread32(bank->base + NPCM8XX_GP_N_EVST);
226 	en  = ioread32(bank->base + NPCM8XX_GP_N_EVEN);
227 	sts &= en;
228 	for_each_set_bit(bit, &sts, NPCM8XX_GPIO_PER_BANK)
229 		generic_handle_domain_irq(gc->irq.domain, bit);
230 	chained_irq_exit(chip, desc);
231 }
232 
233 static int npcmgpio_set_irq_type(struct irq_data *d, unsigned int type)
234 {
235 	struct npcm8xx_gpio *bank =
236 		gpiochip_get_data(irq_data_get_irq_chip_data(d));
237 	unsigned int gpio = BIT(irqd_to_hwirq(d));
238 
239 	switch (type) {
240 	case IRQ_TYPE_EDGE_RISING:
241 		npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio);
242 		npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio);
243 		break;
244 	case IRQ_TYPE_EDGE_FALLING:
245 		npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio);
246 		npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio);
247 		break;
248 	case IRQ_TYPE_EDGE_BOTH:
249 		npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio);
250 		break;
251 	case IRQ_TYPE_LEVEL_LOW:
252 		npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio);
253 		break;
254 	case IRQ_TYPE_LEVEL_HIGH:
255 		npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio);
256 		break;
257 	default:
258 		return -EINVAL;
259 	}
260 
261 	if (type & IRQ_TYPE_LEVEL_MASK) {
262 		npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_EVTYP, gpio);
263 		irq_set_handler_locked(d, handle_level_irq);
264 	} else if (type & IRQ_TYPE_EDGE_BOTH) {
265 		npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_EVTYP, gpio);
266 		irq_set_handler_locked(d, handle_edge_irq);
267 	}
268 
269 	return 0;
270 }
271 
272 static void npcmgpio_irq_ack(struct irq_data *d)
273 {
274 	struct npcm8xx_gpio *bank =
275 		gpiochip_get_data(irq_data_get_irq_chip_data(d));
276 	unsigned int gpio = irqd_to_hwirq(d);
277 
278 	iowrite32(BIT(gpio), bank->base + NPCM8XX_GP_N_EVST);
279 }
280 
281 static void npcmgpio_irq_mask(struct irq_data *d)
282 {
283 	struct npcm8xx_gpio *bank =
284 		gpiochip_get_data(irq_data_get_irq_chip_data(d));
285 	unsigned int gpio = irqd_to_hwirq(d);
286 
287 	iowrite32(BIT(gpio), bank->base + NPCM8XX_GP_N_EVENC);
288 }
289 
290 static void npcmgpio_irq_unmask(struct irq_data *d)
291 {
292 	struct npcm8xx_gpio *bank =
293 		gpiochip_get_data(irq_data_get_irq_chip_data(d));
294 	unsigned int gpio = irqd_to_hwirq(d);
295 
296 	iowrite32(BIT(gpio), bank->base + NPCM8XX_GP_N_EVENS);
297 }
298 
299 static unsigned int npcmgpio_irq_startup(struct irq_data *d)
300 {
301 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
302 	unsigned int gpio = irqd_to_hwirq(d);
303 
304 	/* active-high, input, clear interrupt, enable interrupt */
305 	npcmgpio_direction_input(gc, gpio);
306 	npcmgpio_irq_ack(d);
307 	npcmgpio_irq_unmask(d);
308 
309 	return 0;
310 }
311 
312 static struct irq_chip npcmgpio_irqchip = {
313 	.name = "NPCM8XX-GPIO-IRQ",
314 	.irq_ack = npcmgpio_irq_ack,
315 	.irq_unmask = npcmgpio_irq_unmask,
316 	.irq_mask = npcmgpio_irq_mask,
317 	.irq_set_type = npcmgpio_set_irq_type,
318 	.irq_startup = npcmgpio_irq_startup,
319 	.flags =  IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
320 	GPIOCHIP_IRQ_RESOURCE_HELPERS,
321 };
322 
323 static const int gpi36_pins[] = { 58 };
324 static const int gpi35_pins[] = { 58 };
325 
326 static const int tp_jtag3_pins[] = { 44, 62, 45, 46 };
327 static const int tp_uart_pins[] = { 50, 51 };
328 
329 static const int tp_smb2_pins[] = { 24, 25 };
330 static const int tp_smb1_pins[] = { 142, 143 };
331 
332 static const int tp_gpio7_pins[] = { 96 };
333 static const int tp_gpio6_pins[] = { 97 };
334 static const int tp_gpio5_pins[] = { 98 };
335 static const int tp_gpio4_pins[] = { 99 };
336 static const int tp_gpio3_pins[] = { 100 };
337 static const int tp_gpio2_pins[] = { 16 };
338 static const int tp_gpio1_pins[] = { 9 };
339 static const int tp_gpio0_pins[] = { 8 };
340 
341 static const int tp_gpio2b_pins[] = { 101 };
342 static const int tp_gpio1b_pins[] = { 92 };
343 static const int tp_gpio0b_pins[] = { 91 };
344 
345 static const int vgadig_pins[] = { 102, 103, 104, 105 };
346 
347 static const int nbu1crts_pins[] = { 44, 62 };
348 
349 static const int fm2_pins[] = { 224, 225, 226, 227, 228, 229, 230 };
350 static const int fm1_pins[] = { 175, 176, 177, 203, 191, 192, 233 };
351 static const int fm0_pins[] = { 194, 195, 196, 202, 199, 198, 197 };
352 
353 static const int gpio1836_pins[] = { 183, 184, 185, 186 };
354 static const int gpio1889_pins[] = { 188, 189 };
355 static const int gpo187_pins[] = { 187 };
356 
357 static const int cp1urxd_pins[] = { 41 };
358 static const int r3rxer_pins[] = { 212 };
359 
360 static const int cp1gpio2c_pins[] = { 101 };
361 static const int cp1gpio3c_pins[] = { 100 };
362 
363 static const int cp1gpio0b_pins[] = { 127 };
364 static const int cp1gpio1b_pins[] = { 126 };
365 static const int cp1gpio2b_pins[] = { 125 };
366 static const int cp1gpio3b_pins[] = { 124 };
367 static const int cp1gpio4b_pins[] = { 99 };
368 static const int cp1gpio5b_pins[] = { 98 };
369 static const int cp1gpio6b_pins[] = { 97 };
370 static const int cp1gpio7b_pins[] = { 96 };
371 
372 static const int cp1gpio0_pins[] = {  };
373 static const int cp1gpio1_pins[] = {  };
374 static const int cp1gpio2_pins[] = {  };
375 static const int cp1gpio3_pins[] = {  };
376 static const int cp1gpio4_pins[] = {  };
377 static const int cp1gpio5_pins[] = { 17 };
378 static const int cp1gpio6_pins[] = { 91 };
379 static const int cp1gpio7_pins[] = { 92 };
380 
381 static const int cp1utxd_pins[] = { 42 };
382 
383 static const int spi1cs3_pins[] = { 192 };
384 static const int spi1cs2_pins[] = { 191 };
385 static const int spi1cs1_pins[] = { 233 };
386 static const int spi1cs0_pins[] = { 203 };
387 
388 static const int spi1d23_pins[] = { 191, 192 };
389 
390 static const int j2j3_pins[] = { 44, 62, 45, 46 };
391 
392 static const int r3oen_pins[] = { 213 };
393 static const int r2oen_pins[] = { 90 };
394 static const int r1oen_pins[] = { 56 };
395 static const int bu4b_pins[] = { 98, 99 };
396 static const int bu4_pins[] = { 54, 55 };
397 static const int bu5b_pins[] = { 100, 101 };
398 static const int bu5_pins[] = { 52, 53 };
399 static const int bu6_pins[] = { 50, 51 };
400 static const int rmii3_pins[] = { 110, 111, 209, 211, 210, 214, 215 };
401 
402 static const int jm1_pins[] = { 136, 137, 138, 139, 140 };
403 static const int jm2_pins[] = { 251 };
404 
405 static const int tpgpio5b_pins[] = { 58 };
406 static const int tpgpio4b_pins[] = { 57 };
407 
408 static const int clkrun_pins[] = { 162 };
409 
410 static const int i3c5_pins[] = { 106, 107 };
411 static const int i3c4_pins[] = { 33, 34 };
412 static const int i3c3_pins[] = { 246, 247 };
413 static const int i3c2_pins[] = { 244, 245 };
414 static const int i3c1_pins[] = { 242, 243 };
415 static const int i3c0_pins[] = { 240, 241 };
416 
417 static const int hsi1a_pins[] = { 43, 63 };
418 static const int hsi2a_pins[] = { 48, 49 };
419 static const int hsi1b_pins[] = { 44, 62 };
420 static const int hsi2b_pins[] = { 50, 51 };
421 static const int hsi1c_pins[] = { 45, 46, 47, 61 };
422 static const int hsi2c_pins[] = { 45, 46, 47, 61 };
423 
424 static const int smb0_pins[]  = { 115, 114 };
425 static const int smb0b_pins[] = { 195, 194 };
426 static const int smb0c_pins[] = { 202, 196 };
427 static const int smb0d_pins[] = { 198, 199 };
428 static const int smb0den_pins[] = { 197 };
429 static const int smb1_pins[]  = { 117, 116 };
430 static const int smb1b_pins[] = { 126, 127 };
431 static const int smb1c_pins[] = { 124, 125 };
432 static const int smb1d_pins[] = { 4, 5 };
433 static const int smb2_pins[]  = { 119, 118 };
434 static const int smb2b_pins[] = { 122, 123 };
435 static const int smb2c_pins[] = { 120, 121 };
436 static const int smb2d_pins[] = { 6, 7 };
437 static const int smb3_pins[]  = { 30, 31 };
438 static const int smb3b_pins[] = { 39, 40 };
439 static const int smb3c_pins[] = { 37, 38 };
440 static const int smb3d_pins[] = { 59, 60 };
441 static const int smb4_pins[]  = { 28, 29 };
442 static const int smb4b_pins[] = { 18, 19 };
443 static const int smb4c_pins[] = { 20, 21 };
444 static const int smb4d_pins[] = { 22, 23 };
445 static const int smb4den_pins[] = { 17 };
446 static const int smb5_pins[]  = { 26, 27 };
447 static const int smb5b_pins[] = { 13, 12 };
448 static const int smb5c_pins[] = { 15, 14 };
449 static const int smb5d_pins[] = { 94, 93 };
450 static const int ga20kbc_pins[] = { 94, 93 };
451 
452 static const int smb6_pins[]  = { 172, 171 };
453 static const int smb6b_pins[] = { 2, 3 };
454 static const int smb6c_pins[]  = { 0, 1 };
455 static const int smb6d_pins[]  = { 10, 11 };
456 static const int smb7_pins[]  = { 174, 173 };
457 static const int smb7b_pins[]  = { 16, 141 };
458 static const int smb7c_pins[]  = { 24, 25 };
459 static const int smb7d_pins[]  = { 142, 143 };
460 static const int smb8_pins[]  = { 129, 128 };
461 static const int smb9_pins[]  = { 131, 130 };
462 static const int smb10_pins[] = { 133, 132 };
463 static const int smb11_pins[] = { 135, 134 };
464 static const int smb12_pins[] = { 221, 220 };
465 static const int smb13_pins[] = { 223, 222 };
466 static const int smb14_pins[] = { 22, 23 };
467 static const int smb14b_pins[] = { 32, 187 };
468 static const int smb15_pins[] = { 20, 21 };
469 static const int smb15b_pins[] = { 192, 191 };
470 
471 static const int smb16_pins[] = { 10, 11 };
472 static const int smb16b_pins[] = { 218, 219 };
473 static const int smb17_pins[] = { 3, 2 };
474 static const int smb18_pins[] = { 0, 1 };
475 static const int smb19_pins[] = { 60, 59 };
476 static const int smb20_pins[] = { 234, 235 };
477 static const int smb21_pins[] = { 169, 170 };
478 static const int smb22_pins[] = { 40, 39 };
479 static const int smb23_pins[] = { 38, 37 };
480 static const int smb23b_pins[] = { 134, 135 };
481 
482 static const int fanin0_pins[] = { 64 };
483 static const int fanin1_pins[] = { 65 };
484 static const int fanin2_pins[] = { 66 };
485 static const int fanin3_pins[] = { 67 };
486 static const int fanin4_pins[] = { 68 };
487 static const int fanin5_pins[] = { 69 };
488 static const int fanin6_pins[] = { 70 };
489 static const int fanin7_pins[] = { 71 };
490 static const int fanin8_pins[] = { 72 };
491 static const int fanin9_pins[] = { 73 };
492 static const int fanin10_pins[] = { 74 };
493 static const int fanin11_pins[] = { 75 };
494 static const int fanin12_pins[] = { 76 };
495 static const int fanin13_pins[] = { 77 };
496 static const int fanin14_pins[] = { 78 };
497 static const int fanin15_pins[] = { 79 };
498 static const int faninx_pins[] = { 175, 176, 177, 203 };
499 
500 static const int pwm0_pins[] = { 80 };
501 static const int pwm1_pins[] = { 81 };
502 static const int pwm2_pins[] = { 82 };
503 static const int pwm3_pins[] = { 83 };
504 static const int pwm4_pins[] = { 144 };
505 static const int pwm5_pins[] = { 145 };
506 static const int pwm6_pins[] = { 146 };
507 static const int pwm7_pins[] = { 147 };
508 static const int pwm8_pins[] = { 220 };
509 static const int pwm9_pins[] = { 221 };
510 static const int pwm10_pins[] = { 234 };
511 static const int pwm11_pins[] = { 235 };
512 
513 static const int uart1_pins[] = { 43, 45, 46, 47, 61, 62, 63 };
514 static const int uart2_pins[] = { 48, 49, 50, 51, 52, 53, 54, 55 };
515 
516 static const int sg1mdio_pins[] = { 108, 109 };
517 
518 static const int rg2_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,
519 	213, 214, 215 };
520 static const int rg2mdio_pins[] = { 216, 217 };
521 
522 static const int ddr_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,
523 	213, 214, 215, 216, 217 };
524 
525 static const int iox1_pins[] = { 0, 1, 2, 3 };
526 static const int iox2_pins[] = { 4, 5, 6, 7 };
527 static const int ioxh_pins[] = { 10, 11, 24, 25 };
528 
529 static const int mmc_pins[] = { 152, 154, 156, 157, 158, 159 };
530 static const int mmcwp_pins[] = { 153 };
531 static const int mmccd_pins[] = { 155 };
532 static const int mmcrst_pins[] = { 155 };
533 static const int mmc8_pins[] = { 148, 149, 150, 151 };
534 
535 static const int r1_pins[] = { 178, 179, 180, 181, 182, 193, 201 };
536 static const int r1err_pins[] = { 56 };
537 static const int r1md_pins[] = { 57, 58 };
538 static const int r2_pins[] = { 84, 85, 86, 87, 88, 89, 200 };
539 static const int r2err_pins[] = { 90 };
540 static const int r2md_pins[] = { 91, 92 };
541 static const int sd1_pins[] = { 136, 137, 138, 139, 140, 141, 142, 143 };
542 static const int sd1pwr_pins[] = { 143 };
543 
544 static const int wdog1_pins[] = { 218 };
545 static const int wdog2_pins[] = { 219 };
546 
547 static const int bmcuart0a_pins[] = { 41, 42 };
548 static const int bmcuart0b_pins[] = { 48, 49 };
549 static const int bmcuart1_pins[] = { 43, 44, 62, 63 };
550 
551 static const int scipme_pins[] = { 169 };
552 static const int smi_pins[] = { 170 };
553 static const int serirq_pins[] = { 168 };
554 
555 static const int clkout_pins[] = { 160 };
556 static const int clkreq_pins[] = { 231 };
557 
558 static const int jtag2_pins[] = { 43, 44, 45, 46, 47 };
559 static const int gspi_pins[] = { 12, 13, 14, 15 };
560 
561 static const int spix_pins[] = { 224, 225, 226, 227, 229, 230 };
562 static const int spixcs1_pins[] = { 228 };
563 
564 static const int spi1_pins[] = { 175, 176, 177 };
565 static const int pspi_pins[] = { 17, 18, 19 };
566 
567 static const int spi0cs1_pins[] = { 32 };
568 
569 static const int spi3_pins[] = { 183, 184, 185, 186 };
570 static const int spi3cs1_pins[] = { 187 };
571 static const int spi3quad_pins[] = { 188, 189 };
572 static const int spi3cs2_pins[] = { 188 };
573 static const int spi3cs3_pins[] = { 189 };
574 
575 static const int ddc_pins[] = { 204, 205, 206, 207 };
576 
577 static const int lpc_pins[] = { 95, 161, 163, 164, 165, 166, 167 };
578 static const int lpcclk_pins[] = { 168 };
579 static const int espi_pins[] = { 95, 161, 163, 164, 165, 166, 167, 168 };
580 
581 static const int lkgpo0_pins[] = { 16 };
582 static const int lkgpo1_pins[] = { 8 };
583 static const int lkgpo2_pins[] = { 9 };
584 
585 static const int nprd_smi_pins[] = { 190 };
586 
587 static const int hgpio0_pins[] = { 20 };
588 static const int hgpio1_pins[] = { 21 };
589 static const int hgpio2_pins[] = { 22 };
590 static const int hgpio3_pins[] = { 23 };
591 static const int hgpio4_pins[] = { 24 };
592 static const int hgpio5_pins[] = { 25 };
593 static const int hgpio6_pins[] = { 59 };
594 static const int hgpio7_pins[] = { 60 };
595 
596 /*
597  * pin:	     name, number
598  * group:    name, npins,   pins
599  * function: name, ngroups, groups
600  */
601 struct npcm8xx_pingroup {
602 	const char *name;
603 	const unsigned int *pins;
604 	int npins;
605 };
606 
607 #define NPCM8XX_GRPS \
608 	NPCM8XX_GRP(gpi36), \
609 	NPCM8XX_GRP(gpi35), \
610 	NPCM8XX_GRP(tp_jtag3), \
611 	NPCM8XX_GRP(tp_uart), \
612 	NPCM8XX_GRP(tp_smb2), \
613 	NPCM8XX_GRP(tp_smb1), \
614 	NPCM8XX_GRP(tp_gpio7), \
615 	NPCM8XX_GRP(tp_gpio6), \
616 	NPCM8XX_GRP(tp_gpio5), \
617 	NPCM8XX_GRP(tp_gpio4), \
618 	NPCM8XX_GRP(tp_gpio3), \
619 	NPCM8XX_GRP(tp_gpio2), \
620 	NPCM8XX_GRP(tp_gpio1), \
621 	NPCM8XX_GRP(tp_gpio0), \
622 	NPCM8XX_GRP(tp_gpio2b), \
623 	NPCM8XX_GRP(tp_gpio1b), \
624 	NPCM8XX_GRP(tp_gpio0b), \
625 	NPCM8XX_GRP(vgadig), \
626 	NPCM8XX_GRP(nbu1crts), \
627 	NPCM8XX_GRP(fm2), \
628 	NPCM8XX_GRP(fm1), \
629 	NPCM8XX_GRP(fm0), \
630 	NPCM8XX_GRP(gpio1836), \
631 	NPCM8XX_GRP(gpio1889), \
632 	NPCM8XX_GRP(gpo187), \
633 	NPCM8XX_GRP(cp1urxd), \
634 	NPCM8XX_GRP(r3rxer), \
635 	NPCM8XX_GRP(cp1gpio2c), \
636 	NPCM8XX_GRP(cp1gpio3c), \
637 	NPCM8XX_GRP(cp1gpio0b), \
638 	NPCM8XX_GRP(cp1gpio1b), \
639 	NPCM8XX_GRP(cp1gpio2b), \
640 	NPCM8XX_GRP(cp1gpio3b), \
641 	NPCM8XX_GRP(cp1gpio4b), \
642 	NPCM8XX_GRP(cp1gpio5b), \
643 	NPCM8XX_GRP(cp1gpio6b), \
644 	NPCM8XX_GRP(cp1gpio7b), \
645 	NPCM8XX_GRP(cp1gpio0), \
646 	NPCM8XX_GRP(cp1gpio1), \
647 	NPCM8XX_GRP(cp1gpio2), \
648 	NPCM8XX_GRP(cp1gpio3), \
649 	NPCM8XX_GRP(cp1gpio4), \
650 	NPCM8XX_GRP(cp1gpio5), \
651 	NPCM8XX_GRP(cp1gpio6), \
652 	NPCM8XX_GRP(cp1gpio7), \
653 	NPCM8XX_GRP(cp1utxd), \
654 	NPCM8XX_GRP(spi1cs3), \
655 	NPCM8XX_GRP(spi1cs2), \
656 	NPCM8XX_GRP(spi1cs1), \
657 	NPCM8XX_GRP(spi1cs0), \
658 	NPCM8XX_GRP(spi1d23), \
659 	NPCM8XX_GRP(j2j3), \
660 	NPCM8XX_GRP(r3oen), \
661 	NPCM8XX_GRP(r2oen), \
662 	NPCM8XX_GRP(r1oen), \
663 	NPCM8XX_GRP(bu4b), \
664 	NPCM8XX_GRP(bu4), \
665 	NPCM8XX_GRP(bu5b), \
666 	NPCM8XX_GRP(bu5), \
667 	NPCM8XX_GRP(bu6), \
668 	NPCM8XX_GRP(rmii3), \
669 	NPCM8XX_GRP(jm1), \
670 	NPCM8XX_GRP(jm2), \
671 	NPCM8XX_GRP(tpgpio5b), \
672 	NPCM8XX_GRP(tpgpio4b), \
673 	NPCM8XX_GRP(clkrun), \
674 	NPCM8XX_GRP(i3c5), \
675 	NPCM8XX_GRP(i3c4), \
676 	NPCM8XX_GRP(i3c3), \
677 	NPCM8XX_GRP(i3c2), \
678 	NPCM8XX_GRP(i3c1), \
679 	NPCM8XX_GRP(i3c0), \
680 	NPCM8XX_GRP(hsi1a), \
681 	NPCM8XX_GRP(hsi2a), \
682 	NPCM8XX_GRP(hsi1b), \
683 	NPCM8XX_GRP(hsi2b), \
684 	NPCM8XX_GRP(hsi1c), \
685 	NPCM8XX_GRP(hsi2c), \
686 	NPCM8XX_GRP(smb0), \
687 	NPCM8XX_GRP(smb0b), \
688 	NPCM8XX_GRP(smb0c), \
689 	NPCM8XX_GRP(smb0d), \
690 	NPCM8XX_GRP(smb0den), \
691 	NPCM8XX_GRP(smb1), \
692 	NPCM8XX_GRP(smb1b), \
693 	NPCM8XX_GRP(smb1c), \
694 	NPCM8XX_GRP(smb1d), \
695 	NPCM8XX_GRP(smb2), \
696 	NPCM8XX_GRP(smb2b), \
697 	NPCM8XX_GRP(smb2c), \
698 	NPCM8XX_GRP(smb2d), \
699 	NPCM8XX_GRP(smb3), \
700 	NPCM8XX_GRP(smb3b), \
701 	NPCM8XX_GRP(smb3c), \
702 	NPCM8XX_GRP(smb3d), \
703 	NPCM8XX_GRP(smb4), \
704 	NPCM8XX_GRP(smb4b), \
705 	NPCM8XX_GRP(smb4c), \
706 	NPCM8XX_GRP(smb4d), \
707 	NPCM8XX_GRP(smb4den), \
708 	NPCM8XX_GRP(smb5), \
709 	NPCM8XX_GRP(smb5b), \
710 	NPCM8XX_GRP(smb5c), \
711 	NPCM8XX_GRP(smb5d), \
712 	NPCM8XX_GRP(ga20kbc), \
713 	NPCM8XX_GRP(smb6), \
714 	NPCM8XX_GRP(smb6b), \
715 	NPCM8XX_GRP(smb6c), \
716 	NPCM8XX_GRP(smb6d), \
717 	NPCM8XX_GRP(smb7), \
718 	NPCM8XX_GRP(smb7b), \
719 	NPCM8XX_GRP(smb7c), \
720 	NPCM8XX_GRP(smb7d), \
721 	NPCM8XX_GRP(smb8), \
722 	NPCM8XX_GRP(smb9), \
723 	NPCM8XX_GRP(smb10), \
724 	NPCM8XX_GRP(smb11), \
725 	NPCM8XX_GRP(smb12), \
726 	NPCM8XX_GRP(smb13), \
727 	NPCM8XX_GRP(smb14), \
728 	NPCM8XX_GRP(smb14b), \
729 	NPCM8XX_GRP(smb15), \
730 	NPCM8XX_GRP(smb15b), \
731 	NPCM8XX_GRP(smb16), \
732 	NPCM8XX_GRP(smb16b), \
733 	NPCM8XX_GRP(smb17), \
734 	NPCM8XX_GRP(smb18), \
735 	NPCM8XX_GRP(smb19), \
736 	NPCM8XX_GRP(smb20), \
737 	NPCM8XX_GRP(smb21), \
738 	NPCM8XX_GRP(smb22), \
739 	NPCM8XX_GRP(smb23), \
740 	NPCM8XX_GRP(smb23b), \
741 	NPCM8XX_GRP(fanin0), \
742 	NPCM8XX_GRP(fanin1), \
743 	NPCM8XX_GRP(fanin2), \
744 	NPCM8XX_GRP(fanin3), \
745 	NPCM8XX_GRP(fanin4), \
746 	NPCM8XX_GRP(fanin5), \
747 	NPCM8XX_GRP(fanin6), \
748 	NPCM8XX_GRP(fanin7), \
749 	NPCM8XX_GRP(fanin8), \
750 	NPCM8XX_GRP(fanin9), \
751 	NPCM8XX_GRP(fanin10), \
752 	NPCM8XX_GRP(fanin11), \
753 	NPCM8XX_GRP(fanin12), \
754 	NPCM8XX_GRP(fanin13), \
755 	NPCM8XX_GRP(fanin14), \
756 	NPCM8XX_GRP(fanin15), \
757 	NPCM8XX_GRP(faninx), \
758 	NPCM8XX_GRP(pwm0), \
759 	NPCM8XX_GRP(pwm1), \
760 	NPCM8XX_GRP(pwm2), \
761 	NPCM8XX_GRP(pwm3), \
762 	NPCM8XX_GRP(pwm4), \
763 	NPCM8XX_GRP(pwm5), \
764 	NPCM8XX_GRP(pwm6), \
765 	NPCM8XX_GRP(pwm7), \
766 	NPCM8XX_GRP(pwm8), \
767 	NPCM8XX_GRP(pwm9), \
768 	NPCM8XX_GRP(pwm10), \
769 	NPCM8XX_GRP(pwm11), \
770 	NPCM8XX_GRP(sg1mdio), \
771 	NPCM8XX_GRP(rg2), \
772 	NPCM8XX_GRP(rg2mdio), \
773 	NPCM8XX_GRP(ddr), \
774 	NPCM8XX_GRP(uart1), \
775 	NPCM8XX_GRP(uart2), \
776 	NPCM8XX_GRP(bmcuart0a), \
777 	NPCM8XX_GRP(bmcuart0b), \
778 	NPCM8XX_GRP(bmcuart1), \
779 	NPCM8XX_GRP(iox1), \
780 	NPCM8XX_GRP(iox2), \
781 	NPCM8XX_GRP(ioxh), \
782 	NPCM8XX_GRP(gspi), \
783 	NPCM8XX_GRP(mmc), \
784 	NPCM8XX_GRP(mmcwp), \
785 	NPCM8XX_GRP(mmccd), \
786 	NPCM8XX_GRP(mmcrst), \
787 	NPCM8XX_GRP(mmc8), \
788 	NPCM8XX_GRP(r1), \
789 	NPCM8XX_GRP(r1err), \
790 	NPCM8XX_GRP(r1md), \
791 	NPCM8XX_GRP(r2), \
792 	NPCM8XX_GRP(r2err), \
793 	NPCM8XX_GRP(r2md), \
794 	NPCM8XX_GRP(sd1), \
795 	NPCM8XX_GRP(sd1pwr), \
796 	NPCM8XX_GRP(wdog1), \
797 	NPCM8XX_GRP(wdog2), \
798 	NPCM8XX_GRP(scipme), \
799 	NPCM8XX_GRP(smi), \
800 	NPCM8XX_GRP(serirq), \
801 	NPCM8XX_GRP(jtag2), \
802 	NPCM8XX_GRP(spix), \
803 	NPCM8XX_GRP(spixcs1), \
804 	NPCM8XX_GRP(spi1), \
805 	NPCM8XX_GRP(pspi), \
806 	NPCM8XX_GRP(ddc), \
807 	NPCM8XX_GRP(clkreq), \
808 	NPCM8XX_GRP(clkout), \
809 	NPCM8XX_GRP(spi3), \
810 	NPCM8XX_GRP(spi3cs1), \
811 	NPCM8XX_GRP(spi3quad), \
812 	NPCM8XX_GRP(spi3cs2), \
813 	NPCM8XX_GRP(spi3cs3), \
814 	NPCM8XX_GRP(spi0cs1), \
815 	NPCM8XX_GRP(lpc), \
816 	NPCM8XX_GRP(lpcclk), \
817 	NPCM8XX_GRP(espi), \
818 	NPCM8XX_GRP(lkgpo0), \
819 	NPCM8XX_GRP(lkgpo1), \
820 	NPCM8XX_GRP(lkgpo2), \
821 	NPCM8XX_GRP(nprd_smi), \
822 	NPCM8XX_GRP(hgpio0), \
823 	NPCM8XX_GRP(hgpio1), \
824 	NPCM8XX_GRP(hgpio2), \
825 	NPCM8XX_GRP(hgpio3), \
826 	NPCM8XX_GRP(hgpio4), \
827 	NPCM8XX_GRP(hgpio5), \
828 	NPCM8XX_GRP(hgpio6), \
829 	NPCM8XX_GRP(hgpio7), \
830 	\
831 
832 enum {
833 #define NPCM8XX_GRP(x) fn_ ## x
834 	NPCM8XX_GRPS
835 	NPCM8XX_GRP(none),
836 	NPCM8XX_GRP(gpio),
837 #undef NPCM8XX_GRP
838 };
839 
840 static struct npcm8xx_pingroup npcm8xx_pingroups[] = {
841 #define NPCM8XX_GRP(x) { .name = #x, .pins = x ## _pins, \
842 			.npins = ARRAY_SIZE(x ## _pins) }
843 	NPCM8XX_GRPS
844 #undef NPCM8XX_GRP
845 };
846 
847 #define NPCM8XX_SFUNC(a) NPCM8XX_FUNC(a, #a)
848 #define NPCM8XX_FUNC(a, b...) static const char *a ## _grp[] = { b }
849 #define NPCM8XX_MKFUNC(nm) { .name = #nm, .ngroups = ARRAY_SIZE(nm ## _grp), \
850 			.groups = nm ## _grp }
851 struct npcm8xx_func {
852 	const char *name;
853 	const unsigned int ngroups;
854 	const char *const *groups;
855 };
856 
857 NPCM8XX_SFUNC(gpi36);
858 NPCM8XX_SFUNC(gpi35);
859 NPCM8XX_SFUNC(tp_jtag3);
860 NPCM8XX_SFUNC(tp_uart);
861 NPCM8XX_SFUNC(tp_smb2);
862 NPCM8XX_SFUNC(tp_smb1);
863 NPCM8XX_SFUNC(tp_gpio7);
864 NPCM8XX_SFUNC(tp_gpio6);
865 NPCM8XX_SFUNC(tp_gpio5);
866 NPCM8XX_SFUNC(tp_gpio4);
867 NPCM8XX_SFUNC(tp_gpio3);
868 NPCM8XX_SFUNC(tp_gpio2);
869 NPCM8XX_SFUNC(tp_gpio1);
870 NPCM8XX_SFUNC(tp_gpio0);
871 NPCM8XX_SFUNC(tp_gpio2b);
872 NPCM8XX_SFUNC(tp_gpio1b);
873 NPCM8XX_SFUNC(tp_gpio0b);
874 NPCM8XX_SFUNC(vgadig);
875 NPCM8XX_SFUNC(nbu1crts);
876 NPCM8XX_SFUNC(fm2);
877 NPCM8XX_SFUNC(fm1);
878 NPCM8XX_SFUNC(fm0);
879 NPCM8XX_SFUNC(gpio1836);
880 NPCM8XX_SFUNC(gpio1889);
881 NPCM8XX_SFUNC(gpo187);
882 NPCM8XX_SFUNC(cp1urxd);
883 NPCM8XX_SFUNC(r3rxer);
884 NPCM8XX_SFUNC(cp1gpio2c);
885 NPCM8XX_SFUNC(cp1gpio3c);
886 NPCM8XX_SFUNC(cp1gpio0b);
887 NPCM8XX_SFUNC(cp1gpio1b);
888 NPCM8XX_SFUNC(cp1gpio2b);
889 NPCM8XX_SFUNC(cp1gpio3b);
890 NPCM8XX_SFUNC(cp1gpio4b);
891 NPCM8XX_SFUNC(cp1gpio5b);
892 NPCM8XX_SFUNC(cp1gpio6b);
893 NPCM8XX_SFUNC(cp1gpio7b);
894 NPCM8XX_SFUNC(cp1gpio0);
895 NPCM8XX_SFUNC(cp1gpio1);
896 NPCM8XX_SFUNC(cp1gpio2);
897 NPCM8XX_SFUNC(cp1gpio3);
898 NPCM8XX_SFUNC(cp1gpio4);
899 NPCM8XX_SFUNC(cp1gpio5);
900 NPCM8XX_SFUNC(cp1gpio6);
901 NPCM8XX_SFUNC(cp1gpio7);
902 NPCM8XX_SFUNC(cp1utxd);
903 NPCM8XX_SFUNC(spi1cs3);
904 NPCM8XX_SFUNC(spi1cs2);
905 NPCM8XX_SFUNC(spi1cs1);
906 NPCM8XX_SFUNC(spi1cs0);
907 NPCM8XX_SFUNC(spi1d23);
908 NPCM8XX_SFUNC(j2j3);
909 NPCM8XX_SFUNC(r3oen);
910 NPCM8XX_SFUNC(r2oen);
911 NPCM8XX_SFUNC(r1oen);
912 NPCM8XX_SFUNC(bu4b);
913 NPCM8XX_SFUNC(bu4);
914 NPCM8XX_SFUNC(bu5b);
915 NPCM8XX_SFUNC(bu5);
916 NPCM8XX_SFUNC(bu6);
917 NPCM8XX_SFUNC(rmii3);
918 NPCM8XX_SFUNC(jm1);
919 NPCM8XX_SFUNC(jm2);
920 NPCM8XX_SFUNC(tpgpio5b);
921 NPCM8XX_SFUNC(tpgpio4b);
922 NPCM8XX_SFUNC(clkrun);
923 NPCM8XX_SFUNC(i3c5);
924 NPCM8XX_SFUNC(i3c4);
925 NPCM8XX_SFUNC(i3c3);
926 NPCM8XX_SFUNC(i3c2);
927 NPCM8XX_SFUNC(i3c1);
928 NPCM8XX_SFUNC(i3c0);
929 NPCM8XX_SFUNC(hsi1a);
930 NPCM8XX_SFUNC(hsi2a);
931 NPCM8XX_SFUNC(hsi1b);
932 NPCM8XX_SFUNC(hsi2b);
933 NPCM8XX_SFUNC(hsi1c);
934 NPCM8XX_SFUNC(hsi2c);
935 NPCM8XX_SFUNC(smb0);
936 NPCM8XX_SFUNC(smb0b);
937 NPCM8XX_SFUNC(smb0c);
938 NPCM8XX_SFUNC(smb0d);
939 NPCM8XX_SFUNC(smb0den);
940 NPCM8XX_SFUNC(smb1);
941 NPCM8XX_SFUNC(smb1b);
942 NPCM8XX_SFUNC(smb1c);
943 NPCM8XX_SFUNC(smb1d);
944 NPCM8XX_SFUNC(smb2);
945 NPCM8XX_SFUNC(smb2b);
946 NPCM8XX_SFUNC(smb2c);
947 NPCM8XX_SFUNC(smb2d);
948 NPCM8XX_SFUNC(smb3);
949 NPCM8XX_SFUNC(smb3b);
950 NPCM8XX_SFUNC(smb3c);
951 NPCM8XX_SFUNC(smb3d);
952 NPCM8XX_SFUNC(smb4);
953 NPCM8XX_SFUNC(smb4b);
954 NPCM8XX_SFUNC(smb4c);
955 NPCM8XX_SFUNC(smb4d);
956 NPCM8XX_SFUNC(smb4den);
957 NPCM8XX_SFUNC(smb5);
958 NPCM8XX_SFUNC(smb5b);
959 NPCM8XX_SFUNC(smb5c);
960 NPCM8XX_SFUNC(smb5d);
961 NPCM8XX_SFUNC(ga20kbc);
962 NPCM8XX_SFUNC(smb6);
963 NPCM8XX_SFUNC(smb6b);
964 NPCM8XX_SFUNC(smb6c);
965 NPCM8XX_SFUNC(smb6d);
966 NPCM8XX_SFUNC(smb7);
967 NPCM8XX_SFUNC(smb7b);
968 NPCM8XX_SFUNC(smb7c);
969 NPCM8XX_SFUNC(smb7d);
970 NPCM8XX_SFUNC(smb8);
971 NPCM8XX_SFUNC(smb9);
972 NPCM8XX_SFUNC(smb10);
973 NPCM8XX_SFUNC(smb11);
974 NPCM8XX_SFUNC(smb12);
975 NPCM8XX_SFUNC(smb13);
976 NPCM8XX_SFUNC(smb14);
977 NPCM8XX_SFUNC(smb14b);
978 NPCM8XX_SFUNC(smb15);
979 NPCM8XX_SFUNC(smb16);
980 NPCM8XX_SFUNC(smb16b);
981 NPCM8XX_SFUNC(smb17);
982 NPCM8XX_SFUNC(smb18);
983 NPCM8XX_SFUNC(smb19);
984 NPCM8XX_SFUNC(smb20);
985 NPCM8XX_SFUNC(smb21);
986 NPCM8XX_SFUNC(smb22);
987 NPCM8XX_SFUNC(smb23);
988 NPCM8XX_SFUNC(smb23b);
989 NPCM8XX_SFUNC(fanin0);
990 NPCM8XX_SFUNC(fanin1);
991 NPCM8XX_SFUNC(fanin2);
992 NPCM8XX_SFUNC(fanin3);
993 NPCM8XX_SFUNC(fanin4);
994 NPCM8XX_SFUNC(fanin5);
995 NPCM8XX_SFUNC(fanin6);
996 NPCM8XX_SFUNC(fanin7);
997 NPCM8XX_SFUNC(fanin8);
998 NPCM8XX_SFUNC(fanin9);
999 NPCM8XX_SFUNC(fanin10);
1000 NPCM8XX_SFUNC(fanin11);
1001 NPCM8XX_SFUNC(fanin12);
1002 NPCM8XX_SFUNC(fanin13);
1003 NPCM8XX_SFUNC(fanin14);
1004 NPCM8XX_SFUNC(fanin15);
1005 NPCM8XX_SFUNC(faninx);
1006 NPCM8XX_SFUNC(pwm0);
1007 NPCM8XX_SFUNC(pwm1);
1008 NPCM8XX_SFUNC(pwm2);
1009 NPCM8XX_SFUNC(pwm3);
1010 NPCM8XX_SFUNC(pwm4);
1011 NPCM8XX_SFUNC(pwm5);
1012 NPCM8XX_SFUNC(pwm6);
1013 NPCM8XX_SFUNC(pwm7);
1014 NPCM8XX_SFUNC(pwm8);
1015 NPCM8XX_SFUNC(pwm9);
1016 NPCM8XX_SFUNC(pwm10);
1017 NPCM8XX_SFUNC(pwm11);
1018 NPCM8XX_SFUNC(sg1mdio);
1019 NPCM8XX_SFUNC(rg2);
1020 NPCM8XX_SFUNC(rg2mdio);
1021 NPCM8XX_SFUNC(ddr);
1022 NPCM8XX_SFUNC(uart1);
1023 NPCM8XX_SFUNC(uart2);
1024 NPCM8XX_SFUNC(bmcuart0a);
1025 NPCM8XX_SFUNC(bmcuart0b);
1026 NPCM8XX_SFUNC(bmcuart1);
1027 NPCM8XX_SFUNC(iox1);
1028 NPCM8XX_SFUNC(iox2);
1029 NPCM8XX_SFUNC(ioxh);
1030 NPCM8XX_SFUNC(gspi);
1031 NPCM8XX_SFUNC(mmc);
1032 NPCM8XX_SFUNC(mmcwp);
1033 NPCM8XX_SFUNC(mmccd);
1034 NPCM8XX_SFUNC(mmcrst);
1035 NPCM8XX_SFUNC(mmc8);
1036 NPCM8XX_SFUNC(r1);
1037 NPCM8XX_SFUNC(r1err);
1038 NPCM8XX_SFUNC(r1md);
1039 NPCM8XX_SFUNC(r2);
1040 NPCM8XX_SFUNC(r2err);
1041 NPCM8XX_SFUNC(r2md);
1042 NPCM8XX_SFUNC(sd1);
1043 NPCM8XX_SFUNC(sd1pwr);
1044 NPCM8XX_SFUNC(wdog1);
1045 NPCM8XX_SFUNC(wdog2);
1046 NPCM8XX_SFUNC(scipme);
1047 NPCM8XX_SFUNC(smi);
1048 NPCM8XX_SFUNC(serirq);
1049 NPCM8XX_SFUNC(jtag2);
1050 NPCM8XX_SFUNC(spix);
1051 NPCM8XX_SFUNC(spixcs1);
1052 NPCM8XX_SFUNC(spi1);
1053 NPCM8XX_SFUNC(pspi);
1054 NPCM8XX_SFUNC(ddc);
1055 NPCM8XX_SFUNC(clkreq);
1056 NPCM8XX_SFUNC(clkout);
1057 NPCM8XX_SFUNC(spi3);
1058 NPCM8XX_SFUNC(spi3cs1);
1059 NPCM8XX_SFUNC(spi3quad);
1060 NPCM8XX_SFUNC(spi3cs2);
1061 NPCM8XX_SFUNC(spi3cs3);
1062 NPCM8XX_SFUNC(spi0cs1);
1063 NPCM8XX_SFUNC(lpc);
1064 NPCM8XX_SFUNC(lpcclk);
1065 NPCM8XX_SFUNC(espi);
1066 NPCM8XX_SFUNC(lkgpo0);
1067 NPCM8XX_SFUNC(lkgpo1);
1068 NPCM8XX_SFUNC(lkgpo2);
1069 NPCM8XX_SFUNC(nprd_smi);
1070 NPCM8XX_SFUNC(hgpio0);
1071 NPCM8XX_SFUNC(hgpio1);
1072 NPCM8XX_SFUNC(hgpio2);
1073 NPCM8XX_SFUNC(hgpio3);
1074 NPCM8XX_SFUNC(hgpio4);
1075 NPCM8XX_SFUNC(hgpio5);
1076 NPCM8XX_SFUNC(hgpio6);
1077 NPCM8XX_SFUNC(hgpio7);
1078 
1079 /* Function names */
1080 static struct npcm8xx_func npcm8xx_funcs[] = {
1081 	NPCM8XX_MKFUNC(gpi36),
1082 	NPCM8XX_MKFUNC(gpi35),
1083 	NPCM8XX_MKFUNC(tp_jtag3),
1084 	NPCM8XX_MKFUNC(tp_uart),
1085 	NPCM8XX_MKFUNC(tp_smb2),
1086 	NPCM8XX_MKFUNC(tp_smb1),
1087 	NPCM8XX_MKFUNC(tp_gpio7),
1088 	NPCM8XX_MKFUNC(tp_gpio6),
1089 	NPCM8XX_MKFUNC(tp_gpio5),
1090 	NPCM8XX_MKFUNC(tp_gpio4),
1091 	NPCM8XX_MKFUNC(tp_gpio3),
1092 	NPCM8XX_MKFUNC(tp_gpio2),
1093 	NPCM8XX_MKFUNC(tp_gpio1),
1094 	NPCM8XX_MKFUNC(tp_gpio0),
1095 	NPCM8XX_MKFUNC(tp_gpio2b),
1096 	NPCM8XX_MKFUNC(tp_gpio1b),
1097 	NPCM8XX_MKFUNC(tp_gpio0b),
1098 	NPCM8XX_MKFUNC(vgadig),
1099 	NPCM8XX_MKFUNC(nbu1crts),
1100 	NPCM8XX_MKFUNC(fm2),
1101 	NPCM8XX_MKFUNC(fm1),
1102 	NPCM8XX_MKFUNC(fm0),
1103 	NPCM8XX_MKFUNC(gpio1836),
1104 	NPCM8XX_MKFUNC(gpio1889),
1105 	NPCM8XX_MKFUNC(gpo187),
1106 	NPCM8XX_MKFUNC(cp1urxd),
1107 	NPCM8XX_MKFUNC(r3rxer),
1108 	NPCM8XX_MKFUNC(cp1gpio2c),
1109 	NPCM8XX_MKFUNC(cp1gpio3c),
1110 	NPCM8XX_MKFUNC(cp1gpio0b),
1111 	NPCM8XX_MKFUNC(cp1gpio1b),
1112 	NPCM8XX_MKFUNC(cp1gpio2b),
1113 	NPCM8XX_MKFUNC(cp1gpio3b),
1114 	NPCM8XX_MKFUNC(cp1gpio4b),
1115 	NPCM8XX_MKFUNC(cp1gpio5b),
1116 	NPCM8XX_MKFUNC(cp1gpio6b),
1117 	NPCM8XX_MKFUNC(cp1gpio7b),
1118 	NPCM8XX_MKFUNC(cp1gpio0),
1119 	NPCM8XX_MKFUNC(cp1gpio1),
1120 	NPCM8XX_MKFUNC(cp1gpio2),
1121 	NPCM8XX_MKFUNC(cp1gpio3),
1122 	NPCM8XX_MKFUNC(cp1gpio4),
1123 	NPCM8XX_MKFUNC(cp1gpio5),
1124 	NPCM8XX_MKFUNC(cp1gpio6),
1125 	NPCM8XX_MKFUNC(cp1gpio7),
1126 	NPCM8XX_MKFUNC(cp1utxd),
1127 	NPCM8XX_MKFUNC(spi1cs3),
1128 	NPCM8XX_MKFUNC(spi1cs2),
1129 	NPCM8XX_MKFUNC(spi1cs1),
1130 	NPCM8XX_MKFUNC(spi1cs0),
1131 	NPCM8XX_MKFUNC(spi1d23),
1132 	NPCM8XX_MKFUNC(j2j3),
1133 	NPCM8XX_MKFUNC(r3oen),
1134 	NPCM8XX_MKFUNC(r2oen),
1135 	NPCM8XX_MKFUNC(r1oen),
1136 	NPCM8XX_MKFUNC(bu4b),
1137 	NPCM8XX_MKFUNC(bu4),
1138 	NPCM8XX_MKFUNC(bu5b),
1139 	NPCM8XX_MKFUNC(bu5),
1140 	NPCM8XX_MKFUNC(bu6),
1141 	NPCM8XX_MKFUNC(rmii3),
1142 	NPCM8XX_MKFUNC(jm1),
1143 	NPCM8XX_MKFUNC(jm2),
1144 	NPCM8XX_MKFUNC(tpgpio5b),
1145 	NPCM8XX_MKFUNC(tpgpio4b),
1146 	NPCM8XX_MKFUNC(clkrun),
1147 	NPCM8XX_MKFUNC(i3c5),
1148 	NPCM8XX_MKFUNC(i3c4),
1149 	NPCM8XX_MKFUNC(i3c3),
1150 	NPCM8XX_MKFUNC(i3c2),
1151 	NPCM8XX_MKFUNC(i3c1),
1152 	NPCM8XX_MKFUNC(i3c0),
1153 	NPCM8XX_MKFUNC(hsi1a),
1154 	NPCM8XX_MKFUNC(hsi2a),
1155 	NPCM8XX_MKFUNC(hsi1b),
1156 	NPCM8XX_MKFUNC(hsi2b),
1157 	NPCM8XX_MKFUNC(hsi1c),
1158 	NPCM8XX_MKFUNC(hsi2c),
1159 	NPCM8XX_MKFUNC(smb0),
1160 	NPCM8XX_MKFUNC(smb0b),
1161 	NPCM8XX_MKFUNC(smb0c),
1162 	NPCM8XX_MKFUNC(smb0d),
1163 	NPCM8XX_MKFUNC(smb0den),
1164 	NPCM8XX_MKFUNC(smb1),
1165 	NPCM8XX_MKFUNC(smb1b),
1166 	NPCM8XX_MKFUNC(smb1c),
1167 	NPCM8XX_MKFUNC(smb1d),
1168 	NPCM8XX_MKFUNC(smb2),
1169 	NPCM8XX_MKFUNC(smb2b),
1170 	NPCM8XX_MKFUNC(smb2c),
1171 	NPCM8XX_MKFUNC(smb2d),
1172 	NPCM8XX_MKFUNC(smb3),
1173 	NPCM8XX_MKFUNC(smb3b),
1174 	NPCM8XX_MKFUNC(smb3c),
1175 	NPCM8XX_MKFUNC(smb3d),
1176 	NPCM8XX_MKFUNC(smb4),
1177 	NPCM8XX_MKFUNC(smb4b),
1178 	NPCM8XX_MKFUNC(smb4c),
1179 	NPCM8XX_MKFUNC(smb4d),
1180 	NPCM8XX_MKFUNC(smb4den),
1181 	NPCM8XX_MKFUNC(smb5),
1182 	NPCM8XX_MKFUNC(smb5b),
1183 	NPCM8XX_MKFUNC(smb5c),
1184 	NPCM8XX_MKFUNC(smb5d),
1185 	NPCM8XX_MKFUNC(ga20kbc),
1186 	NPCM8XX_MKFUNC(smb6),
1187 	NPCM8XX_MKFUNC(smb6b),
1188 	NPCM8XX_MKFUNC(smb6c),
1189 	NPCM8XX_MKFUNC(smb6d),
1190 	NPCM8XX_MKFUNC(smb7),
1191 	NPCM8XX_MKFUNC(smb7b),
1192 	NPCM8XX_MKFUNC(smb7c),
1193 	NPCM8XX_MKFUNC(smb7d),
1194 	NPCM8XX_MKFUNC(smb8),
1195 	NPCM8XX_MKFUNC(smb9),
1196 	NPCM8XX_MKFUNC(smb10),
1197 	NPCM8XX_MKFUNC(smb11),
1198 	NPCM8XX_MKFUNC(smb12),
1199 	NPCM8XX_MKFUNC(smb13),
1200 	NPCM8XX_MKFUNC(smb14),
1201 	NPCM8XX_MKFUNC(smb14b),
1202 	NPCM8XX_MKFUNC(smb15),
1203 	NPCM8XX_MKFUNC(smb16),
1204 	NPCM8XX_MKFUNC(smb16b),
1205 	NPCM8XX_MKFUNC(smb17),
1206 	NPCM8XX_MKFUNC(smb18),
1207 	NPCM8XX_MKFUNC(smb19),
1208 	NPCM8XX_MKFUNC(smb20),
1209 	NPCM8XX_MKFUNC(smb21),
1210 	NPCM8XX_MKFUNC(smb22),
1211 	NPCM8XX_MKFUNC(smb23),
1212 	NPCM8XX_MKFUNC(smb23b),
1213 	NPCM8XX_MKFUNC(fanin0),
1214 	NPCM8XX_MKFUNC(fanin1),
1215 	NPCM8XX_MKFUNC(fanin2),
1216 	NPCM8XX_MKFUNC(fanin3),
1217 	NPCM8XX_MKFUNC(fanin4),
1218 	NPCM8XX_MKFUNC(fanin5),
1219 	NPCM8XX_MKFUNC(fanin6),
1220 	NPCM8XX_MKFUNC(fanin7),
1221 	NPCM8XX_MKFUNC(fanin8),
1222 	NPCM8XX_MKFUNC(fanin9),
1223 	NPCM8XX_MKFUNC(fanin10),
1224 	NPCM8XX_MKFUNC(fanin11),
1225 	NPCM8XX_MKFUNC(fanin12),
1226 	NPCM8XX_MKFUNC(fanin13),
1227 	NPCM8XX_MKFUNC(fanin14),
1228 	NPCM8XX_MKFUNC(fanin15),
1229 	NPCM8XX_MKFUNC(faninx),
1230 	NPCM8XX_MKFUNC(pwm0),
1231 	NPCM8XX_MKFUNC(pwm1),
1232 	NPCM8XX_MKFUNC(pwm2),
1233 	NPCM8XX_MKFUNC(pwm3),
1234 	NPCM8XX_MKFUNC(pwm4),
1235 	NPCM8XX_MKFUNC(pwm5),
1236 	NPCM8XX_MKFUNC(pwm6),
1237 	NPCM8XX_MKFUNC(pwm7),
1238 	NPCM8XX_MKFUNC(pwm8),
1239 	NPCM8XX_MKFUNC(pwm9),
1240 	NPCM8XX_MKFUNC(pwm10),
1241 	NPCM8XX_MKFUNC(pwm11),
1242 	NPCM8XX_MKFUNC(sg1mdio),
1243 	NPCM8XX_MKFUNC(rg2),
1244 	NPCM8XX_MKFUNC(rg2mdio),
1245 	NPCM8XX_MKFUNC(ddr),
1246 	NPCM8XX_MKFUNC(uart1),
1247 	NPCM8XX_MKFUNC(uart2),
1248 	NPCM8XX_MKFUNC(bmcuart0a),
1249 	NPCM8XX_MKFUNC(bmcuart0b),
1250 	NPCM8XX_MKFUNC(bmcuart1),
1251 	NPCM8XX_MKFUNC(iox1),
1252 	NPCM8XX_MKFUNC(iox2),
1253 	NPCM8XX_MKFUNC(ioxh),
1254 	NPCM8XX_MKFUNC(gspi),
1255 	NPCM8XX_MKFUNC(mmc),
1256 	NPCM8XX_MKFUNC(mmcwp),
1257 	NPCM8XX_MKFUNC(mmccd),
1258 	NPCM8XX_MKFUNC(mmcrst),
1259 	NPCM8XX_MKFUNC(mmc8),
1260 	NPCM8XX_MKFUNC(r1),
1261 	NPCM8XX_MKFUNC(r1err),
1262 	NPCM8XX_MKFUNC(r1md),
1263 	NPCM8XX_MKFUNC(r2),
1264 	NPCM8XX_MKFUNC(r2err),
1265 	NPCM8XX_MKFUNC(r2md),
1266 	NPCM8XX_MKFUNC(sd1),
1267 	NPCM8XX_MKFUNC(sd1pwr),
1268 	NPCM8XX_MKFUNC(wdog1),
1269 	NPCM8XX_MKFUNC(wdog2),
1270 	NPCM8XX_MKFUNC(scipme),
1271 	NPCM8XX_MKFUNC(smi),
1272 	NPCM8XX_MKFUNC(serirq),
1273 	NPCM8XX_MKFUNC(jtag2),
1274 	NPCM8XX_MKFUNC(spix),
1275 	NPCM8XX_MKFUNC(spixcs1),
1276 	NPCM8XX_MKFUNC(spi1),
1277 	NPCM8XX_MKFUNC(pspi),
1278 	NPCM8XX_MKFUNC(ddc),
1279 	NPCM8XX_MKFUNC(clkreq),
1280 	NPCM8XX_MKFUNC(clkout),
1281 	NPCM8XX_MKFUNC(spi3),
1282 	NPCM8XX_MKFUNC(spi3cs1),
1283 	NPCM8XX_MKFUNC(spi3quad),
1284 	NPCM8XX_MKFUNC(spi3cs2),
1285 	NPCM8XX_MKFUNC(spi3cs3),
1286 	NPCM8XX_MKFUNC(spi0cs1),
1287 	NPCM8XX_MKFUNC(lpc),
1288 	NPCM8XX_MKFUNC(lpcclk),
1289 	NPCM8XX_MKFUNC(espi),
1290 	NPCM8XX_MKFUNC(lkgpo0),
1291 	NPCM8XX_MKFUNC(lkgpo1),
1292 	NPCM8XX_MKFUNC(lkgpo2),
1293 	NPCM8XX_MKFUNC(nprd_smi),
1294 	NPCM8XX_MKFUNC(hgpio0),
1295 	NPCM8XX_MKFUNC(hgpio1),
1296 	NPCM8XX_MKFUNC(hgpio2),
1297 	NPCM8XX_MKFUNC(hgpio3),
1298 	NPCM8XX_MKFUNC(hgpio4),
1299 	NPCM8XX_MKFUNC(hgpio5),
1300 	NPCM8XX_MKFUNC(hgpio6),
1301 	NPCM8XX_MKFUNC(hgpio7),
1302 };
1303 
1304 #define NPCM8XX_PINCFG(a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, q) \
1305 	[a] { .fn0 = fn_ ## b, .reg0 = NPCM8XX_GCR_ ## c, .bit0 = d, \
1306 			.fn1 = fn_ ## e, .reg1 = NPCM8XX_GCR_ ## f, .bit1 = g, \
1307 			.fn2 = fn_ ## h, .reg2 = NPCM8XX_GCR_ ## i, .bit2 = j, \
1308 			.fn3 = fn_ ## k, .reg3 = NPCM8XX_GCR_ ## l, .bit3 = m, \
1309 			.fn4 = fn_ ## n, .reg4 = NPCM8XX_GCR_ ## o, .bit4 = p, \
1310 			.flag = q }
1311 
1312 /* Drive strength controlled by NPCM8XX_GP_N_ODSC */
1313 #define DRIVE_STRENGTH_LO_SHIFT		8
1314 #define DRIVE_STRENGTH_HI_SHIFT		12
1315 #define DRIVE_STRENGTH_MASK		GENMASK(15, 8)
1316 
1317 #define DSTR(lo, hi)	(((lo) << DRIVE_STRENGTH_LO_SHIFT) | \
1318 			 ((hi) << DRIVE_STRENGTH_HI_SHIFT))
1319 #define DSLO(x)		(((x) >> DRIVE_STRENGTH_LO_SHIFT) & GENMASK(3, 0))
1320 #define DSHI(x)		(((x) >> DRIVE_STRENGTH_HI_SHIFT) & GENMASK(3, 0))
1321 
1322 #define GPI		BIT(0) /* Not GPO */
1323 #define GPO		BIT(1) /* Not GPI */
1324 #define SLEW		BIT(2) /* Has Slew Control, NPCM8XX_GP_N_OSRC */
1325 #define SLEWLPC		BIT(3) /* Has Slew Control, SRCNT.3 */
1326 
1327 struct npcm8xx_pincfg {
1328 	int flag;
1329 	int fn0, reg0, bit0;
1330 	int fn1, reg1, bit1;
1331 	int fn2, reg2, bit2;
1332 	int fn3, reg3, bit3;
1333 	int fn4, reg4, bit4;
1334 };
1335 
1336 static const struct npcm8xx_pincfg pincfg[] = {
1337 	/*		PIN	  FUNCTION 1		   FUNCTION 2		  FUNCTION 3		FUNCTION 4		FUNCTION 5		FLAGS */
1338 	NPCM8XX_PINCFG(0,	iox1, MFSEL1, 30,	smb6c, I2CSEGSEL, 25,	smb18, MFSEL5, 26,	none, NONE, 0,		none, NONE, 0,		SLEW),
1339 	NPCM8XX_PINCFG(1,	iox1, MFSEL1, 30,	smb6c, I2CSEGSEL, 25,	smb18, MFSEL5, 26,	none, NONE, 0,		none, NONE, 0,		SLEW),
1340 	NPCM8XX_PINCFG(2,	iox1, MFSEL1, 30,	smb6b, I2CSEGSEL, 24,	smb17, MFSEL5, 25,	none, NONE, 0,		none, NONE, 0,		SLEW),
1341 	NPCM8XX_PINCFG(3,	iox1, MFSEL1, 30,	smb6b, I2CSEGSEL, 24,	smb17, MFSEL5, 25,	none, NONE, 0,		none, NONE, 0,		SLEW),
1342 	NPCM8XX_PINCFG(4,	iox2, MFSEL3, 14,	smb1d, I2CSEGSEL, 7,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1343 	NPCM8XX_PINCFG(5,	iox2, MFSEL3, 14,	smb1d, I2CSEGSEL, 7,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1344 	NPCM8XX_PINCFG(6,	iox2, MFSEL3, 14,	smb2d, I2CSEGSEL, 10,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1345 	NPCM8XX_PINCFG(7,	iox2, MFSEL3, 14,	smb2d, I2CSEGSEL, 10,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1346 	NPCM8XX_PINCFG(8,	lkgpo1,	FLOCKR1, 4,	tp_gpio0b, MFSEL7, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12)),
1347 	NPCM8XX_PINCFG(9,	lkgpo2,	FLOCKR1, 8,	tp_gpio1b, MFSEL7, 9,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12)),
1348 	NPCM8XX_PINCFG(10,	ioxh, MFSEL3, 18,	smb6d, I2CSEGSEL, 26,	smb16, MFSEL5, 24,	none, NONE, 0,		none, NONE, 0,		SLEW),
1349 	NPCM8XX_PINCFG(11,	ioxh, MFSEL3, 18,	smb6d, I2CSEGSEL, 26,	smb16, MFSEL5, 24,	none, NONE, 0,		none, NONE, 0,		SLEW),
1350 	NPCM8XX_PINCFG(12,	gspi, MFSEL1, 24,	smb5b, I2CSEGSEL, 19,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1351 	NPCM8XX_PINCFG(13,	gspi, MFSEL1, 24,	smb5b, I2CSEGSEL, 19,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1352 	NPCM8XX_PINCFG(14,	gspi, MFSEL1, 24,	smb5c, I2CSEGSEL, 20,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1353 	NPCM8XX_PINCFG(15,	gspi, MFSEL1, 24,	smb5c, I2CSEGSEL, 20,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1354 	NPCM8XX_PINCFG(16,	lkgpo0, FLOCKR1, 0,	smb7b, I2CSEGSEL, 27,	tp_gpio2b, MFSEL7, 10,	none, NONE, 0,		none, NONE, 0,		SLEW),
1355 	NPCM8XX_PINCFG(17,	pspi, MFSEL3, 13,	cp1gpio5, MFSEL6, 7,	smb4den, I2CSEGSEL, 23,	none, NONE, 0,		none, NONE, 0,		SLEW),
1356 	NPCM8XX_PINCFG(18,	pspi, MFSEL3, 13,	smb4b, I2CSEGSEL, 14,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1357 	NPCM8XX_PINCFG(19,	pspi, MFSEL3, 13,	smb4b, I2CSEGSEL, 14,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1358 	NPCM8XX_PINCFG(20,	hgpio0,	MFSEL2, 24,	smb15, MFSEL3, 8,	smb4c, I2CSEGSEL, 15,	none, NONE, 0,		none, NONE, 0,		SLEW),
1359 	NPCM8XX_PINCFG(21,	hgpio1,	MFSEL2, 25,	smb15, MFSEL3, 8,	smb4c, I2CSEGSEL, 15,	none, NONE, 0,		none, NONE, 0,		SLEW),
1360 	NPCM8XX_PINCFG(22,	hgpio2,	MFSEL2, 26,	smb14, MFSEL3, 7,	smb4d, I2CSEGSEL, 16,	none, NONE, 0,		none, NONE, 0,		SLEW),
1361 	NPCM8XX_PINCFG(23,	hgpio3,	MFSEL2, 27,	smb14, MFSEL3, 7,	smb4d, I2CSEGSEL, 16,	none, NONE, 0,		none, NONE, 0,		SLEW),
1362 	NPCM8XX_PINCFG(24,	hgpio4,	MFSEL2, 28,	ioxh, MFSEL3, 18,	smb7c, I2CSEGSEL, 28,	tp_smb2, MFSEL7, 28,	none, NONE, 0,		SLEW),
1363 	NPCM8XX_PINCFG(25,	hgpio5,	MFSEL2, 29,	ioxh, MFSEL3, 18,	smb7c, I2CSEGSEL, 28,	tp_smb2, MFSEL7, 28,	none, NONE, 0,		SLEW),
1364 	NPCM8XX_PINCFG(26,	smb5, MFSEL1, 2,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1365 	NPCM8XX_PINCFG(27,	smb5, MFSEL1, 2,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1366 	NPCM8XX_PINCFG(28,	smb4, MFSEL1, 1,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1367 	NPCM8XX_PINCFG(29,	smb4, MFSEL1, 1,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1368 	NPCM8XX_PINCFG(30,	smb3, MFSEL1, 0,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1369 	NPCM8XX_PINCFG(31,	smb3, MFSEL1, 0,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1370 	NPCM8XX_PINCFG(32,	spi0cs1, MFSEL1, 3,	smb14b, MFSEL7, 26,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1371 	NPCM8XX_PINCFG(33,	i3c4, MFSEL6, 10,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1372 	NPCM8XX_PINCFG(34,	i3c4, MFSEL6, 10,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1373 	NPCM8XX_PINCFG(37,	smb3c, I2CSEGSEL, 12,	smb23, MFSEL5, 31,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1374 	NPCM8XX_PINCFG(38,	smb3c, I2CSEGSEL, 12,	smb23, MFSEL5, 31,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1375 	NPCM8XX_PINCFG(39,	smb3b, I2CSEGSEL, 11,	smb22, MFSEL5, 30,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1376 	NPCM8XX_PINCFG(40,	smb3b, I2CSEGSEL, 11,	smb22, MFSEL5, 30,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1377 	NPCM8XX_PINCFG(41,	bmcuart0a, MFSEL1, 9,	cp1urxd, MFSEL6, 31,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1378 	NPCM8XX_PINCFG(42,	bmcuart0a, MFSEL1, 9,	cp1utxd, MFSEL6, 1,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(2, 4) | GPO),
1379 	NPCM8XX_PINCFG(43,	uart1, MFSEL1, 10,	bmcuart1, MFSEL3, 24,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1380 	NPCM8XX_PINCFG(44,	hsi1b, MFSEL1, 28,	nbu1crts, MFSEL6, 15,	jtag2, MFSEL4, 0,	tp_jtag3, MFSEL7, 13,	j2j3, MFSEL5, 2,	GPO),
1381 	NPCM8XX_PINCFG(45,	hsi1c, MFSEL1, 4,	jtag2, MFSEL4, 0,	j2j3, MFSEL5, 2,	tp_jtag3, MFSEL7, 13,	none, NONE, 0,		GPO),
1382 	NPCM8XX_PINCFG(46,	hsi1c, MFSEL1, 4,	jtag2, MFSEL4, 0,	j2j3, MFSEL5, 2,	tp_jtag3, MFSEL7, 13,	none, NONE, 0,		GPO),
1383 	NPCM8XX_PINCFG(47,	hsi1c, MFSEL1, 4,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(2, 8)),
1384 	NPCM8XX_PINCFG(48,	hsi2a, MFSEL1, 11,	bmcuart0b, MFSEL4, 1,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1385 	NPCM8XX_PINCFG(49,	hsi2a, MFSEL1, 11,	bmcuart0b, MFSEL4, 1,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1386 	NPCM8XX_PINCFG(50,	hsi2b, MFSEL1, 29,	bu6, MFSEL5, 6,		tp_uart, MFSEL7, 12,	none, NONE, 0,		none, NONE, 0,		GPO),
1387 	NPCM8XX_PINCFG(51,	hsi2b, MFSEL1, 29,	bu6, MFSEL5, 6,		tp_uart, MFSEL7, 12,	none, NONE, 0,		none, NONE, 0,		GPO),
1388 	NPCM8XX_PINCFG(52,	hsi2c, MFSEL1, 5,	bu5, MFSEL5, 7,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1389 	NPCM8XX_PINCFG(53,	hsi2c, MFSEL1, 5,	bu5, MFSEL5, 7,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1390 	NPCM8XX_PINCFG(54,	hsi2c, MFSEL1, 5,	bu4, MFSEL5, 8,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1391 	NPCM8XX_PINCFG(55,	hsi2c, MFSEL1, 5,	bu4, MFSEL5, 8,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1392 	NPCM8XX_PINCFG(56,	r1err, MFSEL1, 12,	r1oen, MFSEL5, 9,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1393 	NPCM8XX_PINCFG(57,	r1md, MFSEL1, 13,	tpgpio4b, MFSEL5, 20,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(2, 4)),
1394 	NPCM8XX_PINCFG(58,	r1md, MFSEL1, 13,	tpgpio5b, MFSEL5, 22,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(2, 4)),
1395 	NPCM8XX_PINCFG(59,	hgpio6, MFSEL2, 30,	smb3d, I2CSEGSEL, 13,	smb19, MFSEL5, 27,	none, NONE, 0,		none, NONE, 0,		0),
1396 	NPCM8XX_PINCFG(60,	hgpio7, MFSEL2, 31,	smb3d, I2CSEGSEL, 13,	smb19, MFSEL5, 27,	none, NONE, 0,		none, NONE, 0,		0),
1397 	NPCM8XX_PINCFG(61,	hsi1c, MFSEL1, 4,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1398 	NPCM8XX_PINCFG(62,	hsi1b, MFSEL1, 28,	jtag2, MFSEL4, 0,	j2j3, MFSEL5, 2,	nbu1crts, MFSEL6, 15,	tp_jtag3, MFSEL7, 13,	GPO),
1399 	NPCM8XX_PINCFG(63,	hsi1a, MFSEL1, 10,	bmcuart1, MFSEL3, 24,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1400 	NPCM8XX_PINCFG(64,	fanin0, MFSEL2, 0,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1401 	NPCM8XX_PINCFG(65,	fanin1, MFSEL2, 1,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1402 	NPCM8XX_PINCFG(66,	fanin2, MFSEL2, 2,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1403 	NPCM8XX_PINCFG(67,	fanin3, MFSEL2, 3,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1404 	NPCM8XX_PINCFG(68,	fanin4, MFSEL2, 4,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1405 	NPCM8XX_PINCFG(69,	fanin5, MFSEL2, 5,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1406 	NPCM8XX_PINCFG(70,	fanin6, MFSEL2, 6,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1407 	NPCM8XX_PINCFG(71,	fanin7, MFSEL2, 7,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1408 	NPCM8XX_PINCFG(72,	fanin8, MFSEL2, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1409 	NPCM8XX_PINCFG(73,	fanin9, MFSEL2, 9,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1410 	NPCM8XX_PINCFG(74,	fanin10, MFSEL2, 10,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1411 	NPCM8XX_PINCFG(75,	fanin11, MFSEL2, 11,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1412 	NPCM8XX_PINCFG(76,	fanin12, MFSEL2, 12,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1413 	NPCM8XX_PINCFG(77,	fanin13, MFSEL2, 13,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1414 	NPCM8XX_PINCFG(78,	fanin14, MFSEL2, 14,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1415 	NPCM8XX_PINCFG(79,	fanin15, MFSEL2, 15,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1416 	NPCM8XX_PINCFG(80,	pwm0, MFSEL2, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(4, 8)),
1417 	NPCM8XX_PINCFG(81,	pwm1, MFSEL2, 17,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(4, 8)),
1418 	NPCM8XX_PINCFG(82,	pwm2, MFSEL2, 18,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(4, 8)),
1419 	NPCM8XX_PINCFG(83,	pwm3, MFSEL2, 19,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(4, 8)),
1420 	NPCM8XX_PINCFG(84,	r2, MFSEL1, 14,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1421 	NPCM8XX_PINCFG(85,	r2, MFSEL1, 14,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1422 	NPCM8XX_PINCFG(86,	r2, MFSEL1, 14,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1423 	NPCM8XX_PINCFG(87,	r2, MFSEL1, 14,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1424 	NPCM8XX_PINCFG(88,	r2, MFSEL1, 14,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1425 	NPCM8XX_PINCFG(89,	r2, MFSEL1, 14,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1426 	NPCM8XX_PINCFG(90,	r2err, MFSEL1, 15,	r2oen, MFSEL5, 10,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1427 	NPCM8XX_PINCFG(91,	r2md, MFSEL1, 16,	cp1gpio6, MFSEL6, 8,	tp_gpio0, MFSEL7, 0,	none, NONE, 0,		none, NONE, 0,		DSTR(2, 4)),
1428 	NPCM8XX_PINCFG(92,	r2md, MFSEL1, 16,	cp1gpio7, MFSEL6, 9,	tp_gpio1, MFSEL7, 1,	none, NONE, 0,		none, NONE, 0,		DSTR(2, 4)),
1429 	NPCM8XX_PINCFG(93,	ga20kbc, MFSEL1, 17,	smb5d, I2CSEGSEL, 21,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1430 	NPCM8XX_PINCFG(94,	ga20kbc, MFSEL1, 17,	smb5d, I2CSEGSEL, 21,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1431 	NPCM8XX_PINCFG(95,	lpc, MFSEL1, 26,	espi, MFSEL4, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1432 	NPCM8XX_PINCFG(96,	cp1gpio7b, MFSEL6, 24,	tp_gpio7, MFSEL7, 7,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1433 	NPCM8XX_PINCFG(97,	cp1gpio6b, MFSEL6, 25,	tp_gpio6, MFSEL7, 6,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1434 	NPCM8XX_PINCFG(98,	bu4b, MFSEL5, 13,	cp1gpio5b, MFSEL6, 26,	tp_gpio5, MFSEL7, 5,	none, NONE, 0,		none, NONE, 0,		SLEW),
1435 	NPCM8XX_PINCFG(99,	bu4b, MFSEL5, 13,	cp1gpio4b, MFSEL6, 27,	tp_gpio4, MFSEL7, 4,	none, NONE, 0,		none, NONE, 0,		SLEW),
1436 	NPCM8XX_PINCFG(100,	bu5b, MFSEL5, 12,	cp1gpio3c, MFSEL6, 28,	tp_gpio3, MFSEL7, 3,	none, NONE, 0,		none, NONE, 0,		SLEW),
1437 	NPCM8XX_PINCFG(101,	bu5b, MFSEL5, 12,	cp1gpio2c, MFSEL6, 29,	tp_gpio2, MFSEL7, 2,	none, NONE, 0,		none, NONE, 0,		SLEW),
1438 	NPCM8XX_PINCFG(102,	vgadig, MFSEL7, 29,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(4, 8)),
1439 	NPCM8XX_PINCFG(103,	vgadig, MFSEL7, 29,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(4, 8)),
1440 	NPCM8XX_PINCFG(104,	vgadig, MFSEL7, 29,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1441 	NPCM8XX_PINCFG(105,	vgadig, MFSEL7, 29,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1442 	NPCM8XX_PINCFG(106,	i3c5, MFSEL3, 22,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1443 	NPCM8XX_PINCFG(107,	i3c5, MFSEL3, 22,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1444 	NPCM8XX_PINCFG(108,	sg1mdio, MFSEL4, 21,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1445 	NPCM8XX_PINCFG(109,	sg1mdio, MFSEL4, 21,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1446 	NPCM8XX_PINCFG(110,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	rmii3, MFSEL5, 11,	none, NONE, 0,		none, NONE, 0,		0),
1447 	NPCM8XX_PINCFG(111,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	rmii3, MFSEL5, 11,	none, NONE, 0,		none, NONE, 0,		0),
1448 	NPCM8XX_PINCFG(112,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1449 	NPCM8XX_PINCFG(113,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1450 	NPCM8XX_PINCFG(114,	smb0, MFSEL1, 6,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1451 	NPCM8XX_PINCFG(115,	smb0, MFSEL1, 6,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1452 	NPCM8XX_PINCFG(116,	smb1, MFSEL1, 7,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1453 	NPCM8XX_PINCFG(117,	smb1, MFSEL1, 7,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1454 	NPCM8XX_PINCFG(118,	smb2, MFSEL1, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1455 	NPCM8XX_PINCFG(119,	smb2, MFSEL1, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1456 	NPCM8XX_PINCFG(120,	smb2c, I2CSEGSEL, 9,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1457 	NPCM8XX_PINCFG(121,	smb2c, I2CSEGSEL, 9,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1458 	NPCM8XX_PINCFG(122,	smb2b, I2CSEGSEL, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1459 	NPCM8XX_PINCFG(123,	smb2b, I2CSEGSEL, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1460 	NPCM8XX_PINCFG(124,	smb1c, I2CSEGSEL, 6,	cp1gpio3b, MFSEL6, 23,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1461 	NPCM8XX_PINCFG(125,	smb1c, I2CSEGSEL, 6,	cp1gpio2b, MFSEL6, 22,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1462 	NPCM8XX_PINCFG(126,	smb1b, I2CSEGSEL, 5,	cp1gpio1b, MFSEL6, 21,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1463 	NPCM8XX_PINCFG(127,	smb1b, I2CSEGSEL, 5,	cp1gpio0b, MFSEL6, 20,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1464 	NPCM8XX_PINCFG(128,	smb8, MFSEL4, 11,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1465 	NPCM8XX_PINCFG(129,	smb8, MFSEL4, 11,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1466 	NPCM8XX_PINCFG(130,	smb9, MFSEL4, 12,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1467 	NPCM8XX_PINCFG(131,	smb9, MFSEL4, 12,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1468 	NPCM8XX_PINCFG(132,	smb10, MFSEL4, 13,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1469 	NPCM8XX_PINCFG(133,	smb10, MFSEL4, 13,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1470 	NPCM8XX_PINCFG(134,	smb11, MFSEL4, 14,	smb23b, MFSEL6, 0,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1471 	NPCM8XX_PINCFG(135,	smb11, MFSEL4, 14,	smb23b, MFSEL6, 0,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1472 	NPCM8XX_PINCFG(136,	jm1, MFSEL5, 15,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1473 	NPCM8XX_PINCFG(137,	jm1, MFSEL5, 15,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1474 	NPCM8XX_PINCFG(138,	jm1, MFSEL5, 15,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1475 	NPCM8XX_PINCFG(139,	jm1, MFSEL5, 15,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1476 	NPCM8XX_PINCFG(140,	jm1, MFSEL5, 15,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1477 	NPCM8XX_PINCFG(141,	smb7b, I2CSEGSEL, 27,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1478 	NPCM8XX_PINCFG(142,	smb7d, I2CSEGSEL, 29,	tp_smb1, MFSEL7, 11,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1479 	NPCM8XX_PINCFG(143,	smb7d, I2CSEGSEL, 29,	tp_smb1, MFSEL7, 11,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1480 	NPCM8XX_PINCFG(144,	pwm4, MFSEL2, 20,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(4, 8)),
1481 	NPCM8XX_PINCFG(145,	pwm5, MFSEL2, 21,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(4, 8)),
1482 	NPCM8XX_PINCFG(146,	pwm6, MFSEL2, 22,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(4, 8)),
1483 	NPCM8XX_PINCFG(147,	pwm7, MFSEL2, 23,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(4, 8)),
1484 	NPCM8XX_PINCFG(148,	mmc8, MFSEL3, 11,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1485 	NPCM8XX_PINCFG(149,	mmc8, MFSEL3, 11,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1486 	NPCM8XX_PINCFG(150,	mmc8, MFSEL3, 11,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1487 	NPCM8XX_PINCFG(151,	mmc8, MFSEL3, 11,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1488 	NPCM8XX_PINCFG(152,	mmc, MFSEL3, 10,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1489 	NPCM8XX_PINCFG(153,	mmcwp, FLOCKR1, 24,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1490 	NPCM8XX_PINCFG(154,	mmc, MFSEL3, 10,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1491 	NPCM8XX_PINCFG(155,	mmccd, MFSEL3, 25,	mmcrst, MFSEL4, 6,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1492 	NPCM8XX_PINCFG(156,	mmc, MFSEL3, 10,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1493 	NPCM8XX_PINCFG(157,	mmc, MFSEL3, 10,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1494 	NPCM8XX_PINCFG(158,	mmc, MFSEL3, 10,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1495 	NPCM8XX_PINCFG(159,	mmc, MFSEL3, 10,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1496 	NPCM8XX_PINCFG(160,	clkout, MFSEL1, 21,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1497 	NPCM8XX_PINCFG(161,	lpc, MFSEL1, 26,	espi, MFSEL4, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1498 	NPCM8XX_PINCFG(162,	serirq, MFSEL1, 31,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12)),
1499 	NPCM8XX_PINCFG(163,	lpc, MFSEL1, 26,	espi, MFSEL4, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1500 	NPCM8XX_PINCFG(164,	lpc, MFSEL1, 26,	espi, MFSEL4, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1501 	NPCM8XX_PINCFG(165,	lpc, MFSEL1, 26,	espi, MFSEL4, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1502 	NPCM8XX_PINCFG(166,	lpc, MFSEL1, 26,	espi, MFSEL4, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1503 	NPCM8XX_PINCFG(167,	lpc, MFSEL1, 26,	espi, MFSEL4, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1504 	NPCM8XX_PINCFG(168,	lpcclk, MFSEL1, 31,	espi, MFSEL4, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1505 	NPCM8XX_PINCFG(169,	scipme, MFSEL3, 0,	smb21, MFSEL5, 29,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1506 	NPCM8XX_PINCFG(170,	smi, MFSEL1, 22,	smb21, MFSEL5, 29,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1507 	NPCM8XX_PINCFG(171,	smb6, MFSEL3, 1,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1508 	NPCM8XX_PINCFG(172,	smb6, MFSEL3, 1,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1509 	NPCM8XX_PINCFG(173,	smb7, MFSEL3, 2,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1510 	NPCM8XX_PINCFG(174,	smb7, MFSEL3, 2,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1511 	NPCM8XX_PINCFG(175,	spi1, MFSEL3, 4,	faninx, MFSEL3, 3,	fm1, MFSEL6, 17,	none, NONE, 0,		none, NONE, 0,		DSTR(8, 12)),
1512 	NPCM8XX_PINCFG(176,	spi1, MFSEL3, 4,	faninx, MFSEL3, 3,	fm1, MFSEL6, 17,	none, NONE, 0,		none, NONE, 0,		DSTR(8, 12)),
1513 	NPCM8XX_PINCFG(177,	spi1, MFSEL3, 4,	faninx, MFSEL3, 3,	fm1, MFSEL6, 17,	none, NONE, 0,		none, NONE, 0,		DSTR(8, 12)),
1514 	NPCM8XX_PINCFG(178,	r1, MFSEL3, 9,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1515 	NPCM8XX_PINCFG(179,	r1, MFSEL3, 9,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1516 	NPCM8XX_PINCFG(180,	r1, MFSEL3, 9,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1517 	NPCM8XX_PINCFG(181,	r1, MFSEL3, 9,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1518 	NPCM8XX_PINCFG(182,	r1, MFSEL3, 9,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1519 	NPCM8XX_PINCFG(183,	gpio1836, MFSEL6, 19,	spi3, MFSEL4, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1520 	NPCM8XX_PINCFG(184,	gpio1836, MFSEL6, 19,	spi3, MFSEL4, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1521 	NPCM8XX_PINCFG(185,	gpio1836, MFSEL6, 19,	spi3, MFSEL4, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1522 	NPCM8XX_PINCFG(186,	gpio1836, MFSEL6, 19,	spi3, MFSEL4, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12)),
1523 	NPCM8XX_PINCFG(187,	gpo187, MFSEL7, 24,	smb14b, MFSEL7, 26,	spi3cs1, MFSEL4, 17,	none, NONE, 0,		none, NONE, 0,		0),
1524 	NPCM8XX_PINCFG(188,	gpio1889, MFSEL7, 25,	spi3cs2, MFSEL4, 18,	spi3quad, MFSEL4, 20,	none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1525 	NPCM8XX_PINCFG(189,	gpio1889, MFSEL7, 25,	spi3cs3, MFSEL4, 19,	spi3quad, MFSEL4, 20,	none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1526 	NPCM8XX_PINCFG(190,	nprd_smi, FLOCKR1, 20,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(2, 4)),
1527 	NPCM8XX_PINCFG(191,	spi1d23, MFSEL5, 3,	spi1cs2, MFSEL5, 4,	fm1, MFSEL6, 17,	smb15, MFSEL7, 27,	none, NONE, 0,		DSTR(0, 2)),  /* XX */
1528 	NPCM8XX_PINCFG(192,	spi1d23, MFSEL5, 3,	spi1cs3, MFSEL5, 5,	fm1, MFSEL6, 17,	smb15, MFSEL7, 27,	none, NONE, 0,		DSTR(0, 2)),  /* XX */
1529 	NPCM8XX_PINCFG(193,	r1, MFSEL3, 9,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1530 	NPCM8XX_PINCFG(194,	smb0b, I2CSEGSEL, 0,	fm0, MFSEL6, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(0, 1)),
1531 	NPCM8XX_PINCFG(195,	smb0b, I2CSEGSEL, 0,	fm0, MFSEL6, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(0, 1)),
1532 	NPCM8XX_PINCFG(196,	smb0c, I2CSEGSEL, 1,	fm0, MFSEL6, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(0, 1)),
1533 	NPCM8XX_PINCFG(197,	smb0den, I2CSEGSEL, 22,	fm0, MFSEL6, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(0, 1)),
1534 	NPCM8XX_PINCFG(198,	smb0d, I2CSEGSEL, 2,	fm0, MFSEL6, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(0, 1)),
1535 	NPCM8XX_PINCFG(199,	smb0d, I2CSEGSEL, 2,	fm0, MFSEL6, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(0, 1)),
1536 	NPCM8XX_PINCFG(200,	r2, MFSEL1, 14,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1537 	NPCM8XX_PINCFG(201,	r1, MFSEL3, 9,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1538 	NPCM8XX_PINCFG(202,	smb0c, I2CSEGSEL, 1,	fm0, MFSEL6, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(0, 1)),
1539 	NPCM8XX_PINCFG(203,	faninx, MFSEL3, 3,	spi1cs0, MFSEL3, 4,	fm1, MFSEL6, 17,	none, NONE, 0,		none, NONE, 0,		DSTR(8, 12)),
1540 	NPCM8XX_PINCFG(208,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW), /* DSCNT */
1541 	NPCM8XX_PINCFG(209,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	rmii3, MFSEL5, 11,	none, NONE, 0,		none, NONE, 0,		SLEW), /* DSCNT */
1542 	NPCM8XX_PINCFG(210,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	rmii3, MFSEL5, 11,	none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1543 	NPCM8XX_PINCFG(211,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	rmii3, MFSEL5, 11,	none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1544 	NPCM8XX_PINCFG(212,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	r3rxer, MFSEL6, 30,	none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1545 	NPCM8XX_PINCFG(213,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	r3oen, MFSEL5, 14,	none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1546 	NPCM8XX_PINCFG(214,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	rmii3, MFSEL5, 11,	none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1547 	NPCM8XX_PINCFG(215,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	rmii3, MFSEL5, 11,	none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1548 	NPCM8XX_PINCFG(216,	rg2mdio, MFSEL4, 23,	ddr, MFSEL3, 26,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1549 	NPCM8XX_PINCFG(217,	rg2mdio, MFSEL4, 23,	ddr, MFSEL3, 26,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1550 	NPCM8XX_PINCFG(218,	wdog1, MFSEL3, 19,	smb16b, MFSEL7, 30,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1551 	NPCM8XX_PINCFG(219,	wdog2, MFSEL3, 20,	smb16b, MFSEL7, 30,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1552 	NPCM8XX_PINCFG(220,	smb12, MFSEL3, 5,	pwm8, MFSEL6, 11,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1553 	NPCM8XX_PINCFG(221,	smb12, MFSEL3, 5,	pwm9, MFSEL6, 12,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1554 	NPCM8XX_PINCFG(222,	smb13, MFSEL3, 6,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1555 	NPCM8XX_PINCFG(223,	smb13, MFSEL3, 6,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1556 	NPCM8XX_PINCFG(224,	spix, MFSEL4, 27,	fm2, MFSEL6, 18,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1557 	NPCM8XX_PINCFG(225,	spix, MFSEL4, 27,	fm2, MFSEL6, 18,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1558 	NPCM8XX_PINCFG(226,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO | DSTR(8, 12) | SLEW),
1559 	NPCM8XX_PINCFG(227,	spix, MFSEL4, 27,	fm2, MFSEL6, 18,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1560 	NPCM8XX_PINCFG(228,	spixcs1, MFSEL4, 28,	fm2, MFSEL6, 18,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1561 	NPCM8XX_PINCFG(229,	spix, MFSEL4, 27,	fm2, MFSEL6, 18,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1562 	NPCM8XX_PINCFG(230,	spix, MFSEL4, 27,	fm2, MFSEL6, 18,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1563 	NPCM8XX_PINCFG(231,	clkreq, MFSEL4, 9,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(4, 12) | SLEW),
1564 	NPCM8XX_PINCFG(233,	spi1cs1, MFSEL5, 0,	fm1, MFSEL6, 17,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEWLPC), /* slewlpc ? */
1565 	NPCM8XX_PINCFG(234,	pwm10, MFSEL6, 13,	smb20, MFSEL5, 28,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1566 	NPCM8XX_PINCFG(235,	pwm11, MFSEL6, 14,	smb20, MFSEL5, 28,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1567 	NPCM8XX_PINCFG(240,	i3c0, MFSEL5, 17,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1568 	NPCM8XX_PINCFG(241,	i3c0, MFSEL5, 17,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1569 	NPCM8XX_PINCFG(242,	i3c1, MFSEL5, 19,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1570 	NPCM8XX_PINCFG(243,	i3c1, MFSEL5, 19,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1571 	NPCM8XX_PINCFG(244,	i3c2, MFSEL5, 21,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1572 	NPCM8XX_PINCFG(245,	i3c2, MFSEL5, 21,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1573 	NPCM8XX_PINCFG(246,	i3c3, MFSEL5, 23,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1574 	NPCM8XX_PINCFG(247,	i3c3, MFSEL5, 23,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1575 	NPCM8XX_PINCFG(251,	jm2, MFSEL5, 1,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1576 	NPCM8XX_PINCFG(253,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPI), /* SDHC1 power */
1577 	NPCM8XX_PINCFG(254,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPI), /* SDHC2 power */
1578 	NPCM8XX_PINCFG(255,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPI), /* DACOSEL */
1579 };
1580 
1581 /* number, name, drv_data */
1582 static const struct pinctrl_pin_desc npcm8xx_pins[] = {
1583 	PINCTRL_PIN(0,	"GPIO0/IOX1_DI/SMB6C_SDA/SMB18_SDA"),
1584 	PINCTRL_PIN(1,	"GPIO1/IOX1_LD/SMB6C_SCL/SMB18_SCL"),
1585 	PINCTRL_PIN(2,	"GPIO2/IOX1_CK/SMB6B_SDA/SMB17_SDA"),
1586 	PINCTRL_PIN(3,	"GPIO3/IOX1_DO/SMB6B_SCL/SMB17_SCL"),
1587 	PINCTRL_PIN(4,	"GPIO4/IOX2_DI/SMB1D_SDA"),
1588 	PINCTRL_PIN(5,	"GPIO5/IOX2_LD/SMB1D_SCL"),
1589 	PINCTRL_PIN(6,	"GPIO6/IOX2_CK/SMB2D_SDA"),
1590 	PINCTRL_PIN(7,	"GPIO7/IOX2_D0/SMB2D_SCL"),
1591 	PINCTRL_PIN(8,	"GPIO8/LKGPO1/TP_GPIO0"),
1592 	PINCTRL_PIN(9,	"GPIO9/LKGPO2/TP_GPIO1"),
1593 	PINCTRL_PIN(10, "GPIO10/IOXH_LD/SMB6D_SCL/SMB16_SCL"),
1594 	PINCTRL_PIN(11, "GPIO11/IOXH_CK/SMB6D_SDA/SMB16_SDA"),
1595 	PINCTRL_PIN(12, "GPIO12/GSPI_CK/SMB5B_SCL"),
1596 	PINCTRL_PIN(13, "GPIO13/GSPI_DO/SMB5B_SDA"),
1597 	PINCTRL_PIN(14, "GPIO14/GSPI_DI/SMB5C_SCL"),
1598 	PINCTRL_PIN(15, "GPIO15/GSPI_CS/SMB5C_SDA"),
1599 	PINCTRL_PIN(16, "GPIO16/SMB7B_SDA/LKGPO0/TP_GPIO2"),
1600 	PINCTRL_PIN(17, "GPIO17/PSPI_DI/CP1_GPIO5"),
1601 	PINCTRL_PIN(18, "GPIO18/PSPI_D0/SMB4B_SDA"),
1602 	PINCTRL_PIN(19, "GPIO19/PSPI_CK/SMB4B_SCL"),
1603 	PINCTRL_PIN(20, "GPIO20/H_GPIO0/SMB4C_SDA/SMB15_SDA"),
1604 	PINCTRL_PIN(21, "GPIO21/H_GPIO1/SMB4C_SCL/SMB15_SCL"),
1605 	PINCTRL_PIN(22, "GPIO22/H_GPIO2/SMB4D_SDA/SMB14_SDA"),
1606 	PINCTRL_PIN(23, "GPIO23/H_GPIO3/SMB4D_SCL/SMB14_SCL"),
1607 	PINCTRL_PIN(24, "GPIO24/IOXH_DO/H_GPIO4/SMB7C_SCL/TP_SMB2_SCL"),
1608 	PINCTRL_PIN(25, "GPIO25/IOXH_DI/H_GPIO4/SMB7C_SDA/TP_SMB2_SDA"),
1609 	PINCTRL_PIN(26, "GPIO26/SMB5_SDA"),
1610 	PINCTRL_PIN(27, "GPIO27/SMB5_SCL"),
1611 	PINCTRL_PIN(28, "GPIO28/SMB4_SDA"),
1612 	PINCTRL_PIN(29, "GPIO29/SMB4_SCL"),
1613 	PINCTRL_PIN(30, "GPIO30/SMB3_SDA"),
1614 	PINCTRL_PIN(31, "GPIO31/SMB3_SCL"),
1615 	PINCTRL_PIN(32, "GPIO32/SMB14B_SCL/SPI0_nCS1"),
1616 	PINCTRL_PIN(33, "GPIO33/I3C4_SCL"),
1617 	PINCTRL_PIN(34, "GPIO34/I3C4_SDA"),
1618 	PINCTRL_PIN(37, "GPIO37/SMB3C_SDA/SMB23_SDA"),
1619 	PINCTRL_PIN(38, "GPIO38/SMB3C_SCL/SMB23_SCL"),
1620 	PINCTRL_PIN(39, "GPIO39/SMB3B_SDA/SMB22_SDA"),
1621 	PINCTRL_PIN(40, "GPIO40/SMB3B_SCL/SMB22_SCL"),
1622 	PINCTRL_PIN(41, "GPIO41/BU0_RXD/CP1U_RXD"),
1623 	PINCTRL_PIN(42, "GPIO42/BU0_TXD/CP1U_TXD"),
1624 	PINCTRL_PIN(43, "GPIO43/SI1_RXD/BU1_RXD"),
1625 	PINCTRL_PIN(44, "GPIO44/SI1_nCTS/BU1_nCTS/CP_TDI/TP_TDI/CP_TP_TDI"),
1626 	PINCTRL_PIN(45, "GPIO45/SI1_nDCD/CP_TMS_SWIO/TP_TMS_SWIO/CP_TP_TMS_SWIO"),
1627 	PINCTRL_PIN(46, "GPIO46/SI1_nDSR/CP_TCK_SWCLK/TP_TCK_SWCLK/CP_TP_TCK_SWCLK"),
1628 	PINCTRL_PIN(47, "GPIO47/SI1n_RI1"),
1629 	PINCTRL_PIN(48, "GPIO48/SI2_TXD/BU0_TXD/STRAP5"),
1630 	PINCTRL_PIN(49, "GPIO49/SI2_RXD/BU0_RXD"),
1631 	PINCTRL_PIN(50, "GPIO50/SI2_nCTS/BU6_TXD/TPU_TXD"),
1632 	PINCTRL_PIN(51, "GPIO51/SI2_nRTS/BU6_RXD/TPU_RXD"),
1633 	PINCTRL_PIN(52, "GPIO52/SI2_nDCD/BU5_RXD"),
1634 	PINCTRL_PIN(53, "GPIO53/SI2_nDTR_BOUT2/BU5_TXD"),
1635 	PINCTRL_PIN(54, "GPIO54/SI2_nDSR/BU4_TXD"),
1636 	PINCTRL_PIN(55, "GPIO55/SI2_RI2/BU4_RXD"),
1637 	PINCTRL_PIN(56, "GPIO56/R1_RXERR/R1_OEN"),
1638 	PINCTRL_PIN(57, "GPIO57/R1_MDC/TP_GPIO4"),
1639 	PINCTRL_PIN(58, "GPIO58/R1_MDIO/TP_GPIO5"),
1640 	PINCTRL_PIN(59, "GPIO59/H_GPIO06/SMB3D_SDA/SMB19_SDA"),
1641 	PINCTRL_PIN(60, "GPIO60/H_GPIO07/SMB3D_SCL/SMB19_SCL"),
1642 	PINCTRL_PIN(61, "GPIO61/SI1_nDTR_BOUT"),
1643 	PINCTRL_PIN(62, "GPIO62/SI1_nRTS/BU1_nRTS/CP_TDO_SWO/TP_TDO_SWO/CP_TP_TDO_SWO"),
1644 	PINCTRL_PIN(63, "GPIO63/BU1_TXD1/SI1_TXD"),
1645 	PINCTRL_PIN(64, "GPIO64/FANIN0"),
1646 	PINCTRL_PIN(65, "GPIO65/FANIN1"),
1647 	PINCTRL_PIN(66, "GPIO66/FANIN2"),
1648 	PINCTRL_PIN(67, "GPIO67/FANIN3"),
1649 	PINCTRL_PIN(68, "GPIO68/FANIN4"),
1650 	PINCTRL_PIN(69, "GPIO69/FANIN5"),
1651 	PINCTRL_PIN(70, "GPIO70/FANIN6"),
1652 	PINCTRL_PIN(71, "GPIO71/FANIN7"),
1653 	PINCTRL_PIN(72, "GPIO72/FANIN8"),
1654 	PINCTRL_PIN(73, "GPIO73/FANIN9"),
1655 	PINCTRL_PIN(74, "GPIO74/FANIN10"),
1656 	PINCTRL_PIN(75, "GPIO75/FANIN11"),
1657 	PINCTRL_PIN(76, "GPIO76/FANIN12"),
1658 	PINCTRL_PIN(77, "GPIO77/FANIN13"),
1659 	PINCTRL_PIN(78, "GPIO78/FANIN14"),
1660 	PINCTRL_PIN(79, "GPIO79/FANIN15"),
1661 	PINCTRL_PIN(80, "GPIO80/PWM0"),
1662 	PINCTRL_PIN(81, "GPIO81/PWM1"),
1663 	PINCTRL_PIN(82, "GPIO82/PWM2"),
1664 	PINCTRL_PIN(83, "GPIO83/PWM3"),
1665 	PINCTRL_PIN(84, "GPIO84/R2_TXD0"),
1666 	PINCTRL_PIN(85, "GPIO85/R2_TXD1"),
1667 	PINCTRL_PIN(86, "GPIO86/R2_TXEN"),
1668 	PINCTRL_PIN(87, "GPIO87/R2_RXD0"),
1669 	PINCTRL_PIN(88, "GPIO88/R2_RXD1"),
1670 	PINCTRL_PIN(89, "GPIO89/R2_CRSDV"),
1671 	PINCTRL_PIN(90, "GPIO90/R2_RXERR/R2_OEN"),
1672 	PINCTRL_PIN(91, "GPIO91/R2_MDC/CP1_GPIO6/TP_GPIO0"),
1673 	PINCTRL_PIN(92, "GPIO92/R2_MDIO/CP1_GPIO7/TP_GPIO1"),
1674 	PINCTRL_PIN(93, "GPIO93/GA20/SMB5D_SCL"),
1675 	PINCTRL_PIN(94, "GPIO94/nKBRST/SMB5D_SDA"),
1676 	PINCTRL_PIN(95, "GPIO95/nESPIRST/LPC_nLRESET"),
1677 	PINCTRL_PIN(96, "GPIO96/CP1_GPIO7/BU2_TXD/TP_GPIO7"),
1678 	PINCTRL_PIN(97, "GPIO97/CP1_GPIO6/BU2_RXD/TP_GPIO6"),
1679 	PINCTRL_PIN(98, "GPIO98/CP1_GPIO5/BU4_TXD/TP_GPIO5"),
1680 	PINCTRL_PIN(99, "GPIO99/CP1_GPIO4/BU4_RXD/TP_GPIO4"),
1681 	PINCTRL_PIN(100, "GPIO100/CP1_GPIO3/BU5_TXD/TP_GPIO3"),
1682 	PINCTRL_PIN(101, "GPIO101/CP1_GPIO2/BU5_RXD/TP_GPIO2"),
1683 	PINCTRL_PIN(102, "GPIO102/HSYNC"),
1684 	PINCTRL_PIN(103, "GPIO103/VSYNC"),
1685 	PINCTRL_PIN(104, "GPIO104/DDC_SCL"),
1686 	PINCTRL_PIN(105, "GPIO105/DDC_SDA"),
1687 	PINCTRL_PIN(106, "GPIO106/I3C5_SCL"),
1688 	PINCTRL_PIN(107, "GPIO107/I3C5_SDA"),
1689 	PINCTRL_PIN(108, "GPIO108/SG1_MDC"),
1690 	PINCTRL_PIN(109, "GPIO109/SG1_MDIO"),
1691 	PINCTRL_PIN(110, "GPIO110/RG2_TXD0/DDRV0/R3_TXD0"),
1692 	PINCTRL_PIN(111, "GPIO111/RG2_TXD1/DDRV1/R3_TXD1"),
1693 	PINCTRL_PIN(112, "GPIO112/RG2_TXD2/DDRV2"),
1694 	PINCTRL_PIN(113, "GPIO113/RG2_TXD3/DDRV3"),
1695 	PINCTRL_PIN(114, "GPIO114/SMB0_SCL"),
1696 	PINCTRL_PIN(115, "GPIO115/SMB0_SDA"),
1697 	PINCTRL_PIN(116, "GPIO116/SMB1_SCL"),
1698 	PINCTRL_PIN(117, "GPIO117/SMB1_SDA"),
1699 	PINCTRL_PIN(118, "GPIO118/SMB2_SCL"),
1700 	PINCTRL_PIN(119, "GPIO119/SMB2_SDA"),
1701 	PINCTRL_PIN(120, "GPIO120/SMB2C_SDA"),
1702 	PINCTRL_PIN(121, "GPIO121/SMB2C_SCL"),
1703 	PINCTRL_PIN(122, "GPIO122/SMB2B_SDA"),
1704 	PINCTRL_PIN(123, "GPIO123/SMB2B_SCL"),
1705 	PINCTRL_PIN(124, "GPIO124/SMB1C_SDA/CP1_GPIO3"),
1706 	PINCTRL_PIN(125, "GPIO125/SMB1C_SCL/CP1_GPIO2"),
1707 	PINCTRL_PIN(126, "GPIO126/SMB1B_SDA/CP1_GPIO1"),
1708 	PINCTRL_PIN(127, "GPIO127/SMB1B_SCL/CP1_GPIO0"),
1709 	PINCTRL_PIN(128, "GPIO128/SMB824_SCL"),
1710 	PINCTRL_PIN(129, "GPIO129/SMB824_SDA"),
1711 	PINCTRL_PIN(130, "GPIO130/SMB925_SCL"),
1712 	PINCTRL_PIN(131, "GPIO131/SMB925_SDA"),
1713 	PINCTRL_PIN(132, "GPIO132/SMB1026_SCL"),
1714 	PINCTRL_PIN(133, "GPIO133/SMB1026_SDA"),
1715 	PINCTRL_PIN(134, "GPIO134/SMB11_SCL/SMB23B_SCL"),
1716 	PINCTRL_PIN(135, "GPIO135/SMB11_SDA/SMB23B_SDA"),
1717 	PINCTRL_PIN(136, "GPIO136/JM1_TCK"),
1718 	PINCTRL_PIN(137, "GPIO137/JM1_TDO"),
1719 	PINCTRL_PIN(138, "GPIO138/JM1_TMS"),
1720 	PINCTRL_PIN(139, "GPIO139/JM1_TDI"),
1721 	PINCTRL_PIN(140, "GPIO140/JM1_nTRST"),
1722 	PINCTRL_PIN(141, "GPIO141/SMB7B_SCL"),
1723 	PINCTRL_PIN(142, "GPIO142/SMB7D_SCL/TPSMB1_SCL"),
1724 	PINCTRL_PIN(143, "GPIO143/SMB7D_SDA/TPSMB1_SDA"),
1725 	PINCTRL_PIN(144, "GPIO144/PWM4"),
1726 	PINCTRL_PIN(145, "GPIO145/PWM5"),
1727 	PINCTRL_PIN(146, "GPIO146/PWM6"),
1728 	PINCTRL_PIN(147, "GPIO147/PWM7"),
1729 	PINCTRL_PIN(148, "GPIO148/MMC_DT4"),
1730 	PINCTRL_PIN(149, "GPIO149/MMC_DT5"),
1731 	PINCTRL_PIN(150, "GPIO150/MMC_DT6"),
1732 	PINCTRL_PIN(151, "GPIO151/MMC_DT7"),
1733 	PINCTRL_PIN(152, "GPIO152/MMC_CLK"),
1734 	PINCTRL_PIN(153, "GPIO153/MMC_WP"),
1735 	PINCTRL_PIN(154, "GPIO154/MMC_CMD"),
1736 	PINCTRL_PIN(155, "GPIO155/MMC_nCD/MMC_nRSTLK"),
1737 	PINCTRL_PIN(156, "GPIO156/MMC_DT0"),
1738 	PINCTRL_PIN(157, "GPIO157/MMC_DT1"),
1739 	PINCTRL_PIN(158, "GPIO158/MMC_DT2"),
1740 	PINCTRL_PIN(159, "GPIO159/MMC_DT3"),
1741 	PINCTRL_PIN(160, "GPIO160/CLKOUT/RNGOSCOUT/GFXBYPCK"),
1742 	PINCTRL_PIN(161, "GPIO161/ESPI_nCS/LPC_nLFRAME"),
1743 	PINCTRL_PIN(162, "GPIO162/SERIRQ"),
1744 	PINCTRL_PIN(163, "GPIO163/ESPI_CK/LPC_LCLK"),
1745 	PINCTRL_PIN(164, "GPIO164/ESPI_IO0/LPC_LAD0"),
1746 	PINCTRL_PIN(165, "GPIO165/ESPI_IO1/LPC_LAD1"),
1747 	PINCTRL_PIN(166, "GPIO166/ESPI_IO2/LPC_LAD2"),
1748 	PINCTRL_PIN(167, "GPIO167/ESPI_IO3/LPC_LAD3"),
1749 	PINCTRL_PIN(168, "GPIO168/ESPI_nALERT/LPC_nCLKRUN"),
1750 	PINCTRL_PIN(169, "GPIO169/nSCIPME/SMB21_SCL"),
1751 	PINCTRL_PIN(170, "GPIO170/nSMI/SMB21_SDA"),
1752 	PINCTRL_PIN(171, "GPIO171/SMB6_SCL"),
1753 	PINCTRL_PIN(172, "GPIO172/SMB6_SDA"),
1754 	PINCTRL_PIN(173, "GPIO173/SMB7_SCL"),
1755 	PINCTRL_PIN(174, "GPIO174/SMB7_SDA"),
1756 	PINCTRL_PIN(175, "GPIO175/SPI1_CK/FANIN19/FM1_CK"),
1757 	PINCTRL_PIN(176, "GPIO176/SPI1_DO/FANIN18/FM1_DO/STRAP9"),
1758 	PINCTRL_PIN(177, "GPIO177/SPI1_DI/FANIN17/FM1_D1/STRAP10"),
1759 	PINCTRL_PIN(178, "GPIO178/R1_TXD0"),
1760 	PINCTRL_PIN(179, "GPIO179/R1_TXD1"),
1761 	PINCTRL_PIN(180, "GPIO180/R1_TXEN"),
1762 	PINCTRL_PIN(181, "GPIO181/R1_RXD0"),
1763 	PINCTRL_PIN(182, "GPIO182/R1_RXD1"),
1764 	PINCTRL_PIN(183, "GPIO183/SPI3_SEL"),
1765 	PINCTRL_PIN(184, "GPIO184/SPI3_D0/STRAP13"),
1766 	PINCTRL_PIN(185, "GPIO185/SPI3_D1"),
1767 	PINCTRL_PIN(186, "GPIO186/SPI3_nCS0"),
1768 	PINCTRL_PIN(187, "GPO187/SPI3_nCS1_SMB14B_SDA"),
1769 	PINCTRL_PIN(188, "GPIO188/SPI3_D2/SPI3_nCS2"),
1770 	PINCTRL_PIN(189, "GPIO189/SPI3_D3/SPI3_nCS3"),
1771 	PINCTRL_PIN(190, "GPIO190/nPRD_SMI"),
1772 	PINCTRL_PIN(191, "GPIO191/SPI1_D1/FANIN17/FM1_D1/STRAP10"),
1773 	PINCTRL_PIN(192, "GPIO192/SPI1_D3/SPI_nCS3/FM1_D3/SMB15_SCL"),
1774 	PINCTRL_PIN(193, "GPIO193/R1_CRSDV"),
1775 	PINCTRL_PIN(194, "GPIO194/SMB0B_SCL/FM0_CK"),
1776 	PINCTRL_PIN(195, "GPIO195/SMB0B_SDA/FM0_D0"),
1777 	PINCTRL_PIN(196, "GPIO196/SMB0C_SCL/FM0_D1"),
1778 	PINCTRL_PIN(197, "GPIO197/SMB0DEN/FM0_D3"),
1779 	PINCTRL_PIN(198, "GPIO198/SMB0D_SDA/FM0_D2"),
1780 	PINCTRL_PIN(199, "GPIO199/SMB0D_SCL/FM0_CSO"),
1781 	PINCTRL_PIN(200, "GPIO200/R2_CK"),
1782 	PINCTRL_PIN(201, "GPIO201/R1_CK"),
1783 	PINCTRL_PIN(202, "GPIO202/SMB0C_SDA/FM0_CSI"),
1784 	PINCTRL_PIN(203, "GPIO203/SPI1_nCS0/FANIN16/FM1_CSI"),
1785 	PINCTRL_PIN(208, "GPIO208/RG2_TXC/DVCK"),
1786 	PINCTRL_PIN(209, "GPIO209/RG2_TXCTL/DDRV4/R3_TXEN"),
1787 	PINCTRL_PIN(210, "GPIO210/RG2_RXD0/DDRV5/R3_RXD0"),
1788 	PINCTRL_PIN(211, "GPIO211/RG2_RXD1/DDRV6/R3_RXD1"),
1789 	PINCTRL_PIN(212, "GPIO212/RG2_RXD2/DDRV7/R3_RXD2"),
1790 	PINCTRL_PIN(213, "GPIO213/RG2_RXD3/DDRV8/R3_OEN"),
1791 	PINCTRL_PIN(214, "GPIO214/RG2_RXC/DDRV9/R3_CK"),
1792 	PINCTRL_PIN(215, "GPIO215/RG2_RXCTL/DDRV10/R3_CRSDV"),
1793 	PINCTRL_PIN(216, "GPIO216/RG2_MDC/DDRV11"),
1794 	PINCTRL_PIN(217, "GPIO217/RG2_MDIO/DVHSYNC"),
1795 	PINCTRL_PIN(218, "GPIO218/nWDO1/SMB16_SCL"),
1796 	PINCTRL_PIN(219, "GPIO219/nWDO2/SMB16_SDA"),
1797 	PINCTRL_PIN(220, "GPIO220/SMB12_SCL/PWM8"),
1798 	PINCTRL_PIN(221, "GPIO221/SMB12_SDA/PWM9"),
1799 	PINCTRL_PIN(222, "GPIO222/SMB13_SCL"),
1800 	PINCTRL_PIN(223, "GPIO223/SMB13_SDA"),
1801 	PINCTRL_PIN(224, "GPIO224/SPIX_CK/FM2_CK"),
1802 	PINCTRL_PIN(225, "GPO225/SPIX_D0/FM2_D0/STRAP1"),
1803 	PINCTRL_PIN(226, "GPO226/SPIX_D1/FM2_D1/STRAP2"),
1804 	PINCTRL_PIN(227, "GPIO227/SPIX_nCS0/FM2_CSI"),
1805 	PINCTRL_PIN(228, "GPIO228/SPIX_nCS1/FM2_CSO"),
1806 	PINCTRL_PIN(229, "GPO229/SPIX_D2/FM2_D2/STRAP3"),
1807 	PINCTRL_PIN(230, "GPO230/SPIX_D3/FM2_D3/STRAP6"),
1808 	PINCTRL_PIN(231, "GPIO231/EP_nCLKREQ"),
1809 	PINCTRL_PIN(233, "GPIO233/SPI1_nCS1/FM1_CSO"),
1810 	PINCTRL_PIN(234, "GPIO234/PWM10/SMB20_SCL"),
1811 	PINCTRL_PIN(235, "GPIO235/PWM11/SMB20_SDA"),
1812 	PINCTRL_PIN(240, "GPIO240/I3C0_SCL"),
1813 	PINCTRL_PIN(241, "GPIO241/I3C0_SDA"),
1814 	PINCTRL_PIN(242, "GPIO242/I3C1_SCL"),
1815 	PINCTRL_PIN(243, "GPIO243/I3C1_SDA"),
1816 	PINCTRL_PIN(244, "GPIO244/I3C2_SCL"),
1817 	PINCTRL_PIN(245, "GPIO245/I3C2_SDA"),
1818 	PINCTRL_PIN(246, "GPIO246/I3C3_SCL"),
1819 	PINCTRL_PIN(247, "GPIO247/I3C3_SDA"),
1820 	PINCTRL_PIN(250, "GPIO250/RG2_REFCK/DVVSYNC"),
1821 	PINCTRL_PIN(251, "JM2/CP1_GPIO"),
1822 	};
1823 
1824 /* Enable mode in pin group */
1825 static void npcm8xx_setfunc(struct regmap *gcr_regmap, const unsigned int *pin,
1826 			    int pin_number, int mode)
1827 {
1828 	const struct npcm8xx_pincfg *cfg;
1829 	int i;
1830 
1831 	for (i = 0 ; i < pin_number ; i++) {
1832 		cfg = &pincfg[pin[i]];
1833 		if (mode == fn_gpio || cfg->fn0 == mode || cfg->fn1 == mode ||
1834 		    cfg->fn2 == mode || cfg->fn3 == mode || cfg->fn4 == mode) {
1835 			if (cfg->reg0)
1836 				regmap_update_bits(gcr_regmap, cfg->reg0,
1837 						   BIT(cfg->bit0),
1838 						   (cfg->fn0 == mode) ?
1839 						   BIT(cfg->bit0) : 0);
1840 			if (cfg->reg1)
1841 				regmap_update_bits(gcr_regmap, cfg->reg1,
1842 						   BIT(cfg->bit1),
1843 						   (cfg->fn1 == mode) ?
1844 						   BIT(cfg->bit1) : 0);
1845 			if (cfg->reg2)
1846 				regmap_update_bits(gcr_regmap, cfg->reg2,
1847 						   BIT(cfg->bit2),
1848 						   (cfg->fn2 == mode) ?
1849 						   BIT(cfg->bit2) : 0);
1850 			if (cfg->reg3)
1851 				regmap_update_bits(gcr_regmap, cfg->reg3,
1852 						   BIT(cfg->bit3),
1853 						   (cfg->fn3 == mode) ?
1854 						   BIT(cfg->bit3) : 0);
1855 			if (cfg->reg4)
1856 				regmap_update_bits(gcr_regmap, cfg->reg4,
1857 						   BIT(cfg->bit4),
1858 						   (cfg->fn4 == mode) ?
1859 						   BIT(cfg->bit4) : 0);
1860 		}
1861 	}
1862 }
1863 
1864 static int npcm8xx_get_slew_rate(struct npcm8xx_gpio *bank,
1865 				 struct regmap *gcr_regmap, unsigned int pin)
1866 {
1867 	int gpio = pin % bank->gc.ngpio;
1868 	unsigned long pinmask = BIT(gpio);
1869 	u32 val;
1870 
1871 	if (pincfg[pin].flag & SLEW)
1872 		return ioread32(bank->base + NPCM8XX_GP_N_OSRC) & pinmask;
1873 	/* LPC Slew rate in SRCNT register */
1874 	if (pincfg[pin].flag & SLEWLPC) {
1875 		regmap_read(gcr_regmap, NPCM8XX_GCR_SRCNT, &val);
1876 		return !!(val & SRCNT_ESPI);
1877 	}
1878 
1879 	return -EINVAL;
1880 }
1881 
1882 static int npcm8xx_set_slew_rate(struct npcm8xx_gpio *bank,
1883 				 struct regmap *gcr_regmap, unsigned int pin,
1884 				 int arg)
1885 {
1886 	void __iomem *OSRC_Offset = bank->base + NPCM8XX_GP_N_OSRC;
1887 	int gpio = BIT(pin % bank->gc.ngpio);
1888 
1889 	if (pincfg[pin].flag & SLEW) {
1890 		switch (arg) {
1891 		case 0:
1892 			npcm_gpio_clr(&bank->gc, OSRC_Offset, gpio);
1893 			return 0;
1894 		case 1:
1895 			npcm_gpio_set(&bank->gc, OSRC_Offset, gpio);
1896 			return 0;
1897 		default:
1898 			return -EINVAL;
1899 		}
1900 	}
1901 
1902 	if (!(pincfg[pin].flag & SLEWLPC))
1903 		return -EINVAL;
1904 
1905 	switch (arg) {
1906 	case 0:
1907 		regmap_update_bits(gcr_regmap, NPCM8XX_GCR_SRCNT,
1908 				   SRCNT_ESPI, 0);
1909 		break;
1910 	case 1:
1911 		regmap_update_bits(gcr_regmap, NPCM8XX_GCR_SRCNT,
1912 				   SRCNT_ESPI, SRCNT_ESPI);
1913 		break;
1914 	default:
1915 		return -EINVAL;
1916 		}
1917 
1918 	return 0;
1919 }
1920 
1921 static int npcm8xx_get_drive_strength(struct pinctrl_dev *pctldev,
1922 				      unsigned int pin)
1923 {
1924 	struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
1925 	struct npcm8xx_gpio *bank =
1926 		&npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];
1927 	int gpio = pin % bank->gc.ngpio;
1928 	unsigned long pinmask = BIT(gpio);
1929 	int flg, val;
1930 	u32 ds = 0;
1931 
1932 	flg = pincfg[pin].flag;
1933 	if (!(flg & DRIVE_STRENGTH_MASK))
1934 		return -EINVAL;
1935 
1936 	val = ioread32(bank->base + NPCM8XX_GP_N_ODSC) & pinmask;
1937 	ds = val ? DSHI(flg) : DSLO(flg);
1938 	dev_dbg(bank->gc.parent, "pin %d strength %d = %d\n", pin, val, ds);
1939 
1940 	return ds;
1941 }
1942 
1943 static int npcm8xx_set_drive_strength(struct npcm8xx_pinctrl *npcm,
1944 				      unsigned int pin, int nval)
1945 {
1946 	struct npcm8xx_gpio *bank =
1947 		&npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];
1948 	int gpio = BIT(pin % bank->gc.ngpio);
1949 	int v;
1950 
1951 	v = pincfg[pin].flag & DRIVE_STRENGTH_MASK;
1952 
1953 	if (DSLO(v) == nval)
1954 		npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_ODSC, gpio);
1955 	else if (DSHI(v) == nval)
1956 		npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_ODSC, gpio);
1957 	else
1958 		return -ENOTSUPP;
1959 
1960 	return 0;
1961 }
1962 
1963 /* pinctrl_ops */
1964 static int npcm8xx_get_groups_count(struct pinctrl_dev *pctldev)
1965 {
1966 	return ARRAY_SIZE(npcm8xx_pingroups);
1967 }
1968 
1969 static const char *npcm8xx_get_group_name(struct pinctrl_dev *pctldev,
1970 					  unsigned int selector)
1971 {
1972 	return npcm8xx_pingroups[selector].name;
1973 }
1974 
1975 static int npcm8xx_get_group_pins(struct pinctrl_dev *pctldev,
1976 				  unsigned int selector,
1977 				  const unsigned int **pins,
1978 				  unsigned int *npins)
1979 {
1980 	*npins = npcm8xx_pingroups[selector].npins;
1981 	*pins  = npcm8xx_pingroups[selector].pins;
1982 
1983 	return 0;
1984 }
1985 
1986 static int npcm8xx_dt_node_to_map(struct pinctrl_dev *pctldev,
1987 				  struct device_node *np_config,
1988 				  struct pinctrl_map **map,
1989 				  u32 *num_maps)
1990 {
1991 	return pinconf_generic_dt_node_to_map(pctldev, np_config,
1992 					      map, num_maps,
1993 					      PIN_MAP_TYPE_INVALID);
1994 }
1995 
1996 static void npcm8xx_dt_free_map(struct pinctrl_dev *pctldev,
1997 				struct pinctrl_map *map, u32 num_maps)
1998 {
1999 	kfree(map);
2000 }
2001 
2002 static const struct pinctrl_ops npcm8xx_pinctrl_ops = {
2003 	.get_groups_count = npcm8xx_get_groups_count,
2004 	.get_group_name = npcm8xx_get_group_name,
2005 	.get_group_pins = npcm8xx_get_group_pins,
2006 	.dt_node_to_map = npcm8xx_dt_node_to_map,
2007 	.dt_free_map = npcm8xx_dt_free_map,
2008 };
2009 
2010 static int npcm8xx_get_functions_count(struct pinctrl_dev *pctldev)
2011 {
2012 	return ARRAY_SIZE(npcm8xx_funcs);
2013 }
2014 
2015 static const char *npcm8xx_get_function_name(struct pinctrl_dev *pctldev,
2016 					     unsigned int function)
2017 {
2018 	return npcm8xx_funcs[function].name;
2019 }
2020 
2021 static int npcm8xx_get_function_groups(struct pinctrl_dev *pctldev,
2022 				       unsigned int function,
2023 				       const char * const **groups,
2024 				       unsigned int * const ngroups)
2025 {
2026 	*ngroups = npcm8xx_funcs[function].ngroups;
2027 	*groups	 = npcm8xx_funcs[function].groups;
2028 
2029 	return 0;
2030 }
2031 
2032 static int npcm8xx_pinmux_set_mux(struct pinctrl_dev *pctldev,
2033 				  unsigned int function,
2034 				  unsigned int group)
2035 {
2036 	struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
2037 
2038 	npcm8xx_setfunc(npcm->gcr_regmap, npcm8xx_pingroups[group].pins,
2039 			npcm8xx_pingroups[group].npins, group);
2040 
2041 	return 0;
2042 }
2043 
2044 static int npcm8xx_gpio_request_enable(struct pinctrl_dev *pctldev,
2045 				       struct pinctrl_gpio_range *range,
2046 				       unsigned int offset)
2047 {
2048 	struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
2049 	const unsigned int *pin = &offset;
2050 	int mode = fn_gpio;
2051 
2052 	if (pin[0] >= 183 && pin[0] <= 189)
2053 		mode = pincfg[pin[0]].fn0;
2054 
2055 	npcm8xx_setfunc(npcm->gcr_regmap, &offset, 1, mode);
2056 
2057 	return 0;
2058 }
2059 
2060 static void npcm8xx_gpio_request_free(struct pinctrl_dev *pctldev,
2061 				      struct pinctrl_gpio_range *range,
2062 				      unsigned int offset)
2063 {
2064 	struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
2065 	int virq;
2066 
2067 	virq = irq_find_mapping(npcm->domain, offset);
2068 	if (virq)
2069 		irq_dispose_mapping(virq);
2070 }
2071 
2072 static int npcm_gpio_set_direction(struct pinctrl_dev *pctldev,
2073 				   struct pinctrl_gpio_range *range,
2074 				   unsigned int offset, bool input)
2075 {
2076 	struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
2077 	struct npcm8xx_gpio *bank =
2078 		&npcm->gpio_bank[offset / NPCM8XX_GPIO_PER_BANK];
2079 	int gpio = BIT(offset % bank->gc.ngpio);
2080 
2081 	if (input)
2082 		iowrite32(gpio, bank->base + NPCM8XX_GP_N_OEC);
2083 	else
2084 		iowrite32(gpio, bank->base + NPCM8XX_GP_N_OES);
2085 
2086 	return 0;
2087 }
2088 
2089 static const struct pinmux_ops npcm8xx_pinmux_ops = {
2090 	.get_functions_count = npcm8xx_get_functions_count,
2091 	.get_function_name = npcm8xx_get_function_name,
2092 	.get_function_groups = npcm8xx_get_function_groups,
2093 	.set_mux = npcm8xx_pinmux_set_mux,
2094 	.gpio_request_enable = npcm8xx_gpio_request_enable,
2095 	.gpio_disable_free = npcm8xx_gpio_request_free,
2096 	.gpio_set_direction = npcm_gpio_set_direction,
2097 };
2098 
2099 static int debounce_timing_setting(struct npcm8xx_gpio *bank, u32 gpio,
2100 				   u32 nanosecs)
2101 {
2102 	void __iomem *DBNCS_offset = bank->base + NPCM8XX_GP_N_DBNCS0 + (gpio / 4);
2103 	int gpio_debounce = (gpio % 16) * 2, debounce_select, i;
2104 	u32 dbncp_val, dbncp_val_mod;
2105 
2106 	for (i = 0 ; i < NPCM8XX_DEBOUNCE_MAX ; i++) {
2107 		if (bank->debounce.set_val[i]) {
2108 			if (bank->debounce.nanosec_val[i] == nanosecs) {
2109 				debounce_select = i << gpio_debounce;
2110 				npcm_gpio_set(&bank->gc, DBNCS_offset,
2111 					      debounce_select);
2112 				break;
2113 			}
2114 		} else {
2115 			bank->debounce.set_val[i] = true;
2116 			bank->debounce.nanosec_val[i] = nanosecs;
2117 			debounce_select = i << gpio_debounce;
2118 			npcm_gpio_set(&bank->gc, DBNCS_offset, debounce_select);
2119 			switch (nanosecs) {
2120 			case 1 ... 1040:
2121 				iowrite32(0, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2122 				break;
2123 			case 1041 ... 1640:
2124 				iowrite32(0x10, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2125 				break;
2126 			case 1641 ... 2280:
2127 				iowrite32(0x20, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2128 				break;
2129 			case 2281 ... 2700:
2130 				iowrite32(0x30, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2131 				break;
2132 			case 2701 ... 2856:
2133 				iowrite32(0x40, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2134 				break;
2135 			case 2857 ... 3496:
2136 				iowrite32(0x50, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2137 				break;
2138 			case 3497 ... 4136:
2139 				iowrite32(0x60, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2140 				break;
2141 			case 4137 ... 5025:
2142 				iowrite32(0x70, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2143 				break;
2144 			default:
2145 				dbncp_val = DIV_ROUND_CLOSEST(nanosecs, NPCM8XX_DEBOUNCE_NSEC);
2146 				if (dbncp_val > NPCM8XX_DEBOUNCE_MAX_VAL)
2147 					return -ENOTSUPP;
2148 				dbncp_val_mod = dbncp_val & GENMASK(3, 0);
2149 				if (dbncp_val_mod > GENMASK(2, 0))
2150 					dbncp_val += 0x10;
2151 				iowrite32(dbncp_val & NPCM8XX_DEBOUNCE_VAL_MASK,
2152 					  bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2153 				break;
2154 			}
2155 			break;
2156 		}
2157 	}
2158 
2159 	if (i == 4)
2160 		return -ENOTSUPP;
2161 
2162 	return 0;
2163 }
2164 
2165 static int npcm_set_debounce(struct npcm8xx_pinctrl *npcm, unsigned int pin,
2166 			     u32 nanosecs)
2167 {
2168 	struct npcm8xx_gpio *bank =
2169 		&npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];
2170 	int gpio = BIT(pin % bank->gc.ngpio);
2171 	int ret;
2172 
2173 	if (nanosecs) {
2174 		ret = debounce_timing_setting(bank, pin % bank->gc.ngpio,
2175 					      nanosecs);
2176 		if (ret)
2177 			dev_err(npcm->dev, "Pin %d, All four debounce timing values are used, please use one of exist debounce values\n", pin);
2178 		else
2179 			npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_DBNC,
2180 				      gpio);
2181 		return ret;
2182 	}
2183 
2184 	npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_DBNC, gpio);
2185 
2186 	return 0;
2187 }
2188 
2189 /* pinconf_ops */
2190 static int npcm8xx_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
2191 			      unsigned long *config)
2192 {
2193 	enum pin_config_param param = pinconf_to_config_param(*config);
2194 	struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
2195 	struct npcm8xx_gpio *bank =
2196 		&npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];
2197 	int gpio = pin % bank->gc.ngpio;
2198 	unsigned long pinmask = BIT(gpio);
2199 	u32 ie, oe, pu, pd;
2200 	int rc = 0;
2201 
2202 	switch (param) {
2203 	case PIN_CONFIG_BIAS_DISABLE:
2204 	case PIN_CONFIG_BIAS_PULL_UP:
2205 	case PIN_CONFIG_BIAS_PULL_DOWN:
2206 		pu = ioread32(bank->base + NPCM8XX_GP_N_PU) & pinmask;
2207 		pd = ioread32(bank->base + NPCM8XX_GP_N_PD) & pinmask;
2208 		if (param == PIN_CONFIG_BIAS_DISABLE)
2209 			rc = !pu && !pd;
2210 		else if (param == PIN_CONFIG_BIAS_PULL_UP)
2211 			rc = pu && !pd;
2212 		else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
2213 			rc = !pu && pd;
2214 		break;
2215 	case PIN_CONFIG_OUTPUT:
2216 	case PIN_CONFIG_INPUT_ENABLE:
2217 		ie = ioread32(bank->base + NPCM8XX_GP_N_IEM) & pinmask;
2218 		oe = ioread32(bank->base + NPCM8XX_GP_N_OE) & pinmask;
2219 		if (param == PIN_CONFIG_INPUT_ENABLE)
2220 			rc = (ie && !oe);
2221 		else if (param == PIN_CONFIG_OUTPUT)
2222 			rc = (!ie && oe);
2223 		break;
2224 	case PIN_CONFIG_DRIVE_PUSH_PULL:
2225 		rc = !(ioread32(bank->base + NPCM8XX_GP_N_OTYP) & pinmask);
2226 		break;
2227 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
2228 		rc = ioread32(bank->base + NPCM8XX_GP_N_OTYP) & pinmask;
2229 		break;
2230 	case PIN_CONFIG_INPUT_DEBOUNCE:
2231 		rc = ioread32(bank->base + NPCM8XX_GP_N_DBNC) & pinmask;
2232 		break;
2233 	case PIN_CONFIG_DRIVE_STRENGTH:
2234 		rc = npcm8xx_get_drive_strength(pctldev, pin);
2235 		if (rc)
2236 			*config = pinconf_to_config_packed(param, rc);
2237 		break;
2238 	case PIN_CONFIG_SLEW_RATE:
2239 		rc = npcm8xx_get_slew_rate(bank, npcm->gcr_regmap, pin);
2240 		if (rc >= 0)
2241 			*config = pinconf_to_config_packed(param, rc);
2242 		break;
2243 	default:
2244 		return -ENOTSUPP;
2245 	}
2246 
2247 	if (!rc)
2248 		return -EINVAL;
2249 
2250 	return 0;
2251 }
2252 
2253 static int npcm8xx_config_set_one(struct npcm8xx_pinctrl *npcm,
2254 				  unsigned int pin, unsigned long config)
2255 {
2256 	enum pin_config_param param = pinconf_to_config_param(config);
2257 	struct npcm8xx_gpio *bank =
2258 		&npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];
2259 	u32 arg = pinconf_to_config_argument(config);
2260 	int gpio = BIT(pin % bank->gc.ngpio);
2261 
2262 	switch (param) {
2263 	case PIN_CONFIG_BIAS_DISABLE:
2264 		npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PU, gpio);
2265 		npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PD, gpio);
2266 		break;
2267 	case PIN_CONFIG_BIAS_PULL_DOWN:
2268 		npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PU, gpio);
2269 		npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_PD, gpio);
2270 		break;
2271 	case PIN_CONFIG_BIAS_PULL_UP:
2272 		npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PD, gpio);
2273 		npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_PU, gpio);
2274 		break;
2275 	case PIN_CONFIG_INPUT_ENABLE:
2276 		iowrite32(gpio, bank->base + NPCM8XX_GP_N_OEC);
2277 		bank->direction_input(&bank->gc, pin % bank->gc.ngpio);
2278 		break;
2279 	case PIN_CONFIG_OUTPUT:
2280 		bank->direction_output(&bank->gc, pin % bank->gc.ngpio, arg);
2281 		iowrite32(gpio, bank->base + NPCM8XX_GP_N_OES);
2282 		break;
2283 	case PIN_CONFIG_DRIVE_PUSH_PULL:
2284 		npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_OTYP, gpio);
2285 		break;
2286 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
2287 		npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_OTYP, gpio);
2288 		break;
2289 	case PIN_CONFIG_INPUT_DEBOUNCE:
2290 		return npcm_set_debounce(npcm, pin, arg * 1000);
2291 	case PIN_CONFIG_SLEW_RATE:
2292 		return npcm8xx_set_slew_rate(bank, npcm->gcr_regmap, pin, arg);
2293 	case PIN_CONFIG_DRIVE_STRENGTH:
2294 		return npcm8xx_set_drive_strength(npcm, pin, arg);
2295 	default:
2296 		return -ENOTSUPP;
2297 	}
2298 
2299 	return 0;
2300 }
2301 
2302 static int npcm8xx_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
2303 			      unsigned long *configs, unsigned int num_configs)
2304 {
2305 	struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
2306 	int rc;
2307 
2308 	while (num_configs--) {
2309 		rc = npcm8xx_config_set_one(npcm, pin, *configs++);
2310 		if (rc)
2311 			return rc;
2312 	}
2313 
2314 	return 0;
2315 }
2316 
2317 static const struct pinconf_ops npcm8xx_pinconf_ops = {
2318 	.is_generic = true,
2319 	.pin_config_get = npcm8xx_config_get,
2320 	.pin_config_set = npcm8xx_config_set,
2321 };
2322 
2323 /* pinctrl_desc */
2324 static struct pinctrl_desc npcm8xx_pinctrl_desc = {
2325 	.name = "npcm8xx-pinctrl",
2326 	.pins = npcm8xx_pins,
2327 	.npins = ARRAY_SIZE(npcm8xx_pins),
2328 	.pctlops = &npcm8xx_pinctrl_ops,
2329 	.pmxops = &npcm8xx_pinmux_ops,
2330 	.confops = &npcm8xx_pinconf_ops,
2331 	.owner = THIS_MODULE,
2332 };
2333 
2334 static int npcmgpio_add_pin_ranges(struct gpio_chip *chip)
2335 {
2336 	struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
2337 
2338 	return gpiochip_add_pin_range(&bank->gc, dev_name(chip->parent),
2339 				      bank->pinctrl_id, bank->gc.base,
2340 				      bank->gc.ngpio);
2341 }
2342 
2343 static int npcm8xx_gpio_fw(struct npcm8xx_pinctrl *pctrl)
2344 {
2345 	struct fwnode_reference_args args;
2346 	struct device *dev = pctrl->dev;
2347 	struct fwnode_handle *child;
2348 	int ret = -ENXIO;
2349 	int id = 0, i;
2350 
2351 	for_each_gpiochip_node(dev, child) {
2352 		pctrl->gpio_bank[id].base = fwnode_iomap(child, 0);
2353 		if (!pctrl->gpio_bank[id].base)
2354 			return dev_err_probe(dev, -ENXIO, "fwnode_iomap id %d failed\n", id);
2355 
2356 		ret = bgpio_init(&pctrl->gpio_bank[id].gc, dev, 4,
2357 				 pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DIN,
2358 				 pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DOUT,
2359 				 NULL,
2360 				 NULL,
2361 				 pctrl->gpio_bank[id].base + NPCM8XX_GP_N_IEM,
2362 				 BGPIOF_READ_OUTPUT_REG_SET);
2363 		if (ret)
2364 			return dev_err_probe(dev, ret, "bgpio_init() failed\n");
2365 
2366 		ret = fwnode_property_get_reference_args(child, "gpio-ranges", NULL, 3, 0, &args);
2367 		if (ret < 0)
2368 			return dev_err_probe(dev, ret, "gpio-ranges fail for GPIO bank %u\n", id);
2369 
2370 		ret = fwnode_irq_get(child, 0);
2371 		if (!ret)
2372 			return dev_err_probe(dev, ret, "No IRQ for GPIO bank %u\n", id);
2373 
2374 		pctrl->gpio_bank[id].irq = ret;
2375 		pctrl->gpio_bank[id].irq_chip = npcmgpio_irqchip;
2376 		pctrl->gpio_bank[id].irqbase = id * NPCM8XX_GPIO_PER_BANK;
2377 		pctrl->gpio_bank[id].pinctrl_id = args.args[0];
2378 		pctrl->gpio_bank[id].gc.base = -1;
2379 		pctrl->gpio_bank[id].gc.ngpio = args.args[2];
2380 		pctrl->gpio_bank[id].gc.owner = THIS_MODULE;
2381 		pctrl->gpio_bank[id].gc.parent = dev;
2382 		pctrl->gpio_bank[id].gc.fwnode = child;
2383 		pctrl->gpio_bank[id].gc.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", child);
2384 		pctrl->gpio_bank[id].gc.dbg_show = npcmgpio_dbg_show;
2385 		pctrl->gpio_bank[id].direction_input = pctrl->gpio_bank[id].gc.direction_input;
2386 		pctrl->gpio_bank[id].gc.direction_input = npcmgpio_direction_input;
2387 		pctrl->gpio_bank[id].direction_output = pctrl->gpio_bank[id].gc.direction_output;
2388 		pctrl->gpio_bank[id].gc.direction_output = npcmgpio_direction_output;
2389 		pctrl->gpio_bank[id].request = pctrl->gpio_bank[id].gc.request;
2390 		pctrl->gpio_bank[id].gc.request = npcmgpio_gpio_request;
2391 		pctrl->gpio_bank[id].gc.free = npcmgpio_gpio_free;
2392 		for (i = 0 ; i < NPCM8XX_DEBOUNCE_MAX ; i++)
2393 			pctrl->gpio_bank[id].debounce.set_val[i] = false;
2394 		pctrl->gpio_bank[id].gc.add_pin_ranges = npcmgpio_add_pin_ranges;
2395 		id++;
2396 	}
2397 
2398 	pctrl->bank_num = id;
2399 	return ret;
2400 }
2401 
2402 static int npcm8xx_gpio_register(struct npcm8xx_pinctrl *pctrl)
2403 {
2404 	int ret, id;
2405 
2406 	for (id = 0 ; id < pctrl->bank_num ; id++) {
2407 		struct gpio_irq_chip *girq;
2408 
2409 		girq = &pctrl->gpio_bank[id].gc.irq;
2410 		girq->chip = &pctrl->gpio_bank[id].irq_chip;
2411 		girq->parent_handler = npcmgpio_irq_handler;
2412 		girq->num_parents = 1;
2413 		girq->parents = devm_kcalloc(pctrl->dev, girq->num_parents,
2414 					     sizeof(*girq->parents),
2415 					     GFP_KERNEL);
2416 		if (!girq->parents)
2417 			return -ENOMEM;
2418 
2419 		girq->parents[0] = pctrl->gpio_bank[id].irq;
2420 		girq->default_type = IRQ_TYPE_NONE;
2421 		girq->handler = handle_level_irq;
2422 		ret = devm_gpiochip_add_data(pctrl->dev,
2423 					     &pctrl->gpio_bank[id].gc,
2424 					     &pctrl->gpio_bank[id]);
2425 		if (ret)
2426 			return dev_err_probe(pctrl->dev, ret, "Failed to add GPIO chip %u\n", id);
2427 	}
2428 
2429 	return 0;
2430 }
2431 
2432 static int npcm8xx_pinctrl_probe(struct platform_device *pdev)
2433 {
2434 	struct device *dev = &pdev->dev;
2435 	struct npcm8xx_pinctrl *pctrl;
2436 	int ret;
2437 
2438 	pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
2439 	if (!pctrl)
2440 		return -ENOMEM;
2441 
2442 	pctrl->dev = dev;
2443 	platform_set_drvdata(pdev, pctrl);
2444 
2445 	pctrl->gcr_regmap =
2446 		syscon_regmap_lookup_by_phandle(dev->of_node, "nuvoton,sysgcr");
2447 	if (IS_ERR(pctrl->gcr_regmap))
2448 		return dev_err_probe(dev, PTR_ERR(pctrl->gcr_regmap),
2449 				      "Failed to find nuvoton,sysgcr property\n");
2450 
2451 	ret = npcm8xx_gpio_fw(pctrl);
2452 	if (ret < 0)
2453 		return dev_err_probe(dev, ret,
2454 				      "Failed to gpio dt-binding\n");
2455 
2456 	pctrl->pctldev = devm_pinctrl_register(dev, &npcm8xx_pinctrl_desc, pctrl);
2457 	if (IS_ERR(pctrl->pctldev))
2458 		return dev_err_probe(dev, PTR_ERR(pctrl->pctldev),
2459 				     "Failed to register pinctrl device\n");
2460 
2461 	ret = npcm8xx_gpio_register(pctrl);
2462 	if (ret < 0)
2463 		dev_err_probe(dev, ret, "Failed to register gpio\n");
2464 
2465 	return 0;
2466 }
2467 
2468 static const struct of_device_id npcm8xx_pinctrl_match[] = {
2469 	{ .compatible = "nuvoton,npcm845-pinctrl" },
2470 	{ }
2471 };
2472 MODULE_DEVICE_TABLE(of, npcm8xx_pinctrl_match);
2473 
2474 static struct platform_driver npcm8xx_pinctrl_driver = {
2475 	.probe = npcm8xx_pinctrl_probe,
2476 	.driver = {
2477 		.name = "npcm8xx-pinctrl",
2478 		.of_match_table = npcm8xx_pinctrl_match,
2479 		.suppress_bind_attrs = true,
2480 	},
2481 };
2482 
2483 static int __init npcm8xx_pinctrl_register(void)
2484 {
2485 	return platform_driver_register(&npcm8xx_pinctrl_driver);
2486 }
2487 arch_initcall(npcm8xx_pinctrl_register);
2488 
2489 MODULE_LICENSE("GPL v2");
2490 MODULE_AUTHOR("tomer.maimon@nuvoton.com");
2491 MODULE_DESCRIPTION("Nuvoton NPCM8XX Pinctrl and GPIO driver");
2492