1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel Cannon Lake PCH pinctrl/GPIO driver 4 * 5 * Copyright (C) 2017, Intel Corporation 6 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 7 * Mika Westerberg <mika.westerberg@linux.intel.com> 8 */ 9 10 #include <linux/mod_devicetable.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm.h> 14 15 #include <linux/pinctrl/pinctrl.h> 16 17 #include "pinctrl-intel.h" 18 19 #define CNL_PAD_OWN 0x020 20 #define CNL_PADCFGLOCK 0x080 21 #define CNL_HOSTSW_OWN 0x0b0 22 #define CNL_GPI_IE 0x120 23 24 #define CNL_GPP(r, s, e, g) \ 25 { \ 26 .reg_num = (r), \ 27 .base = (s), \ 28 .size = ((e) - (s) + 1), \ 29 .gpio_base = (g), \ 30 } 31 32 #define CNL_NO_GPIO -1 33 34 #define CNL_COMMUNITY(b, s, e, g) \ 35 { \ 36 .barno = (b), \ 37 .padown_offset = CNL_PAD_OWN, \ 38 .padcfglock_offset = CNL_PADCFGLOCK, \ 39 .hostown_offset = CNL_HOSTSW_OWN, \ 40 .ie_offset = CNL_GPI_IE, \ 41 .pin_base = (s), \ 42 .npins = ((e) - (s) + 1), \ 43 .gpps = (g), \ 44 .ngpps = ARRAY_SIZE(g), \ 45 } 46 47 /* Cannon Lake-H */ 48 static const struct pinctrl_pin_desc cnlh_pins[] = { 49 /* GPP_A */ 50 PINCTRL_PIN(0, "RCINB"), 51 PINCTRL_PIN(1, "LAD_0"), 52 PINCTRL_PIN(2, "LAD_1"), 53 PINCTRL_PIN(3, "LAD_2"), 54 PINCTRL_PIN(4, "LAD_3"), 55 PINCTRL_PIN(5, "LFRAMEB"), 56 PINCTRL_PIN(6, "SERIRQ"), 57 PINCTRL_PIN(7, "PIRQAB"), 58 PINCTRL_PIN(8, "CLKRUNB"), 59 PINCTRL_PIN(9, "CLKOUT_LPC_0"), 60 PINCTRL_PIN(10, "CLKOUT_LPC_1"), 61 PINCTRL_PIN(11, "PMEB"), 62 PINCTRL_PIN(12, "BM_BUSYB"), 63 PINCTRL_PIN(13, "SUSWARNB_SUSPWRDNACK"), 64 PINCTRL_PIN(14, "SUS_STATB"), 65 PINCTRL_PIN(15, "SUSACKB"), 66 PINCTRL_PIN(16, "CLKOUT_48"), 67 PINCTRL_PIN(17, "SD_VDD1_PWR_EN_B"), 68 PINCTRL_PIN(18, "ISH_GP_0"), 69 PINCTRL_PIN(19, "ISH_GP_1"), 70 PINCTRL_PIN(20, "ISH_GP_2"), 71 PINCTRL_PIN(21, "ISH_GP_3"), 72 PINCTRL_PIN(22, "ISH_GP_4"), 73 PINCTRL_PIN(23, "ISH_GP_5"), 74 PINCTRL_PIN(24, "ESPI_CLK_LOOPBK"), 75 /* GPP_B */ 76 PINCTRL_PIN(25, "GSPI0_CS1B"), 77 PINCTRL_PIN(26, "GSPI1_CS1B"), 78 PINCTRL_PIN(27, "VRALERTB"), 79 PINCTRL_PIN(28, "CPU_GP_2"), 80 PINCTRL_PIN(29, "CPU_GP_3"), 81 PINCTRL_PIN(30, "SRCCLKREQB_0"), 82 PINCTRL_PIN(31, "SRCCLKREQB_1"), 83 PINCTRL_PIN(32, "SRCCLKREQB_2"), 84 PINCTRL_PIN(33, "SRCCLKREQB_3"), 85 PINCTRL_PIN(34, "SRCCLKREQB_4"), 86 PINCTRL_PIN(35, "SRCCLKREQB_5"), 87 PINCTRL_PIN(36, "SSP_MCLK"), 88 PINCTRL_PIN(37, "SLP_S0B"), 89 PINCTRL_PIN(38, "PLTRSTB"), 90 PINCTRL_PIN(39, "SPKR"), 91 PINCTRL_PIN(40, "GSPI0_CS0B"), 92 PINCTRL_PIN(41, "GSPI0_CLK"), 93 PINCTRL_PIN(42, "GSPI0_MISO"), 94 PINCTRL_PIN(43, "GSPI0_MOSI"), 95 PINCTRL_PIN(44, "GSPI1_CS0B"), 96 PINCTRL_PIN(45, "GSPI1_CLK"), 97 PINCTRL_PIN(46, "GSPI1_MISO"), 98 PINCTRL_PIN(47, "GSPI1_MOSI"), 99 PINCTRL_PIN(48, "SML1ALERTB"), 100 PINCTRL_PIN(49, "GSPI0_CLK_LOOPBK"), 101 PINCTRL_PIN(50, "GSPI1_CLK_LOOPBK"), 102 /* GPP_C */ 103 PINCTRL_PIN(51, "SMBCLK"), 104 PINCTRL_PIN(52, "SMBDATA"), 105 PINCTRL_PIN(53, "SMBALERTB"), 106 PINCTRL_PIN(54, "SML0CLK"), 107 PINCTRL_PIN(55, "SML0DATA"), 108 PINCTRL_PIN(56, "SML0ALERTB"), 109 PINCTRL_PIN(57, "SML1CLK"), 110 PINCTRL_PIN(58, "SML1DATA"), 111 PINCTRL_PIN(59, "UART0_RXD"), 112 PINCTRL_PIN(60, "UART0_TXD"), 113 PINCTRL_PIN(61, "UART0_RTSB"), 114 PINCTRL_PIN(62, "UART0_CTSB"), 115 PINCTRL_PIN(63, "UART1_RXD"), 116 PINCTRL_PIN(64, "UART1_TXD"), 117 PINCTRL_PIN(65, "UART1_RTSB"), 118 PINCTRL_PIN(66, "UART1_CTSB"), 119 PINCTRL_PIN(67, "I2C0_SDA"), 120 PINCTRL_PIN(68, "I2C0_SCL"), 121 PINCTRL_PIN(69, "I2C1_SDA"), 122 PINCTRL_PIN(70, "I2C1_SCL"), 123 PINCTRL_PIN(71, "UART2_RXD"), 124 PINCTRL_PIN(72, "UART2_TXD"), 125 PINCTRL_PIN(73, "UART2_RTSB"), 126 PINCTRL_PIN(74, "UART2_CTSB"), 127 /* GPP_D */ 128 PINCTRL_PIN(75, "SPI1_CSB"), 129 PINCTRL_PIN(76, "SPI1_CLK"), 130 PINCTRL_PIN(77, "SPI1_MISO_IO_1"), 131 PINCTRL_PIN(78, "SPI1_MOSI_IO_0"), 132 PINCTRL_PIN(79, "ISH_I2C2_SDA"), 133 PINCTRL_PIN(80, "SSP2_SFRM"), 134 PINCTRL_PIN(81, "SSP2_TXD"), 135 PINCTRL_PIN(82, "SSP2_RXD"), 136 PINCTRL_PIN(83, "SSP2_SCLK"), 137 PINCTRL_PIN(84, "ISH_SPI_CSB"), 138 PINCTRL_PIN(85, "ISH_SPI_CLK"), 139 PINCTRL_PIN(86, "ISH_SPI_MISO"), 140 PINCTRL_PIN(87, "ISH_SPI_MOSI"), 141 PINCTRL_PIN(88, "ISH_UART0_RXD"), 142 PINCTRL_PIN(89, "ISH_UART0_TXD"), 143 PINCTRL_PIN(90, "ISH_UART0_RTSB"), 144 PINCTRL_PIN(91, "ISH_UART0_CTSB"), 145 PINCTRL_PIN(92, "DMIC_CLK_1"), 146 PINCTRL_PIN(93, "DMIC_DATA_1"), 147 PINCTRL_PIN(94, "DMIC_CLK_0"), 148 PINCTRL_PIN(95, "DMIC_DATA_0"), 149 PINCTRL_PIN(96, "SPI1_IO_2"), 150 PINCTRL_PIN(97, "SPI1_IO_3"), 151 PINCTRL_PIN(98, "ISH_I2C2_SCL"), 152 /* GPP_G */ 153 PINCTRL_PIN(99, "SD3_CMD"), 154 PINCTRL_PIN(100, "SD3_D0"), 155 PINCTRL_PIN(101, "SD3_D1"), 156 PINCTRL_PIN(102, "SD3_D2"), 157 PINCTRL_PIN(103, "SD3_D3"), 158 PINCTRL_PIN(104, "SD3_CDB"), 159 PINCTRL_PIN(105, "SD3_CLK"), 160 PINCTRL_PIN(106, "SD3_WP"), 161 /* AZA */ 162 PINCTRL_PIN(107, "HDA_BCLK"), 163 PINCTRL_PIN(108, "HDA_RSTB"), 164 PINCTRL_PIN(109, "HDA_SYNC"), 165 PINCTRL_PIN(110, "HDA_SDO"), 166 PINCTRL_PIN(111, "HDA_SDI_0"), 167 PINCTRL_PIN(112, "HDA_SDI_1"), 168 PINCTRL_PIN(113, "SSP1_SFRM"), 169 PINCTRL_PIN(114, "SSP1_TXD"), 170 /* vGPIO */ 171 PINCTRL_PIN(115, "CNV_BTEN"), 172 PINCTRL_PIN(116, "CNV_GNEN"), 173 PINCTRL_PIN(117, "CNV_WFEN"), 174 PINCTRL_PIN(118, "CNV_WCEN"), 175 PINCTRL_PIN(119, "CNV_BT_HOST_WAKEB"), 176 PINCTRL_PIN(120, "vCNV_GNSS_HOST_WAKEB"), 177 PINCTRL_PIN(121, "vSD3_CD_B"), 178 PINCTRL_PIN(122, "CNV_BT_IF_SELECT"), 179 PINCTRL_PIN(123, "vCNV_BT_UART_TXD"), 180 PINCTRL_PIN(124, "vCNV_BT_UART_RXD"), 181 PINCTRL_PIN(125, "vCNV_BT_UART_CTS_B"), 182 PINCTRL_PIN(126, "vCNV_BT_UART_RTS_B"), 183 PINCTRL_PIN(127, "vCNV_MFUART1_TXD"), 184 PINCTRL_PIN(128, "vCNV_MFUART1_RXD"), 185 PINCTRL_PIN(129, "vCNV_MFUART1_CTS_B"), 186 PINCTRL_PIN(130, "vCNV_MFUART1_RTS_B"), 187 PINCTRL_PIN(131, "vCNV_GNSS_UART_TXD"), 188 PINCTRL_PIN(132, "vCNV_GNSS_UART_RXD"), 189 PINCTRL_PIN(133, "vCNV_GNSS_UART_CTS_B"), 190 PINCTRL_PIN(134, "vCNV_GNSS_UART_RTS_B"), 191 PINCTRL_PIN(135, "vUART0_TXD"), 192 PINCTRL_PIN(136, "vUART0_RXD"), 193 PINCTRL_PIN(137, "vUART0_CTS_B"), 194 PINCTRL_PIN(138, "vUART0_RTSB"), 195 PINCTRL_PIN(139, "vISH_UART0_TXD"), 196 PINCTRL_PIN(140, "vISH_UART0_RXD"), 197 PINCTRL_PIN(141, "vISH_UART0_CTS_B"), 198 PINCTRL_PIN(142, "vISH_UART0_RTSB"), 199 PINCTRL_PIN(143, "vISH_UART1_TXD"), 200 PINCTRL_PIN(144, "vISH_UART1_RXD"), 201 PINCTRL_PIN(145, "vISH_UART1_CTS_B"), 202 PINCTRL_PIN(146, "vISH_UART1_RTS_B"), 203 PINCTRL_PIN(147, "vCNV_BT_I2S_BCLK"), 204 PINCTRL_PIN(148, "vCNV_BT_I2S_WS_SYNC"), 205 PINCTRL_PIN(149, "vCNV_BT_I2S_SDO"), 206 PINCTRL_PIN(150, "vCNV_BT_I2S_SDI"), 207 PINCTRL_PIN(151, "vSSP2_SCLK"), 208 PINCTRL_PIN(152, "vSSP2_SFRM"), 209 PINCTRL_PIN(153, "vSSP2_TXD"), 210 PINCTRL_PIN(154, "vSSP2_RXD"), 211 /* GPP_K */ 212 PINCTRL_PIN(155, "FAN_TACH_0"), 213 PINCTRL_PIN(156, "FAN_TACH_1"), 214 PINCTRL_PIN(157, "FAN_TACH_2"), 215 PINCTRL_PIN(158, "FAN_TACH_3"), 216 PINCTRL_PIN(159, "FAN_TACH_4"), 217 PINCTRL_PIN(160, "FAN_TACH_5"), 218 PINCTRL_PIN(161, "FAN_TACH_6"), 219 PINCTRL_PIN(162, "FAN_TACH_7"), 220 PINCTRL_PIN(163, "FAN_PWM_0"), 221 PINCTRL_PIN(164, "FAN_PWM_1"), 222 PINCTRL_PIN(165, "FAN_PWM_2"), 223 PINCTRL_PIN(166, "FAN_PWM_3"), 224 PINCTRL_PIN(167, "GSXDOUT"), 225 PINCTRL_PIN(168, "GSXSLOAD"), 226 PINCTRL_PIN(169, "GSXDIN"), 227 PINCTRL_PIN(170, "GSXSRESETB"), 228 PINCTRL_PIN(171, "GSXCLK"), 229 PINCTRL_PIN(172, "ADR_COMPLETE"), 230 PINCTRL_PIN(173, "NMIB"), 231 PINCTRL_PIN(174, "SMIB"), 232 PINCTRL_PIN(175, "CORE_VID_0"), 233 PINCTRL_PIN(176, "CORE_VID_1"), 234 PINCTRL_PIN(177, "IMGCLKOUT_0"), 235 PINCTRL_PIN(178, "IMGCLKOUT_1"), 236 /* GPP_H */ 237 PINCTRL_PIN(179, "SRCCLKREQB_6"), 238 PINCTRL_PIN(180, "SRCCLKREQB_7"), 239 PINCTRL_PIN(181, "SRCCLKREQB_8"), 240 PINCTRL_PIN(182, "SRCCLKREQB_9"), 241 PINCTRL_PIN(183, "SRCCLKREQB_10"), 242 PINCTRL_PIN(184, "SRCCLKREQB_11"), 243 PINCTRL_PIN(185, "SRCCLKREQB_12"), 244 PINCTRL_PIN(186, "SRCCLKREQB_13"), 245 PINCTRL_PIN(187, "SRCCLKREQB_14"), 246 PINCTRL_PIN(188, "SRCCLKREQB_15"), 247 PINCTRL_PIN(189, "SML2CLK"), 248 PINCTRL_PIN(190, "SML2DATA"), 249 PINCTRL_PIN(191, "SML2ALERTB"), 250 PINCTRL_PIN(192, "SML3CLK"), 251 PINCTRL_PIN(193, "SML3DATA"), 252 PINCTRL_PIN(194, "SML3ALERTB"), 253 PINCTRL_PIN(195, "SML4CLK"), 254 PINCTRL_PIN(196, "SML4DATA"), 255 PINCTRL_PIN(197, "SML4ALERTB"), 256 PINCTRL_PIN(198, "ISH_I2C0_SDA"), 257 PINCTRL_PIN(199, "ISH_I2C0_SCL"), 258 PINCTRL_PIN(200, "ISH_I2C1_SDA"), 259 PINCTRL_PIN(201, "ISH_I2C1_SCL"), 260 PINCTRL_PIN(202, "TIME_SYNC_0"), 261 /* GPP_E */ 262 PINCTRL_PIN(203, "SATAXPCIE_0"), 263 PINCTRL_PIN(204, "SATAXPCIE_1"), 264 PINCTRL_PIN(205, "SATAXPCIE_2"), 265 PINCTRL_PIN(206, "CPU_GP_0"), 266 PINCTRL_PIN(207, "SATA_DEVSLP_0"), 267 PINCTRL_PIN(208, "SATA_DEVSLP_1"), 268 PINCTRL_PIN(209, "SATA_DEVSLP_2"), 269 PINCTRL_PIN(210, "CPU_GP_1"), 270 PINCTRL_PIN(211, "SATA_LEDB"), 271 PINCTRL_PIN(212, "USB2_OCB_0"), 272 PINCTRL_PIN(213, "USB2_OCB_1"), 273 PINCTRL_PIN(214, "USB2_OCB_2"), 274 PINCTRL_PIN(215, "USB2_OCB_3"), 275 /* GPP_F */ 276 PINCTRL_PIN(216, "SATAXPCIE_3"), 277 PINCTRL_PIN(217, "SATAXPCIE_4"), 278 PINCTRL_PIN(218, "SATAXPCIE_5"), 279 PINCTRL_PIN(219, "SATAXPCIE_6"), 280 PINCTRL_PIN(220, "SATAXPCIE_7"), 281 PINCTRL_PIN(221, "SATA_DEVSLP_3"), 282 PINCTRL_PIN(222, "SATA_DEVSLP_4"), 283 PINCTRL_PIN(223, "SATA_DEVSLP_5"), 284 PINCTRL_PIN(224, "SATA_DEVSLP_6"), 285 PINCTRL_PIN(225, "SATA_DEVSLP_7"), 286 PINCTRL_PIN(226, "SATA_SCLOCK"), 287 PINCTRL_PIN(227, "SATA_SLOAD"), 288 PINCTRL_PIN(228, "SATA_SDATAOUT1"), 289 PINCTRL_PIN(229, "SATA_SDATAOUT0"), 290 PINCTRL_PIN(230, "EXT_PWR_GATEB"), 291 PINCTRL_PIN(231, "USB2_OCB_4"), 292 PINCTRL_PIN(232, "USB2_OCB_5"), 293 PINCTRL_PIN(233, "USB2_OCB_6"), 294 PINCTRL_PIN(234, "USB2_OCB_7"), 295 PINCTRL_PIN(235, "L_VDDEN"), 296 PINCTRL_PIN(236, "L_BKLTEN"), 297 PINCTRL_PIN(237, "L_BKLTCTL"), 298 PINCTRL_PIN(238, "DDPF_CTRLCLK"), 299 PINCTRL_PIN(239, "DDPF_CTRLDATA"), 300 /* SPI */ 301 PINCTRL_PIN(240, "SPI0_IO_2"), 302 PINCTRL_PIN(241, "SPI0_IO_3"), 303 PINCTRL_PIN(242, "SPI0_MOSI_IO_0"), 304 PINCTRL_PIN(243, "SPI0_MISO_IO_1"), 305 PINCTRL_PIN(244, "SPI0_TPM_CSB"), 306 PINCTRL_PIN(245, "SPI0_FLASH_0_CSB"), 307 PINCTRL_PIN(246, "SPI0_FLASH_1_CSB"), 308 PINCTRL_PIN(247, "SPI0_CLK"), 309 PINCTRL_PIN(248, "SPI0_CLK_LOOPBK"), 310 /* CPU */ 311 PINCTRL_PIN(249, "HDACPU_SDI"), 312 PINCTRL_PIN(250, "HDACPU_SDO"), 313 PINCTRL_PIN(251, "HDACPU_SCLK"), 314 PINCTRL_PIN(252, "PM_SYNC"), 315 PINCTRL_PIN(253, "PECI"), 316 PINCTRL_PIN(254, "CPUPWRGD"), 317 PINCTRL_PIN(255, "THRMTRIPB"), 318 PINCTRL_PIN(256, "PLTRST_CPUB"), 319 PINCTRL_PIN(257, "PM_DOWN"), 320 PINCTRL_PIN(258, "TRIGGER_IN"), 321 PINCTRL_PIN(259, "TRIGGER_OUT"), 322 /* JTAG */ 323 PINCTRL_PIN(260, "JTAG_TDO"), 324 PINCTRL_PIN(261, "JTAGX"), 325 PINCTRL_PIN(262, "PRDYB"), 326 PINCTRL_PIN(263, "PREQB"), 327 PINCTRL_PIN(264, "CPU_TRSTB"), 328 PINCTRL_PIN(265, "JTAG_TDI"), 329 PINCTRL_PIN(266, "JTAG_TMS"), 330 PINCTRL_PIN(267, "JTAG_TCK"), 331 PINCTRL_PIN(268, "ITP_PMODE"), 332 /* GPP_I */ 333 PINCTRL_PIN(269, "DDSP_HPD_0"), 334 PINCTRL_PIN(270, "DDSP_HPD_1"), 335 PINCTRL_PIN(271, "DDSP_HPD_2"), 336 PINCTRL_PIN(272, "DDSP_HPD_3"), 337 PINCTRL_PIN(273, "EDP_HPD"), 338 PINCTRL_PIN(274, "DDPB_CTRLCLK"), 339 PINCTRL_PIN(275, "DDPB_CTRLDATA"), 340 PINCTRL_PIN(276, "DDPC_CTRLCLK"), 341 PINCTRL_PIN(277, "DDPC_CTRLDATA"), 342 PINCTRL_PIN(278, "DDPD_CTRLCLK"), 343 PINCTRL_PIN(279, "DDPD_CTRLDATA"), 344 PINCTRL_PIN(280, "M2_SKT2_CFG_0"), 345 PINCTRL_PIN(281, "M2_SKT2_CFG_1"), 346 PINCTRL_PIN(282, "M2_SKT2_CFG_2"), 347 PINCTRL_PIN(283, "M2_SKT2_CFG_3"), 348 PINCTRL_PIN(284, "SYS_PWROK"), 349 PINCTRL_PIN(285, "SYS_RESETB"), 350 PINCTRL_PIN(286, "MLK_RSTB"), 351 /* GPP_J */ 352 PINCTRL_PIN(287, "CNV_PA_BLANKING"), 353 PINCTRL_PIN(288, "CNV_GNSS_FTA"), 354 PINCTRL_PIN(289, "CNV_GNSS_SYSCK"), 355 PINCTRL_PIN(290, "CNV_RF_RESET_B"), 356 PINCTRL_PIN(291, "CNV_BRI_DT"), 357 PINCTRL_PIN(292, "CNV_BRI_RSP"), 358 PINCTRL_PIN(293, "CNV_RGI_DT"), 359 PINCTRL_PIN(294, "CNV_RGI_RSP"), 360 PINCTRL_PIN(295, "CNV_MFUART2_RXD"), 361 PINCTRL_PIN(296, "CNV_MFUART2_TXD"), 362 PINCTRL_PIN(297, "CNV_MODEM_CLKREQ"), 363 PINCTRL_PIN(298, "A4WP_PRESENT"), 364 }; 365 366 static const struct intel_padgroup cnlh_community0_gpps[] = { 367 CNL_GPP(0, 0, 24, 0), /* GPP_A */ 368 CNL_GPP(1, 25, 50, 32), /* GPP_B */ 369 }; 370 371 static const struct intel_padgroup cnlh_community1_gpps[] = { 372 CNL_GPP(0, 51, 74, 64), /* GPP_C */ 373 CNL_GPP(1, 75, 98, 96), /* GPP_D */ 374 CNL_GPP(2, 99, 106, 128), /* GPP_G */ 375 CNL_GPP(3, 107, 114, CNL_NO_GPIO), /* AZA */ 376 CNL_GPP(4, 115, 146, 160), /* vGPIO_0 */ 377 CNL_GPP(5, 147, 154, CNL_NO_GPIO), /* vGPIO_1 */ 378 }; 379 380 static const struct intel_padgroup cnlh_community3_gpps[] = { 381 CNL_GPP(0, 155, 178, 192), /* GPP_K */ 382 CNL_GPP(1, 179, 202, 224), /* GPP_H */ 383 CNL_GPP(2, 203, 215, 258), /* GPP_E */ 384 CNL_GPP(3, 216, 239, 288), /* GPP_F */ 385 CNL_GPP(4, 240, 248, CNL_NO_GPIO), /* SPI */ 386 }; 387 388 static const struct intel_padgroup cnlh_community4_gpps[] = { 389 CNL_GPP(0, 249, 259, CNL_NO_GPIO), /* CPU */ 390 CNL_GPP(1, 260, 268, CNL_NO_GPIO), /* JTAG */ 391 CNL_GPP(2, 269, 286, 320), /* GPP_I */ 392 CNL_GPP(3, 287, 298, 352), /* GPP_J */ 393 }; 394 395 static const unsigned int cnlh_spi0_pins[] = { 40, 41, 42, 43 }; 396 static const unsigned int cnlh_spi1_pins[] = { 44, 45, 46, 47 }; 397 static const unsigned int cnlh_spi2_pins[] = { 84, 85, 86, 87 }; 398 399 static const unsigned int cnlh_uart0_pins[] = { 59, 60, 61, 62 }; 400 static const unsigned int cnlh_uart1_pins[] = { 63, 64, 65, 66 }; 401 static const unsigned int cnlh_uart2_pins[] = { 71, 72, 73, 74 }; 402 403 static const unsigned int cnlh_i2c0_pins[] = { 67, 68 }; 404 static const unsigned int cnlh_i2c1_pins[] = { 69, 70 }; 405 static const unsigned int cnlh_i2c2_pins[] = { 88, 89 }; 406 static const unsigned int cnlh_i2c3_pins[] = { 79, 98 }; 407 408 static const struct intel_pingroup cnlh_groups[] = { 409 PIN_GROUP("spi0_grp", cnlh_spi0_pins, 1), 410 PIN_GROUP("spi1_grp", cnlh_spi1_pins, 1), 411 PIN_GROUP("spi2_grp", cnlh_spi2_pins, 3), 412 PIN_GROUP("uart0_grp", cnlh_uart0_pins, 1), 413 PIN_GROUP("uart1_grp", cnlh_uart1_pins, 1), 414 PIN_GROUP("uart2_grp", cnlh_uart2_pins, 1), 415 PIN_GROUP("i2c0_grp", cnlh_i2c0_pins, 1), 416 PIN_GROUP("i2c1_grp", cnlh_i2c1_pins, 1), 417 PIN_GROUP("i2c2_grp", cnlh_i2c2_pins, 3), 418 PIN_GROUP("i2c3_grp", cnlh_i2c3_pins, 2), 419 }; 420 421 static const char * const cnlh_spi0_groups[] = { "spi0_grp" }; 422 static const char * const cnlh_spi1_groups[] = { "spi1_grp" }; 423 static const char * const cnlh_spi2_groups[] = { "spi2_grp" }; 424 static const char * const cnlh_uart0_groups[] = { "uart0_grp" }; 425 static const char * const cnlh_uart1_groups[] = { "uart1_grp" }; 426 static const char * const cnlh_uart2_groups[] = { "uart2_grp" }; 427 static const char * const cnlh_i2c0_groups[] = { "i2c0_grp" }; 428 static const char * const cnlh_i2c1_groups[] = { "i2c1_grp" }; 429 static const char * const cnlh_i2c2_groups[] = { "i2c2_grp" }; 430 static const char * const cnlh_i2c3_groups[] = { "i2c3_grp" }; 431 432 static const struct intel_function cnlh_functions[] = { 433 FUNCTION("spi0", cnlh_spi0_groups), 434 FUNCTION("spi1", cnlh_spi1_groups), 435 FUNCTION("spi2", cnlh_spi2_groups), 436 FUNCTION("uart0", cnlh_uart0_groups), 437 FUNCTION("uart1", cnlh_uart1_groups), 438 FUNCTION("uart2", cnlh_uart2_groups), 439 FUNCTION("i2c0", cnlh_i2c0_groups), 440 FUNCTION("i2c1", cnlh_i2c1_groups), 441 FUNCTION("i2c2", cnlh_i2c2_groups), 442 FUNCTION("i2c3", cnlh_i2c3_groups), 443 }; 444 445 static const struct intel_community cnlh_communities[] = { 446 CNL_COMMUNITY(0, 0, 50, cnlh_community0_gpps), 447 CNL_COMMUNITY(1, 51, 154, cnlh_community1_gpps), 448 CNL_COMMUNITY(2, 155, 248, cnlh_community3_gpps), 449 CNL_COMMUNITY(3, 249, 298, cnlh_community4_gpps), 450 }; 451 452 static const struct intel_pinctrl_soc_data cnlh_soc_data = { 453 .pins = cnlh_pins, 454 .npins = ARRAY_SIZE(cnlh_pins), 455 .groups = cnlh_groups, 456 .ngroups = ARRAY_SIZE(cnlh_groups), 457 .functions = cnlh_functions, 458 .nfunctions = ARRAY_SIZE(cnlh_functions), 459 .communities = cnlh_communities, 460 .ncommunities = ARRAY_SIZE(cnlh_communities), 461 }; 462 463 /* Cannon Lake-LP */ 464 static const struct pinctrl_pin_desc cnllp_pins[] = { 465 /* GPP_A */ 466 PINCTRL_PIN(0, "RCINB"), 467 PINCTRL_PIN(1, "LAD_0"), 468 PINCTRL_PIN(2, "LAD_1"), 469 PINCTRL_PIN(3, "LAD_2"), 470 PINCTRL_PIN(4, "LAD_3"), 471 PINCTRL_PIN(5, "LFRAMEB"), 472 PINCTRL_PIN(6, "SERIRQ"), 473 PINCTRL_PIN(7, "PIRQAB"), 474 PINCTRL_PIN(8, "CLKRUNB"), 475 PINCTRL_PIN(9, "CLKOUT_LPC_0"), 476 PINCTRL_PIN(10, "CLKOUT_LPC_1"), 477 PINCTRL_PIN(11, "PMEB"), 478 PINCTRL_PIN(12, "BM_BUSYB"), 479 PINCTRL_PIN(13, "SUSWARNB_SUSPWRDNACK"), 480 PINCTRL_PIN(14, "SUS_STATB"), 481 PINCTRL_PIN(15, "SUSACKB"), 482 PINCTRL_PIN(16, "SD_1P8_SEL"), 483 PINCTRL_PIN(17, "SD_PWR_EN_B"), 484 PINCTRL_PIN(18, "ISH_GP_0"), 485 PINCTRL_PIN(19, "ISH_GP_1"), 486 PINCTRL_PIN(20, "ISH_GP_2"), 487 PINCTRL_PIN(21, "ISH_GP_3"), 488 PINCTRL_PIN(22, "ISH_GP_4"), 489 PINCTRL_PIN(23, "ISH_GP_5"), 490 PINCTRL_PIN(24, "ESPI_CLK_LOOPBK"), 491 /* GPP_B */ 492 PINCTRL_PIN(25, "CORE_VID_0"), 493 PINCTRL_PIN(26, "CORE_VID_1"), 494 PINCTRL_PIN(27, "VRALERTB"), 495 PINCTRL_PIN(28, "CPU_GP_2"), 496 PINCTRL_PIN(29, "CPU_GP_3"), 497 PINCTRL_PIN(30, "SRCCLKREQB_0"), 498 PINCTRL_PIN(31, "SRCCLKREQB_1"), 499 PINCTRL_PIN(32, "SRCCLKREQB_2"), 500 PINCTRL_PIN(33, "SRCCLKREQB_3"), 501 PINCTRL_PIN(34, "SRCCLKREQB_4"), 502 PINCTRL_PIN(35, "SRCCLKREQB_5"), 503 PINCTRL_PIN(36, "EXT_PWR_GATEB"), 504 PINCTRL_PIN(37, "SLP_S0B"), 505 PINCTRL_PIN(38, "PLTRSTB"), 506 PINCTRL_PIN(39, "SPKR"), 507 PINCTRL_PIN(40, "GSPI0_CS0B"), 508 PINCTRL_PIN(41, "GSPI0_CLK"), 509 PINCTRL_PIN(42, "GSPI0_MISO"), 510 PINCTRL_PIN(43, "GSPI0_MOSI"), 511 PINCTRL_PIN(44, "GSPI1_CS0B"), 512 PINCTRL_PIN(45, "GSPI1_CLK"), 513 PINCTRL_PIN(46, "GSPI1_MISO"), 514 PINCTRL_PIN(47, "GSPI1_MOSI"), 515 PINCTRL_PIN(48, "SML1ALERTB"), 516 PINCTRL_PIN(49, "GSPI0_CLK_LOOPBK"), 517 PINCTRL_PIN(50, "GSPI1_CLK_LOOPBK"), 518 /* GPP_G */ 519 PINCTRL_PIN(51, "SD3_CMD"), 520 PINCTRL_PIN(52, "SD3_D0_SD4_RCLK_P"), 521 PINCTRL_PIN(53, "SD3_D1_SD4_RCLK_N"), 522 PINCTRL_PIN(54, "SD3_D2"), 523 PINCTRL_PIN(55, "SD3_D3"), 524 PINCTRL_PIN(56, "SD3_CDB"), 525 PINCTRL_PIN(57, "SD3_CLK"), 526 PINCTRL_PIN(58, "SD3_WP"), 527 /* SPI */ 528 PINCTRL_PIN(59, "SPI0_IO_2"), 529 PINCTRL_PIN(60, "SPI0_IO_3"), 530 PINCTRL_PIN(61, "SPI0_MOSI_IO_0"), 531 PINCTRL_PIN(62, "SPI0_MISO_IO_1"), 532 PINCTRL_PIN(63, "SPI0_TPM_CSB"), 533 PINCTRL_PIN(64, "SPI0_FLASH_0_CSB"), 534 PINCTRL_PIN(65, "SPI0_FLASH_1_CSB"), 535 PINCTRL_PIN(66, "SPI0_CLK"), 536 PINCTRL_PIN(67, "SPI0_CLK_LOOPBK"), 537 /* GPP_D */ 538 PINCTRL_PIN(68, "SPI1_CSB"), 539 PINCTRL_PIN(69, "SPI1_CLK"), 540 PINCTRL_PIN(70, "SPI1_MISO_IO_1"), 541 PINCTRL_PIN(71, "SPI1_MOSI_IO_0"), 542 PINCTRL_PIN(72, "IMGCLKOUT_0"), 543 PINCTRL_PIN(73, "ISH_I2C0_SDA"), 544 PINCTRL_PIN(74, "ISH_I2C0_SCL"), 545 PINCTRL_PIN(75, "ISH_I2C1_SDA"), 546 PINCTRL_PIN(76, "ISH_I2C1_SCL"), 547 PINCTRL_PIN(77, "ISH_SPI_CSB"), 548 PINCTRL_PIN(78, "ISH_SPI_CLK"), 549 PINCTRL_PIN(79, "ISH_SPI_MISO"), 550 PINCTRL_PIN(80, "ISH_SPI_MOSI"), 551 PINCTRL_PIN(81, "ISH_UART0_RXD"), 552 PINCTRL_PIN(82, "ISH_UART0_TXD"), 553 PINCTRL_PIN(83, "ISH_UART0_RTSB"), 554 PINCTRL_PIN(84, "ISH_UART0_CTSB"), 555 PINCTRL_PIN(85, "DMIC_CLK_1"), 556 PINCTRL_PIN(86, "DMIC_DATA_1"), 557 PINCTRL_PIN(87, "DMIC_CLK_0"), 558 PINCTRL_PIN(88, "DMIC_DATA_0"), 559 PINCTRL_PIN(89, "SPI1_IO_2"), 560 PINCTRL_PIN(90, "SPI1_IO_3"), 561 PINCTRL_PIN(91, "SSP_MCLK"), 562 PINCTRL_PIN(92, "GSPI2_CLK_LOOPBK"), 563 /* GPP_F */ 564 PINCTRL_PIN(93, "CNV_GNSS_PA_BLANKING"), 565 PINCTRL_PIN(94, "CNV_GNSS_FTA"), 566 PINCTRL_PIN(95, "CNV_GNSS_SYSCK"), 567 PINCTRL_PIN(96, "EMMC_HIP_MON"), 568 PINCTRL_PIN(97, "CNV_BRI_DT"), 569 PINCTRL_PIN(98, "CNV_BRI_RSP"), 570 PINCTRL_PIN(99, "CNV_RGI_DT"), 571 PINCTRL_PIN(100, "CNV_RGI_RSP"), 572 PINCTRL_PIN(101, "CNV_MFUART2_RXD"), 573 PINCTRL_PIN(102, "CNV_MFUART2_TXD"), 574 PINCTRL_PIN(103, "GPP_F_10"), 575 PINCTRL_PIN(104, "EMMC_CMD"), 576 PINCTRL_PIN(105, "EMMC_DATA_0"), 577 PINCTRL_PIN(106, "EMMC_DATA_1"), 578 PINCTRL_PIN(107, "EMMC_DATA_2"), 579 PINCTRL_PIN(108, "EMMC_DATA_3"), 580 PINCTRL_PIN(109, "EMMC_DATA_4"), 581 PINCTRL_PIN(110, "EMMC_DATA_5"), 582 PINCTRL_PIN(111, "EMMC_DATA_6"), 583 PINCTRL_PIN(112, "EMMC_DATA_7"), 584 PINCTRL_PIN(113, "EMMC_RCLK"), 585 PINCTRL_PIN(114, "EMMC_CLK"), 586 PINCTRL_PIN(115, "EMMC_RESETB"), 587 PINCTRL_PIN(116, "A4WP_PRESENT"), 588 /* GPP_H */ 589 PINCTRL_PIN(117, "SSP2_SCLK"), 590 PINCTRL_PIN(118, "SSP2_SFRM"), 591 PINCTRL_PIN(119, "SSP2_TXD"), 592 PINCTRL_PIN(120, "SSP2_RXD"), 593 PINCTRL_PIN(121, "I2C2_SDA"), 594 PINCTRL_PIN(122, "I2C2_SCL"), 595 PINCTRL_PIN(123, "I2C3_SDA"), 596 PINCTRL_PIN(124, "I2C3_SCL"), 597 PINCTRL_PIN(125, "I2C4_SDA"), 598 PINCTRL_PIN(126, "I2C4_SCL"), 599 PINCTRL_PIN(127, "I2C5_SDA"), 600 PINCTRL_PIN(128, "I2C5_SCL"), 601 PINCTRL_PIN(129, "M2_SKT2_CFG_0"), 602 PINCTRL_PIN(130, "M2_SKT2_CFG_1"), 603 PINCTRL_PIN(131, "M2_SKT2_CFG_2"), 604 PINCTRL_PIN(132, "M2_SKT2_CFG_3"), 605 PINCTRL_PIN(133, "DDPF_CTRLCLK"), 606 PINCTRL_PIN(134, "DDPF_CTRLDATA"), 607 PINCTRL_PIN(135, "CPU_VCCIO_PWR_GATEB"), 608 PINCTRL_PIN(136, "TIMESYNC_0"), 609 PINCTRL_PIN(137, "IMGCLKOUT_1"), 610 PINCTRL_PIN(138, "GPPC_H_21"), 611 PINCTRL_PIN(139, "GPPC_H_22"), 612 PINCTRL_PIN(140, "GPPC_H_23"), 613 /* vGPIO */ 614 PINCTRL_PIN(141, "CNV_BTEN"), 615 PINCTRL_PIN(142, "CNV_GNEN"), 616 PINCTRL_PIN(143, "CNV_WFEN"), 617 PINCTRL_PIN(144, "CNV_WCEN"), 618 PINCTRL_PIN(145, "CNV_BT_HOST_WAKEB"), 619 PINCTRL_PIN(146, "CNV_BT_IF_SELECT"), 620 PINCTRL_PIN(147, "vCNV_BT_UART_TXD"), 621 PINCTRL_PIN(148, "vCNV_BT_UART_RXD"), 622 PINCTRL_PIN(149, "vCNV_BT_UART_CTS_B"), 623 PINCTRL_PIN(150, "vCNV_BT_UART_RTS_B"), 624 PINCTRL_PIN(151, "vCNV_MFUART1_TXD"), 625 PINCTRL_PIN(152, "vCNV_MFUART1_RXD"), 626 PINCTRL_PIN(153, "vCNV_MFUART1_CTS_B"), 627 PINCTRL_PIN(154, "vCNV_MFUART1_RTS_B"), 628 PINCTRL_PIN(155, "vCNV_GNSS_UART_TXD"), 629 PINCTRL_PIN(156, "vCNV_GNSS_UART_RXD"), 630 PINCTRL_PIN(157, "vCNV_GNSS_UART_CTS_B"), 631 PINCTRL_PIN(158, "vCNV_GNSS_UART_RTS_B"), 632 PINCTRL_PIN(159, "vUART0_TXD"), 633 PINCTRL_PIN(160, "vUART0_RXD"), 634 PINCTRL_PIN(161, "vUART0_CTS_B"), 635 PINCTRL_PIN(162, "vUART0_RTS_B"), 636 PINCTRL_PIN(163, "vISH_UART0_TXD"), 637 PINCTRL_PIN(164, "vISH_UART0_RXD"), 638 PINCTRL_PIN(165, "vISH_UART0_CTS_B"), 639 PINCTRL_PIN(166, "vISH_UART0_RTS_B"), 640 PINCTRL_PIN(167, "vISH_UART1_TXD"), 641 PINCTRL_PIN(168, "vISH_UART1_RXD"), 642 PINCTRL_PIN(169, "vISH_UART1_CTS_B"), 643 PINCTRL_PIN(170, "vISH_UART1_RTS_B"), 644 PINCTRL_PIN(171, "vCNV_BT_I2S_BCLK"), 645 PINCTRL_PIN(172, "vCNV_BT_I2S_WS_SYNC"), 646 PINCTRL_PIN(173, "vCNV_BT_I2S_SDO"), 647 PINCTRL_PIN(174, "vCNV_BT_I2S_SDI"), 648 PINCTRL_PIN(175, "vSSP2_SCLK"), 649 PINCTRL_PIN(176, "vSSP2_SFRM"), 650 PINCTRL_PIN(177, "vSSP2_TXD"), 651 PINCTRL_PIN(178, "vSSP2_RXD"), 652 PINCTRL_PIN(179, "vCNV_GNSS_HOST_WAKEB"), 653 PINCTRL_PIN(180, "vSD3_CD_B"), 654 /* GPP_C */ 655 PINCTRL_PIN(181, "SMBCLK"), 656 PINCTRL_PIN(182, "SMBDATA"), 657 PINCTRL_PIN(183, "SMBALERTB"), 658 PINCTRL_PIN(184, "SML0CLK"), 659 PINCTRL_PIN(185, "SML0DATA"), 660 PINCTRL_PIN(186, "SML0ALERTB"), 661 PINCTRL_PIN(187, "SML1CLK"), 662 PINCTRL_PIN(188, "SML1DATA"), 663 PINCTRL_PIN(189, "UART0_RXD"), 664 PINCTRL_PIN(190, "UART0_TXD"), 665 PINCTRL_PIN(191, "UART0_RTSB"), 666 PINCTRL_PIN(192, "UART0_CTSB"), 667 PINCTRL_PIN(193, "UART1_RXD"), 668 PINCTRL_PIN(194, "UART1_TXD"), 669 PINCTRL_PIN(195, "UART1_RTSB"), 670 PINCTRL_PIN(196, "UART1_CTSB"), 671 PINCTRL_PIN(197, "I2C0_SDA"), 672 PINCTRL_PIN(198, "I2C0_SCL"), 673 PINCTRL_PIN(199, "I2C1_SDA"), 674 PINCTRL_PIN(200, "I2C1_SCL"), 675 PINCTRL_PIN(201, "UART2_RXD"), 676 PINCTRL_PIN(202, "UART2_TXD"), 677 PINCTRL_PIN(203, "UART2_RTSB"), 678 PINCTRL_PIN(204, "UART2_CTSB"), 679 /* GPP_E */ 680 PINCTRL_PIN(205, "SATAXPCIE_0"), 681 PINCTRL_PIN(206, "SATAXPCIE_1"), 682 PINCTRL_PIN(207, "SATAXPCIE_2"), 683 PINCTRL_PIN(208, "CPU_GP_0"), 684 PINCTRL_PIN(209, "SATA_DEVSLP_0"), 685 PINCTRL_PIN(210, "SATA_DEVSLP_1"), 686 PINCTRL_PIN(211, "SATA_DEVSLP_2"), 687 PINCTRL_PIN(212, "CPU_GP_1"), 688 PINCTRL_PIN(213, "SATA_LEDB"), 689 PINCTRL_PIN(214, "USB2_OCB_0"), 690 PINCTRL_PIN(215, "USB2_OCB_1"), 691 PINCTRL_PIN(216, "USB2_OCB_2"), 692 PINCTRL_PIN(217, "USB2_OCB_3"), 693 PINCTRL_PIN(218, "DDSP_HPD_0"), 694 PINCTRL_PIN(219, "DDSP_HPD_1"), 695 PINCTRL_PIN(220, "DDSP_HPD_2"), 696 PINCTRL_PIN(221, "DDSP_HPD_3"), 697 PINCTRL_PIN(222, "EDP_HPD"), 698 PINCTRL_PIN(223, "DDPB_CTRLCLK"), 699 PINCTRL_PIN(224, "DDPB_CTRLDATA"), 700 PINCTRL_PIN(225, "DDPC_CTRLCLK"), 701 PINCTRL_PIN(226, "DDPC_CTRLDATA"), 702 PINCTRL_PIN(227, "DDPD_CTRLCLK"), 703 PINCTRL_PIN(228, "DDPD_CTRLDATA"), 704 /* JTAG */ 705 PINCTRL_PIN(229, "JTAG_TDO"), 706 PINCTRL_PIN(230, "JTAGX"), 707 PINCTRL_PIN(231, "PRDYB"), 708 PINCTRL_PIN(232, "PREQB"), 709 PINCTRL_PIN(233, "CPU_TRSTB"), 710 PINCTRL_PIN(234, "JTAG_TDI"), 711 PINCTRL_PIN(235, "JTAG_TMS"), 712 PINCTRL_PIN(236, "JTAG_TCK"), 713 PINCTRL_PIN(237, "ITP_PMODE"), 714 /* HVCMOS */ 715 PINCTRL_PIN(238, "L_BKLTEN"), 716 PINCTRL_PIN(239, "L_BKLTCTL"), 717 PINCTRL_PIN(240, "L_VDDEN"), 718 PINCTRL_PIN(241, "SYS_PWROK"), 719 PINCTRL_PIN(242, "SYS_RESETB"), 720 PINCTRL_PIN(243, "MLK_RSTB"), 721 }; 722 723 static const unsigned int cnllp_spi0_pins[] = { 40, 41, 42, 43, 7 }; 724 static const unsigned int cnllp_spi0_modes[] = { 1, 1, 1, 1, 2 }; 725 static const unsigned int cnllp_spi1_pins[] = { 44, 45, 46, 47, 11 }; 726 static const unsigned int cnllp_spi1_modes[] = { 1, 1, 1, 1, 2 }; 727 static const unsigned int cnllp_spi2_pins[] = { 77, 78, 79, 80, 83 }; 728 static const unsigned int cnllp_spi2_modes[] = { 3, 3, 3, 3, 2 }; 729 730 static const unsigned int cnllp_i2c0_pins[] = { 197, 198 }; 731 static const unsigned int cnllp_i2c1_pins[] = { 199, 200 }; 732 static const unsigned int cnllp_i2c2_pins[] = { 121, 122 }; 733 static const unsigned int cnllp_i2c3_pins[] = { 123, 124 }; 734 static const unsigned int cnllp_i2c4_pins[] = { 125, 126 }; 735 static const unsigned int cnllp_i2c5_pins[] = { 127, 128 }; 736 737 static const unsigned int cnllp_uart0_pins[] = { 189, 190, 191, 192 }; 738 static const unsigned int cnllp_uart1_pins[] = { 193, 194, 195, 196 }; 739 static const unsigned int cnllp_uart2_pins[] = { 201, 202, 203, 204 }; 740 741 static const struct intel_pingroup cnllp_groups[] = { 742 PIN_GROUP("spi0_grp", cnllp_spi0_pins, cnllp_spi0_modes), 743 PIN_GROUP("spi1_grp", cnllp_spi1_pins, cnllp_spi1_modes), 744 PIN_GROUP("spi2_grp", cnllp_spi2_pins, cnllp_spi2_modes), 745 PIN_GROUP("i2c0_grp", cnllp_i2c0_pins, 1), 746 PIN_GROUP("i2c1_grp", cnllp_i2c1_pins, 1), 747 PIN_GROUP("i2c2_grp", cnllp_i2c2_pins, 1), 748 PIN_GROUP("i2c3_grp", cnllp_i2c3_pins, 1), 749 PIN_GROUP("i2c4_grp", cnllp_i2c4_pins, 1), 750 PIN_GROUP("i2c5_grp", cnllp_i2c5_pins, 1), 751 PIN_GROUP("uart0_grp", cnllp_uart0_pins, 1), 752 PIN_GROUP("uart1_grp", cnllp_uart1_pins, 1), 753 PIN_GROUP("uart2_grp", cnllp_uart2_pins, 1), 754 }; 755 756 static const char * const cnllp_spi0_groups[] = { "spi0_grp" }; 757 static const char * const cnllp_spi1_groups[] = { "spi1_grp" }; 758 static const char * const cnllp_spi2_groups[] = { "spi2_grp" }; 759 static const char * const cnllp_i2c0_groups[] = { "i2c0_grp" }; 760 static const char * const cnllp_i2c1_groups[] = { "i2c1_grp" }; 761 static const char * const cnllp_i2c2_groups[] = { "i2c2_grp" }; 762 static const char * const cnllp_i2c3_groups[] = { "i2c3_grp" }; 763 static const char * const cnllp_i2c4_groups[] = { "i2c4_grp" }; 764 static const char * const cnllp_i2c5_groups[] = { "i2c5_grp" }; 765 static const char * const cnllp_uart0_groups[] = { "uart0_grp" }; 766 static const char * const cnllp_uart1_groups[] = { "uart1_grp" }; 767 static const char * const cnllp_uart2_groups[] = { "uart2_grp" }; 768 769 static const struct intel_function cnllp_functions[] = { 770 FUNCTION("spi0", cnllp_spi0_groups), 771 FUNCTION("spi1", cnllp_spi1_groups), 772 FUNCTION("spi2", cnllp_spi2_groups), 773 FUNCTION("i2c0", cnllp_i2c0_groups), 774 FUNCTION("i2c1", cnllp_i2c1_groups), 775 FUNCTION("i2c2", cnllp_i2c2_groups), 776 FUNCTION("i2c3", cnllp_i2c3_groups), 777 FUNCTION("i2c4", cnllp_i2c4_groups), 778 FUNCTION("i2c5", cnllp_i2c5_groups), 779 FUNCTION("uart0", cnllp_uart0_groups), 780 FUNCTION("uart1", cnllp_uart1_groups), 781 FUNCTION("uart2", cnllp_uart2_groups), 782 }; 783 784 static const struct intel_padgroup cnllp_community0_gpps[] = { 785 CNL_GPP(0, 0, 24, 0), /* GPP_A */ 786 CNL_GPP(1, 25, 50, 32), /* GPP_B */ 787 CNL_GPP(2, 51, 58, 64), /* GPP_G */ 788 CNL_GPP(3, 59, 67, CNL_NO_GPIO), /* SPI */ 789 }; 790 791 static const struct intel_padgroup cnllp_community1_gpps[] = { 792 CNL_GPP(0, 68, 92, 96), /* GPP_D */ 793 CNL_GPP(1, 93, 116, 128), /* GPP_F */ 794 CNL_GPP(2, 117, 140, 160), /* GPP_H */ 795 CNL_GPP(3, 141, 172, 192), /* vGPIO */ 796 CNL_GPP(4, 173, 180, 224), /* vGPIO */ 797 }; 798 799 static const struct intel_padgroup cnllp_community4_gpps[] = { 800 CNL_GPP(0, 181, 204, 256), /* GPP_C */ 801 CNL_GPP(1, 205, 228, 288), /* GPP_E */ 802 CNL_GPP(2, 229, 237, CNL_NO_GPIO), /* JTAG */ 803 CNL_GPP(3, 238, 243, CNL_NO_GPIO), /* HVCMOS */ 804 }; 805 806 static const struct intel_community cnllp_communities[] = { 807 CNL_COMMUNITY(0, 0, 67, cnllp_community0_gpps), 808 CNL_COMMUNITY(1, 68, 180, cnllp_community1_gpps), 809 CNL_COMMUNITY(2, 181, 243, cnllp_community4_gpps), 810 }; 811 812 static const struct intel_pinctrl_soc_data cnllp_soc_data = { 813 .pins = cnllp_pins, 814 .npins = ARRAY_SIZE(cnllp_pins), 815 .groups = cnllp_groups, 816 .ngroups = ARRAY_SIZE(cnllp_groups), 817 .functions = cnllp_functions, 818 .nfunctions = ARRAY_SIZE(cnllp_functions), 819 .communities = cnllp_communities, 820 .ncommunities = ARRAY_SIZE(cnllp_communities), 821 }; 822 823 static const struct acpi_device_id cnl_pinctrl_acpi_match[] = { 824 { "INT3450", (kernel_ulong_t)&cnlh_soc_data }, 825 { "INT34BB", (kernel_ulong_t)&cnllp_soc_data }, 826 { }, 827 }; 828 MODULE_DEVICE_TABLE(acpi, cnl_pinctrl_acpi_match); 829 830 static int cnl_pinctrl_probe(struct platform_device *pdev) 831 { 832 return intel_pinctrl_probe_by_hid(pdev); 833 } 834 835 static const struct dev_pm_ops cnl_pinctrl_pm_ops = { 836 SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend, 837 intel_pinctrl_resume) 838 }; 839 840 static struct platform_driver cnl_pinctrl_driver = { 841 .probe = cnl_pinctrl_probe, 842 .driver = { 843 .name = "cannonlake-pinctrl", 844 .acpi_match_table = cnl_pinctrl_acpi_match, 845 .pm = &cnl_pinctrl_pm_ops, 846 }, 847 }; 848 849 module_platform_driver(cnl_pinctrl_driver); 850 851 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 852 MODULE_DESCRIPTION("Intel Cannon Lake PCH pinctrl/GPIO driver"); 853 MODULE_LICENSE("GPL v2"); 854