1 /* 2 * Intel Cannon Lake PCH pinctrl/GPIO driver 3 * 4 * Copyright (C) 2017, Intel Corporation 5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/acpi.h> 13 #include <linux/module.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm.h> 16 #include <linux/pinctrl/pinctrl.h> 17 18 #include "pinctrl-intel.h" 19 20 #define CNL_PAD_OWN 0x020 21 #define CNL_PADCFGLOCK 0x080 22 #define CNL_HOSTSW_OWN 0x0b0 23 #define CNL_GPI_IE 0x120 24 25 #define CNL_GPP(r, s, e) \ 26 { \ 27 .reg_num = (r), \ 28 .base = (s), \ 29 .size = ((e) - (s) + 1), \ 30 } 31 32 #define CNL_COMMUNITY(b, s, e, g) \ 33 { \ 34 .barno = (b), \ 35 .padown_offset = CNL_PAD_OWN, \ 36 .padcfglock_offset = CNL_PADCFGLOCK, \ 37 .hostown_offset = CNL_HOSTSW_OWN, \ 38 .ie_offset = CNL_GPI_IE, \ 39 .pin_base = (s), \ 40 .npins = ((e) - (s) + 1), \ 41 .gpps = (g), \ 42 .ngpps = ARRAY_SIZE(g), \ 43 } 44 45 /* Cannon Lake-LP */ 46 static const struct pinctrl_pin_desc cnllp_pins[] = { 47 /* GPP_A */ 48 PINCTRL_PIN(0, "RCINB"), 49 PINCTRL_PIN(1, "LAD_0"), 50 PINCTRL_PIN(2, "LAD_1"), 51 PINCTRL_PIN(3, "LAD_2"), 52 PINCTRL_PIN(4, "LAD_3"), 53 PINCTRL_PIN(5, "LFRAMEB"), 54 PINCTRL_PIN(6, "SERIRQ"), 55 PINCTRL_PIN(7, "PIRQAB"), 56 PINCTRL_PIN(8, "CLKRUNB"), 57 PINCTRL_PIN(9, "CLKOUT_LPC_0"), 58 PINCTRL_PIN(10, "CLKOUT_LPC_1"), 59 PINCTRL_PIN(11, "PMEB"), 60 PINCTRL_PIN(12, "BM_BUSYB"), 61 PINCTRL_PIN(13, "SUSWARNB_SUSPWRDNACK"), 62 PINCTRL_PIN(14, "SUS_STATB"), 63 PINCTRL_PIN(15, "SUSACKB"), 64 PINCTRL_PIN(16, "SD_1P8_SEL"), 65 PINCTRL_PIN(17, "SD_PWR_EN_B"), 66 PINCTRL_PIN(18, "ISH_GP_0"), 67 PINCTRL_PIN(19, "ISH_GP_1"), 68 PINCTRL_PIN(20, "ISH_GP_2"), 69 PINCTRL_PIN(21, "ISH_GP_3"), 70 PINCTRL_PIN(22, "ISH_GP_4"), 71 PINCTRL_PIN(23, "ISH_GP_5"), 72 PINCTRL_PIN(24, "ESPI_CLK_LOOPBK"), 73 /* GPP_B */ 74 PINCTRL_PIN(25, "CORE_VID_0"), 75 PINCTRL_PIN(26, "CORE_VID_1"), 76 PINCTRL_PIN(27, "VRALERTB"), 77 PINCTRL_PIN(28, "CPU_GP_2"), 78 PINCTRL_PIN(29, "CPU_GP_3"), 79 PINCTRL_PIN(30, "SRCCLKREQB_0"), 80 PINCTRL_PIN(31, "SRCCLKREQB_1"), 81 PINCTRL_PIN(32, "SRCCLKREQB_2"), 82 PINCTRL_PIN(33, "SRCCLKREQB_3"), 83 PINCTRL_PIN(34, "SRCCLKREQB_4"), 84 PINCTRL_PIN(35, "SRCCLKREQB_5"), 85 PINCTRL_PIN(36, "EXT_PWR_GATEB"), 86 PINCTRL_PIN(37, "SLP_S0B"), 87 PINCTRL_PIN(38, "PLTRSTB"), 88 PINCTRL_PIN(39, "SPKR"), 89 PINCTRL_PIN(40, "GSPI0_CS0B"), 90 PINCTRL_PIN(41, "GSPI0_CLK"), 91 PINCTRL_PIN(42, "GSPI0_MISO"), 92 PINCTRL_PIN(43, "GSPI0_MOSI"), 93 PINCTRL_PIN(44, "GSPI1_CS0B"), 94 PINCTRL_PIN(45, "GSPI1_CLK"), 95 PINCTRL_PIN(46, "GSPI1_MISO"), 96 PINCTRL_PIN(47, "GSPI1_MOSI"), 97 PINCTRL_PIN(48, "SML1ALERTB"), 98 PINCTRL_PIN(49, "GSPI0_CLK_LOOPBK"), 99 PINCTRL_PIN(50, "GSPI1_CLK_LOOPBK"), 100 /* GPP_G */ 101 PINCTRL_PIN(51, "SD3_CMD"), 102 PINCTRL_PIN(52, "SD3_D0_SD4_RCLK_P"), 103 PINCTRL_PIN(53, "SD3_D1_SD4_RCLK_N"), 104 PINCTRL_PIN(54, "SD3_D2"), 105 PINCTRL_PIN(55, "SD3_D3"), 106 PINCTRL_PIN(56, "SD3_CDB"), 107 PINCTRL_PIN(57, "SD3_CLK"), 108 PINCTRL_PIN(58, "SD3_WP"), 109 /* SPI */ 110 PINCTRL_PIN(59, "SPI0_IO_2"), 111 PINCTRL_PIN(60, "SPI0_IO_3"), 112 PINCTRL_PIN(61, "SPI0_MOSI_IO_0"), 113 PINCTRL_PIN(62, "SPI0_MISO_IO_1"), 114 PINCTRL_PIN(63, "SPI0_TPM_CSB"), 115 PINCTRL_PIN(64, "SPI0_FLASH_0_CSB"), 116 PINCTRL_PIN(65, "SPI0_FLASH_1_CSB"), 117 PINCTRL_PIN(66, "SPI0_CLK"), 118 PINCTRL_PIN(67, "SPI0_CLK_LOOPBK"), 119 /* GPP_D */ 120 PINCTRL_PIN(68, "SPI1_CSB"), 121 PINCTRL_PIN(69, "SPI1_CLK"), 122 PINCTRL_PIN(70, "SPI1_MISO_IO_1"), 123 PINCTRL_PIN(71, "SPI1_MOSI_IO_0"), 124 PINCTRL_PIN(72, "IMGCLKOUT_0"), 125 PINCTRL_PIN(73, "ISH_I2C0_SDA"), 126 PINCTRL_PIN(74, "ISH_I2C0_SCL"), 127 PINCTRL_PIN(75, "ISH_I2C1_SDA"), 128 PINCTRL_PIN(76, "ISH_I2C1_SCL"), 129 PINCTRL_PIN(77, "ISH_SPI_CSB"), 130 PINCTRL_PIN(78, "ISH_SPI_CLK"), 131 PINCTRL_PIN(79, "ISH_SPI_MISO"), 132 PINCTRL_PIN(80, "ISH_SPI_MOSI"), 133 PINCTRL_PIN(81, "ISH_UART0_RXD"), 134 PINCTRL_PIN(82, "ISH_UART0_TXD"), 135 PINCTRL_PIN(83, "ISH_UART0_RTSB"), 136 PINCTRL_PIN(84, "ISH_UART0_CTSB"), 137 PINCTRL_PIN(85, "DMIC_CLK_1"), 138 PINCTRL_PIN(86, "DMIC_DATA_1"), 139 PINCTRL_PIN(87, "DMIC_CLK_0"), 140 PINCTRL_PIN(88, "DMIC_DATA_0"), 141 PINCTRL_PIN(89, "SPI1_IO_2"), 142 PINCTRL_PIN(90, "SPI1_IO_3"), 143 PINCTRL_PIN(91, "SSP_MCLK"), 144 PINCTRL_PIN(92, "GSPI2_CLK_LOOPBK"), 145 /* GPP_F */ 146 PINCTRL_PIN(93, "CNV_GNSS_PA_BLANKING"), 147 PINCTRL_PIN(94, "CNV_GNSS_FTA"), 148 PINCTRL_PIN(95, "CNV_GNSS_SYSCK"), 149 PINCTRL_PIN(96, "EMMC_HIP_MON"), 150 PINCTRL_PIN(97, "CNV_BRI_DT"), 151 PINCTRL_PIN(98, "CNV_BRI_RSP"), 152 PINCTRL_PIN(99, "CNV_RGI_DT"), 153 PINCTRL_PIN(100, "CNV_RGI_RSP"), 154 PINCTRL_PIN(101, "CNV_MFUART2_RXD"), 155 PINCTRL_PIN(102, "CNV_MFUART2_TXD"), 156 PINCTRL_PIN(103, "GPP_F_10"), 157 PINCTRL_PIN(104, "EMMC_CMD"), 158 PINCTRL_PIN(105, "EMMC_DATA_0"), 159 PINCTRL_PIN(106, "EMMC_DATA_1"), 160 PINCTRL_PIN(107, "EMMC_DATA_2"), 161 PINCTRL_PIN(108, "EMMC_DATA_3"), 162 PINCTRL_PIN(109, "EMMC_DATA_4"), 163 PINCTRL_PIN(110, "EMMC_DATA_5"), 164 PINCTRL_PIN(111, "EMMC_DATA_6"), 165 PINCTRL_PIN(112, "EMMC_DATA_7"), 166 PINCTRL_PIN(113, "EMMC_RCLK"), 167 PINCTRL_PIN(114, "EMMC_CLK"), 168 PINCTRL_PIN(115, "EMMC_RESETB"), 169 PINCTRL_PIN(116, "A4WP_PRESENT"), 170 /* GPP_H */ 171 PINCTRL_PIN(117, "SSP2_SCLK"), 172 PINCTRL_PIN(118, "SSP2_SFRM"), 173 PINCTRL_PIN(119, "SSP2_TXD"), 174 PINCTRL_PIN(120, "SSP2_RXD"), 175 PINCTRL_PIN(121, "I2C2_SDA"), 176 PINCTRL_PIN(122, "I2C2_SCL"), 177 PINCTRL_PIN(123, "I2C3_SDA"), 178 PINCTRL_PIN(124, "I2C3_SCL"), 179 PINCTRL_PIN(125, "I2C4_SDA"), 180 PINCTRL_PIN(126, "I2C4_SCL"), 181 PINCTRL_PIN(127, "I2C5_SDA"), 182 PINCTRL_PIN(128, "I2C5_SCL"), 183 PINCTRL_PIN(129, "M2_SKT2_CFG_0"), 184 PINCTRL_PIN(130, "M2_SKT2_CFG_1"), 185 PINCTRL_PIN(131, "M2_SKT2_CFG_2"), 186 PINCTRL_PIN(132, "M2_SKT2_CFG_3"), 187 PINCTRL_PIN(133, "DDPF_CTRLCLK"), 188 PINCTRL_PIN(134, "DDPF_CTRLDATA"), 189 PINCTRL_PIN(135, "CPU_VCCIO_PWR_GATEB"), 190 PINCTRL_PIN(136, "TIMESYNC_0"), 191 PINCTRL_PIN(137, "IMGCLKOUT_1"), 192 PINCTRL_PIN(138, "GPPC_H_21"), 193 PINCTRL_PIN(139, "GPPC_H_22"), 194 PINCTRL_PIN(140, "GPPC_H_23"), 195 /* vGPIO */ 196 PINCTRL_PIN(141, "CNV_BTEN"), 197 PINCTRL_PIN(142, "CNV_GNEN"), 198 PINCTRL_PIN(143, "CNV_WFEN"), 199 PINCTRL_PIN(144, "CNV_WCEN"), 200 PINCTRL_PIN(145, "CNV_BT_HOST_WAKEB"), 201 PINCTRL_PIN(146, "CNV_BT_IF_SELECT"), 202 PINCTRL_PIN(147, "vCNV_BT_UART_TXD"), 203 PINCTRL_PIN(148, "vCNV_BT_UART_RXD"), 204 PINCTRL_PIN(149, "vCNV_BT_UART_CTS_B"), 205 PINCTRL_PIN(150, "vCNV_BT_UART_RTS_B"), 206 PINCTRL_PIN(151, "vCNV_MFUART1_TXD"), 207 PINCTRL_PIN(152, "vCNV_MFUART1_RXD"), 208 PINCTRL_PIN(153, "vCNV_MFUART1_CTS_B"), 209 PINCTRL_PIN(154, "vCNV_MFUART1_RTS_B"), 210 PINCTRL_PIN(155, "vCNV_GNSS_UART_TXD"), 211 PINCTRL_PIN(156, "vCNV_GNSS_UART_RXD"), 212 PINCTRL_PIN(157, "vCNV_GNSS_UART_CTS_B"), 213 PINCTRL_PIN(158, "vCNV_GNSS_UART_RTS_B"), 214 PINCTRL_PIN(159, "vUART0_TXD"), 215 PINCTRL_PIN(160, "vUART0_RXD"), 216 PINCTRL_PIN(161, "vUART0_CTS_B"), 217 PINCTRL_PIN(162, "vUART0_RTS_B"), 218 PINCTRL_PIN(163, "vISH_UART0_TXD"), 219 PINCTRL_PIN(164, "vISH_UART0_RXD"), 220 PINCTRL_PIN(165, "vISH_UART0_CTS_B"), 221 PINCTRL_PIN(166, "vISH_UART0_RTS_B"), 222 PINCTRL_PIN(167, "vISH_UART1_TXD"), 223 PINCTRL_PIN(168, "vISH_UART1_RXD"), 224 PINCTRL_PIN(169, "vISH_UART1_CTS_B"), 225 PINCTRL_PIN(170, "vISH_UART1_RTS_B"), 226 PINCTRL_PIN(171, "vCNV_BT_I2S_BCLK"), 227 PINCTRL_PIN(172, "vCNV_BT_I2S_WS_SYNC"), 228 PINCTRL_PIN(173, "vCNV_BT_I2S_SDO"), 229 PINCTRL_PIN(174, "vCNV_BT_I2S_SDI"), 230 PINCTRL_PIN(175, "vSSP2_SCLK"), 231 PINCTRL_PIN(176, "vSSP2_SFRM"), 232 PINCTRL_PIN(177, "vSSP2_TXD"), 233 PINCTRL_PIN(178, "vSSP2_RXD"), 234 PINCTRL_PIN(179, "vCNV_GNSS_HOST_WAKEB"), 235 PINCTRL_PIN(180, "vSD3_CD_B"), 236 /* GPP_C */ 237 PINCTRL_PIN(181, "SMBCLK"), 238 PINCTRL_PIN(182, "SMBDATA"), 239 PINCTRL_PIN(183, "SMBALERTB"), 240 PINCTRL_PIN(184, "SML0CLK"), 241 PINCTRL_PIN(185, "SML0DATA"), 242 PINCTRL_PIN(186, "SML0ALERTB"), 243 PINCTRL_PIN(187, "SML1CLK"), 244 PINCTRL_PIN(188, "SML1DATA"), 245 PINCTRL_PIN(189, "UART0_RXD"), 246 PINCTRL_PIN(190, "UART0_TXD"), 247 PINCTRL_PIN(191, "UART0_RTSB"), 248 PINCTRL_PIN(192, "UART0_CTSB"), 249 PINCTRL_PIN(193, "UART1_RXD"), 250 PINCTRL_PIN(194, "UART1_TXD"), 251 PINCTRL_PIN(195, "UART1_RTSB"), 252 PINCTRL_PIN(196, "UART1_CTSB"), 253 PINCTRL_PIN(197, "I2C0_SDA"), 254 PINCTRL_PIN(198, "I2C0_SCL"), 255 PINCTRL_PIN(199, "I2C1_SDA"), 256 PINCTRL_PIN(200, "I2C1_SCL"), 257 PINCTRL_PIN(201, "UART2_RXD"), 258 PINCTRL_PIN(202, "UART2_TXD"), 259 PINCTRL_PIN(203, "UART2_RTSB"), 260 PINCTRL_PIN(204, "UART2_CTSB"), 261 /* GPP_E */ 262 PINCTRL_PIN(205, "SATAXPCIE_0"), 263 PINCTRL_PIN(206, "SATAXPCIE_1"), 264 PINCTRL_PIN(207, "SATAXPCIE_2"), 265 PINCTRL_PIN(208, "CPU_GP_0"), 266 PINCTRL_PIN(209, "SATA_DEVSLP_0"), 267 PINCTRL_PIN(210, "SATA_DEVSLP_1"), 268 PINCTRL_PIN(211, "SATA_DEVSLP_2"), 269 PINCTRL_PIN(212, "CPU_GP_1"), 270 PINCTRL_PIN(213, "SATA_LEDB"), 271 PINCTRL_PIN(214, "USB2_OCB_0"), 272 PINCTRL_PIN(215, "USB2_OCB_1"), 273 PINCTRL_PIN(216, "USB2_OCB_2"), 274 PINCTRL_PIN(217, "USB2_OCB_3"), 275 PINCTRL_PIN(218, "DDSP_HPD_0"), 276 PINCTRL_PIN(219, "DDSP_HPD_1"), 277 PINCTRL_PIN(220, "DDSP_HPD_2"), 278 PINCTRL_PIN(221, "DDSP_HPD_3"), 279 PINCTRL_PIN(222, "EDP_HPD"), 280 PINCTRL_PIN(223, "DDPB_CTRLCLK"), 281 PINCTRL_PIN(224, "DDPB_CTRLDATA"), 282 PINCTRL_PIN(225, "DDPC_CTRLCLK"), 283 PINCTRL_PIN(226, "DDPC_CTRLDATA"), 284 PINCTRL_PIN(227, "DDPD_CTRLCLK"), 285 PINCTRL_PIN(228, "DDPD_CTRLDATA"), 286 /* JTAG */ 287 PINCTRL_PIN(229, "JTAG_TDO"), 288 PINCTRL_PIN(230, "JTAGX"), 289 PINCTRL_PIN(231, "PRDYB"), 290 PINCTRL_PIN(232, "PREQB"), 291 PINCTRL_PIN(233, "CPU_TRSTB"), 292 PINCTRL_PIN(234, "JTAG_TDI"), 293 PINCTRL_PIN(235, "JTAG_TMS"), 294 PINCTRL_PIN(236, "JTAG_TCK"), 295 PINCTRL_PIN(237, "ITP_PMODE"), 296 /* HVCMOS */ 297 PINCTRL_PIN(238, "L_BKLTEN"), 298 PINCTRL_PIN(239, "L_BKLTCTL"), 299 PINCTRL_PIN(240, "L_VDDEN"), 300 PINCTRL_PIN(241, "SYS_PWROK"), 301 PINCTRL_PIN(242, "SYS_RESETB"), 302 PINCTRL_PIN(243, "MLK_RSTB"), 303 }; 304 305 static const unsigned int cnllp_spi0_pins[] = { 40, 41, 42, 43, 7 }; 306 static const unsigned int cnllp_spi0_modes[] = { 1, 1, 1, 1, 2 }; 307 static const unsigned int cnllp_spi1_pins[] = { 44, 45, 46, 47, 11 }; 308 static const unsigned int cnllp_spi1_modes[] = { 1, 1, 1, 1, 2 }; 309 static const unsigned int cnllp_spi2_pins[] = { 77, 78, 79, 80, 83 }; 310 static const unsigned int cnllp_spi2_modes[] = { 3, 3, 3, 3, 2 }; 311 312 static const unsigned int cnllp_i2c0_pins[] = { 197, 198 }; 313 static const unsigned int cnllp_i2c1_pins[] = { 199, 200 }; 314 static const unsigned int cnllp_i2c2_pins[] = { 121, 122 }; 315 static const unsigned int cnllp_i2c3_pins[] = { 123, 124 }; 316 static const unsigned int cnllp_i2c4_pins[] = { 125, 126 }; 317 static const unsigned int cnllp_i2c5_pins[] = { 127, 128 }; 318 319 static const unsigned int cnllp_uart0_pins[] = { 189, 190, 191, 192 }; 320 static const unsigned int cnllp_uart1_pins[] = { 193, 194, 195, 196 }; 321 static const unsigned int cnllp_uart2_pins[] = { 201, 202, 203, 204 }; 322 323 static const struct intel_pingroup cnllp_groups[] = { 324 PIN_GROUP("spi0_grp", cnllp_spi0_pins, cnllp_spi0_modes), 325 PIN_GROUP("spi1_grp", cnllp_spi1_pins, cnllp_spi1_modes), 326 PIN_GROUP("spi2_grp", cnllp_spi2_pins, cnllp_spi2_modes), 327 PIN_GROUP("i2c0_grp", cnllp_i2c0_pins, 1), 328 PIN_GROUP("i2c1_grp", cnllp_i2c1_pins, 1), 329 PIN_GROUP("i2c2_grp", cnllp_i2c2_pins, 1), 330 PIN_GROUP("i2c3_grp", cnllp_i2c3_pins, 1), 331 PIN_GROUP("i2c4_grp", cnllp_i2c4_pins, 1), 332 PIN_GROUP("i2c5_grp", cnllp_i2c5_pins, 1), 333 PIN_GROUP("uart0_grp", cnllp_uart0_pins, 1), 334 PIN_GROUP("uart1_grp", cnllp_uart1_pins, 1), 335 PIN_GROUP("uart2_grp", cnllp_uart2_pins, 1), 336 }; 337 338 static const char * const cnllp_spi0_groups[] = { "spi0_grp" }; 339 static const char * const cnllp_spi1_groups[] = { "spi1_grp" }; 340 static const char * const cnllp_spi2_groups[] = { "spi2_grp" }; 341 static const char * const cnllp_i2c0_groups[] = { "i2c0_grp" }; 342 static const char * const cnllp_i2c1_groups[] = { "i2c1_grp" }; 343 static const char * const cnllp_i2c2_groups[] = { "i2c2_grp" }; 344 static const char * const cnllp_i2c3_groups[] = { "i2c3_grp" }; 345 static const char * const cnllp_i2c4_groups[] = { "i2c4_grp" }; 346 static const char * const cnllp_i2c5_groups[] = { "i2c5_grp" }; 347 static const char * const cnllp_uart0_groups[] = { "uart0_grp" }; 348 static const char * const cnllp_uart1_groups[] = { "uart1_grp" }; 349 static const char * const cnllp_uart2_groups[] = { "uart2_grp" }; 350 351 static const struct intel_function cnllp_functions[] = { 352 FUNCTION("spi0", cnllp_spi0_groups), 353 FUNCTION("spi1", cnllp_spi1_groups), 354 FUNCTION("spi2", cnllp_spi2_groups), 355 FUNCTION("i2c0", cnllp_i2c0_groups), 356 FUNCTION("i2c1", cnllp_i2c1_groups), 357 FUNCTION("i2c2", cnllp_i2c2_groups), 358 FUNCTION("i2c3", cnllp_i2c3_groups), 359 FUNCTION("i2c4", cnllp_i2c4_groups), 360 FUNCTION("i2c5", cnllp_i2c5_groups), 361 FUNCTION("uart0", cnllp_uart0_groups), 362 FUNCTION("uart1", cnllp_uart1_groups), 363 FUNCTION("uart2", cnllp_uart2_groups), 364 }; 365 366 static const struct intel_padgroup cnllp_community0_gpps[] = { 367 CNL_GPP(0, 0, 24), /* GPP_A */ 368 CNL_GPP(1, 25, 50), /* GPP_B */ 369 CNL_GPP(2, 51, 58), /* GPP_G */ 370 CNL_GPP(3, 59, 67), /* SPI */ 371 }; 372 373 static const struct intel_padgroup cnllp_community1_gpps[] = { 374 CNL_GPP(0, 68, 92), /* GPP_D */ 375 CNL_GPP(1, 93, 116), /* GPP_F */ 376 CNL_GPP(2, 117, 140), /* GPP_H */ 377 CNL_GPP(3, 141, 172), /* vGPIO */ 378 CNL_GPP(4, 173, 180), /* vGPIO */ 379 }; 380 381 static const struct intel_padgroup cnllp_community4_gpps[] = { 382 CNL_GPP(0, 181, 204), /* GPP_C */ 383 CNL_GPP(1, 205, 228), /* GPP_E */ 384 CNL_GPP(2, 229, 237), /* JTAG */ 385 CNL_GPP(3, 238, 243), /* HVCMOS */ 386 }; 387 388 static const struct intel_community cnllp_communities[] = { 389 CNL_COMMUNITY(0, 0, 67, cnllp_community0_gpps), 390 CNL_COMMUNITY(1, 68, 180, cnllp_community1_gpps), 391 CNL_COMMUNITY(2, 181, 243, cnllp_community4_gpps), 392 }; 393 394 static const struct intel_pinctrl_soc_data cnllp_soc_data = { 395 .pins = cnllp_pins, 396 .npins = ARRAY_SIZE(cnllp_pins), 397 .groups = cnllp_groups, 398 .ngroups = ARRAY_SIZE(cnllp_groups), 399 .functions = cnllp_functions, 400 .nfunctions = ARRAY_SIZE(cnllp_functions), 401 .communities = cnllp_communities, 402 .ncommunities = ARRAY_SIZE(cnllp_communities), 403 }; 404 405 static const struct acpi_device_id cnl_pinctrl_acpi_match[] = { 406 { "INT34BB", (kernel_ulong_t)&cnllp_soc_data }, 407 { }, 408 }; 409 MODULE_DEVICE_TABLE(acpi, cnl_pinctrl_acpi_match); 410 411 static int cnl_pinctrl_probe(struct platform_device *pdev) 412 { 413 const struct intel_pinctrl_soc_data *soc_data; 414 const struct acpi_device_id *id; 415 416 id = acpi_match_device(cnl_pinctrl_acpi_match, &pdev->dev); 417 if (!id || !id->driver_data) 418 return -ENODEV; 419 420 soc_data = (const struct intel_pinctrl_soc_data *)id->driver_data; 421 return intel_pinctrl_probe(pdev, soc_data); 422 } 423 424 static const struct dev_pm_ops cnl_pinctrl_pm_ops = { 425 SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend, 426 intel_pinctrl_resume) 427 }; 428 429 static struct platform_driver cnl_pinctrl_driver = { 430 .probe = cnl_pinctrl_probe, 431 .driver = { 432 .name = "cannonlake-pinctrl", 433 .acpi_match_table = cnl_pinctrl_acpi_match, 434 .pm = &cnl_pinctrl_pm_ops, 435 }, 436 }; 437 438 module_platform_driver(cnl_pinctrl_driver); 439 440 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 441 MODULE_DESCRIPTION("Intel Cannon Lake PCH pinctrl/GPIO driver"); 442 MODULE_LICENSE("GPL v2"); 443