1 /* 2 * Pinctrl GPIO driver for Intel Baytrail 3 * Copyright (c) 2012-2013, Intel Corporation. 4 * 5 * Author: Mathias Nyman <mathias.nyman@linux.intel.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program; if not, write to the Free Software Foundation, Inc., 18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 */ 21 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/init.h> 25 #include <linux/types.h> 26 #include <linux/bitops.h> 27 #include <linux/interrupt.h> 28 #include <linux/gpio.h> 29 #include <linux/acpi.h> 30 #include <linux/platform_device.h> 31 #include <linux/seq_file.h> 32 #include <linux/io.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/pinctrl/pinctrl.h> 35 36 /* memory mapped register offsets */ 37 #define BYT_CONF0_REG 0x000 38 #define BYT_CONF1_REG 0x004 39 #define BYT_VAL_REG 0x008 40 #define BYT_DFT_REG 0x00c 41 #define BYT_INT_STAT_REG 0x800 42 43 /* BYT_CONF0_REG register bits */ 44 #define BYT_IODEN BIT(31) 45 #define BYT_DIRECT_IRQ_EN BIT(27) 46 #define BYT_TRIG_NEG BIT(26) 47 #define BYT_TRIG_POS BIT(25) 48 #define BYT_TRIG_LVL BIT(24) 49 #define BYT_PULL_STR_SHIFT 9 50 #define BYT_PULL_STR_MASK (3 << BYT_PULL_STR_SHIFT) 51 #define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT) 52 #define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT) 53 #define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT) 54 #define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT) 55 #define BYT_PULL_ASSIGN_SHIFT 7 56 #define BYT_PULL_ASSIGN_MASK (3 << BYT_PULL_ASSIGN_SHIFT) 57 #define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT) 58 #define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT) 59 #define BYT_PIN_MUX 0x07 60 61 /* BYT_VAL_REG register bits */ 62 #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/ 63 #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/ 64 #define BYT_LEVEL BIT(0) 65 66 #define BYT_DIR_MASK (BIT(1) | BIT(2)) 67 #define BYT_TRIG_MASK (BIT(26) | BIT(25) | BIT(24)) 68 69 #define BYT_CONF0_RESTORE_MASK (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | \ 70 BYT_PIN_MUX) 71 #define BYT_VAL_RESTORE_MASK (BYT_DIR_MASK | BYT_LEVEL) 72 73 #define BYT_NGPIO_SCORE 102 74 #define BYT_NGPIO_NCORE 28 75 #define BYT_NGPIO_SUS 44 76 77 #define BYT_SCORE_ACPI_UID "1" 78 #define BYT_NCORE_ACPI_UID "2" 79 #define BYT_SUS_ACPI_UID "3" 80 81 /* 82 * Baytrail gpio controller consist of three separate sub-controllers called 83 * SCORE, NCORE and SUS. The sub-controllers are identified by their acpi UID. 84 * 85 * GPIO numbering is _not_ ordered meaning that gpio # 0 in ACPI namespace does 86 * _not_ correspond to the first gpio register at controller's gpio base. 87 * There is no logic or pattern in mapping gpio numbers to registers (pads) so 88 * each sub-controller needs to have its own mapping table 89 */ 90 91 /* score_pins[gpio_nr] = pad_nr */ 92 93 static unsigned const score_pins[BYT_NGPIO_SCORE] = { 94 85, 89, 93, 96, 99, 102, 98, 101, 34, 37, 95 36, 38, 39, 35, 40, 84, 62, 61, 64, 59, 96 54, 56, 60, 55, 63, 57, 51, 50, 53, 47, 97 52, 49, 48, 43, 46, 41, 45, 42, 58, 44, 98 95, 105, 70, 68, 67, 66, 69, 71, 65, 72, 99 86, 90, 88, 92, 103, 77, 79, 83, 78, 81, 100 80, 82, 13, 12, 15, 14, 17, 18, 19, 16, 101 2, 1, 0, 4, 6, 7, 9, 8, 33, 32, 102 31, 30, 29, 27, 25, 28, 26, 23, 21, 20, 103 24, 22, 5, 3, 10, 11, 106, 87, 91, 104, 104 97, 100, 105 }; 106 107 static unsigned const ncore_pins[BYT_NGPIO_NCORE] = { 108 19, 18, 17, 20, 21, 22, 24, 25, 23, 16, 109 14, 15, 12, 26, 27, 1, 4, 8, 11, 0, 110 3, 6, 10, 13, 2, 5, 9, 7, 111 }; 112 113 static unsigned const sus_pins[BYT_NGPIO_SUS] = { 114 29, 33, 30, 31, 32, 34, 36, 35, 38, 37, 115 18, 7, 11, 20, 17, 1, 8, 10, 19, 12, 116 0, 2, 23, 39, 28, 27, 22, 21, 24, 25, 117 26, 51, 56, 54, 49, 55, 48, 57, 50, 58, 118 52, 53, 59, 40, 119 }; 120 121 static struct pinctrl_gpio_range byt_ranges[] = { 122 { 123 .name = BYT_SCORE_ACPI_UID, /* match with acpi _UID in probe */ 124 .npins = BYT_NGPIO_SCORE, 125 .pins = score_pins, 126 }, 127 { 128 .name = BYT_NCORE_ACPI_UID, 129 .npins = BYT_NGPIO_NCORE, 130 .pins = ncore_pins, 131 }, 132 { 133 .name = BYT_SUS_ACPI_UID, 134 .npins = BYT_NGPIO_SUS, 135 .pins = sus_pins, 136 }, 137 { 138 }, 139 }; 140 141 struct byt_gpio_pin_context { 142 u32 conf0; 143 u32 val; 144 }; 145 146 struct byt_gpio { 147 struct gpio_chip chip; 148 struct platform_device *pdev; 149 spinlock_t lock; 150 void __iomem *reg_base; 151 struct pinctrl_gpio_range *range; 152 struct byt_gpio_pin_context *saved_context; 153 }; 154 155 #define to_byt_gpio(c) container_of(c, struct byt_gpio, chip) 156 157 static void __iomem *byt_gpio_reg(struct gpio_chip *chip, unsigned offset, 158 int reg) 159 { 160 struct byt_gpio *vg = to_byt_gpio(chip); 161 u32 reg_offset; 162 163 if (reg == BYT_INT_STAT_REG) 164 reg_offset = (offset / 32) * 4; 165 else 166 reg_offset = vg->range->pins[offset] * 16; 167 168 return vg->reg_base + reg_offset + reg; 169 } 170 171 static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned offset) 172 { 173 void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG); 174 unsigned long flags; 175 u32 value; 176 177 spin_lock_irqsave(&vg->lock, flags); 178 value = readl(reg); 179 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL); 180 writel(value, reg); 181 spin_unlock_irqrestore(&vg->lock, flags); 182 } 183 184 static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned offset) 185 { 186 /* SCORE pin 92-93 */ 187 if (!strcmp(vg->range->name, BYT_SCORE_ACPI_UID) && 188 offset >= 92 && offset <= 93) 189 return 1; 190 191 /* SUS pin 11-21 */ 192 if (!strcmp(vg->range->name, BYT_SUS_ACPI_UID) && 193 offset >= 11 && offset <= 21) 194 return 1; 195 196 return 0; 197 } 198 199 static int byt_gpio_request(struct gpio_chip *chip, unsigned offset) 200 { 201 struct byt_gpio *vg = to_byt_gpio(chip); 202 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_CONF0_REG); 203 u32 value, gpio_mux; 204 205 /* 206 * In most cases, func pin mux 000 means GPIO function. 207 * But, some pins may have func pin mux 001 represents 208 * GPIO function. 209 * 210 * Because there are devices out there where some pins were not 211 * configured correctly we allow changing the mux value from 212 * request (but print out warning about that). 213 */ 214 value = readl(reg) & BYT_PIN_MUX; 215 gpio_mux = byt_get_gpio_mux(vg, offset); 216 if (WARN_ON(gpio_mux != value)) { 217 unsigned long flags; 218 219 spin_lock_irqsave(&vg->lock, flags); 220 value = readl(reg) & ~BYT_PIN_MUX; 221 value |= gpio_mux; 222 writel(value, reg); 223 spin_unlock_irqrestore(&vg->lock, flags); 224 225 dev_warn(&vg->pdev->dev, 226 "pin %u forcibly re-configured as GPIO\n", offset); 227 } 228 229 pm_runtime_get(&vg->pdev->dev); 230 231 return 0; 232 } 233 234 static void byt_gpio_free(struct gpio_chip *chip, unsigned offset) 235 { 236 struct byt_gpio *vg = to_byt_gpio(chip); 237 238 byt_gpio_clear_triggering(vg, offset); 239 pm_runtime_put(&vg->pdev->dev); 240 } 241 242 static int byt_irq_type(struct irq_data *d, unsigned type) 243 { 244 struct byt_gpio *vg = to_byt_gpio(irq_data_get_irq_chip_data(d)); 245 u32 offset = irqd_to_hwirq(d); 246 u32 value; 247 unsigned long flags; 248 void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG); 249 250 if (offset >= vg->chip.ngpio) 251 return -EINVAL; 252 253 spin_lock_irqsave(&vg->lock, flags); 254 value = readl(reg); 255 256 WARN(value & BYT_DIRECT_IRQ_EN, 257 "Bad pad config for io mode, force direct_irq_en bit clearing"); 258 259 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits 260 * are used to indicate high and low level triggering 261 */ 262 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG | 263 BYT_TRIG_LVL); 264 265 writel(value, reg); 266 267 if (type & IRQ_TYPE_EDGE_BOTH) 268 __irq_set_handler_locked(d->irq, handle_edge_irq); 269 else if (type & IRQ_TYPE_LEVEL_MASK) 270 __irq_set_handler_locked(d->irq, handle_level_irq); 271 272 spin_unlock_irqrestore(&vg->lock, flags); 273 274 return 0; 275 } 276 277 static int byt_gpio_get(struct gpio_chip *chip, unsigned offset) 278 { 279 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG); 280 return readl(reg) & BYT_LEVEL; 281 } 282 283 static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 284 { 285 struct byt_gpio *vg = to_byt_gpio(chip); 286 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG); 287 unsigned long flags; 288 u32 old_val; 289 290 spin_lock_irqsave(&vg->lock, flags); 291 292 old_val = readl(reg); 293 294 if (value) 295 writel(old_val | BYT_LEVEL, reg); 296 else 297 writel(old_val & ~BYT_LEVEL, reg); 298 299 spin_unlock_irqrestore(&vg->lock, flags); 300 } 301 302 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 303 { 304 struct byt_gpio *vg = to_byt_gpio(chip); 305 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG); 306 unsigned long flags; 307 u32 value; 308 309 spin_lock_irqsave(&vg->lock, flags); 310 311 value = readl(reg) | BYT_DIR_MASK; 312 value &= ~BYT_INPUT_EN; /* active low */ 313 writel(value, reg); 314 315 spin_unlock_irqrestore(&vg->lock, flags); 316 317 return 0; 318 } 319 320 static int byt_gpio_direction_output(struct gpio_chip *chip, 321 unsigned gpio, int value) 322 { 323 struct byt_gpio *vg = to_byt_gpio(chip); 324 void __iomem *conf_reg = byt_gpio_reg(chip, gpio, BYT_CONF0_REG); 325 void __iomem *reg = byt_gpio_reg(chip, gpio, BYT_VAL_REG); 326 unsigned long flags; 327 u32 reg_val; 328 329 spin_lock_irqsave(&vg->lock, flags); 330 331 /* 332 * Before making any direction modifications, do a check if gpio 333 * is set for direct IRQ. On baytrail, setting GPIO to output does 334 * not make sense, so let's at least warn the caller before they shoot 335 * themselves in the foot. 336 */ 337 WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN, 338 "Potential Error: Setting GPIO with direct_irq_en to output"); 339 340 reg_val = readl(reg) | BYT_DIR_MASK; 341 reg_val &= ~(BYT_OUTPUT_EN | BYT_INPUT_EN); 342 343 if (value) 344 writel(reg_val | BYT_LEVEL, reg); 345 else 346 writel(reg_val & ~BYT_LEVEL, reg); 347 348 spin_unlock_irqrestore(&vg->lock, flags); 349 350 return 0; 351 } 352 353 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 354 { 355 struct byt_gpio *vg = to_byt_gpio(chip); 356 int i; 357 unsigned long flags; 358 u32 conf0, val, offs; 359 360 spin_lock_irqsave(&vg->lock, flags); 361 362 for (i = 0; i < vg->chip.ngpio; i++) { 363 const char *pull_str = NULL; 364 const char *pull = NULL; 365 const char *label; 366 offs = vg->range->pins[i] * 16; 367 conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG); 368 val = readl(vg->reg_base + offs + BYT_VAL_REG); 369 370 label = gpiochip_is_requested(chip, i); 371 if (!label) 372 label = "Unrequested"; 373 374 switch (conf0 & BYT_PULL_ASSIGN_MASK) { 375 case BYT_PULL_ASSIGN_UP: 376 pull = "up"; 377 break; 378 case BYT_PULL_ASSIGN_DOWN: 379 pull = "down"; 380 break; 381 } 382 383 switch (conf0 & BYT_PULL_STR_MASK) { 384 case BYT_PULL_STR_2K: 385 pull_str = "2k"; 386 break; 387 case BYT_PULL_STR_10K: 388 pull_str = "10k"; 389 break; 390 case BYT_PULL_STR_20K: 391 pull_str = "20k"; 392 break; 393 case BYT_PULL_STR_40K: 394 pull_str = "40k"; 395 break; 396 } 397 398 seq_printf(s, 399 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s", 400 i, 401 label, 402 val & BYT_INPUT_EN ? " " : "in", 403 val & BYT_OUTPUT_EN ? " " : "out", 404 val & BYT_LEVEL ? "hi" : "lo", 405 vg->range->pins[i], offs, 406 conf0 & 0x7, 407 conf0 & BYT_TRIG_NEG ? " fall" : " ", 408 conf0 & BYT_TRIG_POS ? " rise" : " ", 409 conf0 & BYT_TRIG_LVL ? " level" : " "); 410 411 if (pull && pull_str) 412 seq_printf(s, " %-4s %-3s", pull, pull_str); 413 else 414 seq_puts(s, " "); 415 416 if (conf0 & BYT_IODEN) 417 seq_puts(s, " open-drain"); 418 419 seq_puts(s, "\n"); 420 } 421 spin_unlock_irqrestore(&vg->lock, flags); 422 } 423 424 static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc) 425 { 426 struct irq_data *data = irq_desc_get_irq_data(desc); 427 struct byt_gpio *vg = to_byt_gpio(irq_desc_get_handler_data(desc)); 428 struct irq_chip *chip = irq_data_get_irq_chip(data); 429 u32 base, pin; 430 void __iomem *reg; 431 unsigned long pending; 432 unsigned virq; 433 434 /* check from GPIO controller which pin triggered the interrupt */ 435 for (base = 0; base < vg->chip.ngpio; base += 32) { 436 reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG); 437 pending = readl(reg); 438 for_each_set_bit(pin, &pending, 32) { 439 virq = irq_find_mapping(vg->chip.irqdomain, base + pin); 440 generic_handle_irq(virq); 441 } 442 } 443 chip->irq_eoi(data); 444 } 445 446 static void byt_irq_ack(struct irq_data *d) 447 { 448 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 449 struct byt_gpio *vg = to_byt_gpio(gc); 450 unsigned offset = irqd_to_hwirq(d); 451 void __iomem *reg; 452 453 reg = byt_gpio_reg(&vg->chip, offset, BYT_INT_STAT_REG); 454 writel(BIT(offset % 32), reg); 455 } 456 457 static void byt_irq_unmask(struct irq_data *d) 458 { 459 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 460 struct byt_gpio *vg = to_byt_gpio(gc); 461 unsigned offset = irqd_to_hwirq(d); 462 unsigned long flags; 463 void __iomem *reg; 464 u32 value; 465 466 spin_lock_irqsave(&vg->lock, flags); 467 468 reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG); 469 value = readl(reg); 470 471 switch (irqd_get_trigger_type(d)) { 472 case IRQ_TYPE_LEVEL_HIGH: 473 value |= BYT_TRIG_LVL; 474 case IRQ_TYPE_EDGE_RISING: 475 value |= BYT_TRIG_POS; 476 break; 477 case IRQ_TYPE_LEVEL_LOW: 478 value |= BYT_TRIG_LVL; 479 case IRQ_TYPE_EDGE_FALLING: 480 value |= BYT_TRIG_NEG; 481 break; 482 case IRQ_TYPE_EDGE_BOTH: 483 value |= (BYT_TRIG_NEG | BYT_TRIG_POS); 484 break; 485 } 486 487 writel(value, reg); 488 489 spin_unlock_irqrestore(&vg->lock, flags); 490 } 491 492 static void byt_irq_mask(struct irq_data *d) 493 { 494 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 495 struct byt_gpio *vg = to_byt_gpio(gc); 496 497 byt_gpio_clear_triggering(vg, irqd_to_hwirq(d)); 498 } 499 500 static struct irq_chip byt_irqchip = { 501 .name = "BYT-GPIO", 502 .irq_ack = byt_irq_ack, 503 .irq_mask = byt_irq_mask, 504 .irq_unmask = byt_irq_unmask, 505 .irq_set_type = byt_irq_type, 506 .flags = IRQCHIP_SKIP_SET_WAKE, 507 }; 508 509 static void byt_gpio_irq_init_hw(struct byt_gpio *vg) 510 { 511 void __iomem *reg; 512 u32 base, value; 513 int i; 514 515 /* 516 * Clear interrupt triggers for all pins that are GPIOs and 517 * do not use direct IRQ mode. This will prevent spurious 518 * interrupts from misconfigured pins. 519 */ 520 for (i = 0; i < vg->chip.ngpio; i++) { 521 value = readl(byt_gpio_reg(&vg->chip, i, BYT_CONF0_REG)); 522 if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i) && 523 !(value & BYT_DIRECT_IRQ_EN)) { 524 byt_gpio_clear_triggering(vg, i); 525 dev_dbg(&vg->pdev->dev, "disabling GPIO %d\n", i); 526 } 527 } 528 529 /* clear interrupt status trigger registers */ 530 for (base = 0; base < vg->chip.ngpio; base += 32) { 531 reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG); 532 writel(0xffffffff, reg); 533 /* make sure trigger bits are cleared, if not then a pin 534 might be misconfigured in bios */ 535 value = readl(reg); 536 if (value) 537 dev_err(&vg->pdev->dev, 538 "GPIO interrupt error, pins misconfigured\n"); 539 } 540 } 541 542 static int byt_gpio_probe(struct platform_device *pdev) 543 { 544 struct byt_gpio *vg; 545 struct gpio_chip *gc; 546 struct resource *mem_rc, *irq_rc; 547 struct device *dev = &pdev->dev; 548 struct acpi_device *acpi_dev; 549 struct pinctrl_gpio_range *range; 550 acpi_handle handle = ACPI_HANDLE(dev); 551 int ret; 552 553 if (acpi_bus_get_device(handle, &acpi_dev)) 554 return -ENODEV; 555 556 vg = devm_kzalloc(dev, sizeof(struct byt_gpio), GFP_KERNEL); 557 if (!vg) { 558 dev_err(&pdev->dev, "can't allocate byt_gpio chip data\n"); 559 return -ENOMEM; 560 } 561 562 for (range = byt_ranges; range->name; range++) { 563 if (!strcmp(acpi_dev->pnp.unique_id, range->name)) { 564 vg->chip.ngpio = range->npins; 565 vg->range = range; 566 break; 567 } 568 } 569 570 if (!vg->chip.ngpio || !vg->range) 571 return -ENODEV; 572 573 vg->pdev = pdev; 574 platform_set_drvdata(pdev, vg); 575 576 mem_rc = platform_get_resource(pdev, IORESOURCE_MEM, 0); 577 vg->reg_base = devm_ioremap_resource(dev, mem_rc); 578 if (IS_ERR(vg->reg_base)) 579 return PTR_ERR(vg->reg_base); 580 581 spin_lock_init(&vg->lock); 582 583 gc = &vg->chip; 584 gc->label = dev_name(&pdev->dev); 585 gc->owner = THIS_MODULE; 586 gc->request = byt_gpio_request; 587 gc->free = byt_gpio_free; 588 gc->direction_input = byt_gpio_direction_input; 589 gc->direction_output = byt_gpio_direction_output; 590 gc->get = byt_gpio_get; 591 gc->set = byt_gpio_set; 592 gc->dbg_show = byt_gpio_dbg_show; 593 gc->base = -1; 594 gc->can_sleep = false; 595 gc->dev = dev; 596 597 #ifdef CONFIG_PM_SLEEP 598 vg->saved_context = devm_kcalloc(&pdev->dev, gc->ngpio, 599 sizeof(*vg->saved_context), GFP_KERNEL); 600 #endif 601 602 ret = gpiochip_add(gc); 603 if (ret) { 604 dev_err(&pdev->dev, "failed adding byt-gpio chip\n"); 605 return ret; 606 } 607 608 /* set up interrupts */ 609 irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 610 if (irq_rc && irq_rc->start) { 611 byt_gpio_irq_init_hw(vg); 612 ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0, 613 handle_simple_irq, IRQ_TYPE_NONE); 614 if (ret) { 615 dev_err(dev, "failed to add irqchip\n"); 616 gpiochip_remove(gc); 617 return ret; 618 } 619 620 gpiochip_set_chained_irqchip(gc, &byt_irqchip, 621 (unsigned)irq_rc->start, 622 byt_gpio_irq_handler); 623 } 624 625 pm_runtime_enable(dev); 626 627 return 0; 628 } 629 630 #ifdef CONFIG_PM_SLEEP 631 static int byt_gpio_suspend(struct device *dev) 632 { 633 struct platform_device *pdev = to_platform_device(dev); 634 struct byt_gpio *vg = platform_get_drvdata(pdev); 635 int i; 636 637 for (i = 0; i < vg->chip.ngpio; i++) { 638 void __iomem *reg; 639 u32 value; 640 641 reg = byt_gpio_reg(&vg->chip, i, BYT_CONF0_REG); 642 value = readl(reg) & BYT_CONF0_RESTORE_MASK; 643 vg->saved_context[i].conf0 = value; 644 645 reg = byt_gpio_reg(&vg->chip, i, BYT_VAL_REG); 646 value = readl(reg) & BYT_VAL_RESTORE_MASK; 647 vg->saved_context[i].val = value; 648 } 649 650 return 0; 651 } 652 653 static int byt_gpio_resume(struct device *dev) 654 { 655 struct platform_device *pdev = to_platform_device(dev); 656 struct byt_gpio *vg = platform_get_drvdata(pdev); 657 int i; 658 659 for (i = 0; i < vg->chip.ngpio; i++) { 660 void __iomem *reg; 661 u32 value; 662 663 reg = byt_gpio_reg(&vg->chip, i, BYT_CONF0_REG); 664 value = readl(reg); 665 if ((value & BYT_CONF0_RESTORE_MASK) != 666 vg->saved_context[i].conf0) { 667 value &= ~BYT_CONF0_RESTORE_MASK; 668 value |= vg->saved_context[i].conf0; 669 writel(value, reg); 670 dev_info(dev, "restored pin %d conf0 %#08x", i, value); 671 } 672 673 reg = byt_gpio_reg(&vg->chip, i, BYT_VAL_REG); 674 value = readl(reg); 675 if ((value & BYT_VAL_RESTORE_MASK) != 676 vg->saved_context[i].val) { 677 u32 v; 678 679 v = value & ~BYT_VAL_RESTORE_MASK; 680 v |= vg->saved_context[i].val; 681 if (v != value) { 682 writel(v, reg); 683 dev_dbg(dev, "restored pin %d val %#08x\n", 684 i, v); 685 } 686 } 687 } 688 689 return 0; 690 } 691 #endif 692 693 static int byt_gpio_runtime_suspend(struct device *dev) 694 { 695 return 0; 696 } 697 698 static int byt_gpio_runtime_resume(struct device *dev) 699 { 700 return 0; 701 } 702 703 static const struct dev_pm_ops byt_gpio_pm_ops = { 704 SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume) 705 SET_RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume, 706 NULL) 707 }; 708 709 static const struct acpi_device_id byt_gpio_acpi_match[] = { 710 { "INT33B2", 0 }, 711 { "INT33FC", 0 }, 712 { } 713 }; 714 MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match); 715 716 static int byt_gpio_remove(struct platform_device *pdev) 717 { 718 struct byt_gpio *vg = platform_get_drvdata(pdev); 719 720 pm_runtime_disable(&pdev->dev); 721 gpiochip_remove(&vg->chip); 722 723 return 0; 724 } 725 726 static struct platform_driver byt_gpio_driver = { 727 .probe = byt_gpio_probe, 728 .remove = byt_gpio_remove, 729 .driver = { 730 .name = "byt_gpio", 731 .pm = &byt_gpio_pm_ops, 732 .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match), 733 }, 734 }; 735 736 static int __init byt_gpio_init(void) 737 { 738 return platform_driver_register(&byt_gpio_driver); 739 } 740 subsys_initcall(byt_gpio_init); 741 742 static void __exit byt_gpio_exit(void) 743 { 744 platform_driver_unregister(&byt_gpio_driver); 745 } 746 module_exit(byt_gpio_exit); 747