1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Pinctrl GPIO driver for Intel Baytrail
4 *
5 * Copyright (c) 2012-2013, Intel Corporation
6 * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
7 */
8
9 #include <linux/acpi.h>
10 #include <linux/bitops.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/types.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/property.h>
21 #include <linux/seq_file.h>
22 #include <linux/string_helpers.h>
23
24 #include <linux/pinctrl/pinctrl.h>
25 #include <linux/pinctrl/pinmux.h>
26 #include <linux/pinctrl/pinconf.h>
27 #include <linux/pinctrl/pinconf-generic.h>
28
29 #include "pinctrl-intel.h"
30
31 /* memory mapped register offsets */
32 #define BYT_CONF0_REG 0x000
33 #define BYT_CONF1_REG 0x004
34 #define BYT_VAL_REG 0x008
35 #define BYT_DFT_REG 0x00c
36 #define BYT_INT_STAT_REG 0x800
37 #define BYT_DIRECT_IRQ_REG 0x980
38 #define BYT_DEBOUNCE_REG 0x9d0
39
40 /* BYT_CONF0_REG register bits */
41 #define BYT_IODEN BIT(31)
42 #define BYT_DIRECT_IRQ_EN BIT(27)
43 #define BYT_TRIG_MASK GENMASK(26, 24)
44 #define BYT_TRIG_NEG BIT(26)
45 #define BYT_TRIG_POS BIT(25)
46 #define BYT_TRIG_LVL BIT(24)
47 #define BYT_DEBOUNCE_EN BIT(20)
48 #define BYT_GLITCH_FILTER_EN BIT(19)
49 #define BYT_GLITCH_F_SLOW_CLK BIT(17)
50 #define BYT_GLITCH_F_FAST_CLK BIT(16)
51 #define BYT_PULL_STR_SHIFT 9
52 #define BYT_PULL_STR_MASK GENMASK(10, 9)
53 #define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT)
54 #define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT)
55 #define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT)
56 #define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT)
57 #define BYT_PULL_ASSIGN_MASK GENMASK(8, 7)
58 #define BYT_PULL_ASSIGN_DOWN BIT(8)
59 #define BYT_PULL_ASSIGN_UP BIT(7)
60 #define BYT_PIN_MUX GENMASK(2, 0)
61
62 /* BYT_VAL_REG register bits */
63 #define BYT_DIR_MASK GENMASK(2, 1)
64 #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/
65 #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/
66 #define BYT_LEVEL BIT(0)
67
68 #define BYT_CONF0_RESTORE_MASK (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | BYT_PIN_MUX)
69 #define BYT_VAL_RESTORE_MASK (BYT_DIR_MASK | BYT_LEVEL)
70
71 /* BYT_DEBOUNCE_REG bits */
72 #define BYT_DEBOUNCE_PULSE_MASK GENMASK(2, 0)
73 #define BYT_DEBOUNCE_PULSE_375US 1
74 #define BYT_DEBOUNCE_PULSE_750US 2
75 #define BYT_DEBOUNCE_PULSE_1500US 3
76 #define BYT_DEBOUNCE_PULSE_3MS 4
77 #define BYT_DEBOUNCE_PULSE_6MS 5
78 #define BYT_DEBOUNCE_PULSE_12MS 6
79 #define BYT_DEBOUNCE_PULSE_24MS 7
80
81 #define BYT_NGPIO_SCORE 102
82 #define BYT_NGPIO_NCORE 28
83 #define BYT_NGPIO_SUS 44
84
85 #define BYT_SCORE_ACPI_UID "1"
86 #define BYT_NCORE_ACPI_UID "2"
87 #define BYT_SUS_ACPI_UID "3"
88
89 /*
90 * This is the function value most pins have for GPIO muxing. If the value
91 * differs from the default one, it must be explicitly mentioned. Otherwise, the
92 * pin control implementation will set the muxing value to default GPIO if it
93 * does not find a match for the requested function.
94 */
95 #define BYT_DEFAULT_GPIO_MUX 0
96 #define BYT_ALTER_GPIO_MUX 1
97
98 struct intel_pad_context {
99 u32 conf0;
100 u32 val;
101 };
102
103 #define COMMUNITY(p, n, map) \
104 { \
105 .pin_base = (p), \
106 .npins = (n), \
107 .pad_map = (map),\
108 }
109
110 /* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */
111 static const struct pinctrl_pin_desc byt_score_pins[] = {
112 PINCTRL_PIN(0, "SATA_GP0"),
113 PINCTRL_PIN(1, "SATA_GP1"),
114 PINCTRL_PIN(2, "SATA_LED#"),
115 PINCTRL_PIN(3, "PCIE_CLKREQ0"),
116 PINCTRL_PIN(4, "PCIE_CLKREQ1"),
117 PINCTRL_PIN(5, "PCIE_CLKREQ2"),
118 PINCTRL_PIN(6, "PCIE_CLKREQ3"),
119 PINCTRL_PIN(7, "SD3_WP"),
120 PINCTRL_PIN(8, "HDA_RST"),
121 PINCTRL_PIN(9, "HDA_SYNC"),
122 PINCTRL_PIN(10, "HDA_CLK"),
123 PINCTRL_PIN(11, "HDA_SDO"),
124 PINCTRL_PIN(12, "HDA_SDI0"),
125 PINCTRL_PIN(13, "HDA_SDI1"),
126 PINCTRL_PIN(14, "GPIO_S0_SC14"),
127 PINCTRL_PIN(15, "GPIO_S0_SC15"),
128 PINCTRL_PIN(16, "MMC1_CLK"),
129 PINCTRL_PIN(17, "MMC1_D0"),
130 PINCTRL_PIN(18, "MMC1_D1"),
131 PINCTRL_PIN(19, "MMC1_D2"),
132 PINCTRL_PIN(20, "MMC1_D3"),
133 PINCTRL_PIN(21, "MMC1_D4"),
134 PINCTRL_PIN(22, "MMC1_D5"),
135 PINCTRL_PIN(23, "MMC1_D6"),
136 PINCTRL_PIN(24, "MMC1_D7"),
137 PINCTRL_PIN(25, "MMC1_CMD"),
138 PINCTRL_PIN(26, "MMC1_RST"),
139 PINCTRL_PIN(27, "SD2_CLK"),
140 PINCTRL_PIN(28, "SD2_D0"),
141 PINCTRL_PIN(29, "SD2_D1"),
142 PINCTRL_PIN(30, "SD2_D2"),
143 PINCTRL_PIN(31, "SD2_D3_CD"),
144 PINCTRL_PIN(32, "SD2_CMD"),
145 PINCTRL_PIN(33, "SD3_CLK"),
146 PINCTRL_PIN(34, "SD3_D0"),
147 PINCTRL_PIN(35, "SD3_D1"),
148 PINCTRL_PIN(36, "SD3_D2"),
149 PINCTRL_PIN(37, "SD3_D3"),
150 PINCTRL_PIN(38, "SD3_CD"),
151 PINCTRL_PIN(39, "SD3_CMD"),
152 PINCTRL_PIN(40, "SD3_1P8EN"),
153 PINCTRL_PIN(41, "SD3_PWREN#"),
154 PINCTRL_PIN(42, "ILB_LPC_AD0"),
155 PINCTRL_PIN(43, "ILB_LPC_AD1"),
156 PINCTRL_PIN(44, "ILB_LPC_AD2"),
157 PINCTRL_PIN(45, "ILB_LPC_AD3"),
158 PINCTRL_PIN(46, "ILB_LPC_FRAME"),
159 PINCTRL_PIN(47, "ILB_LPC_CLK0"),
160 PINCTRL_PIN(48, "ILB_LPC_CLK1"),
161 PINCTRL_PIN(49, "ILB_LPC_CLKRUN"),
162 PINCTRL_PIN(50, "ILB_LPC_SERIRQ"),
163 PINCTRL_PIN(51, "PCU_SMB_DATA"),
164 PINCTRL_PIN(52, "PCU_SMB_CLK"),
165 PINCTRL_PIN(53, "PCU_SMB_ALERT"),
166 PINCTRL_PIN(54, "ILB_8254_SPKR"),
167 PINCTRL_PIN(55, "GPIO_S0_SC55"),
168 PINCTRL_PIN(56, "GPIO_S0_SC56"),
169 PINCTRL_PIN(57, "GPIO_S0_SC57"),
170 PINCTRL_PIN(58, "GPIO_S0_SC58"),
171 PINCTRL_PIN(59, "GPIO_S0_SC59"),
172 PINCTRL_PIN(60, "GPIO_S0_SC60"),
173 PINCTRL_PIN(61, "GPIO_S0_SC61"),
174 PINCTRL_PIN(62, "LPE_I2S2_CLK"),
175 PINCTRL_PIN(63, "LPE_I2S2_FRM"),
176 PINCTRL_PIN(64, "LPE_I2S2_DATAIN"),
177 PINCTRL_PIN(65, "LPE_I2S2_DATAOUT"),
178 PINCTRL_PIN(66, "SIO_SPI_CS"),
179 PINCTRL_PIN(67, "SIO_SPI_MISO"),
180 PINCTRL_PIN(68, "SIO_SPI_MOSI"),
181 PINCTRL_PIN(69, "SIO_SPI_CLK"),
182 PINCTRL_PIN(70, "SIO_UART1_RXD"),
183 PINCTRL_PIN(71, "SIO_UART1_TXD"),
184 PINCTRL_PIN(72, "SIO_UART1_RTS"),
185 PINCTRL_PIN(73, "SIO_UART1_CTS"),
186 PINCTRL_PIN(74, "SIO_UART2_RXD"),
187 PINCTRL_PIN(75, "SIO_UART2_TXD"),
188 PINCTRL_PIN(76, "SIO_UART2_RTS"),
189 PINCTRL_PIN(77, "SIO_UART2_CTS"),
190 PINCTRL_PIN(78, "SIO_I2C0_DATA"),
191 PINCTRL_PIN(79, "SIO_I2C0_CLK"),
192 PINCTRL_PIN(80, "SIO_I2C1_DATA"),
193 PINCTRL_PIN(81, "SIO_I2C1_CLK"),
194 PINCTRL_PIN(82, "SIO_I2C2_DATA"),
195 PINCTRL_PIN(83, "SIO_I2C2_CLK"),
196 PINCTRL_PIN(84, "SIO_I2C3_DATA"),
197 PINCTRL_PIN(85, "SIO_I2C3_CLK"),
198 PINCTRL_PIN(86, "SIO_I2C4_DATA"),
199 PINCTRL_PIN(87, "SIO_I2C4_CLK"),
200 PINCTRL_PIN(88, "SIO_I2C5_DATA"),
201 PINCTRL_PIN(89, "SIO_I2C5_CLK"),
202 PINCTRL_PIN(90, "SIO_I2C6_DATA"),
203 PINCTRL_PIN(91, "SIO_I2C6_CLK"),
204 PINCTRL_PIN(92, "GPIO_S0_SC92"),
205 PINCTRL_PIN(93, "GPIO_S0_SC93"),
206 PINCTRL_PIN(94, "SIO_PWM0"),
207 PINCTRL_PIN(95, "SIO_PWM1"),
208 PINCTRL_PIN(96, "PMC_PLT_CLK0"),
209 PINCTRL_PIN(97, "PMC_PLT_CLK1"),
210 PINCTRL_PIN(98, "PMC_PLT_CLK2"),
211 PINCTRL_PIN(99, "PMC_PLT_CLK3"),
212 PINCTRL_PIN(100, "PMC_PLT_CLK4"),
213 PINCTRL_PIN(101, "PMC_PLT_CLK5"),
214 };
215
216 static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = {
217 85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
218 36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
219 54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
220 52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
221 95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
222 86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
223 80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
224 2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
225 31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
226 24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
227 97, 100,
228 };
229
230 /* SCORE groups */
231 static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 };
232 static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 };
233
234 static const unsigned int byt_score_pwm0_pins[] = { 94 };
235 static const unsigned int byt_score_pwm1_pins[] = { 95 };
236
237 static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 };
238
239 static const unsigned int byt_score_i2c5_pins[] = { 88, 89 };
240 static const unsigned int byt_score_i2c6_pins[] = { 90, 91 };
241 static const unsigned int byt_score_i2c4_pins[] = { 86, 87 };
242 static const unsigned int byt_score_i2c3_pins[] = { 84, 85 };
243 static const unsigned int byt_score_i2c2_pins[] = { 82, 83 };
244 static const unsigned int byt_score_i2c1_pins[] = { 80, 81 };
245 static const unsigned int byt_score_i2c0_pins[] = { 78, 79 };
246
247 static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 };
248 static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 };
249 static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 };
250
251 static const unsigned int byt_score_sdcard_pins[] = {
252 7, 33, 34, 35, 36, 37, 38, 39, 40, 41,
253 };
254 static const unsigned int byt_score_sdcard_mux_values[] = {
255 2, 1, 1, 1, 1, 1, 1, 1, 1, 1,
256 };
257
258 static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 };
259
260 static const unsigned int byt_score_emmc_pins[] = {
261 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
262 };
263
264 static const unsigned int byt_score_ilb_lpc_pins[] = {
265 42, 43, 44, 45, 46, 47, 48, 49, 50,
266 };
267
268 static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 };
269
270 static const unsigned int byt_score_plt_clk0_pins[] = { 96 };
271 static const unsigned int byt_score_plt_clk1_pins[] = { 97 };
272 static const unsigned int byt_score_plt_clk2_pins[] = { 98 };
273 static const unsigned int byt_score_plt_clk3_pins[] = { 99 };
274 static const unsigned int byt_score_plt_clk4_pins[] = { 100 };
275 static const unsigned int byt_score_plt_clk5_pins[] = { 101 };
276
277 static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 };
278
279 static const struct intel_pingroup byt_score_groups[] = {
280 PIN_GROUP_GPIO("uart1_grp", byt_score_uart1_pins, 1),
281 PIN_GROUP_GPIO("uart2_grp", byt_score_uart2_pins, 1),
282 PIN_GROUP_GPIO("pwm0_grp", byt_score_pwm0_pins, 1),
283 PIN_GROUP_GPIO("pwm1_grp", byt_score_pwm1_pins, 1),
284 PIN_GROUP_GPIO("ssp2_grp", byt_score_ssp2_pins, 1),
285 PIN_GROUP_GPIO("sio_spi_grp", byt_score_sio_spi_pins, 1),
286 PIN_GROUP_GPIO("i2c5_grp", byt_score_i2c5_pins, 1),
287 PIN_GROUP_GPIO("i2c6_grp", byt_score_i2c6_pins, 1),
288 PIN_GROUP_GPIO("i2c4_grp", byt_score_i2c4_pins, 1),
289 PIN_GROUP_GPIO("i2c3_grp", byt_score_i2c3_pins, 1),
290 PIN_GROUP_GPIO("i2c2_grp", byt_score_i2c2_pins, 1),
291 PIN_GROUP_GPIO("i2c1_grp", byt_score_i2c1_pins, 1),
292 PIN_GROUP_GPIO("i2c0_grp", byt_score_i2c0_pins, 1),
293 PIN_GROUP_GPIO("ssp0_grp", byt_score_ssp0_pins, 1),
294 PIN_GROUP_GPIO("ssp1_grp", byt_score_ssp1_pins, 1),
295 PIN_GROUP_GPIO("sdcard_grp", byt_score_sdcard_pins, byt_score_sdcard_mux_values),
296 PIN_GROUP_GPIO("sdio_grp", byt_score_sdio_pins, 1),
297 PIN_GROUP_GPIO("emmc_grp", byt_score_emmc_pins, 1),
298 PIN_GROUP_GPIO("lpc_grp", byt_score_ilb_lpc_pins, 1),
299 PIN_GROUP_GPIO("sata_grp", byt_score_sata_pins, 1),
300 PIN_GROUP_GPIO("plt_clk0_grp", byt_score_plt_clk0_pins, 1),
301 PIN_GROUP_GPIO("plt_clk1_grp", byt_score_plt_clk1_pins, 1),
302 PIN_GROUP_GPIO("plt_clk2_grp", byt_score_plt_clk2_pins, 1),
303 PIN_GROUP_GPIO("plt_clk3_grp", byt_score_plt_clk3_pins, 1),
304 PIN_GROUP_GPIO("plt_clk4_grp", byt_score_plt_clk4_pins, 1),
305 PIN_GROUP_GPIO("plt_clk5_grp", byt_score_plt_clk5_pins, 1),
306 PIN_GROUP_GPIO("smbus_grp", byt_score_smbus_pins, 1),
307 };
308
309 static const char * const byt_score_uart_groups[] = {
310 "uart1_grp", "uart2_grp",
311 };
312 static const char * const byt_score_pwm_groups[] = {
313 "pwm0_grp", "pwm1_grp",
314 };
315 static const char * const byt_score_ssp_groups[] = {
316 "ssp0_grp", "ssp1_grp", "ssp2_grp",
317 };
318 static const char * const byt_score_spi_groups[] = { "sio_spi_grp" };
319 static const char * const byt_score_i2c_groups[] = {
320 "i2c0_grp", "i2c1_grp", "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp",
321 "i2c6_grp",
322 };
323 static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" };
324 static const char * const byt_score_sdio_groups[] = { "sdio_grp" };
325 static const char * const byt_score_emmc_groups[] = { "emmc_grp" };
326 static const char * const byt_score_lpc_groups[] = { "lpc_grp" };
327 static const char * const byt_score_sata_groups[] = { "sata_grp" };
328 static const char * const byt_score_plt_clk_groups[] = {
329 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
330 "plt_clk4_grp", "plt_clk5_grp",
331 };
332 static const char * const byt_score_smbus_groups[] = { "smbus_grp" };
333 static const char * const byt_score_gpio_groups[] = {
334 "uart1_grp_gpio", "uart2_grp_gpio", "pwm0_grp_gpio",
335 "pwm1_grp_gpio", "ssp0_grp_gpio", "ssp1_grp_gpio", "ssp2_grp_gpio",
336 "sio_spi_grp_gpio", "i2c0_grp_gpio", "i2c1_grp_gpio", "i2c2_grp_gpio",
337 "i2c3_grp_gpio", "i2c4_grp_gpio", "i2c5_grp_gpio", "i2c6_grp_gpio",
338 "sdcard_grp_gpio", "sdio_grp_gpio", "emmc_grp_gpio", "lpc_grp_gpio",
339 "sata_grp_gpio", "plt_clk0_grp_gpio", "plt_clk1_grp_gpio",
340 "plt_clk2_grp_gpio", "plt_clk3_grp_gpio", "plt_clk4_grp_gpio",
341 "plt_clk5_grp_gpio", "smbus_grp_gpio",
342 };
343
344 static const struct intel_function byt_score_functions[] = {
345 FUNCTION("uart", byt_score_uart_groups),
346 FUNCTION("pwm", byt_score_pwm_groups),
347 FUNCTION("ssp", byt_score_ssp_groups),
348 FUNCTION("spi", byt_score_spi_groups),
349 FUNCTION("i2c", byt_score_i2c_groups),
350 FUNCTION("sdcard", byt_score_sdcard_groups),
351 FUNCTION("sdio", byt_score_sdio_groups),
352 FUNCTION("emmc", byt_score_emmc_groups),
353 FUNCTION("lpc", byt_score_lpc_groups),
354 FUNCTION("sata", byt_score_sata_groups),
355 FUNCTION("plt_clk", byt_score_plt_clk_groups),
356 FUNCTION("smbus", byt_score_smbus_groups),
357 FUNCTION("gpio", byt_score_gpio_groups),
358 };
359
360 static const struct intel_community byt_score_communities[] = {
361 COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map),
362 };
363
364 static const struct intel_pinctrl_soc_data byt_score_soc_data = {
365 .uid = BYT_SCORE_ACPI_UID,
366 .pins = byt_score_pins,
367 .npins = ARRAY_SIZE(byt_score_pins),
368 .groups = byt_score_groups,
369 .ngroups = ARRAY_SIZE(byt_score_groups),
370 .functions = byt_score_functions,
371 .nfunctions = ARRAY_SIZE(byt_score_functions),
372 .communities = byt_score_communities,
373 .ncommunities = ARRAY_SIZE(byt_score_communities),
374 };
375
376 /* SUS pins, aka GPIOS_<pin_no> or GPIO_S5[<pin_no>] */
377 static const struct pinctrl_pin_desc byt_sus_pins[] = {
378 PINCTRL_PIN(0, "GPIO_S50"),
379 PINCTRL_PIN(1, "GPIO_S51"),
380 PINCTRL_PIN(2, "GPIO_S52"),
381 PINCTRL_PIN(3, "GPIO_S53"),
382 PINCTRL_PIN(4, "GPIO_S54"),
383 PINCTRL_PIN(5, "GPIO_S55"),
384 PINCTRL_PIN(6, "GPIO_S56"),
385 PINCTRL_PIN(7, "GPIO_S57"),
386 PINCTRL_PIN(8, "GPIO_S58"),
387 PINCTRL_PIN(9, "GPIO_S59"),
388 PINCTRL_PIN(10, "GPIO_S510"),
389 PINCTRL_PIN(11, "PMC_SUSPWRDNACK"),
390 PINCTRL_PIN(12, "PMC_SUSCLK0"),
391 PINCTRL_PIN(13, "GPIO_S513"),
392 PINCTRL_PIN(14, "USB_ULPI_RST"),
393 PINCTRL_PIN(15, "PMC_WAKE_PCIE0#"),
394 PINCTRL_PIN(16, "PMC_PWRBTN"),
395 PINCTRL_PIN(17, "GPIO_S517"),
396 PINCTRL_PIN(18, "PMC_SUS_STAT"),
397 PINCTRL_PIN(19, "USB_OC0"),
398 PINCTRL_PIN(20, "USB_OC1"),
399 PINCTRL_PIN(21, "PCU_SPI_CS1"),
400 PINCTRL_PIN(22, "GPIO_S522"),
401 PINCTRL_PIN(23, "GPIO_S523"),
402 PINCTRL_PIN(24, "GPIO_S524"),
403 PINCTRL_PIN(25, "GPIO_S525"),
404 PINCTRL_PIN(26, "GPIO_S526"),
405 PINCTRL_PIN(27, "GPIO_S527"),
406 PINCTRL_PIN(28, "GPIO_S528"),
407 PINCTRL_PIN(29, "GPIO_S529"),
408 PINCTRL_PIN(30, "GPIO_S530"),
409 PINCTRL_PIN(31, "USB_ULPI_CLK"),
410 PINCTRL_PIN(32, "USB_ULPI_DATA0"),
411 PINCTRL_PIN(33, "USB_ULPI_DATA1"),
412 PINCTRL_PIN(34, "USB_ULPI_DATA2"),
413 PINCTRL_PIN(35, "USB_ULPI_DATA3"),
414 PINCTRL_PIN(36, "USB_ULPI_DATA4"),
415 PINCTRL_PIN(37, "USB_ULPI_DATA5"),
416 PINCTRL_PIN(38, "USB_ULPI_DATA6"),
417 PINCTRL_PIN(39, "USB_ULPI_DATA7"),
418 PINCTRL_PIN(40, "USB_ULPI_DIR"),
419 PINCTRL_PIN(41, "USB_ULPI_NXT"),
420 PINCTRL_PIN(42, "USB_ULPI_STP"),
421 PINCTRL_PIN(43, "USB_ULPI_REFCLK"),
422 };
423
424 static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = {
425 29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
426 18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
427 0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
428 26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
429 52, 53, 59, 40,
430 };
431
432 static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 };
433 static const unsigned int byt_sus_usb_over_current_mode_values[] = { 0, 0 };
434 static const unsigned int byt_sus_usb_over_current_gpio_mode_values[] = { 1, 1 };
435
436 static const unsigned int byt_sus_usb_ulpi_pins[] = {
437 14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
438 };
439 static const unsigned int byt_sus_usb_ulpi_mode_values[] = {
440 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
441 };
442 static const unsigned int byt_sus_usb_ulpi_gpio_mode_values[] = {
443 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
444 };
445
446 static const unsigned int byt_sus_pcu_spi_pins[] = { 21 };
447 static const unsigned int byt_sus_pcu_spi_mode_values[] = { 0 };
448 static const unsigned int byt_sus_pcu_spi_gpio_mode_values[] = { 1 };
449
450 static const unsigned int byt_sus_pmu_clk1_pins[] = { 5 };
451 static const unsigned int byt_sus_pmu_clk2_pins[] = { 6 };
452
453 static const struct intel_pingroup byt_sus_groups[] = {
454 PIN_GROUP("usb_oc_grp", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_mode_values),
455 PIN_GROUP("usb_ulpi_grp", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mode_values),
456 PIN_GROUP("pcu_spi_grp", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mode_values),
457 PIN_GROUP("usb_oc_grp_gpio", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_gpio_mode_values),
458 PIN_GROUP("usb_ulpi_grp_gpio", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_gpio_mode_values),
459 PIN_GROUP("pcu_spi_grp_gpio", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_gpio_mode_values),
460 PIN_GROUP_GPIO("pmu_clk1_grp", byt_sus_pmu_clk1_pins, 1),
461 PIN_GROUP_GPIO("pmu_clk2_grp", byt_sus_pmu_clk2_pins, 1),
462 };
463
464 static const char * const byt_sus_usb_groups[] = {
465 "usb_oc_grp", "usb_ulpi_grp",
466 };
467 static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" };
468 static const char * const byt_sus_pmu_clk_groups[] = {
469 "pmu_clk1_grp", "pmu_clk2_grp",
470 };
471 static const char * const byt_sus_gpio_groups[] = {
472 "usb_oc_grp_gpio", "usb_ulpi_grp_gpio", "pcu_spi_grp_gpio",
473 "pmu_clk1_grp_gpio", "pmu_clk2_grp_gpio",
474 };
475
476 static const struct intel_function byt_sus_functions[] = {
477 FUNCTION("usb", byt_sus_usb_groups),
478 FUNCTION("spi", byt_sus_spi_groups),
479 FUNCTION("gpio", byt_sus_gpio_groups),
480 FUNCTION("pmu_clk", byt_sus_pmu_clk_groups),
481 };
482
483 static const struct intel_community byt_sus_communities[] = {
484 COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map),
485 };
486
487 static const struct intel_pinctrl_soc_data byt_sus_soc_data = {
488 .uid = BYT_SUS_ACPI_UID,
489 .pins = byt_sus_pins,
490 .npins = ARRAY_SIZE(byt_sus_pins),
491 .groups = byt_sus_groups,
492 .ngroups = ARRAY_SIZE(byt_sus_groups),
493 .functions = byt_sus_functions,
494 .nfunctions = ARRAY_SIZE(byt_sus_functions),
495 .communities = byt_sus_communities,
496 .ncommunities = ARRAY_SIZE(byt_sus_communities),
497 };
498
499 static const struct pinctrl_pin_desc byt_ncore_pins[] = {
500 PINCTRL_PIN(0, "HV_DDI0_HPD"),
501 PINCTRL_PIN(1, "HV_DDI0_DDC_SDA"),
502 PINCTRL_PIN(2, "HV_DDI0_DDC_SCL"),
503 PINCTRL_PIN(3, "PANEL0_VDDEN"),
504 PINCTRL_PIN(4, "PANEL0_BKLTEN"),
505 PINCTRL_PIN(5, "PANEL0_BKLTCTL"),
506 PINCTRL_PIN(6, "HV_DDI1_HPD"),
507 PINCTRL_PIN(7, "HV_DDI1_DDC_SDA"),
508 PINCTRL_PIN(8, "HV_DDI1_DDC_SCL"),
509 PINCTRL_PIN(9, "PANEL1_VDDEN"),
510 PINCTRL_PIN(10, "PANEL1_BKLTEN"),
511 PINCTRL_PIN(11, "PANEL1_BKLTCTL"),
512 PINCTRL_PIN(12, "GP_INTD_DSI_TE1"),
513 PINCTRL_PIN(13, "HV_DDI2_DDC_SDA"),
514 PINCTRL_PIN(14, "HV_DDI2_DDC_SCL"),
515 PINCTRL_PIN(15, "GP_CAMERASB00"),
516 PINCTRL_PIN(16, "GP_CAMERASB01"),
517 PINCTRL_PIN(17, "GP_CAMERASB02"),
518 PINCTRL_PIN(18, "GP_CAMERASB03"),
519 PINCTRL_PIN(19, "GP_CAMERASB04"),
520 PINCTRL_PIN(20, "GP_CAMERASB05"),
521 PINCTRL_PIN(21, "GP_CAMERASB06"),
522 PINCTRL_PIN(22, "GP_CAMERASB07"),
523 PINCTRL_PIN(23, "GP_CAMERASB08"),
524 PINCTRL_PIN(24, "GP_CAMERASB09"),
525 PINCTRL_PIN(25, "GP_CAMERASB10"),
526 PINCTRL_PIN(26, "GP_CAMERASB11"),
527 PINCTRL_PIN(27, "GP_INTD_DSI_TE2"),
528 };
529
530 static const unsigned int byt_ncore_pins_map[BYT_NGPIO_NCORE] = {
531 19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
532 14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
533 3, 6, 10, 13, 2, 5, 9, 7,
534 };
535
536 static const struct intel_community byt_ncore_communities[] = {
537 COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map),
538 };
539
540 static const struct intel_pinctrl_soc_data byt_ncore_soc_data = {
541 .uid = BYT_NCORE_ACPI_UID,
542 .pins = byt_ncore_pins,
543 .npins = ARRAY_SIZE(byt_ncore_pins),
544 .communities = byt_ncore_communities,
545 .ncommunities = ARRAY_SIZE(byt_ncore_communities),
546 };
547
548 static const struct intel_pinctrl_soc_data *byt_soc_data[] = {
549 &byt_score_soc_data,
550 &byt_sus_soc_data,
551 &byt_ncore_soc_data,
552 NULL
553 };
554
555 static DEFINE_RAW_SPINLOCK(byt_lock);
556
byt_gpio_reg(struct intel_pinctrl * vg,unsigned int offset,int reg)557 static void __iomem *byt_gpio_reg(struct intel_pinctrl *vg, unsigned int offset,
558 int reg)
559 {
560 struct intel_community *comm = intel_get_community(vg, offset);
561 u32 reg_offset;
562
563 if (!comm)
564 return NULL;
565
566 offset -= comm->pin_base;
567 switch (reg) {
568 case BYT_INT_STAT_REG:
569 reg_offset = (offset / 32) * 4;
570 break;
571 case BYT_DEBOUNCE_REG:
572 reg_offset = 0;
573 break;
574 default:
575 reg_offset = comm->pad_map[offset] * 16;
576 break;
577 }
578
579 return comm->pad_regs + reg_offset + reg;
580 }
581
582 static const struct pinctrl_ops byt_pinctrl_ops = {
583 .get_groups_count = intel_get_groups_count,
584 .get_group_name = intel_get_group_name,
585 .get_group_pins = intel_get_group_pins,
586 };
587
byt_set_group_simple_mux(struct intel_pinctrl * vg,const struct intel_pingroup group,unsigned int func)588 static void byt_set_group_simple_mux(struct intel_pinctrl *vg,
589 const struct intel_pingroup group,
590 unsigned int func)
591 {
592 unsigned long flags;
593 int i;
594
595 raw_spin_lock_irqsave(&byt_lock, flags);
596
597 for (i = 0; i < group.grp.npins; i++) {
598 void __iomem *padcfg0;
599 u32 value;
600
601 padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG);
602 if (!padcfg0) {
603 dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n",
604 group.grp.name, i);
605 continue;
606 }
607
608 value = readl(padcfg0);
609 value &= ~BYT_PIN_MUX;
610 value |= func;
611 writel(value, padcfg0);
612 }
613
614 raw_spin_unlock_irqrestore(&byt_lock, flags);
615 }
616
byt_set_group_mixed_mux(struct intel_pinctrl * vg,const struct intel_pingroup group,const unsigned int * func)617 static void byt_set_group_mixed_mux(struct intel_pinctrl *vg,
618 const struct intel_pingroup group,
619 const unsigned int *func)
620 {
621 unsigned long flags;
622 int i;
623
624 raw_spin_lock_irqsave(&byt_lock, flags);
625
626 for (i = 0; i < group.grp.npins; i++) {
627 void __iomem *padcfg0;
628 u32 value;
629
630 padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG);
631 if (!padcfg0) {
632 dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n",
633 group.grp.name, i);
634 continue;
635 }
636
637 value = readl(padcfg0);
638 value &= ~BYT_PIN_MUX;
639 value |= func[i];
640 writel(value, padcfg0);
641 }
642
643 raw_spin_unlock_irqrestore(&byt_lock, flags);
644 }
645
byt_set_mux(struct pinctrl_dev * pctldev,unsigned int func_selector,unsigned int group_selector)646 static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
647 unsigned int group_selector)
648 {
649 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
650 const struct intel_function func = vg->soc->functions[func_selector];
651 const struct intel_pingroup group = vg->soc->groups[group_selector];
652
653 if (group.modes)
654 byt_set_group_mixed_mux(vg, group, group.modes);
655 else if (!strcmp(func.func.name, "gpio"))
656 byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX);
657 else
658 byt_set_group_simple_mux(vg, group, group.mode);
659
660 return 0;
661 }
662
byt_get_gpio_mux(struct intel_pinctrl * vg,unsigned int offset)663 static u32 byt_get_gpio_mux(struct intel_pinctrl *vg, unsigned int offset)
664 {
665 /* SCORE pin 92-93 */
666 if (!strcmp(vg->soc->uid, BYT_SCORE_ACPI_UID) &&
667 offset >= 92 && offset <= 93)
668 return BYT_ALTER_GPIO_MUX;
669
670 /* SUS pin 11-21 */
671 if (!strcmp(vg->soc->uid, BYT_SUS_ACPI_UID) &&
672 offset >= 11 && offset <= 21)
673 return BYT_ALTER_GPIO_MUX;
674
675 return BYT_DEFAULT_GPIO_MUX;
676 }
677
byt_gpio_clear_triggering(struct intel_pinctrl * vg,unsigned int offset)678 static void byt_gpio_clear_triggering(struct intel_pinctrl *vg, unsigned int offset)
679 {
680 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
681 unsigned long flags;
682 u32 value;
683
684 raw_spin_lock_irqsave(&byt_lock, flags);
685 value = readl(reg);
686
687 /* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */
688 if (!(value & BYT_DIRECT_IRQ_EN))
689 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
690
691 writel(value, reg);
692 raw_spin_unlock_irqrestore(&byt_lock, flags);
693 }
694
byt_gpio_request_enable(struct pinctrl_dev * pctl_dev,struct pinctrl_gpio_range * range,unsigned int offset)695 static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
696 struct pinctrl_gpio_range *range,
697 unsigned int offset)
698 {
699 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
700 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
701 u32 value, gpio_mux;
702 unsigned long flags;
703
704 raw_spin_lock_irqsave(&byt_lock, flags);
705
706 /*
707 * In most cases, func pin mux 000 means GPIO function.
708 * But, some pins may have func pin mux 001 represents
709 * GPIO function.
710 *
711 * Because there are devices out there where some pins were not
712 * configured correctly we allow changing the mux value from
713 * request (but print out warning about that).
714 */
715 value = readl(reg) & BYT_PIN_MUX;
716 gpio_mux = byt_get_gpio_mux(vg, offset);
717 if (gpio_mux != value) {
718 value = readl(reg) & ~BYT_PIN_MUX;
719 value |= gpio_mux;
720 writel(value, reg);
721
722 dev_warn(vg->dev, FW_BUG "Pin %i: forcibly re-configured as GPIO\n", offset);
723 }
724
725 raw_spin_unlock_irqrestore(&byt_lock, flags);
726
727 pm_runtime_get(vg->dev);
728
729 return 0;
730 }
731
byt_gpio_disable_free(struct pinctrl_dev * pctl_dev,struct pinctrl_gpio_range * range,unsigned int offset)732 static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev,
733 struct pinctrl_gpio_range *range,
734 unsigned int offset)
735 {
736 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
737
738 byt_gpio_clear_triggering(vg, offset);
739 pm_runtime_put(vg->dev);
740 }
741
byt_gpio_direct_irq_check(struct intel_pinctrl * vg,unsigned int offset)742 static void byt_gpio_direct_irq_check(struct intel_pinctrl *vg,
743 unsigned int offset)
744 {
745 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
746
747 /*
748 * Before making any direction modifications, do a check if gpio is set
749 * for direct IRQ. On Bay Trail, setting GPIO to output does not make
750 * sense, so let's at least inform the caller before they shoot
751 * themselves in the foot.
752 */
753 if (readl(conf_reg) & BYT_DIRECT_IRQ_EN)
754 dev_info_once(vg->dev,
755 "Potential Error: Pin %i: forcibly set GPIO with DIRECT_IRQ_EN to output\n",
756 offset);
757 }
758
byt_gpio_set_direction(struct pinctrl_dev * pctl_dev,struct pinctrl_gpio_range * range,unsigned int offset,bool input)759 static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
760 struct pinctrl_gpio_range *range,
761 unsigned int offset,
762 bool input)
763 {
764 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
765 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
766 unsigned long flags;
767 u32 value;
768
769 raw_spin_lock_irqsave(&byt_lock, flags);
770
771 value = readl(val_reg);
772 value &= ~BYT_DIR_MASK;
773 if (input)
774 value |= BYT_OUTPUT_EN;
775 else
776 byt_gpio_direct_irq_check(vg, offset);
777
778 writel(value, val_reg);
779
780 raw_spin_unlock_irqrestore(&byt_lock, flags);
781
782 return 0;
783 }
784
785 static const struct pinmux_ops byt_pinmux_ops = {
786 .get_functions_count = intel_get_functions_count,
787 .get_function_name = intel_get_function_name,
788 .get_function_groups = intel_get_function_groups,
789 .set_mux = byt_set_mux,
790 .gpio_request_enable = byt_gpio_request_enable,
791 .gpio_disable_free = byt_gpio_disable_free,
792 .gpio_set_direction = byt_gpio_set_direction,
793 };
794
byt_get_pull_strength(u32 reg,u16 * strength)795 static void byt_get_pull_strength(u32 reg, u16 *strength)
796 {
797 switch (reg & BYT_PULL_STR_MASK) {
798 case BYT_PULL_STR_2K:
799 *strength = 2000;
800 break;
801 case BYT_PULL_STR_10K:
802 *strength = 10000;
803 break;
804 case BYT_PULL_STR_20K:
805 *strength = 20000;
806 break;
807 case BYT_PULL_STR_40K:
808 *strength = 40000;
809 break;
810 }
811 }
812
byt_set_pull_strength(u32 * reg,u16 strength)813 static int byt_set_pull_strength(u32 *reg, u16 strength)
814 {
815 *reg &= ~BYT_PULL_STR_MASK;
816
817 switch (strength) {
818 case 2000:
819 *reg |= BYT_PULL_STR_2K;
820 break;
821 case 10000:
822 *reg |= BYT_PULL_STR_10K;
823 break;
824 case 20000:
825 *reg |= BYT_PULL_STR_20K;
826 break;
827 case 40000:
828 *reg |= BYT_PULL_STR_40K;
829 break;
830 default:
831 return -EINVAL;
832 }
833
834 return 0;
835 }
836
byt_pin_config_get(struct pinctrl_dev * pctl_dev,unsigned int offset,unsigned long * config)837 static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
838 unsigned long *config)
839 {
840 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
841 enum pin_config_param param = pinconf_to_config_param(*config);
842 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
843 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
844 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
845 unsigned long flags;
846 u32 conf, pull, val, debounce;
847 u16 arg = 0;
848
849 raw_spin_lock_irqsave(&byt_lock, flags);
850 conf = readl(conf_reg);
851 pull = conf & BYT_PULL_ASSIGN_MASK;
852 val = readl(val_reg);
853 raw_spin_unlock_irqrestore(&byt_lock, flags);
854
855 switch (param) {
856 case PIN_CONFIG_BIAS_DISABLE:
857 if (pull)
858 return -EINVAL;
859 break;
860 case PIN_CONFIG_BIAS_PULL_DOWN:
861 /* Pull assignment is only applicable in input mode */
862 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN)
863 return -EINVAL;
864
865 byt_get_pull_strength(conf, &arg);
866
867 break;
868 case PIN_CONFIG_BIAS_PULL_UP:
869 /* Pull assignment is only applicable in input mode */
870 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP)
871 return -EINVAL;
872
873 byt_get_pull_strength(conf, &arg);
874
875 break;
876 case PIN_CONFIG_INPUT_DEBOUNCE:
877 if (!(conf & BYT_DEBOUNCE_EN))
878 return -EINVAL;
879
880 raw_spin_lock_irqsave(&byt_lock, flags);
881 debounce = readl(db_reg);
882 raw_spin_unlock_irqrestore(&byt_lock, flags);
883
884 switch (debounce & BYT_DEBOUNCE_PULSE_MASK) {
885 case BYT_DEBOUNCE_PULSE_375US:
886 arg = 375;
887 break;
888 case BYT_DEBOUNCE_PULSE_750US:
889 arg = 750;
890 break;
891 case BYT_DEBOUNCE_PULSE_1500US:
892 arg = 1500;
893 break;
894 case BYT_DEBOUNCE_PULSE_3MS:
895 arg = 3000;
896 break;
897 case BYT_DEBOUNCE_PULSE_6MS:
898 arg = 6000;
899 break;
900 case BYT_DEBOUNCE_PULSE_12MS:
901 arg = 12000;
902 break;
903 case BYT_DEBOUNCE_PULSE_24MS:
904 arg = 24000;
905 break;
906 default:
907 return -EINVAL;
908 }
909
910 break;
911 default:
912 return -ENOTSUPP;
913 }
914
915 *config = pinconf_to_config_packed(param, arg);
916
917 return 0;
918 }
919
byt_pin_config_set(struct pinctrl_dev * pctl_dev,unsigned int offset,unsigned long * configs,unsigned int num_configs)920 static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
921 unsigned int offset,
922 unsigned long *configs,
923 unsigned int num_configs)
924 {
925 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
926 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
927 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
928 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
929 u32 conf, val, db_pulse, debounce;
930 enum pin_config_param param;
931 unsigned long flags;
932 int i, ret = 0;
933 u32 arg;
934
935 raw_spin_lock_irqsave(&byt_lock, flags);
936
937 conf = readl(conf_reg);
938 val = readl(val_reg);
939
940 for (i = 0; i < num_configs; i++) {
941 param = pinconf_to_config_param(configs[i]);
942 arg = pinconf_to_config_argument(configs[i]);
943
944 switch (param) {
945 case PIN_CONFIG_BIAS_DISABLE:
946 conf &= ~BYT_PULL_ASSIGN_MASK;
947 break;
948 case PIN_CONFIG_BIAS_PULL_DOWN:
949 /* Set default strength value in case none is given */
950 if (arg == 1)
951 arg = 2000;
952
953 /*
954 * Pull assignment is only applicable in input mode. If
955 * chip is not in input mode, set it and warn about it.
956 */
957 if (val & BYT_INPUT_EN) {
958 val &= ~BYT_INPUT_EN;
959 writel(val, val_reg);
960 dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset);
961 }
962
963 conf &= ~BYT_PULL_ASSIGN_MASK;
964 conf |= BYT_PULL_ASSIGN_DOWN;
965 ret = byt_set_pull_strength(&conf, arg);
966
967 break;
968 case PIN_CONFIG_BIAS_PULL_UP:
969 /* Set default strength value in case none is given */
970 if (arg == 1)
971 arg = 2000;
972
973 /*
974 * Pull assignment is only applicable in input mode. If
975 * chip is not in input mode, set it and warn about it.
976 */
977 if (val & BYT_INPUT_EN) {
978 val &= ~BYT_INPUT_EN;
979 writel(val, val_reg);
980 dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset);
981 }
982
983 conf &= ~BYT_PULL_ASSIGN_MASK;
984 conf |= BYT_PULL_ASSIGN_UP;
985 ret = byt_set_pull_strength(&conf, arg);
986
987 break;
988 case PIN_CONFIG_INPUT_DEBOUNCE:
989 if (arg) {
990 conf |= BYT_DEBOUNCE_EN;
991 } else {
992 conf &= ~BYT_DEBOUNCE_EN;
993
994 /*
995 * No need to update the pulse value.
996 * Debounce is going to be disabled.
997 */
998 break;
999 }
1000
1001 switch (arg) {
1002 case 375:
1003 db_pulse = BYT_DEBOUNCE_PULSE_375US;
1004 break;
1005 case 750:
1006 db_pulse = BYT_DEBOUNCE_PULSE_750US;
1007 break;
1008 case 1500:
1009 db_pulse = BYT_DEBOUNCE_PULSE_1500US;
1010 break;
1011 case 3000:
1012 db_pulse = BYT_DEBOUNCE_PULSE_3MS;
1013 break;
1014 case 6000:
1015 db_pulse = BYT_DEBOUNCE_PULSE_6MS;
1016 break;
1017 case 12000:
1018 db_pulse = BYT_DEBOUNCE_PULSE_12MS;
1019 break;
1020 case 24000:
1021 db_pulse = BYT_DEBOUNCE_PULSE_24MS;
1022 break;
1023 default:
1024 if (arg)
1025 ret = -EINVAL;
1026 break;
1027 }
1028
1029 if (ret)
1030 break;
1031
1032 debounce = readl(db_reg);
1033 debounce = (debounce & ~BYT_DEBOUNCE_PULSE_MASK) | db_pulse;
1034 writel(debounce, db_reg);
1035
1036 break;
1037 default:
1038 ret = -ENOTSUPP;
1039 }
1040
1041 if (ret)
1042 break;
1043 }
1044
1045 if (!ret)
1046 writel(conf, conf_reg);
1047
1048 raw_spin_unlock_irqrestore(&byt_lock, flags);
1049
1050 return ret;
1051 }
1052
1053 static const struct pinconf_ops byt_pinconf_ops = {
1054 .is_generic = true,
1055 .pin_config_get = byt_pin_config_get,
1056 .pin_config_set = byt_pin_config_set,
1057 };
1058
1059 static const struct pinctrl_desc byt_pinctrl_desc = {
1060 .pctlops = &byt_pinctrl_ops,
1061 .pmxops = &byt_pinmux_ops,
1062 .confops = &byt_pinconf_ops,
1063 .owner = THIS_MODULE,
1064 };
1065
byt_gpio_get(struct gpio_chip * chip,unsigned int offset)1066 static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset)
1067 {
1068 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1069 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1070 unsigned long flags;
1071 u32 val;
1072
1073 raw_spin_lock_irqsave(&byt_lock, flags);
1074 val = readl(reg);
1075 raw_spin_unlock_irqrestore(&byt_lock, flags);
1076
1077 return !!(val & BYT_LEVEL);
1078 }
1079
byt_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)1080 static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
1081 {
1082 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1083 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1084 unsigned long flags;
1085 u32 old_val;
1086
1087 if (!reg)
1088 return;
1089
1090 raw_spin_lock_irqsave(&byt_lock, flags);
1091 old_val = readl(reg);
1092 if (value)
1093 writel(old_val | BYT_LEVEL, reg);
1094 else
1095 writel(old_val & ~BYT_LEVEL, reg);
1096 raw_spin_unlock_irqrestore(&byt_lock, flags);
1097 }
1098
byt_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)1099 static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1100 {
1101 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1102 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1103 unsigned long flags;
1104 u32 value;
1105
1106 if (!reg)
1107 return -EINVAL;
1108
1109 raw_spin_lock_irqsave(&byt_lock, flags);
1110 value = readl(reg);
1111 raw_spin_unlock_irqrestore(&byt_lock, flags);
1112
1113 if (!(value & BYT_OUTPUT_EN))
1114 return GPIO_LINE_DIRECTION_OUT;
1115 if (!(value & BYT_INPUT_EN))
1116 return GPIO_LINE_DIRECTION_IN;
1117
1118 return -EINVAL;
1119 }
1120
byt_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)1121 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1122 {
1123 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1124 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1125 unsigned long flags;
1126 u32 reg;
1127
1128 raw_spin_lock_irqsave(&byt_lock, flags);
1129
1130 reg = readl(val_reg);
1131 reg &= ~BYT_DIR_MASK;
1132 reg |= BYT_OUTPUT_EN;
1133 writel(reg, val_reg);
1134
1135 raw_spin_unlock_irqrestore(&byt_lock, flags);
1136 return 0;
1137 }
1138
1139 /*
1140 * Note despite the temptation this MUST NOT be converted into a call to
1141 * pinctrl_gpio_direction_output() + byt_gpio_set() that does not work this
1142 * MUST be done as a single BYT_VAL_REG register write.
1143 * See the commit message of the commit adding this comment for details.
1144 */
byt_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)1145 static int byt_gpio_direction_output(struct gpio_chip *chip,
1146 unsigned int offset, int value)
1147 {
1148 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1149 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1150 unsigned long flags;
1151 u32 reg;
1152
1153 raw_spin_lock_irqsave(&byt_lock, flags);
1154
1155 byt_gpio_direct_irq_check(vg, offset);
1156
1157 reg = readl(val_reg);
1158 reg &= ~BYT_DIR_MASK;
1159 if (value)
1160 reg |= BYT_LEVEL;
1161 else
1162 reg &= ~BYT_LEVEL;
1163
1164 writel(reg, val_reg);
1165
1166 raw_spin_unlock_irqrestore(&byt_lock, flags);
1167 return 0;
1168 }
1169
byt_gpio_dbg_show(struct seq_file * s,struct gpio_chip * chip)1170 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1171 {
1172 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1173 int i;
1174 u32 conf0, val;
1175
1176 for (i = 0; i < vg->soc->npins; i++) {
1177 const struct intel_community *comm;
1178 void __iomem *conf_reg, *val_reg;
1179 const char *pull_str = NULL;
1180 const char *pull = NULL;
1181 unsigned long flags;
1182 const char *label;
1183 unsigned int pin;
1184
1185 pin = vg->soc->pins[i].number;
1186
1187 conf_reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1188 if (!conf_reg) {
1189 seq_printf(s, "Pin %i: can't retrieve CONF0\n", pin);
1190 continue;
1191 }
1192
1193 val_reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1194 if (!val_reg) {
1195 seq_printf(s, "Pin %i: can't retrieve VAL\n", pin);
1196 continue;
1197 }
1198
1199 raw_spin_lock_irqsave(&byt_lock, flags);
1200 conf0 = readl(conf_reg);
1201 val = readl(val_reg);
1202 raw_spin_unlock_irqrestore(&byt_lock, flags);
1203
1204 comm = intel_get_community(vg, pin);
1205 if (!comm) {
1206 seq_printf(s, "Pin %i: can't retrieve community\n", pin);
1207 continue;
1208 }
1209 label = gpiochip_is_requested(chip, i);
1210 if (!label)
1211 label = "Unrequested";
1212
1213 switch (conf0 & BYT_PULL_ASSIGN_MASK) {
1214 case BYT_PULL_ASSIGN_UP:
1215 pull = "up";
1216 break;
1217 case BYT_PULL_ASSIGN_DOWN:
1218 pull = "down";
1219 break;
1220 }
1221
1222 switch (conf0 & BYT_PULL_STR_MASK) {
1223 case BYT_PULL_STR_2K:
1224 pull_str = "2k";
1225 break;
1226 case BYT_PULL_STR_10K:
1227 pull_str = "10k";
1228 break;
1229 case BYT_PULL_STR_20K:
1230 pull_str = "20k";
1231 break;
1232 case BYT_PULL_STR_40K:
1233 pull_str = "40k";
1234 break;
1235 }
1236
1237 seq_printf(s,
1238 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
1239 pin,
1240 label,
1241 val & BYT_INPUT_EN ? " " : "in",
1242 val & BYT_OUTPUT_EN ? " " : "out",
1243 str_hi_lo(val & BYT_LEVEL),
1244 comm->pad_map[i], comm->pad_map[i] * 16,
1245 conf0 & 0x7,
1246 conf0 & BYT_TRIG_NEG ? " fall" : " ",
1247 conf0 & BYT_TRIG_POS ? " rise" : " ",
1248 conf0 & BYT_TRIG_LVL ? " level" : " ");
1249
1250 if (pull && pull_str)
1251 seq_printf(s, " %-4s %-3s", pull, pull_str);
1252 else
1253 seq_puts(s, " ");
1254
1255 if (conf0 & BYT_IODEN)
1256 seq_puts(s, " open-drain");
1257
1258 seq_puts(s, "\n");
1259 }
1260 }
1261
1262 static const struct gpio_chip byt_gpio_chip = {
1263 .owner = THIS_MODULE,
1264 .request = gpiochip_generic_request,
1265 .free = gpiochip_generic_free,
1266 .get_direction = byt_gpio_get_direction,
1267 .direction_input = byt_gpio_direction_input,
1268 .direction_output = byt_gpio_direction_output,
1269 .get = byt_gpio_get,
1270 .set = byt_gpio_set,
1271 .set_config = gpiochip_generic_config,
1272 .dbg_show = byt_gpio_dbg_show,
1273 };
1274
byt_irq_ack(struct irq_data * d)1275 static void byt_irq_ack(struct irq_data *d)
1276 {
1277 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1278 struct intel_pinctrl *vg = gpiochip_get_data(gc);
1279 irq_hw_number_t hwirq = irqd_to_hwirq(d);
1280 void __iomem *reg;
1281
1282 reg = byt_gpio_reg(vg, hwirq, BYT_INT_STAT_REG);
1283 if (!reg)
1284 return;
1285
1286 raw_spin_lock(&byt_lock);
1287 writel(BIT(hwirq % 32), reg);
1288 raw_spin_unlock(&byt_lock);
1289 }
1290
byt_irq_mask(struct irq_data * d)1291 static void byt_irq_mask(struct irq_data *d)
1292 {
1293 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1294 struct intel_pinctrl *vg = gpiochip_get_data(gc);
1295 irq_hw_number_t hwirq = irqd_to_hwirq(d);
1296
1297 byt_gpio_clear_triggering(vg, hwirq);
1298 gpiochip_disable_irq(gc, hwirq);
1299 }
1300
byt_irq_unmask(struct irq_data * d)1301 static void byt_irq_unmask(struct irq_data *d)
1302 {
1303 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1304 struct intel_pinctrl *vg = gpiochip_get_data(gc);
1305 irq_hw_number_t hwirq = irqd_to_hwirq(d);
1306 unsigned long flags;
1307 void __iomem *reg;
1308 u32 value;
1309
1310 gpiochip_enable_irq(gc, hwirq);
1311
1312 reg = byt_gpio_reg(vg, hwirq, BYT_CONF0_REG);
1313 if (!reg)
1314 return;
1315
1316 raw_spin_lock_irqsave(&byt_lock, flags);
1317 value = readl(reg);
1318
1319 switch (irqd_get_trigger_type(d)) {
1320 case IRQ_TYPE_LEVEL_HIGH:
1321 value |= BYT_TRIG_LVL;
1322 fallthrough;
1323 case IRQ_TYPE_EDGE_RISING:
1324 value |= BYT_TRIG_POS;
1325 break;
1326 case IRQ_TYPE_LEVEL_LOW:
1327 value |= BYT_TRIG_LVL;
1328 fallthrough;
1329 case IRQ_TYPE_EDGE_FALLING:
1330 value |= BYT_TRIG_NEG;
1331 break;
1332 case IRQ_TYPE_EDGE_BOTH:
1333 value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
1334 break;
1335 }
1336
1337 writel(value, reg);
1338
1339 raw_spin_unlock_irqrestore(&byt_lock, flags);
1340 }
1341
byt_irq_type(struct irq_data * d,unsigned int type)1342 static int byt_irq_type(struct irq_data *d, unsigned int type)
1343 {
1344 struct intel_pinctrl *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
1345 irq_hw_number_t hwirq = irqd_to_hwirq(d);
1346 u32 value;
1347 unsigned long flags;
1348 void __iomem *reg;
1349
1350 reg = byt_gpio_reg(vg, hwirq, BYT_CONF0_REG);
1351 if (!reg)
1352 return -EINVAL;
1353
1354 raw_spin_lock_irqsave(&byt_lock, flags);
1355 value = readl(reg);
1356
1357 WARN(value & BYT_DIRECT_IRQ_EN,
1358 "Bad pad config for IO mode, force DIRECT_IRQ_EN bit clearing");
1359
1360 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
1361 * are used to indicate high and low level triggering
1362 */
1363 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
1364 BYT_TRIG_LVL);
1365 /* Enable glitch filtering */
1366 value |= BYT_GLITCH_FILTER_EN | BYT_GLITCH_F_SLOW_CLK |
1367 BYT_GLITCH_F_FAST_CLK;
1368
1369 writel(value, reg);
1370
1371 if (type & IRQ_TYPE_EDGE_BOTH)
1372 irq_set_handler_locked(d, handle_edge_irq);
1373 else if (type & IRQ_TYPE_LEVEL_MASK)
1374 irq_set_handler_locked(d, handle_level_irq);
1375
1376 raw_spin_unlock_irqrestore(&byt_lock, flags);
1377
1378 return 0;
1379 }
1380
1381 static const struct irq_chip byt_gpio_irq_chip = {
1382 .name = "BYT-GPIO",
1383 .irq_ack = byt_irq_ack,
1384 .irq_mask = byt_irq_mask,
1385 .irq_unmask = byt_irq_unmask,
1386 .irq_set_type = byt_irq_type,
1387 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE,
1388 GPIOCHIP_IRQ_RESOURCE_HELPERS,
1389 };
1390
byt_gpio_irq_handler(struct irq_desc * desc)1391 static void byt_gpio_irq_handler(struct irq_desc *desc)
1392 {
1393 struct irq_data *data = irq_desc_get_irq_data(desc);
1394 struct intel_pinctrl *vg = gpiochip_get_data(irq_desc_get_handler_data(desc));
1395 struct irq_chip *chip = irq_data_get_irq_chip(data);
1396 u32 base, pin;
1397 void __iomem *reg;
1398 unsigned long pending;
1399
1400 /* check from GPIO controller which pin triggered the interrupt */
1401 for (base = 0; base < vg->chip.ngpio; base += 32) {
1402 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1403
1404 if (!reg) {
1405 dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base);
1406 continue;
1407 }
1408
1409 raw_spin_lock(&byt_lock);
1410 pending = readl(reg);
1411 raw_spin_unlock(&byt_lock);
1412 for_each_set_bit(pin, &pending, 32)
1413 generic_handle_domain_irq(vg->chip.irq.domain, base + pin);
1414 }
1415 chip->irq_eoi(data);
1416 }
1417
byt_direct_irq_sanity_check(struct intel_pinctrl * vg,int pin,u32 conf0)1418 static bool byt_direct_irq_sanity_check(struct intel_pinctrl *vg, int pin, u32 conf0)
1419 {
1420 int direct_irq, ioapic_direct_irq_base;
1421 u8 *match, direct_irq_mux[16];
1422 u32 trig;
1423
1424 memcpy_fromio(direct_irq_mux, vg->communities->pad_regs + BYT_DIRECT_IRQ_REG,
1425 sizeof(direct_irq_mux));
1426 match = memchr(direct_irq_mux, pin, sizeof(direct_irq_mux));
1427 if (!match) {
1428 dev_warn(vg->dev, FW_BUG "Pin %i: DIRECT_IRQ_EN set but no IRQ assigned, clearing\n", pin);
1429 return false;
1430 }
1431
1432 direct_irq = match - direct_irq_mux;
1433 /* Base IO-APIC pin numbers come from atom-e3800-family-datasheet.pdf */
1434 ioapic_direct_irq_base = (vg->communities->npins == BYT_NGPIO_SCORE) ? 51 : 67;
1435 dev_dbg(vg->dev, "Pin %i: uses direct IRQ %d (IO-APIC %d)\n", pin,
1436 direct_irq, direct_irq + ioapic_direct_irq_base);
1437
1438 /*
1439 * Testing has shown that the way direct IRQs work is that the combination of the
1440 * direct-irq-en flag and the direct IRQ mux connect the output of the GPIO's IRQ
1441 * trigger block, which normally sets the status flag in the IRQ status reg at
1442 * 0x800, to one of the IO-APIC pins according to the mux registers.
1443 *
1444 * This means that:
1445 * 1. The TRIG_MASK bits must be set to configure the GPIO's IRQ trigger block
1446 * 2. The TRIG_LVL bit *must* be set, so that the GPIO's input value is directly
1447 * passed (1:1 or inverted) to the IO-APIC pin, if TRIG_LVL is not set,
1448 * selecting edge mode operation then on the first edge the IO-APIC pin goes
1449 * high, but since no write-to-clear write will be done to the IRQ status reg
1450 * at 0x800, the detected edge condition will never get cleared.
1451 */
1452 trig = conf0 & BYT_TRIG_MASK;
1453 if (trig != (BYT_TRIG_POS | BYT_TRIG_LVL) &&
1454 trig != (BYT_TRIG_NEG | BYT_TRIG_LVL)) {
1455 dev_warn(vg->dev,
1456 FW_BUG "Pin %i: DIRECT_IRQ_EN set without trigger (CONF0: %#08x), clearing\n",
1457 pin, conf0);
1458 return false;
1459 }
1460
1461 return true;
1462 }
1463
byt_init_irq_valid_mask(struct gpio_chip * chip,unsigned long * valid_mask,unsigned int ngpios)1464 static void byt_init_irq_valid_mask(struct gpio_chip *chip,
1465 unsigned long *valid_mask,
1466 unsigned int ngpios)
1467 {
1468 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1469 void __iomem *reg;
1470 u32 value;
1471 int i;
1472
1473 /*
1474 * Clear interrupt triggers for all pins that are GPIOs and
1475 * do not use direct IRQ mode. This will prevent spurious
1476 * interrupts from misconfigured pins.
1477 */
1478 for (i = 0; i < vg->soc->npins; i++) {
1479 unsigned int pin = vg->soc->pins[i].number;
1480
1481 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1482 if (!reg) {
1483 dev_warn(vg->dev, "Pin %i: could not retrieve CONF0\n", i);
1484 continue;
1485 }
1486
1487 value = readl(reg);
1488 if (value & BYT_DIRECT_IRQ_EN) {
1489 if (byt_direct_irq_sanity_check(vg, i, value)) {
1490 clear_bit(i, valid_mask);
1491 } else {
1492 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS |
1493 BYT_TRIG_NEG | BYT_TRIG_LVL);
1494 writel(value, reg);
1495 }
1496 } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
1497 byt_gpio_clear_triggering(vg, i);
1498 dev_dbg(vg->dev, "disabling GPIO %d\n", i);
1499 }
1500 }
1501 }
1502
byt_gpio_irq_init_hw(struct gpio_chip * chip)1503 static int byt_gpio_irq_init_hw(struct gpio_chip *chip)
1504 {
1505 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1506 void __iomem *reg;
1507 u32 base, value;
1508
1509 /* clear interrupt status trigger registers */
1510 for (base = 0; base < vg->soc->npins; base += 32) {
1511 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1512
1513 if (!reg) {
1514 dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base);
1515 continue;
1516 }
1517
1518 writel(0xffffffff, reg);
1519 /* make sure trigger bits are cleared, if not then a pin
1520 might be misconfigured in bios */
1521 value = readl(reg);
1522 if (value)
1523 dev_err(vg->dev,
1524 "GPIO interrupt error, pins misconfigured. INT_STAT%u: %#08x\n",
1525 base / 32, value);
1526 }
1527
1528 return 0;
1529 }
1530
byt_gpio_add_pin_ranges(struct gpio_chip * chip)1531 static int byt_gpio_add_pin_ranges(struct gpio_chip *chip)
1532 {
1533 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1534 struct device *dev = vg->dev;
1535 int ret;
1536
1537 ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins);
1538 if (ret)
1539 dev_err(dev, "failed to add GPIO pin range\n");
1540
1541 return ret;
1542 }
1543
byt_gpio_probe(struct intel_pinctrl * vg)1544 static int byt_gpio_probe(struct intel_pinctrl *vg)
1545 {
1546 struct platform_device *pdev = to_platform_device(vg->dev);
1547 struct gpio_chip *gc;
1548 int irq, ret;
1549
1550 /* Set up gpio chip */
1551 vg->chip = byt_gpio_chip;
1552 gc = &vg->chip;
1553 gc->label = dev_name(vg->dev);
1554 gc->base = -1;
1555 gc->can_sleep = false;
1556 gc->add_pin_ranges = byt_gpio_add_pin_ranges;
1557 gc->parent = vg->dev;
1558 gc->ngpio = vg->soc->npins;
1559
1560 #ifdef CONFIG_PM_SLEEP
1561 vg->context.pads = devm_kcalloc(vg->dev, gc->ngpio, sizeof(*vg->context.pads),
1562 GFP_KERNEL);
1563 if (!vg->context.pads)
1564 return -ENOMEM;
1565 #endif
1566
1567 /* set up interrupts */
1568 irq = platform_get_irq_optional(pdev, 0);
1569 if (irq > 0) {
1570 struct gpio_irq_chip *girq;
1571
1572 girq = &gc->irq;
1573 gpio_irq_chip_set_chip(girq, &byt_gpio_irq_chip);
1574 girq->init_hw = byt_gpio_irq_init_hw;
1575 girq->init_valid_mask = byt_init_irq_valid_mask;
1576 girq->parent_handler = byt_gpio_irq_handler;
1577 girq->num_parents = 1;
1578 girq->parents = devm_kcalloc(vg->dev, girq->num_parents,
1579 sizeof(*girq->parents), GFP_KERNEL);
1580 if (!girq->parents)
1581 return -ENOMEM;
1582 girq->parents[0] = irq;
1583 girq->default_type = IRQ_TYPE_NONE;
1584 girq->handler = handle_bad_irq;
1585 }
1586
1587 ret = devm_gpiochip_add_data(vg->dev, gc, vg);
1588 if (ret) {
1589 dev_err(vg->dev, "failed adding byt-gpio chip\n");
1590 return ret;
1591 }
1592
1593 return ret;
1594 }
1595
byt_set_soc_data(struct intel_pinctrl * vg,const struct intel_pinctrl_soc_data * soc)1596 static int byt_set_soc_data(struct intel_pinctrl *vg,
1597 const struct intel_pinctrl_soc_data *soc)
1598 {
1599 struct platform_device *pdev = to_platform_device(vg->dev);
1600 int i;
1601
1602 vg->soc = soc;
1603
1604 vg->ncommunities = vg->soc->ncommunities;
1605 vg->communities = devm_kcalloc(vg->dev, vg->ncommunities,
1606 sizeof(*vg->communities), GFP_KERNEL);
1607 if (!vg->communities)
1608 return -ENOMEM;
1609
1610 for (i = 0; i < vg->soc->ncommunities; i++) {
1611 struct intel_community *comm = vg->communities + i;
1612
1613 *comm = vg->soc->communities[i];
1614
1615 comm->pad_regs = devm_platform_ioremap_resource(pdev, 0);
1616 if (IS_ERR(comm->pad_regs))
1617 return PTR_ERR(comm->pad_regs);
1618 }
1619
1620 return 0;
1621 }
1622
1623 static const struct acpi_device_id byt_gpio_acpi_match[] = {
1624 { "INT33B2", (kernel_ulong_t)byt_soc_data },
1625 { "INT33FC", (kernel_ulong_t)byt_soc_data },
1626 { }
1627 };
1628
byt_pinctrl_probe(struct platform_device * pdev)1629 static int byt_pinctrl_probe(struct platform_device *pdev)
1630 {
1631 const struct intel_pinctrl_soc_data *soc_data;
1632 struct device *dev = &pdev->dev;
1633 struct intel_pinctrl *vg;
1634 int ret;
1635
1636 soc_data = intel_pinctrl_get_soc_data(pdev);
1637 if (IS_ERR(soc_data))
1638 return PTR_ERR(soc_data);
1639
1640 vg = devm_kzalloc(dev, sizeof(*vg), GFP_KERNEL);
1641 if (!vg)
1642 return -ENOMEM;
1643
1644 vg->dev = dev;
1645 ret = byt_set_soc_data(vg, soc_data);
1646 if (ret) {
1647 dev_err(dev, "failed to set soc data\n");
1648 return ret;
1649 }
1650
1651 vg->pctldesc = byt_pinctrl_desc;
1652 vg->pctldesc.name = dev_name(dev);
1653 vg->pctldesc.pins = vg->soc->pins;
1654 vg->pctldesc.npins = vg->soc->npins;
1655
1656 vg->pctldev = devm_pinctrl_register(dev, &vg->pctldesc, vg);
1657 if (IS_ERR(vg->pctldev)) {
1658 dev_err(dev, "failed to register pinctrl driver\n");
1659 return PTR_ERR(vg->pctldev);
1660 }
1661
1662 ret = byt_gpio_probe(vg);
1663 if (ret)
1664 return ret;
1665
1666 platform_set_drvdata(pdev, vg);
1667 pm_runtime_enable(dev);
1668
1669 return 0;
1670 }
1671
byt_gpio_suspend(struct device * dev)1672 static int byt_gpio_suspend(struct device *dev)
1673 {
1674 struct intel_pinctrl *vg = dev_get_drvdata(dev);
1675 unsigned long flags;
1676 int i;
1677
1678 raw_spin_lock_irqsave(&byt_lock, flags);
1679
1680 for (i = 0; i < vg->soc->npins; i++) {
1681 void __iomem *reg;
1682 u32 value;
1683 unsigned int pin = vg->soc->pins[i].number;
1684
1685 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1686 if (!reg) {
1687 dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i);
1688 continue;
1689 }
1690 value = readl(reg) & BYT_CONF0_RESTORE_MASK;
1691 vg->context.pads[i].conf0 = value;
1692
1693 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1694 if (!reg) {
1695 dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n", i);
1696 continue;
1697 }
1698 value = readl(reg) & BYT_VAL_RESTORE_MASK;
1699 vg->context.pads[i].val = value;
1700 }
1701
1702 raw_spin_unlock_irqrestore(&byt_lock, flags);
1703 return 0;
1704 }
1705
byt_gpio_resume(struct device * dev)1706 static int byt_gpio_resume(struct device *dev)
1707 {
1708 struct intel_pinctrl *vg = dev_get_drvdata(dev);
1709 unsigned long flags;
1710 int i;
1711
1712 raw_spin_lock_irqsave(&byt_lock, flags);
1713
1714 for (i = 0; i < vg->soc->npins; i++) {
1715 void __iomem *reg;
1716 u32 value;
1717 unsigned int pin = vg->soc->pins[i].number;
1718
1719 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1720 if (!reg) {
1721 dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i);
1722 continue;
1723 }
1724 value = readl(reg);
1725 if ((value & BYT_CONF0_RESTORE_MASK) !=
1726 vg->context.pads[i].conf0) {
1727 value &= ~BYT_CONF0_RESTORE_MASK;
1728 value |= vg->context.pads[i].conf0;
1729 writel(value, reg);
1730 dev_info(dev, "restored pin %d CONF0 %#08x", i, value);
1731 }
1732
1733 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1734 if (!reg) {
1735 dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n", i);
1736 continue;
1737 }
1738 value = readl(reg);
1739 if ((value & BYT_VAL_RESTORE_MASK) !=
1740 vg->context.pads[i].val) {
1741 u32 v;
1742
1743 v = value & ~BYT_VAL_RESTORE_MASK;
1744 v |= vg->context.pads[i].val;
1745 if (v != value) {
1746 writel(v, reg);
1747 dev_dbg(dev, "restored pin %d VAL %#08x\n", i, v);
1748 }
1749 }
1750 }
1751
1752 raw_spin_unlock_irqrestore(&byt_lock, flags);
1753 return 0;
1754 }
1755
byt_gpio_runtime_suspend(struct device * dev)1756 static int byt_gpio_runtime_suspend(struct device *dev)
1757 {
1758 return 0;
1759 }
1760
byt_gpio_runtime_resume(struct device * dev)1761 static int byt_gpio_runtime_resume(struct device *dev)
1762 {
1763 return 0;
1764 }
1765
1766 static const struct dev_pm_ops byt_gpio_pm_ops = {
1767 LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume)
1768 RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume, NULL)
1769 };
1770
1771 static struct platform_driver byt_gpio_driver = {
1772 .probe = byt_pinctrl_probe,
1773 .driver = {
1774 .name = "byt_gpio",
1775 .pm = pm_ptr(&byt_gpio_pm_ops),
1776 .acpi_match_table = byt_gpio_acpi_match,
1777 .suppress_bind_attrs = true,
1778 },
1779 };
1780
byt_gpio_init(void)1781 static int __init byt_gpio_init(void)
1782 {
1783 return platform_driver_register(&byt_gpio_driver);
1784 }
1785 subsys_initcall(byt_gpio_init);
1786
1787 MODULE_IMPORT_NS(PINCTRL_INTEL);
1788