1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Pinctrl GPIO driver for Intel Baytrail 4 * 5 * Copyright (c) 2012-2013, Intel Corporation 6 * Author: Mathias Nyman <mathias.nyman@linux.intel.com> 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/bitops.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/types.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/property.h> 20 #include <linux/seq_file.h> 21 22 #include <linux/pinctrl/pinctrl.h> 23 #include <linux/pinctrl/pinmux.h> 24 #include <linux/pinctrl/pinconf.h> 25 #include <linux/pinctrl/pinconf-generic.h> 26 27 /* memory mapped register offsets */ 28 #define BYT_CONF0_REG 0x000 29 #define BYT_CONF1_REG 0x004 30 #define BYT_VAL_REG 0x008 31 #define BYT_DFT_REG 0x00c 32 #define BYT_INT_STAT_REG 0x800 33 #define BYT_DEBOUNCE_REG 0x9d0 34 35 /* BYT_CONF0_REG register bits */ 36 #define BYT_IODEN BIT(31) 37 #define BYT_DIRECT_IRQ_EN BIT(27) 38 #define BYT_TRIG_NEG BIT(26) 39 #define BYT_TRIG_POS BIT(25) 40 #define BYT_TRIG_LVL BIT(24) 41 #define BYT_DEBOUNCE_EN BIT(20) 42 #define BYT_GLITCH_FILTER_EN BIT(19) 43 #define BYT_GLITCH_F_SLOW_CLK BIT(17) 44 #define BYT_GLITCH_F_FAST_CLK BIT(16) 45 #define BYT_PULL_STR_SHIFT 9 46 #define BYT_PULL_STR_MASK (3 << BYT_PULL_STR_SHIFT) 47 #define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT) 48 #define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT) 49 #define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT) 50 #define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT) 51 #define BYT_PULL_ASSIGN_SHIFT 7 52 #define BYT_PULL_ASSIGN_MASK (3 << BYT_PULL_ASSIGN_SHIFT) 53 #define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT) 54 #define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT) 55 #define BYT_PIN_MUX 0x07 56 57 /* BYT_VAL_REG register bits */ 58 #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/ 59 #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/ 60 #define BYT_LEVEL BIT(0) 61 62 #define BYT_DIR_MASK (BIT(1) | BIT(2)) 63 #define BYT_TRIG_MASK (BIT(26) | BIT(25) | BIT(24)) 64 65 #define BYT_CONF0_RESTORE_MASK (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | \ 66 BYT_PIN_MUX) 67 #define BYT_VAL_RESTORE_MASK (BYT_DIR_MASK | BYT_LEVEL) 68 69 /* BYT_DEBOUNCE_REG bits */ 70 #define BYT_DEBOUNCE_PULSE_MASK 0x7 71 #define BYT_DEBOUNCE_PULSE_375US 1 72 #define BYT_DEBOUNCE_PULSE_750US 2 73 #define BYT_DEBOUNCE_PULSE_1500US 3 74 #define BYT_DEBOUNCE_PULSE_3MS 4 75 #define BYT_DEBOUNCE_PULSE_6MS 5 76 #define BYT_DEBOUNCE_PULSE_12MS 6 77 #define BYT_DEBOUNCE_PULSE_24MS 7 78 79 #define BYT_NGPIO_SCORE 102 80 #define BYT_NGPIO_NCORE 28 81 #define BYT_NGPIO_SUS 44 82 83 #define BYT_SCORE_ACPI_UID "1" 84 #define BYT_NCORE_ACPI_UID "2" 85 #define BYT_SUS_ACPI_UID "3" 86 87 /* 88 * This is the function value most pins have for GPIO muxing. If the value 89 * differs from the default one, it must be explicitly mentioned. Otherwise, the 90 * pin control implementation will set the muxing value to default GPIO if it 91 * does not find a match for the requested function. 92 */ 93 #define BYT_DEFAULT_GPIO_MUX 0 94 95 struct byt_gpio_pin_context { 96 u32 conf0; 97 u32 val; 98 }; 99 100 struct byt_simple_func_mux { 101 const char *name; 102 unsigned short func; 103 }; 104 105 struct byt_mixed_func_mux { 106 const char *name; 107 const unsigned short *func_values; 108 }; 109 110 struct byt_pingroup { 111 const char *name; 112 const unsigned int *pins; 113 size_t npins; 114 unsigned short has_simple_funcs; 115 union { 116 const struct byt_simple_func_mux *simple_funcs; 117 const struct byt_mixed_func_mux *mixed_funcs; 118 }; 119 size_t nfuncs; 120 }; 121 122 struct byt_function { 123 const char *name; 124 const char * const *groups; 125 size_t ngroups; 126 }; 127 128 struct byt_community { 129 unsigned int pin_base; 130 size_t npins; 131 const unsigned int *pad_map; 132 void __iomem *reg_base; 133 }; 134 135 #define SIMPLE_FUNC(n, f) \ 136 { \ 137 .name = (n), \ 138 .func = (f), \ 139 } 140 #define MIXED_FUNC(n, f) \ 141 { \ 142 .name = (n), \ 143 .func_values = (f), \ 144 } 145 146 #define PIN_GROUP_SIMPLE(n, p, f) \ 147 { \ 148 .name = (n), \ 149 .pins = (p), \ 150 .npins = ARRAY_SIZE((p)), \ 151 .has_simple_funcs = 1, \ 152 { \ 153 .simple_funcs = (f), \ 154 }, \ 155 .nfuncs = ARRAY_SIZE((f)), \ 156 } 157 #define PIN_GROUP_MIXED(n, p, f) \ 158 { \ 159 .name = (n), \ 160 .pins = (p), \ 161 .npins = ARRAY_SIZE((p)), \ 162 .has_simple_funcs = 0, \ 163 { \ 164 .mixed_funcs = (f), \ 165 }, \ 166 .nfuncs = ARRAY_SIZE((f)), \ 167 } 168 169 #define FUNCTION(n, g) \ 170 { \ 171 .name = (n), \ 172 .groups = (g), \ 173 .ngroups = ARRAY_SIZE((g)), \ 174 } 175 176 #define COMMUNITY(p, n, map) \ 177 { \ 178 .pin_base = (p), \ 179 .npins = (n), \ 180 .pad_map = (map),\ 181 } 182 183 struct byt_pinctrl_soc_data { 184 const char *uid; 185 const struct pinctrl_pin_desc *pins; 186 size_t npins; 187 const struct byt_pingroup *groups; 188 size_t ngroups; 189 const struct byt_function *functions; 190 size_t nfunctions; 191 const struct byt_community *communities; 192 size_t ncommunities; 193 }; 194 195 struct byt_gpio { 196 struct gpio_chip chip; 197 struct platform_device *pdev; 198 struct pinctrl_dev *pctl_dev; 199 struct pinctrl_desc pctl_desc; 200 raw_spinlock_t lock; 201 const struct byt_pinctrl_soc_data *soc_data; 202 struct byt_community *communities_copy; 203 struct byt_gpio_pin_context *saved_context; 204 }; 205 206 /* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */ 207 static const struct pinctrl_pin_desc byt_score_pins[] = { 208 PINCTRL_PIN(0, "SATA_GP0"), 209 PINCTRL_PIN(1, "SATA_GP1"), 210 PINCTRL_PIN(2, "SATA_LED#"), 211 PINCTRL_PIN(3, "PCIE_CLKREQ0"), 212 PINCTRL_PIN(4, "PCIE_CLKREQ1"), 213 PINCTRL_PIN(5, "PCIE_CLKREQ2"), 214 PINCTRL_PIN(6, "PCIE_CLKREQ3"), 215 PINCTRL_PIN(7, "SD3_WP"), 216 PINCTRL_PIN(8, "HDA_RST"), 217 PINCTRL_PIN(9, "HDA_SYNC"), 218 PINCTRL_PIN(10, "HDA_CLK"), 219 PINCTRL_PIN(11, "HDA_SDO"), 220 PINCTRL_PIN(12, "HDA_SDI0"), 221 PINCTRL_PIN(13, "HDA_SDI1"), 222 PINCTRL_PIN(14, "GPIO_S0_SC14"), 223 PINCTRL_PIN(15, "GPIO_S0_SC15"), 224 PINCTRL_PIN(16, "MMC1_CLK"), 225 PINCTRL_PIN(17, "MMC1_D0"), 226 PINCTRL_PIN(18, "MMC1_D1"), 227 PINCTRL_PIN(19, "MMC1_D2"), 228 PINCTRL_PIN(20, "MMC1_D3"), 229 PINCTRL_PIN(21, "MMC1_D4"), 230 PINCTRL_PIN(22, "MMC1_D5"), 231 PINCTRL_PIN(23, "MMC1_D6"), 232 PINCTRL_PIN(24, "MMC1_D7"), 233 PINCTRL_PIN(25, "MMC1_CMD"), 234 PINCTRL_PIN(26, "MMC1_RST"), 235 PINCTRL_PIN(27, "SD2_CLK"), 236 PINCTRL_PIN(28, "SD2_D0"), 237 PINCTRL_PIN(29, "SD2_D1"), 238 PINCTRL_PIN(30, "SD2_D2"), 239 PINCTRL_PIN(31, "SD2_D3_CD"), 240 PINCTRL_PIN(32, "SD2_CMD"), 241 PINCTRL_PIN(33, "SD3_CLK"), 242 PINCTRL_PIN(34, "SD3_D0"), 243 PINCTRL_PIN(35, "SD3_D1"), 244 PINCTRL_PIN(36, "SD3_D2"), 245 PINCTRL_PIN(37, "SD3_D3"), 246 PINCTRL_PIN(38, "SD3_CD"), 247 PINCTRL_PIN(39, "SD3_CMD"), 248 PINCTRL_PIN(40, "SD3_1P8EN"), 249 PINCTRL_PIN(41, "SD3_PWREN#"), 250 PINCTRL_PIN(42, "ILB_LPC_AD0"), 251 PINCTRL_PIN(43, "ILB_LPC_AD1"), 252 PINCTRL_PIN(44, "ILB_LPC_AD2"), 253 PINCTRL_PIN(45, "ILB_LPC_AD3"), 254 PINCTRL_PIN(46, "ILB_LPC_FRAME"), 255 PINCTRL_PIN(47, "ILB_LPC_CLK0"), 256 PINCTRL_PIN(48, "ILB_LPC_CLK1"), 257 PINCTRL_PIN(49, "ILB_LPC_CLKRUN"), 258 PINCTRL_PIN(50, "ILB_LPC_SERIRQ"), 259 PINCTRL_PIN(51, "PCU_SMB_DATA"), 260 PINCTRL_PIN(52, "PCU_SMB_CLK"), 261 PINCTRL_PIN(53, "PCU_SMB_ALERT"), 262 PINCTRL_PIN(54, "ILB_8254_SPKR"), 263 PINCTRL_PIN(55, "GPIO_S0_SC55"), 264 PINCTRL_PIN(56, "GPIO_S0_SC56"), 265 PINCTRL_PIN(57, "GPIO_S0_SC57"), 266 PINCTRL_PIN(58, "GPIO_S0_SC58"), 267 PINCTRL_PIN(59, "GPIO_S0_SC59"), 268 PINCTRL_PIN(60, "GPIO_S0_SC60"), 269 PINCTRL_PIN(61, "GPIO_S0_SC61"), 270 PINCTRL_PIN(62, "LPE_I2S2_CLK"), 271 PINCTRL_PIN(63, "LPE_I2S2_FRM"), 272 PINCTRL_PIN(64, "LPE_I2S2_DATAIN"), 273 PINCTRL_PIN(65, "LPE_I2S2_DATAOUT"), 274 PINCTRL_PIN(66, "SIO_SPI_CS"), 275 PINCTRL_PIN(67, "SIO_SPI_MISO"), 276 PINCTRL_PIN(68, "SIO_SPI_MOSI"), 277 PINCTRL_PIN(69, "SIO_SPI_CLK"), 278 PINCTRL_PIN(70, "SIO_UART1_RXD"), 279 PINCTRL_PIN(71, "SIO_UART1_TXD"), 280 PINCTRL_PIN(72, "SIO_UART1_RTS"), 281 PINCTRL_PIN(73, "SIO_UART1_CTS"), 282 PINCTRL_PIN(74, "SIO_UART2_RXD"), 283 PINCTRL_PIN(75, "SIO_UART2_TXD"), 284 PINCTRL_PIN(76, "SIO_UART2_RTS"), 285 PINCTRL_PIN(77, "SIO_UART2_CTS"), 286 PINCTRL_PIN(78, "SIO_I2C0_DATA"), 287 PINCTRL_PIN(79, "SIO_I2C0_CLK"), 288 PINCTRL_PIN(80, "SIO_I2C1_DATA"), 289 PINCTRL_PIN(81, "SIO_I2C1_CLK"), 290 PINCTRL_PIN(82, "SIO_I2C2_DATA"), 291 PINCTRL_PIN(83, "SIO_I2C2_CLK"), 292 PINCTRL_PIN(84, "SIO_I2C3_DATA"), 293 PINCTRL_PIN(85, "SIO_I2C3_CLK"), 294 PINCTRL_PIN(86, "SIO_I2C4_DATA"), 295 PINCTRL_PIN(87, "SIO_I2C4_CLK"), 296 PINCTRL_PIN(88, "SIO_I2C5_DATA"), 297 PINCTRL_PIN(89, "SIO_I2C5_CLK"), 298 PINCTRL_PIN(90, "SIO_I2C6_DATA"), 299 PINCTRL_PIN(91, "SIO_I2C6_CLK"), 300 PINCTRL_PIN(92, "GPIO_S0_SC92"), 301 PINCTRL_PIN(93, "GPIO_S0_SC93"), 302 PINCTRL_PIN(94, "SIO_PWM0"), 303 PINCTRL_PIN(95, "SIO_PWM1"), 304 PINCTRL_PIN(96, "PMC_PLT_CLK0"), 305 PINCTRL_PIN(97, "PMC_PLT_CLK1"), 306 PINCTRL_PIN(98, "PMC_PLT_CLK2"), 307 PINCTRL_PIN(99, "PMC_PLT_CLK3"), 308 PINCTRL_PIN(100, "PMC_PLT_CLK4"), 309 PINCTRL_PIN(101, "PMC_PLT_CLK5"), 310 }; 311 312 static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = { 313 85, 89, 93, 96, 99, 102, 98, 101, 34, 37, 314 36, 38, 39, 35, 40, 84, 62, 61, 64, 59, 315 54, 56, 60, 55, 63, 57, 51, 50, 53, 47, 316 52, 49, 48, 43, 46, 41, 45, 42, 58, 44, 317 95, 105, 70, 68, 67, 66, 69, 71, 65, 72, 318 86, 90, 88, 92, 103, 77, 79, 83, 78, 81, 319 80, 82, 13, 12, 15, 14, 17, 18, 19, 16, 320 2, 1, 0, 4, 6, 7, 9, 8, 33, 32, 321 31, 30, 29, 27, 25, 28, 26, 23, 21, 20, 322 24, 22, 5, 3, 10, 11, 106, 87, 91, 104, 323 97, 100, 324 }; 325 326 /* SCORE groups */ 327 static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 }; 328 static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 }; 329 static const struct byt_simple_func_mux byt_score_uart_mux[] = { 330 SIMPLE_FUNC("uart", 1), 331 }; 332 333 static const unsigned int byt_score_pwm0_pins[] = { 94 }; 334 static const unsigned int byt_score_pwm1_pins[] = { 95 }; 335 static const struct byt_simple_func_mux byt_score_pwm_mux[] = { 336 SIMPLE_FUNC("pwm", 1), 337 }; 338 339 static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 }; 340 static const struct byt_simple_func_mux byt_score_spi_mux[] = { 341 SIMPLE_FUNC("spi", 1), 342 }; 343 344 static const unsigned int byt_score_i2c5_pins[] = { 88, 89 }; 345 static const unsigned int byt_score_i2c6_pins[] = { 90, 91 }; 346 static const unsigned int byt_score_i2c4_pins[] = { 86, 87 }; 347 static const unsigned int byt_score_i2c3_pins[] = { 84, 85 }; 348 static const unsigned int byt_score_i2c2_pins[] = { 82, 83 }; 349 static const unsigned int byt_score_i2c1_pins[] = { 80, 81 }; 350 static const unsigned int byt_score_i2c0_pins[] = { 78, 79 }; 351 static const struct byt_simple_func_mux byt_score_i2c_mux[] = { 352 SIMPLE_FUNC("i2c", 1), 353 }; 354 355 static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 }; 356 static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 }; 357 static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 }; 358 static const struct byt_simple_func_mux byt_score_ssp_mux[] = { 359 SIMPLE_FUNC("ssp", 1), 360 }; 361 362 static const unsigned int byt_score_sdcard_pins[] = { 363 7, 33, 34, 35, 36, 37, 38, 39, 40, 41, 364 }; 365 static const unsigned short byt_score_sdcard_mux_values[] = { 366 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 367 }; 368 static const struct byt_mixed_func_mux byt_score_sdcard_mux[] = { 369 MIXED_FUNC("sdcard", byt_score_sdcard_mux_values), 370 }; 371 372 static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 }; 373 static const struct byt_simple_func_mux byt_score_sdio_mux[] = { 374 SIMPLE_FUNC("sdio", 1), 375 }; 376 377 static const unsigned int byt_score_emmc_pins[] = { 378 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 379 }; 380 static const struct byt_simple_func_mux byt_score_emmc_mux[] = { 381 SIMPLE_FUNC("emmc", 1), 382 }; 383 384 static const unsigned int byt_score_ilb_lpc_pins[] = { 385 42, 43, 44, 45, 46, 47, 48, 49, 50, 386 }; 387 static const struct byt_simple_func_mux byt_score_lpc_mux[] = { 388 SIMPLE_FUNC("lpc", 1), 389 }; 390 391 static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 }; 392 static const struct byt_simple_func_mux byt_score_sata_mux[] = { 393 SIMPLE_FUNC("sata", 1), 394 }; 395 396 static const unsigned int byt_score_plt_clk0_pins[] = { 96 }; 397 static const unsigned int byt_score_plt_clk1_pins[] = { 97 }; 398 static const unsigned int byt_score_plt_clk2_pins[] = { 98 }; 399 static const unsigned int byt_score_plt_clk3_pins[] = { 99 }; 400 static const unsigned int byt_score_plt_clk4_pins[] = { 100 }; 401 static const unsigned int byt_score_plt_clk5_pins[] = { 101 }; 402 static const struct byt_simple_func_mux byt_score_plt_clk_mux[] = { 403 SIMPLE_FUNC("plt_clk", 1), 404 }; 405 406 static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 }; 407 static const struct byt_simple_func_mux byt_score_smbus_mux[] = { 408 SIMPLE_FUNC("smbus", 1), 409 }; 410 411 static const struct byt_pingroup byt_score_groups[] = { 412 PIN_GROUP_SIMPLE("uart1_grp", 413 byt_score_uart1_pins, byt_score_uart_mux), 414 PIN_GROUP_SIMPLE("uart2_grp", 415 byt_score_uart2_pins, byt_score_uart_mux), 416 PIN_GROUP_SIMPLE("pwm0_grp", 417 byt_score_pwm0_pins, byt_score_pwm_mux), 418 PIN_GROUP_SIMPLE("pwm1_grp", 419 byt_score_pwm1_pins, byt_score_pwm_mux), 420 PIN_GROUP_SIMPLE("ssp2_grp", 421 byt_score_ssp2_pins, byt_score_pwm_mux), 422 PIN_GROUP_SIMPLE("sio_spi_grp", 423 byt_score_sio_spi_pins, byt_score_spi_mux), 424 PIN_GROUP_SIMPLE("i2c5_grp", 425 byt_score_i2c5_pins, byt_score_i2c_mux), 426 PIN_GROUP_SIMPLE("i2c6_grp", 427 byt_score_i2c6_pins, byt_score_i2c_mux), 428 PIN_GROUP_SIMPLE("i2c4_grp", 429 byt_score_i2c4_pins, byt_score_i2c_mux), 430 PIN_GROUP_SIMPLE("i2c3_grp", 431 byt_score_i2c3_pins, byt_score_i2c_mux), 432 PIN_GROUP_SIMPLE("i2c2_grp", 433 byt_score_i2c2_pins, byt_score_i2c_mux), 434 PIN_GROUP_SIMPLE("i2c1_grp", 435 byt_score_i2c1_pins, byt_score_i2c_mux), 436 PIN_GROUP_SIMPLE("i2c0_grp", 437 byt_score_i2c0_pins, byt_score_i2c_mux), 438 PIN_GROUP_SIMPLE("ssp0_grp", 439 byt_score_ssp0_pins, byt_score_ssp_mux), 440 PIN_GROUP_SIMPLE("ssp1_grp", 441 byt_score_ssp1_pins, byt_score_ssp_mux), 442 PIN_GROUP_MIXED("sdcard_grp", 443 byt_score_sdcard_pins, byt_score_sdcard_mux), 444 PIN_GROUP_SIMPLE("sdio_grp", 445 byt_score_sdio_pins, byt_score_sdio_mux), 446 PIN_GROUP_SIMPLE("emmc_grp", 447 byt_score_emmc_pins, byt_score_emmc_mux), 448 PIN_GROUP_SIMPLE("lpc_grp", 449 byt_score_ilb_lpc_pins, byt_score_lpc_mux), 450 PIN_GROUP_SIMPLE("sata_grp", 451 byt_score_sata_pins, byt_score_sata_mux), 452 PIN_GROUP_SIMPLE("plt_clk0_grp", 453 byt_score_plt_clk0_pins, byt_score_plt_clk_mux), 454 PIN_GROUP_SIMPLE("plt_clk1_grp", 455 byt_score_plt_clk1_pins, byt_score_plt_clk_mux), 456 PIN_GROUP_SIMPLE("plt_clk2_grp", 457 byt_score_plt_clk2_pins, byt_score_plt_clk_mux), 458 PIN_GROUP_SIMPLE("plt_clk3_grp", 459 byt_score_plt_clk3_pins, byt_score_plt_clk_mux), 460 PIN_GROUP_SIMPLE("plt_clk4_grp", 461 byt_score_plt_clk4_pins, byt_score_plt_clk_mux), 462 PIN_GROUP_SIMPLE("plt_clk5_grp", 463 byt_score_plt_clk5_pins, byt_score_plt_clk_mux), 464 PIN_GROUP_SIMPLE("smbus_grp", 465 byt_score_smbus_pins, byt_score_smbus_mux), 466 }; 467 468 static const char * const byt_score_uart_groups[] = { 469 "uart1_grp", "uart2_grp", 470 }; 471 static const char * const byt_score_pwm_groups[] = { 472 "pwm0_grp", "pwm1_grp", 473 }; 474 static const char * const byt_score_ssp_groups[] = { 475 "ssp0_grp", "ssp1_grp", "ssp2_grp", 476 }; 477 static const char * const byt_score_spi_groups[] = { "sio_spi_grp" }; 478 static const char * const byt_score_i2c_groups[] = { 479 "i2c0_grp", "i2c1_grp", "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", 480 "i2c6_grp", 481 }; 482 static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" }; 483 static const char * const byt_score_sdio_groups[] = { "sdio_grp" }; 484 static const char * const byt_score_emmc_groups[] = { "emmc_grp" }; 485 static const char * const byt_score_lpc_groups[] = { "lpc_grp" }; 486 static const char * const byt_score_sata_groups[] = { "sata_grp" }; 487 static const char * const byt_score_plt_clk_groups[] = { 488 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp", 489 "plt_clk4_grp", "plt_clk5_grp", 490 }; 491 static const char * const byt_score_smbus_groups[] = { "smbus_grp" }; 492 static const char * const byt_score_gpio_groups[] = { 493 "uart1_grp", "uart2_grp", "pwm0_grp", "pwm1_grp", "ssp0_grp", 494 "ssp1_grp", "ssp2_grp", "sio_spi_grp", "i2c0_grp", "i2c1_grp", 495 "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", "i2c6_grp", 496 "sdcard_grp", "sdio_grp", "emmc_grp", "lpc_grp", "sata_grp", 497 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp", 498 "plt_clk4_grp", "plt_clk5_grp", "smbus_grp", 499 500 }; 501 502 static const struct byt_function byt_score_functions[] = { 503 FUNCTION("uart", byt_score_uart_groups), 504 FUNCTION("pwm", byt_score_pwm_groups), 505 FUNCTION("ssp", byt_score_ssp_groups), 506 FUNCTION("spi", byt_score_spi_groups), 507 FUNCTION("i2c", byt_score_i2c_groups), 508 FUNCTION("sdcard", byt_score_sdcard_groups), 509 FUNCTION("sdio", byt_score_sdio_groups), 510 FUNCTION("emmc", byt_score_emmc_groups), 511 FUNCTION("lpc", byt_score_lpc_groups), 512 FUNCTION("sata", byt_score_sata_groups), 513 FUNCTION("plt_clk", byt_score_plt_clk_groups), 514 FUNCTION("smbus", byt_score_smbus_groups), 515 FUNCTION("gpio", byt_score_gpio_groups), 516 }; 517 518 static const struct byt_community byt_score_communities[] = { 519 COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map), 520 }; 521 522 static const struct byt_pinctrl_soc_data byt_score_soc_data = { 523 .uid = BYT_SCORE_ACPI_UID, 524 .pins = byt_score_pins, 525 .npins = ARRAY_SIZE(byt_score_pins), 526 .groups = byt_score_groups, 527 .ngroups = ARRAY_SIZE(byt_score_groups), 528 .functions = byt_score_functions, 529 .nfunctions = ARRAY_SIZE(byt_score_functions), 530 .communities = byt_score_communities, 531 .ncommunities = ARRAY_SIZE(byt_score_communities), 532 }; 533 534 /* SUS pins, aka GPIOS_<pin_no> or GPIO_S5[<pin_no>] */ 535 static const struct pinctrl_pin_desc byt_sus_pins[] = { 536 PINCTRL_PIN(0, "GPIO_S50"), 537 PINCTRL_PIN(1, "GPIO_S51"), 538 PINCTRL_PIN(2, "GPIO_S52"), 539 PINCTRL_PIN(3, "GPIO_S53"), 540 PINCTRL_PIN(4, "GPIO_S54"), 541 PINCTRL_PIN(5, "GPIO_S55"), 542 PINCTRL_PIN(6, "GPIO_S56"), 543 PINCTRL_PIN(7, "GPIO_S57"), 544 PINCTRL_PIN(8, "GPIO_S58"), 545 PINCTRL_PIN(9, "GPIO_S59"), 546 PINCTRL_PIN(10, "GPIO_S510"), 547 PINCTRL_PIN(11, "PMC_SUSPWRDNACK"), 548 PINCTRL_PIN(12, "PMC_SUSCLK0"), 549 PINCTRL_PIN(13, "GPIO_S513"), 550 PINCTRL_PIN(14, "USB_ULPI_RST"), 551 PINCTRL_PIN(15, "PMC_WAKE_PCIE0#"), 552 PINCTRL_PIN(16, "PMC_PWRBTN"), 553 PINCTRL_PIN(17, "GPIO_S517"), 554 PINCTRL_PIN(18, "PMC_SUS_STAT"), 555 PINCTRL_PIN(19, "USB_OC0"), 556 PINCTRL_PIN(20, "USB_OC1"), 557 PINCTRL_PIN(21, "PCU_SPI_CS1"), 558 PINCTRL_PIN(22, "GPIO_S522"), 559 PINCTRL_PIN(23, "GPIO_S523"), 560 PINCTRL_PIN(24, "GPIO_S524"), 561 PINCTRL_PIN(25, "GPIO_S525"), 562 PINCTRL_PIN(26, "GPIO_S526"), 563 PINCTRL_PIN(27, "GPIO_S527"), 564 PINCTRL_PIN(28, "GPIO_S528"), 565 PINCTRL_PIN(29, "GPIO_S529"), 566 PINCTRL_PIN(30, "GPIO_S530"), 567 PINCTRL_PIN(31, "USB_ULPI_CLK"), 568 PINCTRL_PIN(32, "USB_ULPI_DATA0"), 569 PINCTRL_PIN(33, "USB_ULPI_DATA1"), 570 PINCTRL_PIN(34, "USB_ULPI_DATA2"), 571 PINCTRL_PIN(35, "USB_ULPI_DATA3"), 572 PINCTRL_PIN(36, "USB_ULPI_DATA4"), 573 PINCTRL_PIN(37, "USB_ULPI_DATA5"), 574 PINCTRL_PIN(38, "USB_ULPI_DATA6"), 575 PINCTRL_PIN(39, "USB_ULPI_DATA7"), 576 PINCTRL_PIN(40, "USB_ULPI_DIR"), 577 PINCTRL_PIN(41, "USB_ULPI_NXT"), 578 PINCTRL_PIN(42, "USB_ULPI_STP"), 579 PINCTRL_PIN(43, "USB_ULPI_REFCLK"), 580 }; 581 582 static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = { 583 29, 33, 30, 31, 32, 34, 36, 35, 38, 37, 584 18, 7, 11, 20, 17, 1, 8, 10, 19, 12, 585 0, 2, 23, 39, 28, 27, 22, 21, 24, 25, 586 26, 51, 56, 54, 49, 55, 48, 57, 50, 58, 587 52, 53, 59, 40, 588 }; 589 590 static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 }; 591 static const struct byt_simple_func_mux byt_sus_usb_oc_mux[] = { 592 SIMPLE_FUNC("usb", 0), 593 SIMPLE_FUNC("gpio", 1), 594 }; 595 596 static const unsigned int byt_sus_usb_ulpi_pins[] = { 597 14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 598 }; 599 static const unsigned short byt_sus_usb_ulpi_mode_values[] = { 600 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 601 }; 602 static const unsigned short byt_sus_usb_ulpi_gpio_mode_values[] = { 603 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 604 }; 605 static const struct byt_mixed_func_mux byt_sus_usb_ulpi_mux[] = { 606 MIXED_FUNC("usb", byt_sus_usb_ulpi_mode_values), 607 MIXED_FUNC("gpio", byt_sus_usb_ulpi_gpio_mode_values), 608 }; 609 610 static const unsigned int byt_sus_pcu_spi_pins[] = { 21 }; 611 static const struct byt_simple_func_mux byt_sus_pcu_spi_mux[] = { 612 SIMPLE_FUNC("spi", 0), 613 SIMPLE_FUNC("gpio", 1), 614 }; 615 616 static const struct byt_pingroup byt_sus_groups[] = { 617 PIN_GROUP_SIMPLE("usb_oc_grp", 618 byt_sus_usb_over_current_pins, byt_sus_usb_oc_mux), 619 PIN_GROUP_MIXED("usb_ulpi_grp", 620 byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mux), 621 PIN_GROUP_SIMPLE("pcu_spi_grp", 622 byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mux), 623 }; 624 625 static const char * const byt_sus_usb_groups[] = { 626 "usb_oc_grp", "usb_ulpi_grp", 627 }; 628 static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" }; 629 static const char * const byt_sus_gpio_groups[] = { 630 "usb_oc_grp", "usb_ulpi_grp", "pcu_spi_grp", 631 }; 632 633 static const struct byt_function byt_sus_functions[] = { 634 FUNCTION("usb", byt_sus_usb_groups), 635 FUNCTION("spi", byt_sus_spi_groups), 636 FUNCTION("gpio", byt_sus_gpio_groups), 637 }; 638 639 static const struct byt_community byt_sus_communities[] = { 640 COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map), 641 }; 642 643 static const struct byt_pinctrl_soc_data byt_sus_soc_data = { 644 .uid = BYT_SUS_ACPI_UID, 645 .pins = byt_sus_pins, 646 .npins = ARRAY_SIZE(byt_sus_pins), 647 .groups = byt_sus_groups, 648 .ngroups = ARRAY_SIZE(byt_sus_groups), 649 .functions = byt_sus_functions, 650 .nfunctions = ARRAY_SIZE(byt_sus_functions), 651 .communities = byt_sus_communities, 652 .ncommunities = ARRAY_SIZE(byt_sus_communities), 653 }; 654 655 static const struct pinctrl_pin_desc byt_ncore_pins[] = { 656 PINCTRL_PIN(0, "GPIO_NCORE0"), 657 PINCTRL_PIN(1, "GPIO_NCORE1"), 658 PINCTRL_PIN(2, "GPIO_NCORE2"), 659 PINCTRL_PIN(3, "GPIO_NCORE3"), 660 PINCTRL_PIN(4, "GPIO_NCORE4"), 661 PINCTRL_PIN(5, "GPIO_NCORE5"), 662 PINCTRL_PIN(6, "GPIO_NCORE6"), 663 PINCTRL_PIN(7, "GPIO_NCORE7"), 664 PINCTRL_PIN(8, "GPIO_NCORE8"), 665 PINCTRL_PIN(9, "GPIO_NCORE9"), 666 PINCTRL_PIN(10, "GPIO_NCORE10"), 667 PINCTRL_PIN(11, "GPIO_NCORE11"), 668 PINCTRL_PIN(12, "GPIO_NCORE12"), 669 PINCTRL_PIN(13, "GPIO_NCORE13"), 670 PINCTRL_PIN(14, "GPIO_NCORE14"), 671 PINCTRL_PIN(15, "GPIO_NCORE15"), 672 PINCTRL_PIN(16, "GPIO_NCORE16"), 673 PINCTRL_PIN(17, "GPIO_NCORE17"), 674 PINCTRL_PIN(18, "GPIO_NCORE18"), 675 PINCTRL_PIN(19, "GPIO_NCORE19"), 676 PINCTRL_PIN(20, "GPIO_NCORE20"), 677 PINCTRL_PIN(21, "GPIO_NCORE21"), 678 PINCTRL_PIN(22, "GPIO_NCORE22"), 679 PINCTRL_PIN(23, "GPIO_NCORE23"), 680 PINCTRL_PIN(24, "GPIO_NCORE24"), 681 PINCTRL_PIN(25, "GPIO_NCORE25"), 682 PINCTRL_PIN(26, "GPIO_NCORE26"), 683 PINCTRL_PIN(27, "GPIO_NCORE27"), 684 }; 685 686 static const unsigned int byt_ncore_pins_map[BYT_NGPIO_NCORE] = { 687 19, 18, 17, 20, 21, 22, 24, 25, 23, 16, 688 14, 15, 12, 26, 27, 1, 4, 8, 11, 0, 689 3, 6, 10, 13, 2, 5, 9, 7, 690 }; 691 692 static const struct byt_community byt_ncore_communities[] = { 693 COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map), 694 }; 695 696 static const struct byt_pinctrl_soc_data byt_ncore_soc_data = { 697 .uid = BYT_NCORE_ACPI_UID, 698 .pins = byt_ncore_pins, 699 .npins = ARRAY_SIZE(byt_ncore_pins), 700 .communities = byt_ncore_communities, 701 .ncommunities = ARRAY_SIZE(byt_ncore_communities), 702 }; 703 704 static const struct byt_pinctrl_soc_data *byt_soc_data[] = { 705 &byt_score_soc_data, 706 &byt_sus_soc_data, 707 &byt_ncore_soc_data, 708 NULL 709 }; 710 711 static struct byt_community *byt_get_community(struct byt_gpio *vg, 712 unsigned int pin) 713 { 714 struct byt_community *comm; 715 int i; 716 717 for (i = 0; i < vg->soc_data->ncommunities; i++) { 718 comm = vg->communities_copy + i; 719 if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base) 720 return comm; 721 } 722 723 return NULL; 724 } 725 726 static void __iomem *byt_gpio_reg(struct byt_gpio *vg, unsigned int offset, 727 int reg) 728 { 729 struct byt_community *comm = byt_get_community(vg, offset); 730 u32 reg_offset; 731 732 if (!comm) 733 return NULL; 734 735 offset -= comm->pin_base; 736 switch (reg) { 737 case BYT_INT_STAT_REG: 738 reg_offset = (offset / 32) * 4; 739 break; 740 case BYT_DEBOUNCE_REG: 741 reg_offset = 0; 742 break; 743 default: 744 reg_offset = comm->pad_map[offset] * 16; 745 break; 746 } 747 748 return comm->reg_base + reg_offset + reg; 749 } 750 751 static int byt_get_groups_count(struct pinctrl_dev *pctldev) 752 { 753 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); 754 755 return vg->soc_data->ngroups; 756 } 757 758 static const char *byt_get_group_name(struct pinctrl_dev *pctldev, 759 unsigned int selector) 760 { 761 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); 762 763 return vg->soc_data->groups[selector].name; 764 } 765 766 static int byt_get_group_pins(struct pinctrl_dev *pctldev, 767 unsigned int selector, 768 const unsigned int **pins, 769 unsigned int *num_pins) 770 { 771 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); 772 773 *pins = vg->soc_data->groups[selector].pins; 774 *num_pins = vg->soc_data->groups[selector].npins; 775 776 return 0; 777 } 778 779 static const struct pinctrl_ops byt_pinctrl_ops = { 780 .get_groups_count = byt_get_groups_count, 781 .get_group_name = byt_get_group_name, 782 .get_group_pins = byt_get_group_pins, 783 }; 784 785 static int byt_get_functions_count(struct pinctrl_dev *pctldev) 786 { 787 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); 788 789 return vg->soc_data->nfunctions; 790 } 791 792 static const char *byt_get_function_name(struct pinctrl_dev *pctldev, 793 unsigned int selector) 794 { 795 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); 796 797 return vg->soc_data->functions[selector].name; 798 } 799 800 static int byt_get_function_groups(struct pinctrl_dev *pctldev, 801 unsigned int selector, 802 const char * const **groups, 803 unsigned int *num_groups) 804 { 805 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); 806 807 *groups = vg->soc_data->functions[selector].groups; 808 *num_groups = vg->soc_data->functions[selector].ngroups; 809 810 return 0; 811 } 812 813 static int byt_get_group_simple_mux(const struct byt_pingroup group, 814 const char *func_name, 815 unsigned short *func) 816 { 817 int i; 818 819 for (i = 0; i < group.nfuncs; i++) { 820 if (!strcmp(group.simple_funcs[i].name, func_name)) { 821 *func = group.simple_funcs[i].func; 822 return 0; 823 } 824 } 825 826 return 1; 827 } 828 829 static int byt_get_group_mixed_mux(const struct byt_pingroup group, 830 const char *func_name, 831 const unsigned short **func) 832 { 833 int i; 834 835 for (i = 0; i < group.nfuncs; i++) { 836 if (!strcmp(group.mixed_funcs[i].name, func_name)) { 837 *func = group.mixed_funcs[i].func_values; 838 return 0; 839 } 840 } 841 842 return 1; 843 } 844 845 static void byt_set_group_simple_mux(struct byt_gpio *vg, 846 const struct byt_pingroup group, 847 unsigned short func) 848 { 849 unsigned long flags; 850 int i; 851 852 raw_spin_lock_irqsave(&vg->lock, flags); 853 854 for (i = 0; i < group.npins; i++) { 855 void __iomem *padcfg0; 856 u32 value; 857 858 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG); 859 if (!padcfg0) { 860 dev_warn(&vg->pdev->dev, 861 "Group %s, pin %i not muxed (no padcfg0)\n", 862 group.name, i); 863 continue; 864 } 865 866 value = readl(padcfg0); 867 value &= ~BYT_PIN_MUX; 868 value |= func; 869 writel(value, padcfg0); 870 } 871 872 raw_spin_unlock_irqrestore(&vg->lock, flags); 873 } 874 875 static void byt_set_group_mixed_mux(struct byt_gpio *vg, 876 const struct byt_pingroup group, 877 const unsigned short *func) 878 { 879 unsigned long flags; 880 int i; 881 882 raw_spin_lock_irqsave(&vg->lock, flags); 883 884 for (i = 0; i < group.npins; i++) { 885 void __iomem *padcfg0; 886 u32 value; 887 888 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG); 889 if (!padcfg0) { 890 dev_warn(&vg->pdev->dev, 891 "Group %s, pin %i not muxed (no padcfg0)\n", 892 group.name, i); 893 continue; 894 } 895 896 value = readl(padcfg0); 897 value &= ~BYT_PIN_MUX; 898 value |= func[i]; 899 writel(value, padcfg0); 900 } 901 902 raw_spin_unlock_irqrestore(&vg->lock, flags); 903 } 904 905 static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, 906 unsigned int group_selector) 907 { 908 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); 909 const struct byt_function func = vg->soc_data->functions[func_selector]; 910 const struct byt_pingroup group = vg->soc_data->groups[group_selector]; 911 const unsigned short *mixed_func; 912 unsigned short simple_func; 913 int ret = 1; 914 915 if (group.has_simple_funcs) 916 ret = byt_get_group_simple_mux(group, func.name, &simple_func); 917 else 918 ret = byt_get_group_mixed_mux(group, func.name, &mixed_func); 919 920 if (ret) 921 byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX); 922 else if (group.has_simple_funcs) 923 byt_set_group_simple_mux(vg, group, simple_func); 924 else 925 byt_set_group_mixed_mux(vg, group, mixed_func); 926 927 return 0; 928 } 929 930 static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned int offset) 931 { 932 /* SCORE pin 92-93 */ 933 if (!strcmp(vg->soc_data->uid, BYT_SCORE_ACPI_UID) && 934 offset >= 92 && offset <= 93) 935 return 1; 936 937 /* SUS pin 11-21 */ 938 if (!strcmp(vg->soc_data->uid, BYT_SUS_ACPI_UID) && 939 offset >= 11 && offset <= 21) 940 return 1; 941 942 return 0; 943 } 944 945 static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned int offset) 946 { 947 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 948 unsigned long flags; 949 u32 value; 950 951 raw_spin_lock_irqsave(&vg->lock, flags); 952 value = readl(reg); 953 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL); 954 writel(value, reg); 955 raw_spin_unlock_irqrestore(&vg->lock, flags); 956 } 957 958 static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev, 959 struct pinctrl_gpio_range *range, 960 unsigned int offset) 961 { 962 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev); 963 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 964 u32 value, gpio_mux; 965 unsigned long flags; 966 967 raw_spin_lock_irqsave(&vg->lock, flags); 968 969 /* 970 * In most cases, func pin mux 000 means GPIO function. 971 * But, some pins may have func pin mux 001 represents 972 * GPIO function. 973 * 974 * Because there are devices out there where some pins were not 975 * configured correctly we allow changing the mux value from 976 * request (but print out warning about that). 977 */ 978 value = readl(reg) & BYT_PIN_MUX; 979 gpio_mux = byt_get_gpio_mux(vg, offset); 980 if (gpio_mux != value) { 981 value = readl(reg) & ~BYT_PIN_MUX; 982 value |= gpio_mux; 983 writel(value, reg); 984 985 dev_warn(&vg->pdev->dev, FW_BUG 986 "pin %u forcibly re-configured as GPIO\n", offset); 987 } 988 989 raw_spin_unlock_irqrestore(&vg->lock, flags); 990 991 pm_runtime_get(&vg->pdev->dev); 992 993 return 0; 994 } 995 996 static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev, 997 struct pinctrl_gpio_range *range, 998 unsigned int offset) 999 { 1000 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev); 1001 1002 byt_gpio_clear_triggering(vg, offset); 1003 pm_runtime_put(&vg->pdev->dev); 1004 } 1005 1006 static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev, 1007 struct pinctrl_gpio_range *range, 1008 unsigned int offset, 1009 bool input) 1010 { 1011 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev); 1012 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1013 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 1014 unsigned long flags; 1015 u32 value; 1016 1017 raw_spin_lock_irqsave(&vg->lock, flags); 1018 1019 value = readl(val_reg); 1020 value &= ~BYT_DIR_MASK; 1021 if (input) 1022 value |= BYT_OUTPUT_EN; 1023 else 1024 /* 1025 * Before making any direction modifications, do a check if gpio 1026 * is set for direct IRQ. On baytrail, setting GPIO to output 1027 * does not make sense, so let's at least warn the caller before 1028 * they shoot themselves in the foot. 1029 */ 1030 WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN, 1031 "Potential Error: Setting GPIO with direct_irq_en to output"); 1032 writel(value, val_reg); 1033 1034 raw_spin_unlock_irqrestore(&vg->lock, flags); 1035 1036 return 0; 1037 } 1038 1039 static const struct pinmux_ops byt_pinmux_ops = { 1040 .get_functions_count = byt_get_functions_count, 1041 .get_function_name = byt_get_function_name, 1042 .get_function_groups = byt_get_function_groups, 1043 .set_mux = byt_set_mux, 1044 .gpio_request_enable = byt_gpio_request_enable, 1045 .gpio_disable_free = byt_gpio_disable_free, 1046 .gpio_set_direction = byt_gpio_set_direction, 1047 }; 1048 1049 static void byt_get_pull_strength(u32 reg, u16 *strength) 1050 { 1051 switch (reg & BYT_PULL_STR_MASK) { 1052 case BYT_PULL_STR_2K: 1053 *strength = 2000; 1054 break; 1055 case BYT_PULL_STR_10K: 1056 *strength = 10000; 1057 break; 1058 case BYT_PULL_STR_20K: 1059 *strength = 20000; 1060 break; 1061 case BYT_PULL_STR_40K: 1062 *strength = 40000; 1063 break; 1064 } 1065 } 1066 1067 static int byt_set_pull_strength(u32 *reg, u16 strength) 1068 { 1069 *reg &= ~BYT_PULL_STR_MASK; 1070 1071 switch (strength) { 1072 case 2000: 1073 *reg |= BYT_PULL_STR_2K; 1074 break; 1075 case 10000: 1076 *reg |= BYT_PULL_STR_10K; 1077 break; 1078 case 20000: 1079 *reg |= BYT_PULL_STR_20K; 1080 break; 1081 case 40000: 1082 *reg |= BYT_PULL_STR_40K; 1083 break; 1084 default: 1085 return -EINVAL; 1086 } 1087 1088 return 0; 1089 } 1090 1091 static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset, 1092 unsigned long *config) 1093 { 1094 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev); 1095 enum pin_config_param param = pinconf_to_config_param(*config); 1096 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 1097 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1098 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG); 1099 unsigned long flags; 1100 u32 conf, pull, val, debounce; 1101 u16 arg = 0; 1102 1103 raw_spin_lock_irqsave(&vg->lock, flags); 1104 conf = readl(conf_reg); 1105 pull = conf & BYT_PULL_ASSIGN_MASK; 1106 val = readl(val_reg); 1107 raw_spin_unlock_irqrestore(&vg->lock, flags); 1108 1109 switch (param) { 1110 case PIN_CONFIG_BIAS_DISABLE: 1111 if (pull) 1112 return -EINVAL; 1113 break; 1114 case PIN_CONFIG_BIAS_PULL_DOWN: 1115 /* Pull assignment is only applicable in input mode */ 1116 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN) 1117 return -EINVAL; 1118 1119 byt_get_pull_strength(conf, &arg); 1120 1121 break; 1122 case PIN_CONFIG_BIAS_PULL_UP: 1123 /* Pull assignment is only applicable in input mode */ 1124 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP) 1125 return -EINVAL; 1126 1127 byt_get_pull_strength(conf, &arg); 1128 1129 break; 1130 case PIN_CONFIG_INPUT_DEBOUNCE: 1131 if (!(conf & BYT_DEBOUNCE_EN)) 1132 return -EINVAL; 1133 1134 raw_spin_lock_irqsave(&vg->lock, flags); 1135 debounce = readl(db_reg); 1136 raw_spin_unlock_irqrestore(&vg->lock, flags); 1137 1138 switch (debounce & BYT_DEBOUNCE_PULSE_MASK) { 1139 case BYT_DEBOUNCE_PULSE_375US: 1140 arg = 375; 1141 break; 1142 case BYT_DEBOUNCE_PULSE_750US: 1143 arg = 750; 1144 break; 1145 case BYT_DEBOUNCE_PULSE_1500US: 1146 arg = 1500; 1147 break; 1148 case BYT_DEBOUNCE_PULSE_3MS: 1149 arg = 3000; 1150 break; 1151 case BYT_DEBOUNCE_PULSE_6MS: 1152 arg = 6000; 1153 break; 1154 case BYT_DEBOUNCE_PULSE_12MS: 1155 arg = 12000; 1156 break; 1157 case BYT_DEBOUNCE_PULSE_24MS: 1158 arg = 24000; 1159 break; 1160 default: 1161 return -EINVAL; 1162 } 1163 1164 break; 1165 default: 1166 return -ENOTSUPP; 1167 } 1168 1169 *config = pinconf_to_config_packed(param, arg); 1170 1171 return 0; 1172 } 1173 1174 static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, 1175 unsigned int offset, 1176 unsigned long *configs, 1177 unsigned int num_configs) 1178 { 1179 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev); 1180 unsigned int param, arg; 1181 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 1182 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1183 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG); 1184 unsigned long flags; 1185 u32 conf, val, debounce; 1186 int i, ret = 0; 1187 1188 raw_spin_lock_irqsave(&vg->lock, flags); 1189 1190 conf = readl(conf_reg); 1191 val = readl(val_reg); 1192 1193 for (i = 0; i < num_configs; i++) { 1194 param = pinconf_to_config_param(configs[i]); 1195 arg = pinconf_to_config_argument(configs[i]); 1196 1197 switch (param) { 1198 case PIN_CONFIG_BIAS_DISABLE: 1199 conf &= ~BYT_PULL_ASSIGN_MASK; 1200 break; 1201 case PIN_CONFIG_BIAS_PULL_DOWN: 1202 /* Set default strength value in case none is given */ 1203 if (arg == 1) 1204 arg = 2000; 1205 1206 /* 1207 * Pull assignment is only applicable in input mode. If 1208 * chip is not in input mode, set it and warn about it. 1209 */ 1210 if (val & BYT_INPUT_EN) { 1211 val &= ~BYT_INPUT_EN; 1212 writel(val, val_reg); 1213 dev_warn(&vg->pdev->dev, 1214 "pin %u forcibly set to input mode\n", 1215 offset); 1216 } 1217 1218 conf &= ~BYT_PULL_ASSIGN_MASK; 1219 conf |= BYT_PULL_ASSIGN_DOWN; 1220 ret = byt_set_pull_strength(&conf, arg); 1221 1222 break; 1223 case PIN_CONFIG_BIAS_PULL_UP: 1224 /* Set default strength value in case none is given */ 1225 if (arg == 1) 1226 arg = 2000; 1227 1228 /* 1229 * Pull assignment is only applicable in input mode. If 1230 * chip is not in input mode, set it and warn about it. 1231 */ 1232 if (val & BYT_INPUT_EN) { 1233 val &= ~BYT_INPUT_EN; 1234 writel(val, val_reg); 1235 dev_warn(&vg->pdev->dev, 1236 "pin %u forcibly set to input mode\n", 1237 offset); 1238 } 1239 1240 conf &= ~BYT_PULL_ASSIGN_MASK; 1241 conf |= BYT_PULL_ASSIGN_UP; 1242 ret = byt_set_pull_strength(&conf, arg); 1243 1244 break; 1245 case PIN_CONFIG_INPUT_DEBOUNCE: 1246 debounce = readl(db_reg); 1247 debounce &= ~BYT_DEBOUNCE_PULSE_MASK; 1248 1249 if (arg) 1250 conf |= BYT_DEBOUNCE_EN; 1251 else 1252 conf &= ~BYT_DEBOUNCE_EN; 1253 1254 switch (arg) { 1255 case 375: 1256 debounce |= BYT_DEBOUNCE_PULSE_375US; 1257 break; 1258 case 750: 1259 debounce |= BYT_DEBOUNCE_PULSE_750US; 1260 break; 1261 case 1500: 1262 debounce |= BYT_DEBOUNCE_PULSE_1500US; 1263 break; 1264 case 3000: 1265 debounce |= BYT_DEBOUNCE_PULSE_3MS; 1266 break; 1267 case 6000: 1268 debounce |= BYT_DEBOUNCE_PULSE_6MS; 1269 break; 1270 case 12000: 1271 debounce |= BYT_DEBOUNCE_PULSE_12MS; 1272 break; 1273 case 24000: 1274 debounce |= BYT_DEBOUNCE_PULSE_24MS; 1275 break; 1276 default: 1277 if (arg) 1278 ret = -EINVAL; 1279 break; 1280 } 1281 1282 if (!ret) 1283 writel(debounce, db_reg); 1284 break; 1285 default: 1286 ret = -ENOTSUPP; 1287 } 1288 1289 if (ret) 1290 break; 1291 } 1292 1293 if (!ret) 1294 writel(conf, conf_reg); 1295 1296 raw_spin_unlock_irqrestore(&vg->lock, flags); 1297 1298 return ret; 1299 } 1300 1301 static const struct pinconf_ops byt_pinconf_ops = { 1302 .is_generic = true, 1303 .pin_config_get = byt_pin_config_get, 1304 .pin_config_set = byt_pin_config_set, 1305 }; 1306 1307 static const struct pinctrl_desc byt_pinctrl_desc = { 1308 .pctlops = &byt_pinctrl_ops, 1309 .pmxops = &byt_pinmux_ops, 1310 .confops = &byt_pinconf_ops, 1311 .owner = THIS_MODULE, 1312 }; 1313 1314 static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset) 1315 { 1316 struct byt_gpio *vg = gpiochip_get_data(chip); 1317 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1318 unsigned long flags; 1319 u32 val; 1320 1321 raw_spin_lock_irqsave(&vg->lock, flags); 1322 val = readl(reg); 1323 raw_spin_unlock_irqrestore(&vg->lock, flags); 1324 1325 return !!(val & BYT_LEVEL); 1326 } 1327 1328 static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 1329 { 1330 struct byt_gpio *vg = gpiochip_get_data(chip); 1331 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1332 unsigned long flags; 1333 u32 old_val; 1334 1335 if (!reg) 1336 return; 1337 1338 raw_spin_lock_irqsave(&vg->lock, flags); 1339 old_val = readl(reg); 1340 if (value) 1341 writel(old_val | BYT_LEVEL, reg); 1342 else 1343 writel(old_val & ~BYT_LEVEL, reg); 1344 raw_spin_unlock_irqrestore(&vg->lock, flags); 1345 } 1346 1347 static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 1348 { 1349 struct byt_gpio *vg = gpiochip_get_data(chip); 1350 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1351 unsigned long flags; 1352 u32 value; 1353 1354 if (!reg) 1355 return -EINVAL; 1356 1357 raw_spin_lock_irqsave(&vg->lock, flags); 1358 value = readl(reg); 1359 raw_spin_unlock_irqrestore(&vg->lock, flags); 1360 1361 if (!(value & BYT_OUTPUT_EN)) 1362 return 0; 1363 if (!(value & BYT_INPUT_EN)) 1364 return 1; 1365 1366 return -EINVAL; 1367 } 1368 1369 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 1370 { 1371 return pinctrl_gpio_direction_input(chip->base + offset); 1372 } 1373 1374 static int byt_gpio_direction_output(struct gpio_chip *chip, 1375 unsigned int offset, int value) 1376 { 1377 int ret = pinctrl_gpio_direction_output(chip->base + offset); 1378 1379 if (ret) 1380 return ret; 1381 1382 byt_gpio_set(chip, offset, value); 1383 1384 return 0; 1385 } 1386 1387 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 1388 { 1389 struct byt_gpio *vg = gpiochip_get_data(chip); 1390 int i; 1391 u32 conf0, val; 1392 1393 for (i = 0; i < vg->soc_data->npins; i++) { 1394 const struct byt_community *comm; 1395 const char *pull_str = NULL; 1396 const char *pull = NULL; 1397 void __iomem *reg; 1398 unsigned long flags; 1399 const char *label; 1400 unsigned int pin; 1401 1402 raw_spin_lock_irqsave(&vg->lock, flags); 1403 pin = vg->soc_data->pins[i].number; 1404 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1405 if (!reg) { 1406 seq_printf(s, 1407 "Could not retrieve pin %i conf0 reg\n", 1408 pin); 1409 raw_spin_unlock_irqrestore(&vg->lock, flags); 1410 continue; 1411 } 1412 conf0 = readl(reg); 1413 1414 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); 1415 if (!reg) { 1416 seq_printf(s, 1417 "Could not retrieve pin %i val reg\n", pin); 1418 raw_spin_unlock_irqrestore(&vg->lock, flags); 1419 continue; 1420 } 1421 val = readl(reg); 1422 raw_spin_unlock_irqrestore(&vg->lock, flags); 1423 1424 comm = byt_get_community(vg, pin); 1425 if (!comm) { 1426 seq_printf(s, 1427 "Could not get community for pin %i\n", pin); 1428 continue; 1429 } 1430 label = gpiochip_is_requested(chip, i); 1431 if (!label) 1432 label = "Unrequested"; 1433 1434 switch (conf0 & BYT_PULL_ASSIGN_MASK) { 1435 case BYT_PULL_ASSIGN_UP: 1436 pull = "up"; 1437 break; 1438 case BYT_PULL_ASSIGN_DOWN: 1439 pull = "down"; 1440 break; 1441 } 1442 1443 switch (conf0 & BYT_PULL_STR_MASK) { 1444 case BYT_PULL_STR_2K: 1445 pull_str = "2k"; 1446 break; 1447 case BYT_PULL_STR_10K: 1448 pull_str = "10k"; 1449 break; 1450 case BYT_PULL_STR_20K: 1451 pull_str = "20k"; 1452 break; 1453 case BYT_PULL_STR_40K: 1454 pull_str = "40k"; 1455 break; 1456 } 1457 1458 seq_printf(s, 1459 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s", 1460 pin, 1461 label, 1462 val & BYT_INPUT_EN ? " " : "in", 1463 val & BYT_OUTPUT_EN ? " " : "out", 1464 val & BYT_LEVEL ? "hi" : "lo", 1465 comm->pad_map[i], comm->pad_map[i] * 16, 1466 conf0 & 0x7, 1467 conf0 & BYT_TRIG_NEG ? " fall" : " ", 1468 conf0 & BYT_TRIG_POS ? " rise" : " ", 1469 conf0 & BYT_TRIG_LVL ? " level" : " "); 1470 1471 if (pull && pull_str) 1472 seq_printf(s, " %-4s %-3s", pull, pull_str); 1473 else 1474 seq_puts(s, " "); 1475 1476 if (conf0 & BYT_IODEN) 1477 seq_puts(s, " open-drain"); 1478 1479 seq_puts(s, "\n"); 1480 } 1481 } 1482 1483 static const struct gpio_chip byt_gpio_chip = { 1484 .owner = THIS_MODULE, 1485 .request = gpiochip_generic_request, 1486 .free = gpiochip_generic_free, 1487 .get_direction = byt_gpio_get_direction, 1488 .direction_input = byt_gpio_direction_input, 1489 .direction_output = byt_gpio_direction_output, 1490 .get = byt_gpio_get, 1491 .set = byt_gpio_set, 1492 .dbg_show = byt_gpio_dbg_show, 1493 }; 1494 1495 static void byt_irq_ack(struct irq_data *d) 1496 { 1497 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1498 struct byt_gpio *vg = gpiochip_get_data(gc); 1499 unsigned int offset = irqd_to_hwirq(d); 1500 void __iomem *reg; 1501 1502 reg = byt_gpio_reg(vg, offset, BYT_INT_STAT_REG); 1503 if (!reg) 1504 return; 1505 1506 raw_spin_lock(&vg->lock); 1507 writel(BIT(offset % 32), reg); 1508 raw_spin_unlock(&vg->lock); 1509 } 1510 1511 static void byt_irq_mask(struct irq_data *d) 1512 { 1513 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1514 struct byt_gpio *vg = gpiochip_get_data(gc); 1515 1516 byt_gpio_clear_triggering(vg, irqd_to_hwirq(d)); 1517 } 1518 1519 static void byt_irq_unmask(struct irq_data *d) 1520 { 1521 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1522 struct byt_gpio *vg = gpiochip_get_data(gc); 1523 unsigned int offset = irqd_to_hwirq(d); 1524 unsigned long flags; 1525 void __iomem *reg; 1526 u32 value; 1527 1528 reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 1529 if (!reg) 1530 return; 1531 1532 raw_spin_lock_irqsave(&vg->lock, flags); 1533 value = readl(reg); 1534 1535 switch (irqd_get_trigger_type(d)) { 1536 case IRQ_TYPE_LEVEL_HIGH: 1537 value |= BYT_TRIG_LVL; 1538 /* fall through */ 1539 case IRQ_TYPE_EDGE_RISING: 1540 value |= BYT_TRIG_POS; 1541 break; 1542 case IRQ_TYPE_LEVEL_LOW: 1543 value |= BYT_TRIG_LVL; 1544 /* fall through */ 1545 case IRQ_TYPE_EDGE_FALLING: 1546 value |= BYT_TRIG_NEG; 1547 break; 1548 case IRQ_TYPE_EDGE_BOTH: 1549 value |= (BYT_TRIG_NEG | BYT_TRIG_POS); 1550 break; 1551 } 1552 1553 writel(value, reg); 1554 1555 raw_spin_unlock_irqrestore(&vg->lock, flags); 1556 } 1557 1558 static int byt_irq_type(struct irq_data *d, unsigned int type) 1559 { 1560 struct byt_gpio *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d)); 1561 u32 offset = irqd_to_hwirq(d); 1562 u32 value; 1563 unsigned long flags; 1564 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 1565 1566 if (!reg || offset >= vg->chip.ngpio) 1567 return -EINVAL; 1568 1569 raw_spin_lock_irqsave(&vg->lock, flags); 1570 value = readl(reg); 1571 1572 WARN(value & BYT_DIRECT_IRQ_EN, 1573 "Bad pad config for io mode, force direct_irq_en bit clearing"); 1574 1575 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits 1576 * are used to indicate high and low level triggering 1577 */ 1578 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG | 1579 BYT_TRIG_LVL); 1580 /* Enable glitch filtering */ 1581 value |= BYT_GLITCH_FILTER_EN | BYT_GLITCH_F_SLOW_CLK | 1582 BYT_GLITCH_F_FAST_CLK; 1583 1584 writel(value, reg); 1585 1586 if (type & IRQ_TYPE_EDGE_BOTH) 1587 irq_set_handler_locked(d, handle_edge_irq); 1588 else if (type & IRQ_TYPE_LEVEL_MASK) 1589 irq_set_handler_locked(d, handle_level_irq); 1590 1591 raw_spin_unlock_irqrestore(&vg->lock, flags); 1592 1593 return 0; 1594 } 1595 1596 static struct irq_chip byt_irqchip = { 1597 .name = "BYT-GPIO", 1598 .irq_ack = byt_irq_ack, 1599 .irq_mask = byt_irq_mask, 1600 .irq_unmask = byt_irq_unmask, 1601 .irq_set_type = byt_irq_type, 1602 .flags = IRQCHIP_SKIP_SET_WAKE, 1603 }; 1604 1605 static void byt_gpio_irq_handler(struct irq_desc *desc) 1606 { 1607 struct irq_data *data = irq_desc_get_irq_data(desc); 1608 struct byt_gpio *vg = gpiochip_get_data( 1609 irq_desc_get_handler_data(desc)); 1610 struct irq_chip *chip = irq_data_get_irq_chip(data); 1611 u32 base, pin; 1612 void __iomem *reg; 1613 unsigned long pending; 1614 unsigned int virq; 1615 1616 /* check from GPIO controller which pin triggered the interrupt */ 1617 for (base = 0; base < vg->chip.ngpio; base += 32) { 1618 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG); 1619 1620 if (!reg) { 1621 dev_warn(&vg->pdev->dev, 1622 "Pin %i: could not retrieve interrupt status register\n", 1623 base); 1624 continue; 1625 } 1626 1627 raw_spin_lock(&vg->lock); 1628 pending = readl(reg); 1629 raw_spin_unlock(&vg->lock); 1630 for_each_set_bit(pin, &pending, 32) { 1631 virq = irq_find_mapping(vg->chip.irq.domain, base + pin); 1632 generic_handle_irq(virq); 1633 } 1634 } 1635 chip->irq_eoi(data); 1636 } 1637 1638 static void byt_gpio_irq_init_hw(struct byt_gpio *vg) 1639 { 1640 struct gpio_chip *gc = &vg->chip; 1641 struct device *dev = &vg->pdev->dev; 1642 void __iomem *reg; 1643 u32 base, value; 1644 int i; 1645 1646 /* 1647 * Clear interrupt triggers for all pins that are GPIOs and 1648 * do not use direct IRQ mode. This will prevent spurious 1649 * interrupts from misconfigured pins. 1650 */ 1651 for (i = 0; i < vg->soc_data->npins; i++) { 1652 unsigned int pin = vg->soc_data->pins[i].number; 1653 1654 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1655 if (!reg) { 1656 dev_warn(&vg->pdev->dev, 1657 "Pin %i: could not retrieve conf0 register\n", 1658 i); 1659 continue; 1660 } 1661 1662 value = readl(reg); 1663 if (value & BYT_DIRECT_IRQ_EN) { 1664 clear_bit(i, gc->irq.valid_mask); 1665 dev_dbg(dev, "excluding GPIO %d from IRQ domain\n", i); 1666 } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) { 1667 byt_gpio_clear_triggering(vg, i); 1668 dev_dbg(dev, "disabling GPIO %d\n", i); 1669 } 1670 } 1671 1672 /* clear interrupt status trigger registers */ 1673 for (base = 0; base < vg->soc_data->npins; base += 32) { 1674 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG); 1675 1676 if (!reg) { 1677 dev_warn(&vg->pdev->dev, 1678 "Pin %i: could not retrieve irq status reg\n", 1679 base); 1680 continue; 1681 } 1682 1683 writel(0xffffffff, reg); 1684 /* make sure trigger bits are cleared, if not then a pin 1685 might be misconfigured in bios */ 1686 value = readl(reg); 1687 if (value) 1688 dev_err(&vg->pdev->dev, 1689 "GPIO interrupt error, pins misconfigured. INT_STAT%u: 0x%08x\n", 1690 base / 32, value); 1691 } 1692 } 1693 1694 static int byt_gpio_probe(struct byt_gpio *vg) 1695 { 1696 struct gpio_chip *gc; 1697 struct resource *irq_rc; 1698 int ret; 1699 1700 /* Set up gpio chip */ 1701 vg->chip = byt_gpio_chip; 1702 gc = &vg->chip; 1703 gc->label = dev_name(&vg->pdev->dev); 1704 gc->base = -1; 1705 gc->can_sleep = false; 1706 gc->parent = &vg->pdev->dev; 1707 gc->ngpio = vg->soc_data->npins; 1708 gc->irq.need_valid_mask = true; 1709 1710 #ifdef CONFIG_PM_SLEEP 1711 vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio, 1712 sizeof(*vg->saved_context), GFP_KERNEL); 1713 #endif 1714 ret = devm_gpiochip_add_data(&vg->pdev->dev, gc, vg); 1715 if (ret) { 1716 dev_err(&vg->pdev->dev, "failed adding byt-gpio chip\n"); 1717 return ret; 1718 } 1719 1720 ret = gpiochip_add_pin_range(&vg->chip, dev_name(&vg->pdev->dev), 1721 0, 0, vg->soc_data->npins); 1722 if (ret) { 1723 dev_err(&vg->pdev->dev, "failed to add GPIO pin range\n"); 1724 return ret; 1725 } 1726 1727 /* set up interrupts */ 1728 irq_rc = platform_get_resource(vg->pdev, IORESOURCE_IRQ, 0); 1729 if (irq_rc && irq_rc->start) { 1730 byt_gpio_irq_init_hw(vg); 1731 ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0, 1732 handle_bad_irq, IRQ_TYPE_NONE); 1733 if (ret) { 1734 dev_err(&vg->pdev->dev, "failed to add irqchip\n"); 1735 return ret; 1736 } 1737 1738 gpiochip_set_chained_irqchip(gc, &byt_irqchip, 1739 (unsigned)irq_rc->start, 1740 byt_gpio_irq_handler); 1741 } 1742 1743 return ret; 1744 } 1745 1746 static int byt_set_soc_data(struct byt_gpio *vg, 1747 const struct byt_pinctrl_soc_data *soc_data) 1748 { 1749 int i; 1750 1751 vg->soc_data = soc_data; 1752 vg->communities_copy = devm_kcalloc(&vg->pdev->dev, 1753 soc_data->ncommunities, 1754 sizeof(*vg->communities_copy), 1755 GFP_KERNEL); 1756 if (!vg->communities_copy) 1757 return -ENOMEM; 1758 1759 for (i = 0; i < soc_data->ncommunities; i++) { 1760 struct byt_community *comm = vg->communities_copy + i; 1761 struct resource *mem_rc; 1762 1763 *comm = vg->soc_data->communities[i]; 1764 1765 mem_rc = platform_get_resource(vg->pdev, IORESOURCE_MEM, 0); 1766 comm->reg_base = devm_ioremap_resource(&vg->pdev->dev, mem_rc); 1767 if (IS_ERR(comm->reg_base)) 1768 return PTR_ERR(comm->reg_base); 1769 } 1770 1771 return 0; 1772 } 1773 1774 static const struct acpi_device_id byt_gpio_acpi_match[] = { 1775 { "INT33B2", (kernel_ulong_t)byt_soc_data }, 1776 { "INT33FC", (kernel_ulong_t)byt_soc_data }, 1777 { } 1778 }; 1779 1780 static int byt_pinctrl_probe(struct platform_device *pdev) 1781 { 1782 const struct byt_pinctrl_soc_data *soc_data = NULL; 1783 const struct byt_pinctrl_soc_data **soc_table; 1784 struct acpi_device *acpi_dev; 1785 struct byt_gpio *vg; 1786 int i, ret; 1787 1788 acpi_dev = ACPI_COMPANION(&pdev->dev); 1789 if (!acpi_dev) 1790 return -ENODEV; 1791 1792 soc_table = (const struct byt_pinctrl_soc_data **)device_get_match_data(&pdev->dev); 1793 1794 for (i = 0; soc_table[i]; i++) { 1795 if (!strcmp(acpi_dev->pnp.unique_id, soc_table[i]->uid)) { 1796 soc_data = soc_table[i]; 1797 break; 1798 } 1799 } 1800 1801 if (!soc_data) 1802 return -ENODEV; 1803 1804 vg = devm_kzalloc(&pdev->dev, sizeof(*vg), GFP_KERNEL); 1805 if (!vg) 1806 return -ENOMEM; 1807 1808 vg->pdev = pdev; 1809 ret = byt_set_soc_data(vg, soc_data); 1810 if (ret) { 1811 dev_err(&pdev->dev, "failed to set soc data\n"); 1812 return ret; 1813 } 1814 1815 vg->pctl_desc = byt_pinctrl_desc; 1816 vg->pctl_desc.name = dev_name(&pdev->dev); 1817 vg->pctl_desc.pins = vg->soc_data->pins; 1818 vg->pctl_desc.npins = vg->soc_data->npins; 1819 1820 vg->pctl_dev = devm_pinctrl_register(&pdev->dev, &vg->pctl_desc, vg); 1821 if (IS_ERR(vg->pctl_dev)) { 1822 dev_err(&pdev->dev, "failed to register pinctrl driver\n"); 1823 return PTR_ERR(vg->pctl_dev); 1824 } 1825 1826 raw_spin_lock_init(&vg->lock); 1827 1828 ret = byt_gpio_probe(vg); 1829 if (ret) 1830 return ret; 1831 1832 platform_set_drvdata(pdev, vg); 1833 pm_runtime_enable(&pdev->dev); 1834 1835 return 0; 1836 } 1837 1838 #ifdef CONFIG_PM_SLEEP 1839 static int byt_gpio_suspend(struct device *dev) 1840 { 1841 struct byt_gpio *vg = dev_get_drvdata(dev); 1842 int i; 1843 1844 for (i = 0; i < vg->soc_data->npins; i++) { 1845 void __iomem *reg; 1846 u32 value; 1847 unsigned int pin = vg->soc_data->pins[i].number; 1848 1849 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1850 if (!reg) { 1851 dev_warn(&vg->pdev->dev, 1852 "Pin %i: could not retrieve conf0 register\n", 1853 i); 1854 continue; 1855 } 1856 value = readl(reg) & BYT_CONF0_RESTORE_MASK; 1857 vg->saved_context[i].conf0 = value; 1858 1859 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); 1860 value = readl(reg) & BYT_VAL_RESTORE_MASK; 1861 vg->saved_context[i].val = value; 1862 } 1863 1864 return 0; 1865 } 1866 1867 static int byt_gpio_resume(struct device *dev) 1868 { 1869 struct byt_gpio *vg = dev_get_drvdata(dev); 1870 int i; 1871 1872 for (i = 0; i < vg->soc_data->npins; i++) { 1873 void __iomem *reg; 1874 u32 value; 1875 unsigned int pin = vg->soc_data->pins[i].number; 1876 1877 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1878 if (!reg) { 1879 dev_warn(&vg->pdev->dev, 1880 "Pin %i: could not retrieve conf0 register\n", 1881 i); 1882 continue; 1883 } 1884 value = readl(reg); 1885 if ((value & BYT_CONF0_RESTORE_MASK) != 1886 vg->saved_context[i].conf0) { 1887 value &= ~BYT_CONF0_RESTORE_MASK; 1888 value |= vg->saved_context[i].conf0; 1889 writel(value, reg); 1890 dev_info(dev, "restored pin %d conf0 %#08x", i, value); 1891 } 1892 1893 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); 1894 value = readl(reg); 1895 if ((value & BYT_VAL_RESTORE_MASK) != 1896 vg->saved_context[i].val) { 1897 u32 v; 1898 1899 v = value & ~BYT_VAL_RESTORE_MASK; 1900 v |= vg->saved_context[i].val; 1901 if (v != value) { 1902 writel(v, reg); 1903 dev_dbg(dev, "restored pin %d val %#08x\n", 1904 i, v); 1905 } 1906 } 1907 } 1908 1909 return 0; 1910 } 1911 #endif 1912 1913 #ifdef CONFIG_PM 1914 static int byt_gpio_runtime_suspend(struct device *dev) 1915 { 1916 return 0; 1917 } 1918 1919 static int byt_gpio_runtime_resume(struct device *dev) 1920 { 1921 return 0; 1922 } 1923 #endif 1924 1925 static const struct dev_pm_ops byt_gpio_pm_ops = { 1926 SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume) 1927 SET_RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume, 1928 NULL) 1929 }; 1930 1931 static struct platform_driver byt_gpio_driver = { 1932 .probe = byt_pinctrl_probe, 1933 .driver = { 1934 .name = "byt_gpio", 1935 .pm = &byt_gpio_pm_ops, 1936 .suppress_bind_attrs = true, 1937 1938 .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match), 1939 }, 1940 }; 1941 1942 static int __init byt_gpio_init(void) 1943 { 1944 return platform_driver_register(&byt_gpio_driver); 1945 } 1946 subsys_initcall(byt_gpio_init); 1947