1 /* 2 * Pinctrl GPIO driver for Intel Baytrail 3 * Copyright (c) 2012-2013, Intel Corporation. 4 * 5 * Author: Mathias Nyman <mathias.nyman@linux.intel.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 */ 16 17 #include <linux/kernel.h> 18 #include <linux/init.h> 19 #include <linux/types.h> 20 #include <linux/bitops.h> 21 #include <linux/interrupt.h> 22 #include <linux/gpio.h> 23 #include <linux/gpio/driver.h> 24 #include <linux/acpi.h> 25 #include <linux/platform_device.h> 26 #include <linux/seq_file.h> 27 #include <linux/io.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/pinctrl/pinctrl.h> 30 #include <linux/pinctrl/pinmux.h> 31 #include <linux/pinctrl/pinconf.h> 32 #include <linux/pinctrl/pinconf-generic.h> 33 34 /* memory mapped register offsets */ 35 #define BYT_CONF0_REG 0x000 36 #define BYT_CONF1_REG 0x004 37 #define BYT_VAL_REG 0x008 38 #define BYT_DFT_REG 0x00c 39 #define BYT_INT_STAT_REG 0x800 40 #define BYT_DEBOUNCE_REG 0x9d0 41 42 /* BYT_CONF0_REG register bits */ 43 #define BYT_IODEN BIT(31) 44 #define BYT_DIRECT_IRQ_EN BIT(27) 45 #define BYT_TRIG_NEG BIT(26) 46 #define BYT_TRIG_POS BIT(25) 47 #define BYT_TRIG_LVL BIT(24) 48 #define BYT_DEBOUNCE_EN BIT(20) 49 #define BYT_PULL_STR_SHIFT 9 50 #define BYT_PULL_STR_MASK (3 << BYT_PULL_STR_SHIFT) 51 #define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT) 52 #define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT) 53 #define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT) 54 #define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT) 55 #define BYT_PULL_ASSIGN_SHIFT 7 56 #define BYT_PULL_ASSIGN_MASK (3 << BYT_PULL_ASSIGN_SHIFT) 57 #define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT) 58 #define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT) 59 #define BYT_PIN_MUX 0x07 60 61 /* BYT_VAL_REG register bits */ 62 #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/ 63 #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/ 64 #define BYT_LEVEL BIT(0) 65 66 #define BYT_DIR_MASK (BIT(1) | BIT(2)) 67 #define BYT_TRIG_MASK (BIT(26) | BIT(25) | BIT(24)) 68 69 #define BYT_CONF0_RESTORE_MASK (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | \ 70 BYT_PIN_MUX) 71 #define BYT_VAL_RESTORE_MASK (BYT_DIR_MASK | BYT_LEVEL) 72 73 /* BYT_DEBOUNCE_REG bits */ 74 #define BYT_DEBOUNCE_PULSE_MASK 0x7 75 #define BYT_DEBOUNCE_PULSE_375US 1 76 #define BYT_DEBOUNCE_PULSE_750US 2 77 #define BYT_DEBOUNCE_PULSE_1500US 3 78 #define BYT_DEBOUNCE_PULSE_3MS 4 79 #define BYT_DEBOUNCE_PULSE_6MS 5 80 #define BYT_DEBOUNCE_PULSE_12MS 6 81 #define BYT_DEBOUNCE_PULSE_24MS 7 82 83 #define BYT_NGPIO_SCORE 102 84 #define BYT_NGPIO_NCORE 28 85 #define BYT_NGPIO_SUS 44 86 87 #define BYT_SCORE_ACPI_UID "1" 88 #define BYT_NCORE_ACPI_UID "2" 89 #define BYT_SUS_ACPI_UID "3" 90 91 /* 92 * This is the function value most pins have for GPIO muxing. If the value 93 * differs from the default one, it must be explicitly mentioned. Otherwise, the 94 * pin control implementation will set the muxing value to default GPIO if it 95 * does not find a match for the requested function. 96 */ 97 #define BYT_DEFAULT_GPIO_MUX 0 98 99 struct byt_gpio_pin_context { 100 u32 conf0; 101 u32 val; 102 }; 103 104 struct byt_simple_func_mux { 105 const char *name; 106 unsigned short func; 107 }; 108 109 struct byt_mixed_func_mux { 110 const char *name; 111 const unsigned short *func_values; 112 }; 113 114 struct byt_pingroup { 115 const char *name; 116 const unsigned int *pins; 117 size_t npins; 118 unsigned short has_simple_funcs; 119 union { 120 const struct byt_simple_func_mux *simple_funcs; 121 const struct byt_mixed_func_mux *mixed_funcs; 122 }; 123 size_t nfuncs; 124 }; 125 126 struct byt_function { 127 const char *name; 128 const char * const *groups; 129 size_t ngroups; 130 }; 131 132 struct byt_community { 133 unsigned int pin_base; 134 size_t npins; 135 const unsigned int *pad_map; 136 void __iomem *reg_base; 137 }; 138 139 #define SIMPLE_FUNC(n, f) \ 140 { \ 141 .name = (n), \ 142 .func = (f), \ 143 } 144 #define MIXED_FUNC(n, f) \ 145 { \ 146 .name = (n), \ 147 .func_values = (f), \ 148 } 149 150 #define PIN_GROUP_SIMPLE(n, p, f) \ 151 { \ 152 .name = (n), \ 153 .pins = (p), \ 154 .npins = ARRAY_SIZE((p)), \ 155 .has_simple_funcs = 1, \ 156 { \ 157 .simple_funcs = (f), \ 158 }, \ 159 .nfuncs = ARRAY_SIZE((f)), \ 160 } 161 #define PIN_GROUP_MIXED(n, p, f) \ 162 { \ 163 .name = (n), \ 164 .pins = (p), \ 165 .npins = ARRAY_SIZE((p)), \ 166 .has_simple_funcs = 0, \ 167 { \ 168 .mixed_funcs = (f), \ 169 }, \ 170 .nfuncs = ARRAY_SIZE((f)), \ 171 } 172 173 #define FUNCTION(n, g) \ 174 { \ 175 .name = (n), \ 176 .groups = (g), \ 177 .ngroups = ARRAY_SIZE((g)), \ 178 } 179 180 #define COMMUNITY(p, n, map) \ 181 { \ 182 .pin_base = (p), \ 183 .npins = (n), \ 184 .pad_map = (map),\ 185 } 186 187 struct byt_pinctrl_soc_data { 188 const char *uid; 189 const struct pinctrl_pin_desc *pins; 190 size_t npins; 191 const struct byt_pingroup *groups; 192 size_t ngroups; 193 const struct byt_function *functions; 194 size_t nfunctions; 195 const struct byt_community *communities; 196 size_t ncommunities; 197 }; 198 199 struct byt_gpio { 200 struct gpio_chip chip; 201 struct platform_device *pdev; 202 struct pinctrl_dev *pctl_dev; 203 struct pinctrl_desc pctl_desc; 204 raw_spinlock_t lock; 205 const struct byt_pinctrl_soc_data *soc_data; 206 struct byt_community *communities_copy; 207 struct byt_gpio_pin_context *saved_context; 208 }; 209 210 /* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */ 211 static const struct pinctrl_pin_desc byt_score_pins[] = { 212 PINCTRL_PIN(0, "SATA_GP0"), 213 PINCTRL_PIN(1, "SATA_GP1"), 214 PINCTRL_PIN(2, "SATA_LED#"), 215 PINCTRL_PIN(3, "PCIE_CLKREQ0"), 216 PINCTRL_PIN(4, "PCIE_CLKREQ1"), 217 PINCTRL_PIN(5, "PCIE_CLKREQ2"), 218 PINCTRL_PIN(6, "PCIE_CLKREQ3"), 219 PINCTRL_PIN(7, "SD3_WP"), 220 PINCTRL_PIN(8, "HDA_RST"), 221 PINCTRL_PIN(9, "HDA_SYNC"), 222 PINCTRL_PIN(10, "HDA_CLK"), 223 PINCTRL_PIN(11, "HDA_SDO"), 224 PINCTRL_PIN(12, "HDA_SDI0"), 225 PINCTRL_PIN(13, "HDA_SDI1"), 226 PINCTRL_PIN(14, "GPIO_S0_SC14"), 227 PINCTRL_PIN(15, "GPIO_S0_SC15"), 228 PINCTRL_PIN(16, "MMC1_CLK"), 229 PINCTRL_PIN(17, "MMC1_D0"), 230 PINCTRL_PIN(18, "MMC1_D1"), 231 PINCTRL_PIN(19, "MMC1_D2"), 232 PINCTRL_PIN(20, "MMC1_D3"), 233 PINCTRL_PIN(21, "MMC1_D4"), 234 PINCTRL_PIN(22, "MMC1_D5"), 235 PINCTRL_PIN(23, "MMC1_D6"), 236 PINCTRL_PIN(24, "MMC1_D7"), 237 PINCTRL_PIN(25, "MMC1_CMD"), 238 PINCTRL_PIN(26, "MMC1_RST"), 239 PINCTRL_PIN(27, "SD2_CLK"), 240 PINCTRL_PIN(28, "SD2_D0"), 241 PINCTRL_PIN(29, "SD2_D1"), 242 PINCTRL_PIN(30, "SD2_D2"), 243 PINCTRL_PIN(31, "SD2_D3_CD"), 244 PINCTRL_PIN(32, "SD2_CMD"), 245 PINCTRL_PIN(33, "SD3_CLK"), 246 PINCTRL_PIN(34, "SD3_D0"), 247 PINCTRL_PIN(35, "SD3_D1"), 248 PINCTRL_PIN(36, "SD3_D2"), 249 PINCTRL_PIN(37, "SD3_D3"), 250 PINCTRL_PIN(38, "SD3_CD"), 251 PINCTRL_PIN(39, "SD3_CMD"), 252 PINCTRL_PIN(40, "SD3_1P8EN"), 253 PINCTRL_PIN(41, "SD3_PWREN#"), 254 PINCTRL_PIN(42, "ILB_LPC_AD0"), 255 PINCTRL_PIN(43, "ILB_LPC_AD1"), 256 PINCTRL_PIN(44, "ILB_LPC_AD2"), 257 PINCTRL_PIN(45, "ILB_LPC_AD3"), 258 PINCTRL_PIN(46, "ILB_LPC_FRAME"), 259 PINCTRL_PIN(47, "ILB_LPC_CLK0"), 260 PINCTRL_PIN(48, "ILB_LPC_CLK1"), 261 PINCTRL_PIN(49, "ILB_LPC_CLKRUN"), 262 PINCTRL_PIN(50, "ILB_LPC_SERIRQ"), 263 PINCTRL_PIN(51, "PCU_SMB_DATA"), 264 PINCTRL_PIN(52, "PCU_SMB_CLK"), 265 PINCTRL_PIN(53, "PCU_SMB_ALERT"), 266 PINCTRL_PIN(54, "ILB_8254_SPKR"), 267 PINCTRL_PIN(55, "GPIO_S0_SC55"), 268 PINCTRL_PIN(56, "GPIO_S0_SC56"), 269 PINCTRL_PIN(57, "GPIO_S0_SC57"), 270 PINCTRL_PIN(58, "GPIO_S0_SC58"), 271 PINCTRL_PIN(59, "GPIO_S0_SC59"), 272 PINCTRL_PIN(60, "GPIO_S0_SC60"), 273 PINCTRL_PIN(61, "GPIO_S0_SC61"), 274 PINCTRL_PIN(62, "LPE_I2S2_CLK"), 275 PINCTRL_PIN(63, "LPE_I2S2_FRM"), 276 PINCTRL_PIN(64, "LPE_I2S2_DATAIN"), 277 PINCTRL_PIN(65, "LPE_I2S2_DATAOUT"), 278 PINCTRL_PIN(66, "SIO_SPI_CS"), 279 PINCTRL_PIN(67, "SIO_SPI_MISO"), 280 PINCTRL_PIN(68, "SIO_SPI_MOSI"), 281 PINCTRL_PIN(69, "SIO_SPI_CLK"), 282 PINCTRL_PIN(70, "SIO_UART1_RXD"), 283 PINCTRL_PIN(71, "SIO_UART1_TXD"), 284 PINCTRL_PIN(72, "SIO_UART1_RTS"), 285 PINCTRL_PIN(73, "SIO_UART1_CTS"), 286 PINCTRL_PIN(74, "SIO_UART2_RXD"), 287 PINCTRL_PIN(75, "SIO_UART2_TXD"), 288 PINCTRL_PIN(76, "SIO_UART2_RTS"), 289 PINCTRL_PIN(77, "SIO_UART2_CTS"), 290 PINCTRL_PIN(78, "SIO_I2C0_DATA"), 291 PINCTRL_PIN(79, "SIO_I2C0_CLK"), 292 PINCTRL_PIN(80, "SIO_I2C1_DATA"), 293 PINCTRL_PIN(81, "SIO_I2C1_CLK"), 294 PINCTRL_PIN(82, "SIO_I2C2_DATA"), 295 PINCTRL_PIN(83, "SIO_I2C2_CLK"), 296 PINCTRL_PIN(84, "SIO_I2C3_DATA"), 297 PINCTRL_PIN(85, "SIO_I2C3_CLK"), 298 PINCTRL_PIN(86, "SIO_I2C4_DATA"), 299 PINCTRL_PIN(87, "SIO_I2C4_CLK"), 300 PINCTRL_PIN(88, "SIO_I2C5_DATA"), 301 PINCTRL_PIN(89, "SIO_I2C5_CLK"), 302 PINCTRL_PIN(90, "SIO_I2C6_DATA"), 303 PINCTRL_PIN(91, "SIO_I2C6_CLK"), 304 PINCTRL_PIN(92, "GPIO_S0_SC92"), 305 PINCTRL_PIN(93, "GPIO_S0_SC93"), 306 PINCTRL_PIN(94, "SIO_PWM0"), 307 PINCTRL_PIN(95, "SIO_PWM1"), 308 PINCTRL_PIN(96, "PMC_PLT_CLK0"), 309 PINCTRL_PIN(97, "PMC_PLT_CLK1"), 310 PINCTRL_PIN(98, "PMC_PLT_CLK2"), 311 PINCTRL_PIN(99, "PMC_PLT_CLK3"), 312 PINCTRL_PIN(100, "PMC_PLT_CLK4"), 313 PINCTRL_PIN(101, "PMC_PLT_CLK5"), 314 }; 315 316 static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = { 317 85, 89, 93, 96, 99, 102, 98, 101, 34, 37, 318 36, 38, 39, 35, 40, 84, 62, 61, 64, 59, 319 54, 56, 60, 55, 63, 57, 51, 50, 53, 47, 320 52, 49, 48, 43, 46, 41, 45, 42, 58, 44, 321 95, 105, 70, 68, 67, 66, 69, 71, 65, 72, 322 86, 90, 88, 92, 103, 77, 79, 83, 78, 81, 323 80, 82, 13, 12, 15, 14, 17, 18, 19, 16, 324 2, 1, 0, 4, 6, 7, 9, 8, 33, 32, 325 31, 30, 29, 27, 25, 28, 26, 23, 21, 20, 326 24, 22, 5, 3, 10, 11, 106, 87, 91, 104, 327 97, 100, 328 }; 329 330 /* SCORE groups */ 331 static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 }; 332 static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 }; 333 static const struct byt_simple_func_mux byt_score_uart_mux[] = { 334 SIMPLE_FUNC("uart", 1), 335 }; 336 337 static const unsigned int byt_score_pwm0_pins[] = { 94 }; 338 static const unsigned int byt_score_pwm1_pins[] = { 95 }; 339 static const struct byt_simple_func_mux byt_score_pwm_mux[] = { 340 SIMPLE_FUNC("pwm", 1), 341 }; 342 343 static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 }; 344 static const struct byt_simple_func_mux byt_score_spi_mux[] = { 345 SIMPLE_FUNC("spi", 1), 346 }; 347 348 static const unsigned int byt_score_i2c5_pins[] = { 88, 89 }; 349 static const unsigned int byt_score_i2c6_pins[] = { 90, 91 }; 350 static const unsigned int byt_score_i2c4_pins[] = { 86, 87 }; 351 static const unsigned int byt_score_i2c3_pins[] = { 84, 85 }; 352 static const unsigned int byt_score_i2c2_pins[] = { 82, 83 }; 353 static const unsigned int byt_score_i2c1_pins[] = { 80, 81 }; 354 static const unsigned int byt_score_i2c0_pins[] = { 78, 79 }; 355 static const struct byt_simple_func_mux byt_score_i2c_mux[] = { 356 SIMPLE_FUNC("i2c", 1), 357 }; 358 359 static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 }; 360 static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 }; 361 static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 }; 362 static const struct byt_simple_func_mux byt_score_ssp_mux[] = { 363 SIMPLE_FUNC("ssp", 1), 364 }; 365 366 static const unsigned int byt_score_sdcard_pins[] = { 367 7, 33, 34, 35, 36, 37, 38, 39, 40, 41, 368 }; 369 static const unsigned short byt_score_sdcard_mux_values[] = { 370 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 371 }; 372 static const struct byt_mixed_func_mux byt_score_sdcard_mux[] = { 373 MIXED_FUNC("sdcard", byt_score_sdcard_mux_values), 374 }; 375 376 static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 }; 377 static const struct byt_simple_func_mux byt_score_sdio_mux[] = { 378 SIMPLE_FUNC("sdio", 1), 379 }; 380 381 static const unsigned int byt_score_emmc_pins[] = { 382 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 383 }; 384 static const struct byt_simple_func_mux byt_score_emmc_mux[] = { 385 SIMPLE_FUNC("emmc", 1), 386 }; 387 388 static const unsigned int byt_score_ilb_lpc_pins[] = { 389 42, 43, 44, 45, 46, 47, 48, 49, 50, 390 }; 391 static const struct byt_simple_func_mux byt_score_lpc_mux[] = { 392 SIMPLE_FUNC("lpc", 1), 393 }; 394 395 static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 }; 396 static const struct byt_simple_func_mux byt_score_sata_mux[] = { 397 SIMPLE_FUNC("sata", 1), 398 }; 399 400 static const unsigned int byt_score_plt_clk0_pins[] = { 96 }; 401 static const unsigned int byt_score_plt_clk1_pins[] = { 97 }; 402 static const unsigned int byt_score_plt_clk2_pins[] = { 98 }; 403 static const unsigned int byt_score_plt_clk3_pins[] = { 99 }; 404 static const unsigned int byt_score_plt_clk4_pins[] = { 100 }; 405 static const unsigned int byt_score_plt_clk5_pins[] = { 101 }; 406 static const struct byt_simple_func_mux byt_score_plt_clk_mux[] = { 407 SIMPLE_FUNC("plt_clk", 1), 408 }; 409 410 static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 }; 411 static const struct byt_simple_func_mux byt_score_smbus_mux[] = { 412 SIMPLE_FUNC("smbus", 1), 413 }; 414 415 static const struct byt_pingroup byt_score_groups[] = { 416 PIN_GROUP_SIMPLE("uart1_grp", 417 byt_score_uart1_pins, byt_score_uart_mux), 418 PIN_GROUP_SIMPLE("uart2_grp", 419 byt_score_uart2_pins, byt_score_uart_mux), 420 PIN_GROUP_SIMPLE("pwm0_grp", 421 byt_score_pwm0_pins, byt_score_pwm_mux), 422 PIN_GROUP_SIMPLE("pwm1_grp", 423 byt_score_pwm1_pins, byt_score_pwm_mux), 424 PIN_GROUP_SIMPLE("ssp2_grp", 425 byt_score_ssp2_pins, byt_score_pwm_mux), 426 PIN_GROUP_SIMPLE("sio_spi_grp", 427 byt_score_sio_spi_pins, byt_score_spi_mux), 428 PIN_GROUP_SIMPLE("i2c5_grp", 429 byt_score_i2c5_pins, byt_score_i2c_mux), 430 PIN_GROUP_SIMPLE("i2c6_grp", 431 byt_score_i2c6_pins, byt_score_i2c_mux), 432 PIN_GROUP_SIMPLE("i2c4_grp", 433 byt_score_i2c4_pins, byt_score_i2c_mux), 434 PIN_GROUP_SIMPLE("i2c3_grp", 435 byt_score_i2c3_pins, byt_score_i2c_mux), 436 PIN_GROUP_SIMPLE("i2c2_grp", 437 byt_score_i2c2_pins, byt_score_i2c_mux), 438 PIN_GROUP_SIMPLE("i2c1_grp", 439 byt_score_i2c1_pins, byt_score_i2c_mux), 440 PIN_GROUP_SIMPLE("i2c0_grp", 441 byt_score_i2c0_pins, byt_score_i2c_mux), 442 PIN_GROUP_SIMPLE("ssp0_grp", 443 byt_score_ssp0_pins, byt_score_ssp_mux), 444 PIN_GROUP_SIMPLE("ssp1_grp", 445 byt_score_ssp1_pins, byt_score_ssp_mux), 446 PIN_GROUP_MIXED("sdcard_grp", 447 byt_score_sdcard_pins, byt_score_sdcard_mux), 448 PIN_GROUP_SIMPLE("sdio_grp", 449 byt_score_sdio_pins, byt_score_sdio_mux), 450 PIN_GROUP_SIMPLE("emmc_grp", 451 byt_score_emmc_pins, byt_score_emmc_mux), 452 PIN_GROUP_SIMPLE("lpc_grp", 453 byt_score_ilb_lpc_pins, byt_score_lpc_mux), 454 PIN_GROUP_SIMPLE("sata_grp", 455 byt_score_sata_pins, byt_score_sata_mux), 456 PIN_GROUP_SIMPLE("plt_clk0_grp", 457 byt_score_plt_clk0_pins, byt_score_plt_clk_mux), 458 PIN_GROUP_SIMPLE("plt_clk1_grp", 459 byt_score_plt_clk1_pins, byt_score_plt_clk_mux), 460 PIN_GROUP_SIMPLE("plt_clk2_grp", 461 byt_score_plt_clk2_pins, byt_score_plt_clk_mux), 462 PIN_GROUP_SIMPLE("plt_clk3_grp", 463 byt_score_plt_clk3_pins, byt_score_plt_clk_mux), 464 PIN_GROUP_SIMPLE("plt_clk4_grp", 465 byt_score_plt_clk4_pins, byt_score_plt_clk_mux), 466 PIN_GROUP_SIMPLE("plt_clk5_grp", 467 byt_score_plt_clk5_pins, byt_score_plt_clk_mux), 468 PIN_GROUP_SIMPLE("smbus_grp", 469 byt_score_smbus_pins, byt_score_smbus_mux), 470 }; 471 472 static const char * const byt_score_uart_groups[] = { 473 "uart1_grp", "uart2_grp", 474 }; 475 static const char * const byt_score_pwm_groups[] = { 476 "pwm0_grp", "pwm1_grp", 477 }; 478 static const char * const byt_score_ssp_groups[] = { 479 "ssp0_grp", "ssp1_grp", "ssp2_grp", 480 }; 481 static const char * const byt_score_spi_groups[] = { "sio_spi_grp" }; 482 static const char * const byt_score_i2c_groups[] = { 483 "i2c0_grp", "i2c1_grp", "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", 484 "i2c6_grp", 485 }; 486 static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" }; 487 static const char * const byt_score_sdio_groups[] = { "sdio_grp" }; 488 static const char * const byt_score_emmc_groups[] = { "emmc_grp" }; 489 static const char * const byt_score_lpc_groups[] = { "lpc_grp" }; 490 static const char * const byt_score_sata_groups[] = { "sata_grp" }; 491 static const char * const byt_score_plt_clk_groups[] = { 492 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp", 493 "plt_clk4_grp", "plt_clk5_grp", 494 }; 495 static const char * const byt_score_smbus_groups[] = { "smbus_grp" }; 496 static const char * const byt_score_gpio_groups[] = { 497 "uart1_grp", "uart2_grp", "pwm0_grp", "pwm1_grp", "ssp0_grp", 498 "ssp1_grp", "ssp2_grp", "sio_spi_grp", "i2c0_grp", "i2c1_grp", 499 "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", "i2c6_grp", 500 "sdcard_grp", "sdio_grp", "emmc_grp", "lpc_grp", "sata_grp", 501 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp", 502 "plt_clk4_grp", "plt_clk5_grp", "smbus_grp", 503 504 }; 505 506 static const struct byt_function byt_score_functions[] = { 507 FUNCTION("uart", byt_score_uart_groups), 508 FUNCTION("pwm", byt_score_pwm_groups), 509 FUNCTION("ssp", byt_score_ssp_groups), 510 FUNCTION("spi", byt_score_spi_groups), 511 FUNCTION("i2c", byt_score_i2c_groups), 512 FUNCTION("sdcard", byt_score_sdcard_groups), 513 FUNCTION("sdio", byt_score_sdio_groups), 514 FUNCTION("emmc", byt_score_emmc_groups), 515 FUNCTION("lpc", byt_score_lpc_groups), 516 FUNCTION("sata", byt_score_sata_groups), 517 FUNCTION("plt_clk", byt_score_plt_clk_groups), 518 FUNCTION("smbus", byt_score_smbus_groups), 519 FUNCTION("gpio", byt_score_gpio_groups), 520 }; 521 522 static const struct byt_community byt_score_communities[] = { 523 COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map), 524 }; 525 526 static const struct byt_pinctrl_soc_data byt_score_soc_data = { 527 .uid = BYT_SCORE_ACPI_UID, 528 .pins = byt_score_pins, 529 .npins = ARRAY_SIZE(byt_score_pins), 530 .groups = byt_score_groups, 531 .ngroups = ARRAY_SIZE(byt_score_groups), 532 .functions = byt_score_functions, 533 .nfunctions = ARRAY_SIZE(byt_score_functions), 534 .communities = byt_score_communities, 535 .ncommunities = ARRAY_SIZE(byt_score_communities), 536 }; 537 538 /* SUS pins, aka GPIOS_<pin_no> or GPIO_S5[<pin_no>] */ 539 static const struct pinctrl_pin_desc byt_sus_pins[] = { 540 PINCTRL_PIN(0, "GPIO_S50"), 541 PINCTRL_PIN(1, "GPIO_S51"), 542 PINCTRL_PIN(2, "GPIO_S52"), 543 PINCTRL_PIN(3, "GPIO_S53"), 544 PINCTRL_PIN(4, "GPIO_S54"), 545 PINCTRL_PIN(5, "GPIO_S55"), 546 PINCTRL_PIN(6, "GPIO_S56"), 547 PINCTRL_PIN(7, "GPIO_S57"), 548 PINCTRL_PIN(8, "GPIO_S58"), 549 PINCTRL_PIN(9, "GPIO_S59"), 550 PINCTRL_PIN(10, "GPIO_S510"), 551 PINCTRL_PIN(11, "PMC_SUSPWRDNACK"), 552 PINCTRL_PIN(12, "PMC_SUSCLK0"), 553 PINCTRL_PIN(13, "GPIO_S513"), 554 PINCTRL_PIN(14, "USB_ULPI_RST"), 555 PINCTRL_PIN(15, "PMC_WAKE_PCIE0#"), 556 PINCTRL_PIN(16, "PMC_PWRBTN"), 557 PINCTRL_PIN(17, "GPIO_S517"), 558 PINCTRL_PIN(18, "PMC_SUS_STAT"), 559 PINCTRL_PIN(19, "USB_OC0"), 560 PINCTRL_PIN(20, "USB_OC1"), 561 PINCTRL_PIN(21, "PCU_SPI_CS1"), 562 PINCTRL_PIN(22, "GPIO_S522"), 563 PINCTRL_PIN(23, "GPIO_S523"), 564 PINCTRL_PIN(24, "GPIO_S524"), 565 PINCTRL_PIN(25, "GPIO_S525"), 566 PINCTRL_PIN(26, "GPIO_S526"), 567 PINCTRL_PIN(27, "GPIO_S527"), 568 PINCTRL_PIN(28, "GPIO_S528"), 569 PINCTRL_PIN(29, "GPIO_S529"), 570 PINCTRL_PIN(30, "GPIO_S530"), 571 PINCTRL_PIN(31, "USB_ULPI_CLK"), 572 PINCTRL_PIN(32, "USB_ULPI_DATA0"), 573 PINCTRL_PIN(33, "USB_ULPI_DATA1"), 574 PINCTRL_PIN(34, "USB_ULPI_DATA2"), 575 PINCTRL_PIN(35, "USB_ULPI_DATA3"), 576 PINCTRL_PIN(36, "USB_ULPI_DATA4"), 577 PINCTRL_PIN(37, "USB_ULPI_DATA5"), 578 PINCTRL_PIN(38, "USB_ULPI_DATA6"), 579 PINCTRL_PIN(39, "USB_ULPI_DATA7"), 580 PINCTRL_PIN(40, "USB_ULPI_DIR"), 581 PINCTRL_PIN(41, "USB_ULPI_NXT"), 582 PINCTRL_PIN(42, "USB_ULPI_STP"), 583 PINCTRL_PIN(43, "USB_ULPI_REFCLK"), 584 }; 585 586 static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = { 587 29, 33, 30, 31, 32, 34, 36, 35, 38, 37, 588 18, 7, 11, 20, 17, 1, 8, 10, 19, 12, 589 0, 2, 23, 39, 28, 27, 22, 21, 24, 25, 590 26, 51, 56, 54, 49, 55, 48, 57, 50, 58, 591 52, 53, 59, 40, 592 }; 593 594 static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 }; 595 static const struct byt_simple_func_mux byt_sus_usb_oc_mux[] = { 596 SIMPLE_FUNC("usb", 0), 597 SIMPLE_FUNC("gpio", 1), 598 }; 599 600 static const unsigned int byt_sus_usb_ulpi_pins[] = { 601 14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 602 }; 603 static const unsigned short byt_sus_usb_ulpi_mode_values[] = { 604 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 605 }; 606 static const unsigned short byt_sus_usb_ulpi_gpio_mode_values[] = { 607 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 608 }; 609 static const struct byt_mixed_func_mux byt_sus_usb_ulpi_mux[] = { 610 MIXED_FUNC("usb", byt_sus_usb_ulpi_mode_values), 611 MIXED_FUNC("gpio", byt_sus_usb_ulpi_gpio_mode_values), 612 }; 613 614 static const unsigned int byt_sus_pcu_spi_pins[] = { 21 }; 615 static const struct byt_simple_func_mux byt_sus_pcu_spi_mux[] = { 616 SIMPLE_FUNC("spi", 0), 617 SIMPLE_FUNC("gpio", 1), 618 }; 619 620 static const struct byt_pingroup byt_sus_groups[] = { 621 PIN_GROUP_SIMPLE("usb_oc_grp", 622 byt_sus_usb_over_current_pins, byt_sus_usb_oc_mux), 623 PIN_GROUP_MIXED("usb_ulpi_grp", 624 byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mux), 625 PIN_GROUP_SIMPLE("pcu_spi_grp", 626 byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mux), 627 }; 628 629 static const char * const byt_sus_usb_groups[] = { 630 "usb_oc_grp", "usb_ulpi_grp", 631 }; 632 static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" }; 633 static const char * const byt_sus_gpio_groups[] = { 634 "usb_oc_grp", "usb_ulpi_grp", "pcu_spi_grp", 635 }; 636 637 static const struct byt_function byt_sus_functions[] = { 638 FUNCTION("usb", byt_sus_usb_groups), 639 FUNCTION("spi", byt_sus_spi_groups), 640 FUNCTION("gpio", byt_sus_gpio_groups), 641 }; 642 643 static const struct byt_community byt_sus_communities[] = { 644 COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map), 645 }; 646 647 static const struct byt_pinctrl_soc_data byt_sus_soc_data = { 648 .uid = BYT_SUS_ACPI_UID, 649 .pins = byt_sus_pins, 650 .npins = ARRAY_SIZE(byt_sus_pins), 651 .groups = byt_sus_groups, 652 .ngroups = ARRAY_SIZE(byt_sus_groups), 653 .functions = byt_sus_functions, 654 .nfunctions = ARRAY_SIZE(byt_sus_functions), 655 .communities = byt_sus_communities, 656 .ncommunities = ARRAY_SIZE(byt_sus_communities), 657 }; 658 659 static const struct pinctrl_pin_desc byt_ncore_pins[] = { 660 PINCTRL_PIN(0, "GPIO_NCORE0"), 661 PINCTRL_PIN(1, "GPIO_NCORE1"), 662 PINCTRL_PIN(2, "GPIO_NCORE2"), 663 PINCTRL_PIN(3, "GPIO_NCORE3"), 664 PINCTRL_PIN(4, "GPIO_NCORE4"), 665 PINCTRL_PIN(5, "GPIO_NCORE5"), 666 PINCTRL_PIN(6, "GPIO_NCORE6"), 667 PINCTRL_PIN(7, "GPIO_NCORE7"), 668 PINCTRL_PIN(8, "GPIO_NCORE8"), 669 PINCTRL_PIN(9, "GPIO_NCORE9"), 670 PINCTRL_PIN(10, "GPIO_NCORE10"), 671 PINCTRL_PIN(11, "GPIO_NCORE11"), 672 PINCTRL_PIN(12, "GPIO_NCORE12"), 673 PINCTRL_PIN(13, "GPIO_NCORE13"), 674 PINCTRL_PIN(14, "GPIO_NCORE14"), 675 PINCTRL_PIN(15, "GPIO_NCORE15"), 676 PINCTRL_PIN(16, "GPIO_NCORE16"), 677 PINCTRL_PIN(17, "GPIO_NCORE17"), 678 PINCTRL_PIN(18, "GPIO_NCORE18"), 679 PINCTRL_PIN(19, "GPIO_NCORE19"), 680 PINCTRL_PIN(20, "GPIO_NCORE20"), 681 PINCTRL_PIN(21, "GPIO_NCORE21"), 682 PINCTRL_PIN(22, "GPIO_NCORE22"), 683 PINCTRL_PIN(23, "GPIO_NCORE23"), 684 PINCTRL_PIN(24, "GPIO_NCORE24"), 685 PINCTRL_PIN(25, "GPIO_NCORE25"), 686 PINCTRL_PIN(26, "GPIO_NCORE26"), 687 PINCTRL_PIN(27, "GPIO_NCORE27"), 688 }; 689 690 static unsigned const byt_ncore_pins_map[BYT_NGPIO_NCORE] = { 691 19, 18, 17, 20, 21, 22, 24, 25, 23, 16, 692 14, 15, 12, 26, 27, 1, 4, 8, 11, 0, 693 3, 6, 10, 13, 2, 5, 9, 7, 694 }; 695 696 static const struct byt_community byt_ncore_communities[] = { 697 COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map), 698 }; 699 700 static const struct byt_pinctrl_soc_data byt_ncore_soc_data = { 701 .uid = BYT_NCORE_ACPI_UID, 702 .pins = byt_ncore_pins, 703 .npins = ARRAY_SIZE(byt_ncore_pins), 704 .communities = byt_ncore_communities, 705 .ncommunities = ARRAY_SIZE(byt_ncore_communities), 706 }; 707 708 static const struct byt_pinctrl_soc_data *byt_soc_data[] = { 709 &byt_score_soc_data, 710 &byt_sus_soc_data, 711 &byt_ncore_soc_data, 712 NULL, 713 }; 714 715 static struct byt_community *byt_get_community(struct byt_gpio *vg, 716 unsigned int pin) 717 { 718 struct byt_community *comm; 719 int i; 720 721 for (i = 0; i < vg->soc_data->ncommunities; i++) { 722 comm = vg->communities_copy + i; 723 if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base) 724 return comm; 725 } 726 727 return NULL; 728 } 729 730 static void __iomem *byt_gpio_reg(struct byt_gpio *vg, unsigned int offset, 731 int reg) 732 { 733 struct byt_community *comm = byt_get_community(vg, offset); 734 u32 reg_offset; 735 736 if (!comm) 737 return NULL; 738 739 offset -= comm->pin_base; 740 switch (reg) { 741 case BYT_INT_STAT_REG: 742 reg_offset = (offset / 32) * 4; 743 break; 744 case BYT_DEBOUNCE_REG: 745 reg_offset = 0; 746 break; 747 default: 748 reg_offset = comm->pad_map[offset] * 16; 749 break; 750 } 751 752 return comm->reg_base + reg_offset + reg; 753 } 754 755 static int byt_get_groups_count(struct pinctrl_dev *pctldev) 756 { 757 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); 758 759 return vg->soc_data->ngroups; 760 } 761 762 static const char *byt_get_group_name(struct pinctrl_dev *pctldev, 763 unsigned int selector) 764 { 765 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); 766 767 return vg->soc_data->groups[selector].name; 768 } 769 770 static int byt_get_group_pins(struct pinctrl_dev *pctldev, 771 unsigned int selector, 772 const unsigned int **pins, 773 unsigned int *num_pins) 774 { 775 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); 776 777 *pins = vg->soc_data->groups[selector].pins; 778 *num_pins = vg->soc_data->groups[selector].npins; 779 780 return 0; 781 } 782 783 static const struct pinctrl_ops byt_pinctrl_ops = { 784 .get_groups_count = byt_get_groups_count, 785 .get_group_name = byt_get_group_name, 786 .get_group_pins = byt_get_group_pins, 787 }; 788 789 static int byt_get_functions_count(struct pinctrl_dev *pctldev) 790 { 791 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); 792 793 return vg->soc_data->nfunctions; 794 } 795 796 static const char *byt_get_function_name(struct pinctrl_dev *pctldev, 797 unsigned int selector) 798 { 799 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); 800 801 return vg->soc_data->functions[selector].name; 802 } 803 804 static int byt_get_function_groups(struct pinctrl_dev *pctldev, 805 unsigned int selector, 806 const char * const **groups, 807 unsigned int *num_groups) 808 { 809 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); 810 811 *groups = vg->soc_data->functions[selector].groups; 812 *num_groups = vg->soc_data->functions[selector].ngroups; 813 814 return 0; 815 } 816 817 static int byt_get_group_simple_mux(const struct byt_pingroup group, 818 const char *func_name, 819 unsigned short *func) 820 { 821 int i; 822 823 for (i = 0; i < group.nfuncs; i++) { 824 if (!strcmp(group.simple_funcs[i].name, func_name)) { 825 *func = group.simple_funcs[i].func; 826 return 0; 827 } 828 } 829 830 return 1; 831 } 832 833 static int byt_get_group_mixed_mux(const struct byt_pingroup group, 834 const char *func_name, 835 const unsigned short **func) 836 { 837 int i; 838 839 for (i = 0; i < group.nfuncs; i++) { 840 if (!strcmp(group.mixed_funcs[i].name, func_name)) { 841 *func = group.mixed_funcs[i].func_values; 842 return 0; 843 } 844 } 845 846 return 1; 847 } 848 849 static void byt_set_group_simple_mux(struct byt_gpio *vg, 850 const struct byt_pingroup group, 851 unsigned short func) 852 { 853 unsigned long flags; 854 int i; 855 856 raw_spin_lock_irqsave(&vg->lock, flags); 857 858 for (i = 0; i < group.npins; i++) { 859 void __iomem *padcfg0; 860 u32 value; 861 862 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG); 863 if (!padcfg0) { 864 dev_warn(&vg->pdev->dev, 865 "Group %s, pin %i not muxed (no padcfg0)\n", 866 group.name, i); 867 continue; 868 } 869 870 value = readl(padcfg0); 871 value &= ~BYT_PIN_MUX; 872 value |= func; 873 writel(value, padcfg0); 874 } 875 876 raw_spin_unlock_irqrestore(&vg->lock, flags); 877 } 878 879 static void byt_set_group_mixed_mux(struct byt_gpio *vg, 880 const struct byt_pingroup group, 881 const unsigned short *func) 882 { 883 unsigned long flags; 884 int i; 885 886 raw_spin_lock_irqsave(&vg->lock, flags); 887 888 for (i = 0; i < group.npins; i++) { 889 void __iomem *padcfg0; 890 u32 value; 891 892 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG); 893 if (!padcfg0) { 894 dev_warn(&vg->pdev->dev, 895 "Group %s, pin %i not muxed (no padcfg0)\n", 896 group.name, i); 897 continue; 898 } 899 900 value = readl(padcfg0); 901 value &= ~BYT_PIN_MUX; 902 value |= func[i]; 903 writel(value, padcfg0); 904 } 905 906 raw_spin_unlock_irqrestore(&vg->lock, flags); 907 } 908 909 static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, 910 unsigned int group_selector) 911 { 912 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); 913 const struct byt_function func = vg->soc_data->functions[func_selector]; 914 const struct byt_pingroup group = vg->soc_data->groups[group_selector]; 915 const unsigned short *mixed_func; 916 unsigned short simple_func; 917 int ret = 1; 918 919 if (group.has_simple_funcs) 920 ret = byt_get_group_simple_mux(group, func.name, &simple_func); 921 else 922 ret = byt_get_group_mixed_mux(group, func.name, &mixed_func); 923 924 if (ret) 925 byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX); 926 else if (group.has_simple_funcs) 927 byt_set_group_simple_mux(vg, group, simple_func); 928 else 929 byt_set_group_mixed_mux(vg, group, mixed_func); 930 931 return 0; 932 } 933 934 static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned offset) 935 { 936 /* SCORE pin 92-93 */ 937 if (!strcmp(vg->soc_data->uid, BYT_SCORE_ACPI_UID) && 938 offset >= 92 && offset <= 93) 939 return 1; 940 941 /* SUS pin 11-21 */ 942 if (!strcmp(vg->soc_data->uid, BYT_SUS_ACPI_UID) && 943 offset >= 11 && offset <= 21) 944 return 1; 945 946 return 0; 947 } 948 949 static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned int offset) 950 { 951 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 952 unsigned long flags; 953 u32 value; 954 955 raw_spin_lock_irqsave(&vg->lock, flags); 956 value = readl(reg); 957 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL); 958 writel(value, reg); 959 raw_spin_unlock_irqrestore(&vg->lock, flags); 960 } 961 962 static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev, 963 struct pinctrl_gpio_range *range, 964 unsigned int offset) 965 { 966 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev); 967 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 968 u32 value, gpio_mux; 969 unsigned long flags; 970 971 raw_spin_lock_irqsave(&vg->lock, flags); 972 973 /* 974 * In most cases, func pin mux 000 means GPIO function. 975 * But, some pins may have func pin mux 001 represents 976 * GPIO function. 977 * 978 * Because there are devices out there where some pins were not 979 * configured correctly we allow changing the mux value from 980 * request (but print out warning about that). 981 */ 982 value = readl(reg) & BYT_PIN_MUX; 983 gpio_mux = byt_get_gpio_mux(vg, offset); 984 if (gpio_mux != value) { 985 value = readl(reg) & ~BYT_PIN_MUX; 986 value |= gpio_mux; 987 writel(value, reg); 988 989 dev_warn(&vg->pdev->dev, FW_BUG 990 "pin %u forcibly re-configured as GPIO\n", offset); 991 } 992 993 raw_spin_unlock_irqrestore(&vg->lock, flags); 994 995 pm_runtime_get(&vg->pdev->dev); 996 997 return 0; 998 } 999 1000 static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev, 1001 struct pinctrl_gpio_range *range, 1002 unsigned int offset) 1003 { 1004 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev); 1005 1006 byt_gpio_clear_triggering(vg, offset); 1007 pm_runtime_put(&vg->pdev->dev); 1008 } 1009 1010 static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev, 1011 struct pinctrl_gpio_range *range, 1012 unsigned int offset, 1013 bool input) 1014 { 1015 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev); 1016 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1017 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 1018 unsigned long flags; 1019 u32 value; 1020 1021 raw_spin_lock_irqsave(&vg->lock, flags); 1022 1023 value = readl(val_reg); 1024 value &= ~BYT_DIR_MASK; 1025 if (input) 1026 value |= BYT_OUTPUT_EN; 1027 else 1028 /* 1029 * Before making any direction modifications, do a check if gpio 1030 * is set for direct IRQ. On baytrail, setting GPIO to output 1031 * does not make sense, so let's at least warn the caller before 1032 * they shoot themselves in the foot. 1033 */ 1034 WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN, 1035 "Potential Error: Setting GPIO with direct_irq_en to output"); 1036 writel(value, val_reg); 1037 1038 raw_spin_unlock_irqrestore(&vg->lock, flags); 1039 1040 return 0; 1041 } 1042 1043 static const struct pinmux_ops byt_pinmux_ops = { 1044 .get_functions_count = byt_get_functions_count, 1045 .get_function_name = byt_get_function_name, 1046 .get_function_groups = byt_get_function_groups, 1047 .set_mux = byt_set_mux, 1048 .gpio_request_enable = byt_gpio_request_enable, 1049 .gpio_disable_free = byt_gpio_disable_free, 1050 .gpio_set_direction = byt_gpio_set_direction, 1051 }; 1052 1053 static void byt_get_pull_strength(u32 reg, u16 *strength) 1054 { 1055 switch (reg & BYT_PULL_STR_MASK) { 1056 case BYT_PULL_STR_2K: 1057 *strength = 2000; 1058 break; 1059 case BYT_PULL_STR_10K: 1060 *strength = 10000; 1061 break; 1062 case BYT_PULL_STR_20K: 1063 *strength = 20000; 1064 break; 1065 case BYT_PULL_STR_40K: 1066 *strength = 40000; 1067 break; 1068 } 1069 } 1070 1071 static int byt_set_pull_strength(u32 *reg, u16 strength) 1072 { 1073 *reg &= ~BYT_PULL_STR_MASK; 1074 1075 switch (strength) { 1076 case 2000: 1077 *reg |= BYT_PULL_STR_2K; 1078 break; 1079 case 10000: 1080 *reg |= BYT_PULL_STR_10K; 1081 break; 1082 case 20000: 1083 *reg |= BYT_PULL_STR_20K; 1084 break; 1085 case 40000: 1086 *reg |= BYT_PULL_STR_40K; 1087 break; 1088 default: 1089 return -EINVAL; 1090 } 1091 1092 return 0; 1093 } 1094 1095 static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset, 1096 unsigned long *config) 1097 { 1098 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev); 1099 enum pin_config_param param = pinconf_to_config_param(*config); 1100 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 1101 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1102 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG); 1103 unsigned long flags; 1104 u32 conf, pull, val, debounce; 1105 u16 arg = 0; 1106 1107 raw_spin_lock_irqsave(&vg->lock, flags); 1108 conf = readl(conf_reg); 1109 pull = conf & BYT_PULL_ASSIGN_MASK; 1110 val = readl(val_reg); 1111 raw_spin_unlock_irqrestore(&vg->lock, flags); 1112 1113 switch (param) { 1114 case PIN_CONFIG_BIAS_DISABLE: 1115 if (pull) 1116 return -EINVAL; 1117 break; 1118 case PIN_CONFIG_BIAS_PULL_DOWN: 1119 /* Pull assignment is only applicable in input mode */ 1120 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN) 1121 return -EINVAL; 1122 1123 byt_get_pull_strength(conf, &arg); 1124 1125 break; 1126 case PIN_CONFIG_BIAS_PULL_UP: 1127 /* Pull assignment is only applicable in input mode */ 1128 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP) 1129 return -EINVAL; 1130 1131 byt_get_pull_strength(conf, &arg); 1132 1133 break; 1134 case PIN_CONFIG_INPUT_DEBOUNCE: 1135 if (!(conf & BYT_DEBOUNCE_EN)) 1136 return -EINVAL; 1137 1138 raw_spin_lock_irqsave(&vg->lock, flags); 1139 debounce = readl(db_reg); 1140 raw_spin_unlock_irqrestore(&vg->lock, flags); 1141 1142 switch (debounce & BYT_DEBOUNCE_PULSE_MASK) { 1143 case BYT_DEBOUNCE_PULSE_375US: 1144 arg = 375; 1145 break; 1146 case BYT_DEBOUNCE_PULSE_750US: 1147 arg = 750; 1148 break; 1149 case BYT_DEBOUNCE_PULSE_1500US: 1150 arg = 1500; 1151 break; 1152 case BYT_DEBOUNCE_PULSE_3MS: 1153 arg = 3000; 1154 break; 1155 case BYT_DEBOUNCE_PULSE_6MS: 1156 arg = 6000; 1157 break; 1158 case BYT_DEBOUNCE_PULSE_12MS: 1159 arg = 12000; 1160 break; 1161 case BYT_DEBOUNCE_PULSE_24MS: 1162 arg = 24000; 1163 break; 1164 default: 1165 return -EINVAL; 1166 } 1167 1168 break; 1169 default: 1170 return -ENOTSUPP; 1171 } 1172 1173 *config = pinconf_to_config_packed(param, arg); 1174 1175 return 0; 1176 } 1177 1178 static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, 1179 unsigned int offset, 1180 unsigned long *configs, 1181 unsigned int num_configs) 1182 { 1183 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev); 1184 unsigned int param, arg; 1185 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 1186 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1187 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG); 1188 unsigned long flags; 1189 u32 conf, val, debounce; 1190 int i, ret = 0; 1191 1192 raw_spin_lock_irqsave(&vg->lock, flags); 1193 1194 conf = readl(conf_reg); 1195 val = readl(val_reg); 1196 1197 for (i = 0; i < num_configs; i++) { 1198 param = pinconf_to_config_param(configs[i]); 1199 arg = pinconf_to_config_argument(configs[i]); 1200 1201 switch (param) { 1202 case PIN_CONFIG_BIAS_DISABLE: 1203 conf &= ~BYT_PULL_ASSIGN_MASK; 1204 break; 1205 case PIN_CONFIG_BIAS_PULL_DOWN: 1206 /* Set default strength value in case none is given */ 1207 if (arg == 1) 1208 arg = 2000; 1209 1210 /* 1211 * Pull assignment is only applicable in input mode. If 1212 * chip is not in input mode, set it and warn about it. 1213 */ 1214 if (val & BYT_INPUT_EN) { 1215 val &= ~BYT_INPUT_EN; 1216 writel(val, val_reg); 1217 dev_warn(&vg->pdev->dev, 1218 "pin %u forcibly set to input mode\n", 1219 offset); 1220 } 1221 1222 conf &= ~BYT_PULL_ASSIGN_MASK; 1223 conf |= BYT_PULL_ASSIGN_DOWN; 1224 ret = byt_set_pull_strength(&conf, arg); 1225 1226 break; 1227 case PIN_CONFIG_BIAS_PULL_UP: 1228 /* Set default strength value in case none is given */ 1229 if (arg == 1) 1230 arg = 2000; 1231 1232 /* 1233 * Pull assignment is only applicable in input mode. If 1234 * chip is not in input mode, set it and warn about it. 1235 */ 1236 if (val & BYT_INPUT_EN) { 1237 val &= ~BYT_INPUT_EN; 1238 writel(val, val_reg); 1239 dev_warn(&vg->pdev->dev, 1240 "pin %u forcibly set to input mode\n", 1241 offset); 1242 } 1243 1244 conf &= ~BYT_PULL_ASSIGN_MASK; 1245 conf |= BYT_PULL_ASSIGN_UP; 1246 ret = byt_set_pull_strength(&conf, arg); 1247 1248 break; 1249 case PIN_CONFIG_INPUT_DEBOUNCE: 1250 debounce = readl(db_reg); 1251 debounce &= ~BYT_DEBOUNCE_PULSE_MASK; 1252 1253 if (arg) 1254 conf |= BYT_DEBOUNCE_EN; 1255 else 1256 conf &= ~BYT_DEBOUNCE_EN; 1257 1258 switch (arg) { 1259 case 375: 1260 debounce |= BYT_DEBOUNCE_PULSE_375US; 1261 break; 1262 case 750: 1263 debounce |= BYT_DEBOUNCE_PULSE_750US; 1264 break; 1265 case 1500: 1266 debounce |= BYT_DEBOUNCE_PULSE_1500US; 1267 break; 1268 case 3000: 1269 debounce |= BYT_DEBOUNCE_PULSE_3MS; 1270 break; 1271 case 6000: 1272 debounce |= BYT_DEBOUNCE_PULSE_6MS; 1273 break; 1274 case 12000: 1275 debounce |= BYT_DEBOUNCE_PULSE_12MS; 1276 break; 1277 case 24000: 1278 debounce |= BYT_DEBOUNCE_PULSE_24MS; 1279 break; 1280 default: 1281 if (arg) 1282 ret = -EINVAL; 1283 break; 1284 } 1285 1286 if (!ret) 1287 writel(debounce, db_reg); 1288 break; 1289 default: 1290 ret = -ENOTSUPP; 1291 } 1292 1293 if (ret) 1294 break; 1295 } 1296 1297 if (!ret) 1298 writel(conf, conf_reg); 1299 1300 raw_spin_unlock_irqrestore(&vg->lock, flags); 1301 1302 return ret; 1303 } 1304 1305 static const struct pinconf_ops byt_pinconf_ops = { 1306 .is_generic = true, 1307 .pin_config_get = byt_pin_config_get, 1308 .pin_config_set = byt_pin_config_set, 1309 }; 1310 1311 static const struct pinctrl_desc byt_pinctrl_desc = { 1312 .pctlops = &byt_pinctrl_ops, 1313 .pmxops = &byt_pinmux_ops, 1314 .confops = &byt_pinconf_ops, 1315 .owner = THIS_MODULE, 1316 }; 1317 1318 static int byt_gpio_get(struct gpio_chip *chip, unsigned offset) 1319 { 1320 struct byt_gpio *vg = gpiochip_get_data(chip); 1321 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1322 unsigned long flags; 1323 u32 val; 1324 1325 raw_spin_lock_irqsave(&vg->lock, flags); 1326 val = readl(reg); 1327 raw_spin_unlock_irqrestore(&vg->lock, flags); 1328 1329 return !!(val & BYT_LEVEL); 1330 } 1331 1332 static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 1333 { 1334 struct byt_gpio *vg = gpiochip_get_data(chip); 1335 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1336 unsigned long flags; 1337 u32 old_val; 1338 1339 if (!reg) 1340 return; 1341 1342 raw_spin_lock_irqsave(&vg->lock, flags); 1343 old_val = readl(reg); 1344 if (value) 1345 writel(old_val | BYT_LEVEL, reg); 1346 else 1347 writel(old_val & ~BYT_LEVEL, reg); 1348 raw_spin_unlock_irqrestore(&vg->lock, flags); 1349 } 1350 1351 static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 1352 { 1353 struct byt_gpio *vg = gpiochip_get_data(chip); 1354 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1355 unsigned long flags; 1356 u32 value; 1357 1358 if (!reg) 1359 return -EINVAL; 1360 1361 raw_spin_lock_irqsave(&vg->lock, flags); 1362 value = readl(reg); 1363 raw_spin_unlock_irqrestore(&vg->lock, flags); 1364 1365 if (!(value & BYT_OUTPUT_EN)) 1366 return GPIOF_DIR_OUT; 1367 if (!(value & BYT_INPUT_EN)) 1368 return GPIOF_DIR_IN; 1369 1370 return -EINVAL; 1371 } 1372 1373 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 1374 { 1375 return pinctrl_gpio_direction_input(chip->base + offset); 1376 } 1377 1378 static int byt_gpio_direction_output(struct gpio_chip *chip, 1379 unsigned int offset, int value) 1380 { 1381 int ret = pinctrl_gpio_direction_output(chip->base + offset); 1382 1383 if (ret) 1384 return ret; 1385 1386 byt_gpio_set(chip, offset, value); 1387 1388 return 0; 1389 } 1390 1391 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 1392 { 1393 struct byt_gpio *vg = gpiochip_get_data(chip); 1394 int i; 1395 u32 conf0, val; 1396 1397 for (i = 0; i < vg->soc_data->npins; i++) { 1398 const struct byt_community *comm; 1399 const char *pull_str = NULL; 1400 const char *pull = NULL; 1401 void __iomem *reg; 1402 unsigned long flags; 1403 const char *label; 1404 unsigned int pin; 1405 1406 raw_spin_lock_irqsave(&vg->lock, flags); 1407 pin = vg->soc_data->pins[i].number; 1408 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1409 if (!reg) { 1410 seq_printf(s, 1411 "Could not retrieve pin %i conf0 reg\n", 1412 pin); 1413 raw_spin_unlock_irqrestore(&vg->lock, flags); 1414 continue; 1415 } 1416 conf0 = readl(reg); 1417 1418 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); 1419 if (!reg) { 1420 seq_printf(s, 1421 "Could not retrieve pin %i val reg\n", pin); 1422 raw_spin_unlock_irqrestore(&vg->lock, flags); 1423 continue; 1424 } 1425 val = readl(reg); 1426 raw_spin_unlock_irqrestore(&vg->lock, flags); 1427 1428 comm = byt_get_community(vg, pin); 1429 if (!comm) { 1430 seq_printf(s, 1431 "Could not get community for pin %i\n", pin); 1432 continue; 1433 } 1434 label = gpiochip_is_requested(chip, i); 1435 if (!label) 1436 label = "Unrequested"; 1437 1438 switch (conf0 & BYT_PULL_ASSIGN_MASK) { 1439 case BYT_PULL_ASSIGN_UP: 1440 pull = "up"; 1441 break; 1442 case BYT_PULL_ASSIGN_DOWN: 1443 pull = "down"; 1444 break; 1445 } 1446 1447 switch (conf0 & BYT_PULL_STR_MASK) { 1448 case BYT_PULL_STR_2K: 1449 pull_str = "2k"; 1450 break; 1451 case BYT_PULL_STR_10K: 1452 pull_str = "10k"; 1453 break; 1454 case BYT_PULL_STR_20K: 1455 pull_str = "20k"; 1456 break; 1457 case BYT_PULL_STR_40K: 1458 pull_str = "40k"; 1459 break; 1460 } 1461 1462 seq_printf(s, 1463 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s", 1464 pin, 1465 label, 1466 val & BYT_INPUT_EN ? " " : "in", 1467 val & BYT_OUTPUT_EN ? " " : "out", 1468 val & BYT_LEVEL ? "hi" : "lo", 1469 comm->pad_map[i], comm->pad_map[i] * 16, 1470 conf0 & 0x7, 1471 conf0 & BYT_TRIG_NEG ? " fall" : " ", 1472 conf0 & BYT_TRIG_POS ? " rise" : " ", 1473 conf0 & BYT_TRIG_LVL ? " level" : " "); 1474 1475 if (pull && pull_str) 1476 seq_printf(s, " %-4s %-3s", pull, pull_str); 1477 else 1478 seq_puts(s, " "); 1479 1480 if (conf0 & BYT_IODEN) 1481 seq_puts(s, " open-drain"); 1482 1483 seq_puts(s, "\n"); 1484 } 1485 } 1486 1487 static const struct gpio_chip byt_gpio_chip = { 1488 .owner = THIS_MODULE, 1489 .request = gpiochip_generic_request, 1490 .free = gpiochip_generic_free, 1491 .get_direction = byt_gpio_get_direction, 1492 .direction_input = byt_gpio_direction_input, 1493 .direction_output = byt_gpio_direction_output, 1494 .get = byt_gpio_get, 1495 .set = byt_gpio_set, 1496 .dbg_show = byt_gpio_dbg_show, 1497 }; 1498 1499 static void byt_irq_ack(struct irq_data *d) 1500 { 1501 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1502 struct byt_gpio *vg = gpiochip_get_data(gc); 1503 unsigned offset = irqd_to_hwirq(d); 1504 void __iomem *reg; 1505 1506 reg = byt_gpio_reg(vg, offset, BYT_INT_STAT_REG); 1507 if (!reg) 1508 return; 1509 1510 raw_spin_lock(&vg->lock); 1511 writel(BIT(offset % 32), reg); 1512 raw_spin_unlock(&vg->lock); 1513 } 1514 1515 static void byt_irq_mask(struct irq_data *d) 1516 { 1517 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1518 struct byt_gpio *vg = gpiochip_get_data(gc); 1519 1520 byt_gpio_clear_triggering(vg, irqd_to_hwirq(d)); 1521 } 1522 1523 static void byt_irq_unmask(struct irq_data *d) 1524 { 1525 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1526 struct byt_gpio *vg = gpiochip_get_data(gc); 1527 unsigned offset = irqd_to_hwirq(d); 1528 unsigned long flags; 1529 void __iomem *reg; 1530 u32 value; 1531 1532 reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 1533 if (!reg) 1534 return; 1535 1536 raw_spin_lock_irqsave(&vg->lock, flags); 1537 value = readl(reg); 1538 1539 switch (irqd_get_trigger_type(d)) { 1540 case IRQ_TYPE_LEVEL_HIGH: 1541 value |= BYT_TRIG_LVL; 1542 case IRQ_TYPE_EDGE_RISING: 1543 value |= BYT_TRIG_POS; 1544 break; 1545 case IRQ_TYPE_LEVEL_LOW: 1546 value |= BYT_TRIG_LVL; 1547 case IRQ_TYPE_EDGE_FALLING: 1548 value |= BYT_TRIG_NEG; 1549 break; 1550 case IRQ_TYPE_EDGE_BOTH: 1551 value |= (BYT_TRIG_NEG | BYT_TRIG_POS); 1552 break; 1553 } 1554 1555 writel(value, reg); 1556 1557 raw_spin_unlock_irqrestore(&vg->lock, flags); 1558 } 1559 1560 static int byt_irq_type(struct irq_data *d, unsigned int type) 1561 { 1562 struct byt_gpio *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d)); 1563 u32 offset = irqd_to_hwirq(d); 1564 u32 value; 1565 unsigned long flags; 1566 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 1567 1568 if (!reg || offset >= vg->chip.ngpio) 1569 return -EINVAL; 1570 1571 raw_spin_lock_irqsave(&vg->lock, flags); 1572 value = readl(reg); 1573 1574 WARN(value & BYT_DIRECT_IRQ_EN, 1575 "Bad pad config for io mode, force direct_irq_en bit clearing"); 1576 1577 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits 1578 * are used to indicate high and low level triggering 1579 */ 1580 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG | 1581 BYT_TRIG_LVL); 1582 1583 writel(value, reg); 1584 1585 if (type & IRQ_TYPE_EDGE_BOTH) 1586 irq_set_handler_locked(d, handle_edge_irq); 1587 else if (type & IRQ_TYPE_LEVEL_MASK) 1588 irq_set_handler_locked(d, handle_level_irq); 1589 1590 raw_spin_unlock_irqrestore(&vg->lock, flags); 1591 1592 return 0; 1593 } 1594 1595 static struct irq_chip byt_irqchip = { 1596 .name = "BYT-GPIO", 1597 .irq_ack = byt_irq_ack, 1598 .irq_mask = byt_irq_mask, 1599 .irq_unmask = byt_irq_unmask, 1600 .irq_set_type = byt_irq_type, 1601 .flags = IRQCHIP_SKIP_SET_WAKE, 1602 }; 1603 1604 static void byt_gpio_irq_handler(struct irq_desc *desc) 1605 { 1606 struct irq_data *data = irq_desc_get_irq_data(desc); 1607 struct byt_gpio *vg = gpiochip_get_data( 1608 irq_desc_get_handler_data(desc)); 1609 struct irq_chip *chip = irq_data_get_irq_chip(data); 1610 u32 base, pin; 1611 void __iomem *reg; 1612 unsigned long pending; 1613 unsigned int virq; 1614 1615 /* check from GPIO controller which pin triggered the interrupt */ 1616 for (base = 0; base < vg->chip.ngpio; base += 32) { 1617 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG); 1618 1619 if (!reg) { 1620 dev_warn(&vg->pdev->dev, 1621 "Pin %i: could not retrieve interrupt status register\n", 1622 base); 1623 continue; 1624 } 1625 1626 raw_spin_lock(&vg->lock); 1627 pending = readl(reg); 1628 raw_spin_unlock(&vg->lock); 1629 for_each_set_bit(pin, &pending, 32) { 1630 virq = irq_find_mapping(vg->chip.irq.domain, base + pin); 1631 generic_handle_irq(virq); 1632 } 1633 } 1634 chip->irq_eoi(data); 1635 } 1636 1637 static void byt_gpio_irq_init_hw(struct byt_gpio *vg) 1638 { 1639 struct gpio_chip *gc = &vg->chip; 1640 struct device *dev = &vg->pdev->dev; 1641 void __iomem *reg; 1642 u32 base, value; 1643 int i; 1644 1645 /* 1646 * Clear interrupt triggers for all pins that are GPIOs and 1647 * do not use direct IRQ mode. This will prevent spurious 1648 * interrupts from misconfigured pins. 1649 */ 1650 for (i = 0; i < vg->soc_data->npins; i++) { 1651 unsigned int pin = vg->soc_data->pins[i].number; 1652 1653 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1654 if (!reg) { 1655 dev_warn(&vg->pdev->dev, 1656 "Pin %i: could not retrieve conf0 register\n", 1657 i); 1658 continue; 1659 } 1660 1661 value = readl(reg); 1662 if (value & BYT_DIRECT_IRQ_EN) { 1663 clear_bit(i, gc->irq.valid_mask); 1664 dev_dbg(dev, "excluding GPIO %d from IRQ domain\n", i); 1665 } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) { 1666 byt_gpio_clear_triggering(vg, i); 1667 dev_dbg(dev, "disabling GPIO %d\n", i); 1668 } 1669 } 1670 1671 /* clear interrupt status trigger registers */ 1672 for (base = 0; base < vg->soc_data->npins; base += 32) { 1673 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG); 1674 1675 if (!reg) { 1676 dev_warn(&vg->pdev->dev, 1677 "Pin %i: could not retrieve irq status reg\n", 1678 base); 1679 continue; 1680 } 1681 1682 writel(0xffffffff, reg); 1683 /* make sure trigger bits are cleared, if not then a pin 1684 might be misconfigured in bios */ 1685 value = readl(reg); 1686 if (value) 1687 dev_err(&vg->pdev->dev, 1688 "GPIO interrupt error, pins misconfigured\n"); 1689 } 1690 } 1691 1692 static int byt_gpio_probe(struct byt_gpio *vg) 1693 { 1694 struct gpio_chip *gc; 1695 struct resource *irq_rc; 1696 int ret; 1697 1698 /* Set up gpio chip */ 1699 vg->chip = byt_gpio_chip; 1700 gc = &vg->chip; 1701 gc->label = dev_name(&vg->pdev->dev); 1702 gc->base = -1; 1703 gc->can_sleep = false; 1704 gc->parent = &vg->pdev->dev; 1705 gc->ngpio = vg->soc_data->npins; 1706 gc->irq.need_valid_mask = true; 1707 1708 #ifdef CONFIG_PM_SLEEP 1709 vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio, 1710 sizeof(*vg->saved_context), GFP_KERNEL); 1711 #endif 1712 ret = devm_gpiochip_add_data(&vg->pdev->dev, gc, vg); 1713 if (ret) { 1714 dev_err(&vg->pdev->dev, "failed adding byt-gpio chip\n"); 1715 return ret; 1716 } 1717 1718 ret = gpiochip_add_pin_range(&vg->chip, dev_name(&vg->pdev->dev), 1719 0, 0, vg->soc_data->npins); 1720 if (ret) { 1721 dev_err(&vg->pdev->dev, "failed to add GPIO pin range\n"); 1722 return ret; 1723 } 1724 1725 /* set up interrupts */ 1726 irq_rc = platform_get_resource(vg->pdev, IORESOURCE_IRQ, 0); 1727 if (irq_rc && irq_rc->start) { 1728 byt_gpio_irq_init_hw(vg); 1729 ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0, 1730 handle_bad_irq, IRQ_TYPE_NONE); 1731 if (ret) { 1732 dev_err(&vg->pdev->dev, "failed to add irqchip\n"); 1733 return ret; 1734 } 1735 1736 gpiochip_set_chained_irqchip(gc, &byt_irqchip, 1737 (unsigned)irq_rc->start, 1738 byt_gpio_irq_handler); 1739 } 1740 1741 return ret; 1742 } 1743 1744 static int byt_set_soc_data(struct byt_gpio *vg, 1745 const struct byt_pinctrl_soc_data *soc_data) 1746 { 1747 int i; 1748 1749 vg->soc_data = soc_data; 1750 vg->communities_copy = devm_kcalloc(&vg->pdev->dev, 1751 soc_data->ncommunities, 1752 sizeof(*vg->communities_copy), 1753 GFP_KERNEL); 1754 if (!vg->communities_copy) 1755 return -ENOMEM; 1756 1757 for (i = 0; i < soc_data->ncommunities; i++) { 1758 struct byt_community *comm = vg->communities_copy + i; 1759 struct resource *mem_rc; 1760 1761 *comm = vg->soc_data->communities[i]; 1762 1763 mem_rc = platform_get_resource(vg->pdev, IORESOURCE_MEM, 0); 1764 comm->reg_base = devm_ioremap_resource(&vg->pdev->dev, mem_rc); 1765 if (IS_ERR(comm->reg_base)) 1766 return PTR_ERR(comm->reg_base); 1767 } 1768 1769 return 0; 1770 } 1771 1772 static const struct acpi_device_id byt_gpio_acpi_match[] = { 1773 { "INT33B2", (kernel_ulong_t)byt_soc_data }, 1774 { "INT33FC", (kernel_ulong_t)byt_soc_data }, 1775 { } 1776 }; 1777 MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match); 1778 1779 static int byt_pinctrl_probe(struct platform_device *pdev) 1780 { 1781 const struct byt_pinctrl_soc_data *soc_data = NULL; 1782 const struct byt_pinctrl_soc_data **soc_table; 1783 const struct acpi_device_id *acpi_id; 1784 struct acpi_device *acpi_dev; 1785 struct byt_gpio *vg; 1786 int i, ret; 1787 1788 acpi_dev = ACPI_COMPANION(&pdev->dev); 1789 if (!acpi_dev) 1790 return -ENODEV; 1791 1792 acpi_id = acpi_match_device(byt_gpio_acpi_match, &pdev->dev); 1793 if (!acpi_id) 1794 return -ENODEV; 1795 1796 soc_table = (const struct byt_pinctrl_soc_data **)acpi_id->driver_data; 1797 1798 for (i = 0; soc_table[i]; i++) { 1799 if (!strcmp(acpi_dev->pnp.unique_id, soc_table[i]->uid)) { 1800 soc_data = soc_table[i]; 1801 break; 1802 } 1803 } 1804 1805 if (!soc_data) 1806 return -ENODEV; 1807 1808 vg = devm_kzalloc(&pdev->dev, sizeof(*vg), GFP_KERNEL); 1809 if (!vg) 1810 return -ENOMEM; 1811 1812 vg->pdev = pdev; 1813 ret = byt_set_soc_data(vg, soc_data); 1814 if (ret) { 1815 dev_err(&pdev->dev, "failed to set soc data\n"); 1816 return ret; 1817 } 1818 1819 vg->pctl_desc = byt_pinctrl_desc; 1820 vg->pctl_desc.name = dev_name(&pdev->dev); 1821 vg->pctl_desc.pins = vg->soc_data->pins; 1822 vg->pctl_desc.npins = vg->soc_data->npins; 1823 1824 vg->pctl_dev = devm_pinctrl_register(&pdev->dev, &vg->pctl_desc, vg); 1825 if (IS_ERR(vg->pctl_dev)) { 1826 dev_err(&pdev->dev, "failed to register pinctrl driver\n"); 1827 return PTR_ERR(vg->pctl_dev); 1828 } 1829 1830 raw_spin_lock_init(&vg->lock); 1831 1832 ret = byt_gpio_probe(vg); 1833 if (ret) 1834 return ret; 1835 1836 platform_set_drvdata(pdev, vg); 1837 pm_runtime_enable(&pdev->dev); 1838 1839 return 0; 1840 } 1841 1842 #ifdef CONFIG_PM_SLEEP 1843 static int byt_gpio_suspend(struct device *dev) 1844 { 1845 struct platform_device *pdev = to_platform_device(dev); 1846 struct byt_gpio *vg = platform_get_drvdata(pdev); 1847 int i; 1848 1849 for (i = 0; i < vg->soc_data->npins; i++) { 1850 void __iomem *reg; 1851 u32 value; 1852 unsigned int pin = vg->soc_data->pins[i].number; 1853 1854 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1855 if (!reg) { 1856 dev_warn(&vg->pdev->dev, 1857 "Pin %i: could not retrieve conf0 register\n", 1858 i); 1859 continue; 1860 } 1861 value = readl(reg) & BYT_CONF0_RESTORE_MASK; 1862 vg->saved_context[i].conf0 = value; 1863 1864 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); 1865 value = readl(reg) & BYT_VAL_RESTORE_MASK; 1866 vg->saved_context[i].val = value; 1867 } 1868 1869 return 0; 1870 } 1871 1872 static int byt_gpio_resume(struct device *dev) 1873 { 1874 struct platform_device *pdev = to_platform_device(dev); 1875 struct byt_gpio *vg = platform_get_drvdata(pdev); 1876 int i; 1877 1878 for (i = 0; i < vg->soc_data->npins; i++) { 1879 void __iomem *reg; 1880 u32 value; 1881 unsigned int pin = vg->soc_data->pins[i].number; 1882 1883 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1884 if (!reg) { 1885 dev_warn(&vg->pdev->dev, 1886 "Pin %i: could not retrieve conf0 register\n", 1887 i); 1888 continue; 1889 } 1890 value = readl(reg); 1891 if ((value & BYT_CONF0_RESTORE_MASK) != 1892 vg->saved_context[i].conf0) { 1893 value &= ~BYT_CONF0_RESTORE_MASK; 1894 value |= vg->saved_context[i].conf0; 1895 writel(value, reg); 1896 dev_info(dev, "restored pin %d conf0 %#08x", i, value); 1897 } 1898 1899 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); 1900 value = readl(reg); 1901 if ((value & BYT_VAL_RESTORE_MASK) != 1902 vg->saved_context[i].val) { 1903 u32 v; 1904 1905 v = value & ~BYT_VAL_RESTORE_MASK; 1906 v |= vg->saved_context[i].val; 1907 if (v != value) { 1908 writel(v, reg); 1909 dev_dbg(dev, "restored pin %d val %#08x\n", 1910 i, v); 1911 } 1912 } 1913 } 1914 1915 return 0; 1916 } 1917 #endif 1918 1919 #ifdef CONFIG_PM 1920 static int byt_gpio_runtime_suspend(struct device *dev) 1921 { 1922 return 0; 1923 } 1924 1925 static int byt_gpio_runtime_resume(struct device *dev) 1926 { 1927 return 0; 1928 } 1929 #endif 1930 1931 static const struct dev_pm_ops byt_gpio_pm_ops = { 1932 SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume) 1933 SET_RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume, 1934 NULL) 1935 }; 1936 1937 static struct platform_driver byt_gpio_driver = { 1938 .probe = byt_pinctrl_probe, 1939 .driver = { 1940 .name = "byt_gpio", 1941 .pm = &byt_gpio_pm_ops, 1942 .suppress_bind_attrs = true, 1943 1944 .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match), 1945 }, 1946 }; 1947 1948 static int __init byt_gpio_init(void) 1949 { 1950 return platform_driver_register(&byt_gpio_driver); 1951 } 1952 subsys_initcall(byt_gpio_init); 1953