1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Pinctrl GPIO driver for Intel Baytrail 4 * 5 * Copyright (c) 2012-2013, Intel Corporation 6 * Author: Mathias Nyman <mathias.nyman@linux.intel.com> 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/bitops.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/types.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/property.h> 21 #include <linux/seq_file.h> 22 #include <linux/string_helpers.h> 23 24 #include <linux/pinctrl/pinctrl.h> 25 #include <linux/pinctrl/pinmux.h> 26 #include <linux/pinctrl/pinconf.h> 27 #include <linux/pinctrl/pinconf-generic.h> 28 29 #include "pinctrl-intel.h" 30 31 /* memory mapped register offsets */ 32 #define BYT_CONF0_REG 0x000 33 #define BYT_CONF1_REG 0x004 34 #define BYT_VAL_REG 0x008 35 #define BYT_DFT_REG 0x00c 36 #define BYT_INT_STAT_REG 0x800 37 #define BYT_DIRECT_IRQ_REG 0x980 38 #define BYT_DEBOUNCE_REG 0x9d0 39 40 /* BYT_CONF0_REG register bits */ 41 #define BYT_IODEN BIT(31) 42 #define BYT_DIRECT_IRQ_EN BIT(27) 43 #define BYT_TRIG_MASK GENMASK(26, 24) 44 #define BYT_TRIG_NEG BIT(26) 45 #define BYT_TRIG_POS BIT(25) 46 #define BYT_TRIG_LVL BIT(24) 47 #define BYT_DEBOUNCE_EN BIT(20) 48 #define BYT_GLITCH_FILTER_EN BIT(19) 49 #define BYT_GLITCH_F_SLOW_CLK BIT(17) 50 #define BYT_GLITCH_F_FAST_CLK BIT(16) 51 #define BYT_PULL_STR_SHIFT 9 52 #define BYT_PULL_STR_MASK GENMASK(10, 9) 53 #define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT) 54 #define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT) 55 #define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT) 56 #define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT) 57 #define BYT_PULL_ASSIGN_MASK GENMASK(8, 7) 58 #define BYT_PULL_ASSIGN_DOWN BIT(8) 59 #define BYT_PULL_ASSIGN_UP BIT(7) 60 #define BYT_PIN_MUX GENMASK(2, 0) 61 62 /* BYT_VAL_REG register bits */ 63 #define BYT_DIR_MASK GENMASK(2, 1) 64 #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/ 65 #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/ 66 #define BYT_LEVEL BIT(0) 67 68 #define BYT_CONF0_RESTORE_MASK (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | BYT_PIN_MUX) 69 #define BYT_VAL_RESTORE_MASK (BYT_DIR_MASK | BYT_LEVEL) 70 71 /* BYT_DEBOUNCE_REG bits */ 72 #define BYT_DEBOUNCE_PULSE_MASK GENMASK(2, 0) 73 #define BYT_DEBOUNCE_PULSE_375US 1 74 #define BYT_DEBOUNCE_PULSE_750US 2 75 #define BYT_DEBOUNCE_PULSE_1500US 3 76 #define BYT_DEBOUNCE_PULSE_3MS 4 77 #define BYT_DEBOUNCE_PULSE_6MS 5 78 #define BYT_DEBOUNCE_PULSE_12MS 6 79 #define BYT_DEBOUNCE_PULSE_24MS 7 80 81 #define BYT_NGPIO_SCORE 102 82 #define BYT_NGPIO_NCORE 28 83 #define BYT_NGPIO_SUS 44 84 85 #define BYT_SCORE_ACPI_UID "1" 86 #define BYT_NCORE_ACPI_UID "2" 87 #define BYT_SUS_ACPI_UID "3" 88 89 /* 90 * This is the function value most pins have for GPIO muxing. If the value 91 * differs from the default one, it must be explicitly mentioned. Otherwise, the 92 * pin control implementation will set the muxing value to default GPIO if it 93 * does not find a match for the requested function. 94 */ 95 #define BYT_DEFAULT_GPIO_MUX 0 96 #define BYT_ALTER_GPIO_MUX 1 97 98 struct intel_pad_context { 99 u32 conf0; 100 u32 val; 101 }; 102 103 #define COMMUNITY(p, n, map) \ 104 { \ 105 .pin_base = (p), \ 106 .npins = (n), \ 107 .pad_map = (map),\ 108 } 109 110 /* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */ 111 static const struct pinctrl_pin_desc byt_score_pins[] = { 112 PINCTRL_PIN(0, "SATA_GP0"), 113 PINCTRL_PIN(1, "SATA_GP1"), 114 PINCTRL_PIN(2, "SATA_LED#"), 115 PINCTRL_PIN(3, "PCIE_CLKREQ0"), 116 PINCTRL_PIN(4, "PCIE_CLKREQ1"), 117 PINCTRL_PIN(5, "PCIE_CLKREQ2"), 118 PINCTRL_PIN(6, "PCIE_CLKREQ3"), 119 PINCTRL_PIN(7, "SD3_WP"), 120 PINCTRL_PIN(8, "HDA_RST"), 121 PINCTRL_PIN(9, "HDA_SYNC"), 122 PINCTRL_PIN(10, "HDA_CLK"), 123 PINCTRL_PIN(11, "HDA_SDO"), 124 PINCTRL_PIN(12, "HDA_SDI0"), 125 PINCTRL_PIN(13, "HDA_SDI1"), 126 PINCTRL_PIN(14, "GPIO_S0_SC14"), 127 PINCTRL_PIN(15, "GPIO_S0_SC15"), 128 PINCTRL_PIN(16, "MMC1_CLK"), 129 PINCTRL_PIN(17, "MMC1_D0"), 130 PINCTRL_PIN(18, "MMC1_D1"), 131 PINCTRL_PIN(19, "MMC1_D2"), 132 PINCTRL_PIN(20, "MMC1_D3"), 133 PINCTRL_PIN(21, "MMC1_D4"), 134 PINCTRL_PIN(22, "MMC1_D5"), 135 PINCTRL_PIN(23, "MMC1_D6"), 136 PINCTRL_PIN(24, "MMC1_D7"), 137 PINCTRL_PIN(25, "MMC1_CMD"), 138 PINCTRL_PIN(26, "MMC1_RST"), 139 PINCTRL_PIN(27, "SD2_CLK"), 140 PINCTRL_PIN(28, "SD2_D0"), 141 PINCTRL_PIN(29, "SD2_D1"), 142 PINCTRL_PIN(30, "SD2_D2"), 143 PINCTRL_PIN(31, "SD2_D3_CD"), 144 PINCTRL_PIN(32, "SD2_CMD"), 145 PINCTRL_PIN(33, "SD3_CLK"), 146 PINCTRL_PIN(34, "SD3_D0"), 147 PINCTRL_PIN(35, "SD3_D1"), 148 PINCTRL_PIN(36, "SD3_D2"), 149 PINCTRL_PIN(37, "SD3_D3"), 150 PINCTRL_PIN(38, "SD3_CD"), 151 PINCTRL_PIN(39, "SD3_CMD"), 152 PINCTRL_PIN(40, "SD3_1P8EN"), 153 PINCTRL_PIN(41, "SD3_PWREN#"), 154 PINCTRL_PIN(42, "ILB_LPC_AD0"), 155 PINCTRL_PIN(43, "ILB_LPC_AD1"), 156 PINCTRL_PIN(44, "ILB_LPC_AD2"), 157 PINCTRL_PIN(45, "ILB_LPC_AD3"), 158 PINCTRL_PIN(46, "ILB_LPC_FRAME"), 159 PINCTRL_PIN(47, "ILB_LPC_CLK0"), 160 PINCTRL_PIN(48, "ILB_LPC_CLK1"), 161 PINCTRL_PIN(49, "ILB_LPC_CLKRUN"), 162 PINCTRL_PIN(50, "ILB_LPC_SERIRQ"), 163 PINCTRL_PIN(51, "PCU_SMB_DATA"), 164 PINCTRL_PIN(52, "PCU_SMB_CLK"), 165 PINCTRL_PIN(53, "PCU_SMB_ALERT"), 166 PINCTRL_PIN(54, "ILB_8254_SPKR"), 167 PINCTRL_PIN(55, "GPIO_S0_SC55"), 168 PINCTRL_PIN(56, "GPIO_S0_SC56"), 169 PINCTRL_PIN(57, "GPIO_S0_SC57"), 170 PINCTRL_PIN(58, "GPIO_S0_SC58"), 171 PINCTRL_PIN(59, "GPIO_S0_SC59"), 172 PINCTRL_PIN(60, "GPIO_S0_SC60"), 173 PINCTRL_PIN(61, "GPIO_S0_SC61"), 174 PINCTRL_PIN(62, "LPE_I2S2_CLK"), 175 PINCTRL_PIN(63, "LPE_I2S2_FRM"), 176 PINCTRL_PIN(64, "LPE_I2S2_DATAIN"), 177 PINCTRL_PIN(65, "LPE_I2S2_DATAOUT"), 178 PINCTRL_PIN(66, "SIO_SPI_CS"), 179 PINCTRL_PIN(67, "SIO_SPI_MISO"), 180 PINCTRL_PIN(68, "SIO_SPI_MOSI"), 181 PINCTRL_PIN(69, "SIO_SPI_CLK"), 182 PINCTRL_PIN(70, "SIO_UART1_RXD"), 183 PINCTRL_PIN(71, "SIO_UART1_TXD"), 184 PINCTRL_PIN(72, "SIO_UART1_RTS"), 185 PINCTRL_PIN(73, "SIO_UART1_CTS"), 186 PINCTRL_PIN(74, "SIO_UART2_RXD"), 187 PINCTRL_PIN(75, "SIO_UART2_TXD"), 188 PINCTRL_PIN(76, "SIO_UART2_RTS"), 189 PINCTRL_PIN(77, "SIO_UART2_CTS"), 190 PINCTRL_PIN(78, "SIO_I2C0_DATA"), 191 PINCTRL_PIN(79, "SIO_I2C0_CLK"), 192 PINCTRL_PIN(80, "SIO_I2C1_DATA"), 193 PINCTRL_PIN(81, "SIO_I2C1_CLK"), 194 PINCTRL_PIN(82, "SIO_I2C2_DATA"), 195 PINCTRL_PIN(83, "SIO_I2C2_CLK"), 196 PINCTRL_PIN(84, "SIO_I2C3_DATA"), 197 PINCTRL_PIN(85, "SIO_I2C3_CLK"), 198 PINCTRL_PIN(86, "SIO_I2C4_DATA"), 199 PINCTRL_PIN(87, "SIO_I2C4_CLK"), 200 PINCTRL_PIN(88, "SIO_I2C5_DATA"), 201 PINCTRL_PIN(89, "SIO_I2C5_CLK"), 202 PINCTRL_PIN(90, "SIO_I2C6_DATA"), 203 PINCTRL_PIN(91, "SIO_I2C6_CLK"), 204 PINCTRL_PIN(92, "GPIO_S0_SC92"), 205 PINCTRL_PIN(93, "GPIO_S0_SC93"), 206 PINCTRL_PIN(94, "SIO_PWM0"), 207 PINCTRL_PIN(95, "SIO_PWM1"), 208 PINCTRL_PIN(96, "PMC_PLT_CLK0"), 209 PINCTRL_PIN(97, "PMC_PLT_CLK1"), 210 PINCTRL_PIN(98, "PMC_PLT_CLK2"), 211 PINCTRL_PIN(99, "PMC_PLT_CLK3"), 212 PINCTRL_PIN(100, "PMC_PLT_CLK4"), 213 PINCTRL_PIN(101, "PMC_PLT_CLK5"), 214 }; 215 216 static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = { 217 85, 89, 93, 96, 99, 102, 98, 101, 34, 37, 218 36, 38, 39, 35, 40, 84, 62, 61, 64, 59, 219 54, 56, 60, 55, 63, 57, 51, 50, 53, 47, 220 52, 49, 48, 43, 46, 41, 45, 42, 58, 44, 221 95, 105, 70, 68, 67, 66, 69, 71, 65, 72, 222 86, 90, 88, 92, 103, 77, 79, 83, 78, 81, 223 80, 82, 13, 12, 15, 14, 17, 18, 19, 16, 224 2, 1, 0, 4, 6, 7, 9, 8, 33, 32, 225 31, 30, 29, 27, 25, 28, 26, 23, 21, 20, 226 24, 22, 5, 3, 10, 11, 106, 87, 91, 104, 227 97, 100, 228 }; 229 230 /* SCORE groups */ 231 static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 }; 232 static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 }; 233 234 static const unsigned int byt_score_pwm0_pins[] = { 94 }; 235 static const unsigned int byt_score_pwm1_pins[] = { 95 }; 236 237 static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 }; 238 239 static const unsigned int byt_score_i2c5_pins[] = { 88, 89 }; 240 static const unsigned int byt_score_i2c6_pins[] = { 90, 91 }; 241 static const unsigned int byt_score_i2c4_pins[] = { 86, 87 }; 242 static const unsigned int byt_score_i2c3_pins[] = { 84, 85 }; 243 static const unsigned int byt_score_i2c2_pins[] = { 82, 83 }; 244 static const unsigned int byt_score_i2c1_pins[] = { 80, 81 }; 245 static const unsigned int byt_score_i2c0_pins[] = { 78, 79 }; 246 247 static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 }; 248 static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 }; 249 static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 }; 250 251 static const unsigned int byt_score_sdcard_pins[] = { 252 7, 33, 34, 35, 36, 37, 38, 39, 40, 41, 253 }; 254 static const unsigned int byt_score_sdcard_mux_values[] = { 255 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 256 }; 257 258 static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 }; 259 260 static const unsigned int byt_score_emmc_pins[] = { 261 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 262 }; 263 264 static const unsigned int byt_score_ilb_lpc_pins[] = { 265 42, 43, 44, 45, 46, 47, 48, 49, 50, 266 }; 267 268 static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 }; 269 270 static const unsigned int byt_score_plt_clk0_pins[] = { 96 }; 271 static const unsigned int byt_score_plt_clk1_pins[] = { 97 }; 272 static const unsigned int byt_score_plt_clk2_pins[] = { 98 }; 273 static const unsigned int byt_score_plt_clk3_pins[] = { 99 }; 274 static const unsigned int byt_score_plt_clk4_pins[] = { 100 }; 275 static const unsigned int byt_score_plt_clk5_pins[] = { 101 }; 276 277 static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 }; 278 279 static const struct intel_pingroup byt_score_groups[] = { 280 PIN_GROUP("uart1_grp", byt_score_uart1_pins, 1), 281 PIN_GROUP("uart2_grp", byt_score_uart2_pins, 1), 282 PIN_GROUP("pwm0_grp", byt_score_pwm0_pins, 1), 283 PIN_GROUP("pwm1_grp", byt_score_pwm1_pins, 1), 284 PIN_GROUP("ssp2_grp", byt_score_ssp2_pins, 1), 285 PIN_GROUP("sio_spi_grp", byt_score_sio_spi_pins, 1), 286 PIN_GROUP("i2c5_grp", byt_score_i2c5_pins, 1), 287 PIN_GROUP("i2c6_grp", byt_score_i2c6_pins, 1), 288 PIN_GROUP("i2c4_grp", byt_score_i2c4_pins, 1), 289 PIN_GROUP("i2c3_grp", byt_score_i2c3_pins, 1), 290 PIN_GROUP("i2c2_grp", byt_score_i2c2_pins, 1), 291 PIN_GROUP("i2c1_grp", byt_score_i2c1_pins, 1), 292 PIN_GROUP("i2c0_grp", byt_score_i2c0_pins, 1), 293 PIN_GROUP("ssp0_grp", byt_score_ssp0_pins, 1), 294 PIN_GROUP("ssp1_grp", byt_score_ssp1_pins, 1), 295 PIN_GROUP("sdcard_grp", byt_score_sdcard_pins, byt_score_sdcard_mux_values), 296 PIN_GROUP("sdio_grp", byt_score_sdio_pins, 1), 297 PIN_GROUP("emmc_grp", byt_score_emmc_pins, 1), 298 PIN_GROUP("lpc_grp", byt_score_ilb_lpc_pins, 1), 299 PIN_GROUP("sata_grp", byt_score_sata_pins, 1), 300 PIN_GROUP("plt_clk0_grp", byt_score_plt_clk0_pins, 1), 301 PIN_GROUP("plt_clk1_grp", byt_score_plt_clk1_pins, 1), 302 PIN_GROUP("plt_clk2_grp", byt_score_plt_clk2_pins, 1), 303 PIN_GROUP("plt_clk3_grp", byt_score_plt_clk3_pins, 1), 304 PIN_GROUP("plt_clk4_grp", byt_score_plt_clk4_pins, 1), 305 PIN_GROUP("plt_clk5_grp", byt_score_plt_clk5_pins, 1), 306 PIN_GROUP("smbus_grp", byt_score_smbus_pins, 1), 307 }; 308 309 static const char * const byt_score_uart_groups[] = { 310 "uart1_grp", "uart2_grp", 311 }; 312 static const char * const byt_score_pwm_groups[] = { 313 "pwm0_grp", "pwm1_grp", 314 }; 315 static const char * const byt_score_ssp_groups[] = { 316 "ssp0_grp", "ssp1_grp", "ssp2_grp", 317 }; 318 static const char * const byt_score_spi_groups[] = { "sio_spi_grp" }; 319 static const char * const byt_score_i2c_groups[] = { 320 "i2c0_grp", "i2c1_grp", "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", 321 "i2c6_grp", 322 }; 323 static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" }; 324 static const char * const byt_score_sdio_groups[] = { "sdio_grp" }; 325 static const char * const byt_score_emmc_groups[] = { "emmc_grp" }; 326 static const char * const byt_score_lpc_groups[] = { "lpc_grp" }; 327 static const char * const byt_score_sata_groups[] = { "sata_grp" }; 328 static const char * const byt_score_plt_clk_groups[] = { 329 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp", 330 "plt_clk4_grp", "plt_clk5_grp", 331 }; 332 static const char * const byt_score_smbus_groups[] = { "smbus_grp" }; 333 static const char * const byt_score_gpio_groups[] = { 334 "uart1_grp", "uart2_grp", "pwm0_grp", "pwm1_grp", "ssp0_grp", 335 "ssp1_grp", "ssp2_grp", "sio_spi_grp", "i2c0_grp", "i2c1_grp", 336 "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", "i2c6_grp", 337 "sdcard_grp", "sdio_grp", "emmc_grp", "lpc_grp", "sata_grp", 338 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp", 339 "plt_clk4_grp", "plt_clk5_grp", "smbus_grp", 340 }; 341 342 static const struct intel_function byt_score_functions[] = { 343 FUNCTION("uart", byt_score_uart_groups), 344 FUNCTION("pwm", byt_score_pwm_groups), 345 FUNCTION("ssp", byt_score_ssp_groups), 346 FUNCTION("spi", byt_score_spi_groups), 347 FUNCTION("i2c", byt_score_i2c_groups), 348 FUNCTION("sdcard", byt_score_sdcard_groups), 349 FUNCTION("sdio", byt_score_sdio_groups), 350 FUNCTION("emmc", byt_score_emmc_groups), 351 FUNCTION("lpc", byt_score_lpc_groups), 352 FUNCTION("sata", byt_score_sata_groups), 353 FUNCTION("plt_clk", byt_score_plt_clk_groups), 354 FUNCTION("smbus", byt_score_smbus_groups), 355 FUNCTION("gpio", byt_score_gpio_groups), 356 }; 357 358 static const struct intel_community byt_score_communities[] = { 359 COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map), 360 }; 361 362 static const struct intel_pinctrl_soc_data byt_score_soc_data = { 363 .uid = BYT_SCORE_ACPI_UID, 364 .pins = byt_score_pins, 365 .npins = ARRAY_SIZE(byt_score_pins), 366 .groups = byt_score_groups, 367 .ngroups = ARRAY_SIZE(byt_score_groups), 368 .functions = byt_score_functions, 369 .nfunctions = ARRAY_SIZE(byt_score_functions), 370 .communities = byt_score_communities, 371 .ncommunities = ARRAY_SIZE(byt_score_communities), 372 }; 373 374 /* SUS pins, aka GPIOS_<pin_no> or GPIO_S5[<pin_no>] */ 375 static const struct pinctrl_pin_desc byt_sus_pins[] = { 376 PINCTRL_PIN(0, "GPIO_S50"), 377 PINCTRL_PIN(1, "GPIO_S51"), 378 PINCTRL_PIN(2, "GPIO_S52"), 379 PINCTRL_PIN(3, "GPIO_S53"), 380 PINCTRL_PIN(4, "GPIO_S54"), 381 PINCTRL_PIN(5, "GPIO_S55"), 382 PINCTRL_PIN(6, "GPIO_S56"), 383 PINCTRL_PIN(7, "GPIO_S57"), 384 PINCTRL_PIN(8, "GPIO_S58"), 385 PINCTRL_PIN(9, "GPIO_S59"), 386 PINCTRL_PIN(10, "GPIO_S510"), 387 PINCTRL_PIN(11, "PMC_SUSPWRDNACK"), 388 PINCTRL_PIN(12, "PMC_SUSCLK0"), 389 PINCTRL_PIN(13, "GPIO_S513"), 390 PINCTRL_PIN(14, "USB_ULPI_RST"), 391 PINCTRL_PIN(15, "PMC_WAKE_PCIE0#"), 392 PINCTRL_PIN(16, "PMC_PWRBTN"), 393 PINCTRL_PIN(17, "GPIO_S517"), 394 PINCTRL_PIN(18, "PMC_SUS_STAT"), 395 PINCTRL_PIN(19, "USB_OC0"), 396 PINCTRL_PIN(20, "USB_OC1"), 397 PINCTRL_PIN(21, "PCU_SPI_CS1"), 398 PINCTRL_PIN(22, "GPIO_S522"), 399 PINCTRL_PIN(23, "GPIO_S523"), 400 PINCTRL_PIN(24, "GPIO_S524"), 401 PINCTRL_PIN(25, "GPIO_S525"), 402 PINCTRL_PIN(26, "GPIO_S526"), 403 PINCTRL_PIN(27, "GPIO_S527"), 404 PINCTRL_PIN(28, "GPIO_S528"), 405 PINCTRL_PIN(29, "GPIO_S529"), 406 PINCTRL_PIN(30, "GPIO_S530"), 407 PINCTRL_PIN(31, "USB_ULPI_CLK"), 408 PINCTRL_PIN(32, "USB_ULPI_DATA0"), 409 PINCTRL_PIN(33, "USB_ULPI_DATA1"), 410 PINCTRL_PIN(34, "USB_ULPI_DATA2"), 411 PINCTRL_PIN(35, "USB_ULPI_DATA3"), 412 PINCTRL_PIN(36, "USB_ULPI_DATA4"), 413 PINCTRL_PIN(37, "USB_ULPI_DATA5"), 414 PINCTRL_PIN(38, "USB_ULPI_DATA6"), 415 PINCTRL_PIN(39, "USB_ULPI_DATA7"), 416 PINCTRL_PIN(40, "USB_ULPI_DIR"), 417 PINCTRL_PIN(41, "USB_ULPI_NXT"), 418 PINCTRL_PIN(42, "USB_ULPI_STP"), 419 PINCTRL_PIN(43, "USB_ULPI_REFCLK"), 420 }; 421 422 static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = { 423 29, 33, 30, 31, 32, 34, 36, 35, 38, 37, 424 18, 7, 11, 20, 17, 1, 8, 10, 19, 12, 425 0, 2, 23, 39, 28, 27, 22, 21, 24, 25, 426 26, 51, 56, 54, 49, 55, 48, 57, 50, 58, 427 52, 53, 59, 40, 428 }; 429 430 static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 }; 431 static const unsigned int byt_sus_usb_over_current_mode_values[] = { 0, 0 }; 432 static const unsigned int byt_sus_usb_over_current_gpio_mode_values[] = { 1, 1 }; 433 434 static const unsigned int byt_sus_usb_ulpi_pins[] = { 435 14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 436 }; 437 static const unsigned int byt_sus_usb_ulpi_mode_values[] = { 438 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 439 }; 440 static const unsigned int byt_sus_usb_ulpi_gpio_mode_values[] = { 441 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 442 }; 443 444 static const unsigned int byt_sus_pcu_spi_pins[] = { 21 }; 445 static const unsigned int byt_sus_pcu_spi_mode_values[] = { 0 }; 446 static const unsigned int byt_sus_pcu_spi_gpio_mode_values[] = { 1 }; 447 448 static const unsigned int byt_sus_pmu_clk1_pins[] = { 5 }; 449 static const unsigned int byt_sus_pmu_clk2_pins[] = { 6 }; 450 451 static const struct intel_pingroup byt_sus_groups[] = { 452 PIN_GROUP("usb_oc_grp", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_mode_values), 453 PIN_GROUP("usb_ulpi_grp", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mode_values), 454 PIN_GROUP("pcu_spi_grp", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mode_values), 455 PIN_GROUP("usb_oc_grp_gpio", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_gpio_mode_values), 456 PIN_GROUP("usb_ulpi_grp_gpio", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_gpio_mode_values), 457 PIN_GROUP("pcu_spi_grp_gpio", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_gpio_mode_values), 458 PIN_GROUP("pmu_clk1_grp", byt_sus_pmu_clk1_pins, 1), 459 PIN_GROUP("pmu_clk2_grp", byt_sus_pmu_clk2_pins, 1), 460 }; 461 462 static const char * const byt_sus_usb_groups[] = { 463 "usb_oc_grp", "usb_ulpi_grp", 464 }; 465 static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" }; 466 static const char * const byt_sus_pmu_clk_groups[] = { 467 "pmu_clk1_grp", "pmu_clk2_grp", 468 }; 469 static const char * const byt_sus_gpio_groups[] = { 470 "usb_oc_grp_gpio", "usb_ulpi_grp_gpio", "pcu_spi_grp_gpio", 471 "pmu_clk1_grp", "pmu_clk2_grp", 472 }; 473 474 static const struct intel_function byt_sus_functions[] = { 475 FUNCTION("usb", byt_sus_usb_groups), 476 FUNCTION("spi", byt_sus_spi_groups), 477 FUNCTION("gpio", byt_sus_gpio_groups), 478 FUNCTION("pmu_clk", byt_sus_pmu_clk_groups), 479 }; 480 481 static const struct intel_community byt_sus_communities[] = { 482 COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map), 483 }; 484 485 static const struct intel_pinctrl_soc_data byt_sus_soc_data = { 486 .uid = BYT_SUS_ACPI_UID, 487 .pins = byt_sus_pins, 488 .npins = ARRAY_SIZE(byt_sus_pins), 489 .groups = byt_sus_groups, 490 .ngroups = ARRAY_SIZE(byt_sus_groups), 491 .functions = byt_sus_functions, 492 .nfunctions = ARRAY_SIZE(byt_sus_functions), 493 .communities = byt_sus_communities, 494 .ncommunities = ARRAY_SIZE(byt_sus_communities), 495 }; 496 497 static const struct pinctrl_pin_desc byt_ncore_pins[] = { 498 PINCTRL_PIN(0, "HV_DDI0_HPD"), 499 PINCTRL_PIN(1, "HV_DDI0_DDC_SDA"), 500 PINCTRL_PIN(2, "HV_DDI0_DDC_SCL"), 501 PINCTRL_PIN(3, "PANEL0_VDDEN"), 502 PINCTRL_PIN(4, "PANEL0_BKLTEN"), 503 PINCTRL_PIN(5, "PANEL0_BKLTCTL"), 504 PINCTRL_PIN(6, "HV_DDI1_HPD"), 505 PINCTRL_PIN(7, "HV_DDI1_DDC_SDA"), 506 PINCTRL_PIN(8, "HV_DDI1_DDC_SCL"), 507 PINCTRL_PIN(9, "PANEL1_VDDEN"), 508 PINCTRL_PIN(10, "PANEL1_BKLTEN"), 509 PINCTRL_PIN(11, "PANEL1_BKLTCTL"), 510 PINCTRL_PIN(12, "GP_INTD_DSI_TE1"), 511 PINCTRL_PIN(13, "HV_DDI2_DDC_SDA"), 512 PINCTRL_PIN(14, "HV_DDI2_DDC_SCL"), 513 PINCTRL_PIN(15, "GP_CAMERASB00"), 514 PINCTRL_PIN(16, "GP_CAMERASB01"), 515 PINCTRL_PIN(17, "GP_CAMERASB02"), 516 PINCTRL_PIN(18, "GP_CAMERASB03"), 517 PINCTRL_PIN(19, "GP_CAMERASB04"), 518 PINCTRL_PIN(20, "GP_CAMERASB05"), 519 PINCTRL_PIN(21, "GP_CAMERASB06"), 520 PINCTRL_PIN(22, "GP_CAMERASB07"), 521 PINCTRL_PIN(23, "GP_CAMERASB08"), 522 PINCTRL_PIN(24, "GP_CAMERASB09"), 523 PINCTRL_PIN(25, "GP_CAMERASB10"), 524 PINCTRL_PIN(26, "GP_CAMERASB11"), 525 PINCTRL_PIN(27, "GP_INTD_DSI_TE2"), 526 }; 527 528 static const unsigned int byt_ncore_pins_map[BYT_NGPIO_NCORE] = { 529 19, 18, 17, 20, 21, 22, 24, 25, 23, 16, 530 14, 15, 12, 26, 27, 1, 4, 8, 11, 0, 531 3, 6, 10, 13, 2, 5, 9, 7, 532 }; 533 534 static const struct intel_community byt_ncore_communities[] = { 535 COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map), 536 }; 537 538 static const struct intel_pinctrl_soc_data byt_ncore_soc_data = { 539 .uid = BYT_NCORE_ACPI_UID, 540 .pins = byt_ncore_pins, 541 .npins = ARRAY_SIZE(byt_ncore_pins), 542 .communities = byt_ncore_communities, 543 .ncommunities = ARRAY_SIZE(byt_ncore_communities), 544 }; 545 546 static const struct intel_pinctrl_soc_data *byt_soc_data[] = { 547 &byt_score_soc_data, 548 &byt_sus_soc_data, 549 &byt_ncore_soc_data, 550 NULL 551 }; 552 553 static DEFINE_RAW_SPINLOCK(byt_lock); 554 555 static void __iomem *byt_gpio_reg(struct intel_pinctrl *vg, unsigned int offset, 556 int reg) 557 { 558 struct intel_community *comm = intel_get_community(vg, offset); 559 u32 reg_offset; 560 561 if (!comm) 562 return NULL; 563 564 offset -= comm->pin_base; 565 switch (reg) { 566 case BYT_INT_STAT_REG: 567 reg_offset = (offset / 32) * 4; 568 break; 569 case BYT_DEBOUNCE_REG: 570 reg_offset = 0; 571 break; 572 default: 573 reg_offset = comm->pad_map[offset] * 16; 574 break; 575 } 576 577 return comm->pad_regs + reg_offset + reg; 578 } 579 580 static const struct pinctrl_ops byt_pinctrl_ops = { 581 .get_groups_count = intel_get_groups_count, 582 .get_group_name = intel_get_group_name, 583 .get_group_pins = intel_get_group_pins, 584 }; 585 586 static void byt_set_group_simple_mux(struct intel_pinctrl *vg, 587 const struct intel_pingroup group, 588 unsigned int func) 589 { 590 unsigned long flags; 591 int i; 592 593 raw_spin_lock_irqsave(&byt_lock, flags); 594 595 for (i = 0; i < group.grp.npins; i++) { 596 void __iomem *padcfg0; 597 u32 value; 598 599 padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG); 600 if (!padcfg0) { 601 dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n", 602 group.grp.name, i); 603 continue; 604 } 605 606 value = readl(padcfg0); 607 value &= ~BYT_PIN_MUX; 608 value |= func; 609 writel(value, padcfg0); 610 } 611 612 raw_spin_unlock_irqrestore(&byt_lock, flags); 613 } 614 615 static void byt_set_group_mixed_mux(struct intel_pinctrl *vg, 616 const struct intel_pingroup group, 617 const unsigned int *func) 618 { 619 unsigned long flags; 620 int i; 621 622 raw_spin_lock_irqsave(&byt_lock, flags); 623 624 for (i = 0; i < group.grp.npins; i++) { 625 void __iomem *padcfg0; 626 u32 value; 627 628 padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG); 629 if (!padcfg0) { 630 dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n", 631 group.grp.name, i); 632 continue; 633 } 634 635 value = readl(padcfg0); 636 value &= ~BYT_PIN_MUX; 637 value |= func[i]; 638 writel(value, padcfg0); 639 } 640 641 raw_spin_unlock_irqrestore(&byt_lock, flags); 642 } 643 644 static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, 645 unsigned int group_selector) 646 { 647 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); 648 const struct intel_function func = vg->soc->functions[func_selector]; 649 const struct intel_pingroup group = vg->soc->groups[group_selector]; 650 651 if (group.modes) 652 byt_set_group_mixed_mux(vg, group, group.modes); 653 else if (!strcmp(func.func.name, "gpio")) 654 byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX); 655 else 656 byt_set_group_simple_mux(vg, group, group.mode); 657 658 return 0; 659 } 660 661 static u32 byt_get_gpio_mux(struct intel_pinctrl *vg, unsigned int offset) 662 { 663 /* SCORE pin 92-93 */ 664 if (!strcmp(vg->soc->uid, BYT_SCORE_ACPI_UID) && 665 offset >= 92 && offset <= 93) 666 return BYT_ALTER_GPIO_MUX; 667 668 /* SUS pin 11-21 */ 669 if (!strcmp(vg->soc->uid, BYT_SUS_ACPI_UID) && 670 offset >= 11 && offset <= 21) 671 return BYT_ALTER_GPIO_MUX; 672 673 return BYT_DEFAULT_GPIO_MUX; 674 } 675 676 static void byt_gpio_clear_triggering(struct intel_pinctrl *vg, unsigned int offset) 677 { 678 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 679 unsigned long flags; 680 u32 value; 681 682 raw_spin_lock_irqsave(&byt_lock, flags); 683 value = readl(reg); 684 685 /* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */ 686 if (!(value & BYT_DIRECT_IRQ_EN)) 687 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL); 688 689 writel(value, reg); 690 raw_spin_unlock_irqrestore(&byt_lock, flags); 691 } 692 693 static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev, 694 struct pinctrl_gpio_range *range, 695 unsigned int offset) 696 { 697 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); 698 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 699 u32 value, gpio_mux; 700 unsigned long flags; 701 702 raw_spin_lock_irqsave(&byt_lock, flags); 703 704 /* 705 * In most cases, func pin mux 000 means GPIO function. 706 * But, some pins may have func pin mux 001 represents 707 * GPIO function. 708 * 709 * Because there are devices out there where some pins were not 710 * configured correctly we allow changing the mux value from 711 * request (but print out warning about that). 712 */ 713 value = readl(reg) & BYT_PIN_MUX; 714 gpio_mux = byt_get_gpio_mux(vg, offset); 715 if (gpio_mux != value) { 716 value = readl(reg) & ~BYT_PIN_MUX; 717 value |= gpio_mux; 718 writel(value, reg); 719 720 dev_warn(vg->dev, FW_BUG "Pin %i: forcibly re-configured as GPIO\n", offset); 721 } 722 723 raw_spin_unlock_irqrestore(&byt_lock, flags); 724 725 pm_runtime_get(vg->dev); 726 727 return 0; 728 } 729 730 static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev, 731 struct pinctrl_gpio_range *range, 732 unsigned int offset) 733 { 734 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); 735 736 byt_gpio_clear_triggering(vg, offset); 737 pm_runtime_put(vg->dev); 738 } 739 740 static void byt_gpio_direct_irq_check(struct intel_pinctrl *vg, 741 unsigned int offset) 742 { 743 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 744 745 /* 746 * Before making any direction modifications, do a check if gpio is set 747 * for direct IRQ. On Bay Trail, setting GPIO to output does not make 748 * sense, so let's at least inform the caller before they shoot 749 * themselves in the foot. 750 */ 751 if (readl(conf_reg) & BYT_DIRECT_IRQ_EN) 752 dev_info_once(vg->dev, 753 "Potential Error: Pin %i: forcibly set GPIO with DIRECT_IRQ_EN to output\n", 754 offset); 755 } 756 757 static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev, 758 struct pinctrl_gpio_range *range, 759 unsigned int offset, 760 bool input) 761 { 762 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); 763 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 764 unsigned long flags; 765 u32 value; 766 767 raw_spin_lock_irqsave(&byt_lock, flags); 768 769 value = readl(val_reg); 770 value &= ~BYT_DIR_MASK; 771 if (input) 772 value |= BYT_OUTPUT_EN; 773 else 774 byt_gpio_direct_irq_check(vg, offset); 775 776 writel(value, val_reg); 777 778 raw_spin_unlock_irqrestore(&byt_lock, flags); 779 780 return 0; 781 } 782 783 static const struct pinmux_ops byt_pinmux_ops = { 784 .get_functions_count = intel_get_functions_count, 785 .get_function_name = intel_get_function_name, 786 .get_function_groups = intel_get_function_groups, 787 .set_mux = byt_set_mux, 788 .gpio_request_enable = byt_gpio_request_enable, 789 .gpio_disable_free = byt_gpio_disable_free, 790 .gpio_set_direction = byt_gpio_set_direction, 791 }; 792 793 static void byt_get_pull_strength(u32 reg, u16 *strength) 794 { 795 switch (reg & BYT_PULL_STR_MASK) { 796 case BYT_PULL_STR_2K: 797 *strength = 2000; 798 break; 799 case BYT_PULL_STR_10K: 800 *strength = 10000; 801 break; 802 case BYT_PULL_STR_20K: 803 *strength = 20000; 804 break; 805 case BYT_PULL_STR_40K: 806 *strength = 40000; 807 break; 808 } 809 } 810 811 static int byt_set_pull_strength(u32 *reg, u16 strength) 812 { 813 *reg &= ~BYT_PULL_STR_MASK; 814 815 switch (strength) { 816 case 2000: 817 *reg |= BYT_PULL_STR_2K; 818 break; 819 case 10000: 820 *reg |= BYT_PULL_STR_10K; 821 break; 822 case 20000: 823 *reg |= BYT_PULL_STR_20K; 824 break; 825 case 40000: 826 *reg |= BYT_PULL_STR_40K; 827 break; 828 default: 829 return -EINVAL; 830 } 831 832 return 0; 833 } 834 835 static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset, 836 unsigned long *config) 837 { 838 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); 839 enum pin_config_param param = pinconf_to_config_param(*config); 840 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 841 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 842 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG); 843 unsigned long flags; 844 u32 conf, pull, val, debounce; 845 u16 arg = 0; 846 847 raw_spin_lock_irqsave(&byt_lock, flags); 848 conf = readl(conf_reg); 849 pull = conf & BYT_PULL_ASSIGN_MASK; 850 val = readl(val_reg); 851 raw_spin_unlock_irqrestore(&byt_lock, flags); 852 853 switch (param) { 854 case PIN_CONFIG_BIAS_DISABLE: 855 if (pull) 856 return -EINVAL; 857 break; 858 case PIN_CONFIG_BIAS_PULL_DOWN: 859 /* Pull assignment is only applicable in input mode */ 860 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN) 861 return -EINVAL; 862 863 byt_get_pull_strength(conf, &arg); 864 865 break; 866 case PIN_CONFIG_BIAS_PULL_UP: 867 /* Pull assignment is only applicable in input mode */ 868 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP) 869 return -EINVAL; 870 871 byt_get_pull_strength(conf, &arg); 872 873 break; 874 case PIN_CONFIG_INPUT_DEBOUNCE: 875 if (!(conf & BYT_DEBOUNCE_EN)) 876 return -EINVAL; 877 878 raw_spin_lock_irqsave(&byt_lock, flags); 879 debounce = readl(db_reg); 880 raw_spin_unlock_irqrestore(&byt_lock, flags); 881 882 switch (debounce & BYT_DEBOUNCE_PULSE_MASK) { 883 case BYT_DEBOUNCE_PULSE_375US: 884 arg = 375; 885 break; 886 case BYT_DEBOUNCE_PULSE_750US: 887 arg = 750; 888 break; 889 case BYT_DEBOUNCE_PULSE_1500US: 890 arg = 1500; 891 break; 892 case BYT_DEBOUNCE_PULSE_3MS: 893 arg = 3000; 894 break; 895 case BYT_DEBOUNCE_PULSE_6MS: 896 arg = 6000; 897 break; 898 case BYT_DEBOUNCE_PULSE_12MS: 899 arg = 12000; 900 break; 901 case BYT_DEBOUNCE_PULSE_24MS: 902 arg = 24000; 903 break; 904 default: 905 return -EINVAL; 906 } 907 908 break; 909 default: 910 return -ENOTSUPP; 911 } 912 913 *config = pinconf_to_config_packed(param, arg); 914 915 return 0; 916 } 917 918 static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, 919 unsigned int offset, 920 unsigned long *configs, 921 unsigned int num_configs) 922 { 923 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); 924 unsigned int param, arg; 925 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 926 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 927 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG); 928 u32 conf, val, db_pulse, debounce; 929 unsigned long flags; 930 int i, ret = 0; 931 932 raw_spin_lock_irqsave(&byt_lock, flags); 933 934 conf = readl(conf_reg); 935 val = readl(val_reg); 936 937 for (i = 0; i < num_configs; i++) { 938 param = pinconf_to_config_param(configs[i]); 939 arg = pinconf_to_config_argument(configs[i]); 940 941 switch (param) { 942 case PIN_CONFIG_BIAS_DISABLE: 943 conf &= ~BYT_PULL_ASSIGN_MASK; 944 break; 945 case PIN_CONFIG_BIAS_PULL_DOWN: 946 /* Set default strength value in case none is given */ 947 if (arg == 1) 948 arg = 2000; 949 950 /* 951 * Pull assignment is only applicable in input mode. If 952 * chip is not in input mode, set it and warn about it. 953 */ 954 if (val & BYT_INPUT_EN) { 955 val &= ~BYT_INPUT_EN; 956 writel(val, val_reg); 957 dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset); 958 } 959 960 conf &= ~BYT_PULL_ASSIGN_MASK; 961 conf |= BYT_PULL_ASSIGN_DOWN; 962 ret = byt_set_pull_strength(&conf, arg); 963 964 break; 965 case PIN_CONFIG_BIAS_PULL_UP: 966 /* Set default strength value in case none is given */ 967 if (arg == 1) 968 arg = 2000; 969 970 /* 971 * Pull assignment is only applicable in input mode. If 972 * chip is not in input mode, set it and warn about it. 973 */ 974 if (val & BYT_INPUT_EN) { 975 val &= ~BYT_INPUT_EN; 976 writel(val, val_reg); 977 dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset); 978 } 979 980 conf &= ~BYT_PULL_ASSIGN_MASK; 981 conf |= BYT_PULL_ASSIGN_UP; 982 ret = byt_set_pull_strength(&conf, arg); 983 984 break; 985 case PIN_CONFIG_INPUT_DEBOUNCE: 986 if (arg) { 987 conf |= BYT_DEBOUNCE_EN; 988 } else { 989 conf &= ~BYT_DEBOUNCE_EN; 990 991 /* 992 * No need to update the pulse value. 993 * Debounce is going to be disabled. 994 */ 995 break; 996 } 997 998 switch (arg) { 999 case 375: 1000 db_pulse = BYT_DEBOUNCE_PULSE_375US; 1001 break; 1002 case 750: 1003 db_pulse = BYT_DEBOUNCE_PULSE_750US; 1004 break; 1005 case 1500: 1006 db_pulse = BYT_DEBOUNCE_PULSE_1500US; 1007 break; 1008 case 3000: 1009 db_pulse = BYT_DEBOUNCE_PULSE_3MS; 1010 break; 1011 case 6000: 1012 db_pulse = BYT_DEBOUNCE_PULSE_6MS; 1013 break; 1014 case 12000: 1015 db_pulse = BYT_DEBOUNCE_PULSE_12MS; 1016 break; 1017 case 24000: 1018 db_pulse = BYT_DEBOUNCE_PULSE_24MS; 1019 break; 1020 default: 1021 if (arg) 1022 ret = -EINVAL; 1023 break; 1024 } 1025 1026 if (ret) 1027 break; 1028 1029 debounce = readl(db_reg); 1030 debounce = (debounce & ~BYT_DEBOUNCE_PULSE_MASK) | db_pulse; 1031 writel(debounce, db_reg); 1032 1033 break; 1034 default: 1035 ret = -ENOTSUPP; 1036 } 1037 1038 if (ret) 1039 break; 1040 } 1041 1042 if (!ret) 1043 writel(conf, conf_reg); 1044 1045 raw_spin_unlock_irqrestore(&byt_lock, flags); 1046 1047 return ret; 1048 } 1049 1050 static const struct pinconf_ops byt_pinconf_ops = { 1051 .is_generic = true, 1052 .pin_config_get = byt_pin_config_get, 1053 .pin_config_set = byt_pin_config_set, 1054 }; 1055 1056 static const struct pinctrl_desc byt_pinctrl_desc = { 1057 .pctlops = &byt_pinctrl_ops, 1058 .pmxops = &byt_pinmux_ops, 1059 .confops = &byt_pinconf_ops, 1060 .owner = THIS_MODULE, 1061 }; 1062 1063 static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset) 1064 { 1065 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1066 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1067 unsigned long flags; 1068 u32 val; 1069 1070 raw_spin_lock_irqsave(&byt_lock, flags); 1071 val = readl(reg); 1072 raw_spin_unlock_irqrestore(&byt_lock, flags); 1073 1074 return !!(val & BYT_LEVEL); 1075 } 1076 1077 static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 1078 { 1079 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1080 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1081 unsigned long flags; 1082 u32 old_val; 1083 1084 if (!reg) 1085 return; 1086 1087 raw_spin_lock_irqsave(&byt_lock, flags); 1088 old_val = readl(reg); 1089 if (value) 1090 writel(old_val | BYT_LEVEL, reg); 1091 else 1092 writel(old_val & ~BYT_LEVEL, reg); 1093 raw_spin_unlock_irqrestore(&byt_lock, flags); 1094 } 1095 1096 static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 1097 { 1098 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1099 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1100 unsigned long flags; 1101 u32 value; 1102 1103 if (!reg) 1104 return -EINVAL; 1105 1106 raw_spin_lock_irqsave(&byt_lock, flags); 1107 value = readl(reg); 1108 raw_spin_unlock_irqrestore(&byt_lock, flags); 1109 1110 if (!(value & BYT_OUTPUT_EN)) 1111 return GPIO_LINE_DIRECTION_OUT; 1112 if (!(value & BYT_INPUT_EN)) 1113 return GPIO_LINE_DIRECTION_IN; 1114 1115 return -EINVAL; 1116 } 1117 1118 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 1119 { 1120 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1121 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1122 unsigned long flags; 1123 u32 reg; 1124 1125 raw_spin_lock_irqsave(&byt_lock, flags); 1126 1127 reg = readl(val_reg); 1128 reg &= ~BYT_DIR_MASK; 1129 reg |= BYT_OUTPUT_EN; 1130 writel(reg, val_reg); 1131 1132 raw_spin_unlock_irqrestore(&byt_lock, flags); 1133 return 0; 1134 } 1135 1136 /* 1137 * Note despite the temptation this MUST NOT be converted into a call to 1138 * pinctrl_gpio_direction_output() + byt_gpio_set() that does not work this 1139 * MUST be done as a single BYT_VAL_REG register write. 1140 * See the commit message of the commit adding this comment for details. 1141 */ 1142 static int byt_gpio_direction_output(struct gpio_chip *chip, 1143 unsigned int offset, int value) 1144 { 1145 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1146 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1147 unsigned long flags; 1148 u32 reg; 1149 1150 raw_spin_lock_irqsave(&byt_lock, flags); 1151 1152 byt_gpio_direct_irq_check(vg, offset); 1153 1154 reg = readl(val_reg); 1155 reg &= ~BYT_DIR_MASK; 1156 if (value) 1157 reg |= BYT_LEVEL; 1158 else 1159 reg &= ~BYT_LEVEL; 1160 1161 writel(reg, val_reg); 1162 1163 raw_spin_unlock_irqrestore(&byt_lock, flags); 1164 return 0; 1165 } 1166 1167 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 1168 { 1169 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1170 int i; 1171 u32 conf0, val; 1172 1173 for (i = 0; i < vg->soc->npins; i++) { 1174 const struct intel_community *comm; 1175 void __iomem *conf_reg, *val_reg; 1176 const char *pull_str = NULL; 1177 const char *pull = NULL; 1178 unsigned long flags; 1179 const char *label; 1180 unsigned int pin; 1181 1182 pin = vg->soc->pins[i].number; 1183 1184 conf_reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1185 if (!conf_reg) { 1186 seq_printf(s, "Pin %i: can't retrieve CONF0\n", pin); 1187 continue; 1188 } 1189 1190 val_reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); 1191 if (!val_reg) { 1192 seq_printf(s, "Pin %i: can't retrieve VAL\n", pin); 1193 continue; 1194 } 1195 1196 raw_spin_lock_irqsave(&byt_lock, flags); 1197 conf0 = readl(conf_reg); 1198 val = readl(val_reg); 1199 raw_spin_unlock_irqrestore(&byt_lock, flags); 1200 1201 comm = intel_get_community(vg, pin); 1202 if (!comm) { 1203 seq_printf(s, "Pin %i: can't retrieve community\n", pin); 1204 continue; 1205 } 1206 label = gpiochip_is_requested(chip, i); 1207 if (!label) 1208 label = "Unrequested"; 1209 1210 switch (conf0 & BYT_PULL_ASSIGN_MASK) { 1211 case BYT_PULL_ASSIGN_UP: 1212 pull = "up"; 1213 break; 1214 case BYT_PULL_ASSIGN_DOWN: 1215 pull = "down"; 1216 break; 1217 } 1218 1219 switch (conf0 & BYT_PULL_STR_MASK) { 1220 case BYT_PULL_STR_2K: 1221 pull_str = "2k"; 1222 break; 1223 case BYT_PULL_STR_10K: 1224 pull_str = "10k"; 1225 break; 1226 case BYT_PULL_STR_20K: 1227 pull_str = "20k"; 1228 break; 1229 case BYT_PULL_STR_40K: 1230 pull_str = "40k"; 1231 break; 1232 } 1233 1234 seq_printf(s, 1235 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s", 1236 pin, 1237 label, 1238 val & BYT_INPUT_EN ? " " : "in", 1239 val & BYT_OUTPUT_EN ? " " : "out", 1240 str_hi_lo(val & BYT_LEVEL), 1241 comm->pad_map[i], comm->pad_map[i] * 16, 1242 conf0 & 0x7, 1243 conf0 & BYT_TRIG_NEG ? " fall" : " ", 1244 conf0 & BYT_TRIG_POS ? " rise" : " ", 1245 conf0 & BYT_TRIG_LVL ? " level" : " "); 1246 1247 if (pull && pull_str) 1248 seq_printf(s, " %-4s %-3s", pull, pull_str); 1249 else 1250 seq_puts(s, " "); 1251 1252 if (conf0 & BYT_IODEN) 1253 seq_puts(s, " open-drain"); 1254 1255 seq_puts(s, "\n"); 1256 } 1257 } 1258 1259 static const struct gpio_chip byt_gpio_chip = { 1260 .owner = THIS_MODULE, 1261 .request = gpiochip_generic_request, 1262 .free = gpiochip_generic_free, 1263 .get_direction = byt_gpio_get_direction, 1264 .direction_input = byt_gpio_direction_input, 1265 .direction_output = byt_gpio_direction_output, 1266 .get = byt_gpio_get, 1267 .set = byt_gpio_set, 1268 .set_config = gpiochip_generic_config, 1269 .dbg_show = byt_gpio_dbg_show, 1270 }; 1271 1272 static void byt_irq_ack(struct irq_data *d) 1273 { 1274 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1275 struct intel_pinctrl *vg = gpiochip_get_data(gc); 1276 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1277 void __iomem *reg; 1278 1279 reg = byt_gpio_reg(vg, hwirq, BYT_INT_STAT_REG); 1280 if (!reg) 1281 return; 1282 1283 raw_spin_lock(&byt_lock); 1284 writel(BIT(hwirq % 32), reg); 1285 raw_spin_unlock(&byt_lock); 1286 } 1287 1288 static void byt_irq_mask(struct irq_data *d) 1289 { 1290 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1291 struct intel_pinctrl *vg = gpiochip_get_data(gc); 1292 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1293 1294 byt_gpio_clear_triggering(vg, hwirq); 1295 gpiochip_disable_irq(gc, hwirq); 1296 } 1297 1298 static void byt_irq_unmask(struct irq_data *d) 1299 { 1300 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1301 struct intel_pinctrl *vg = gpiochip_get_data(gc); 1302 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1303 unsigned long flags; 1304 void __iomem *reg; 1305 u32 value; 1306 1307 gpiochip_enable_irq(gc, hwirq); 1308 1309 reg = byt_gpio_reg(vg, hwirq, BYT_CONF0_REG); 1310 if (!reg) 1311 return; 1312 1313 raw_spin_lock_irqsave(&byt_lock, flags); 1314 value = readl(reg); 1315 1316 switch (irqd_get_trigger_type(d)) { 1317 case IRQ_TYPE_LEVEL_HIGH: 1318 value |= BYT_TRIG_LVL; 1319 fallthrough; 1320 case IRQ_TYPE_EDGE_RISING: 1321 value |= BYT_TRIG_POS; 1322 break; 1323 case IRQ_TYPE_LEVEL_LOW: 1324 value |= BYT_TRIG_LVL; 1325 fallthrough; 1326 case IRQ_TYPE_EDGE_FALLING: 1327 value |= BYT_TRIG_NEG; 1328 break; 1329 case IRQ_TYPE_EDGE_BOTH: 1330 value |= (BYT_TRIG_NEG | BYT_TRIG_POS); 1331 break; 1332 } 1333 1334 writel(value, reg); 1335 1336 raw_spin_unlock_irqrestore(&byt_lock, flags); 1337 } 1338 1339 static int byt_irq_type(struct irq_data *d, unsigned int type) 1340 { 1341 struct intel_pinctrl *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d)); 1342 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1343 u32 value; 1344 unsigned long flags; 1345 void __iomem *reg; 1346 1347 reg = byt_gpio_reg(vg, hwirq, BYT_CONF0_REG); 1348 if (!reg) 1349 return -EINVAL; 1350 1351 raw_spin_lock_irqsave(&byt_lock, flags); 1352 value = readl(reg); 1353 1354 WARN(value & BYT_DIRECT_IRQ_EN, 1355 "Bad pad config for IO mode, force DIRECT_IRQ_EN bit clearing"); 1356 1357 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits 1358 * are used to indicate high and low level triggering 1359 */ 1360 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG | 1361 BYT_TRIG_LVL); 1362 /* Enable glitch filtering */ 1363 value |= BYT_GLITCH_FILTER_EN | BYT_GLITCH_F_SLOW_CLK | 1364 BYT_GLITCH_F_FAST_CLK; 1365 1366 writel(value, reg); 1367 1368 if (type & IRQ_TYPE_EDGE_BOTH) 1369 irq_set_handler_locked(d, handle_edge_irq); 1370 else if (type & IRQ_TYPE_LEVEL_MASK) 1371 irq_set_handler_locked(d, handle_level_irq); 1372 1373 raw_spin_unlock_irqrestore(&byt_lock, flags); 1374 1375 return 0; 1376 } 1377 1378 static const struct irq_chip byt_gpio_irq_chip = { 1379 .name = "BYT-GPIO", 1380 .irq_ack = byt_irq_ack, 1381 .irq_mask = byt_irq_mask, 1382 .irq_unmask = byt_irq_unmask, 1383 .irq_set_type = byt_irq_type, 1384 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE, 1385 GPIOCHIP_IRQ_RESOURCE_HELPERS, 1386 }; 1387 1388 static void byt_gpio_irq_handler(struct irq_desc *desc) 1389 { 1390 struct irq_data *data = irq_desc_get_irq_data(desc); 1391 struct intel_pinctrl *vg = gpiochip_get_data(irq_desc_get_handler_data(desc)); 1392 struct irq_chip *chip = irq_data_get_irq_chip(data); 1393 u32 base, pin; 1394 void __iomem *reg; 1395 unsigned long pending; 1396 1397 /* check from GPIO controller which pin triggered the interrupt */ 1398 for (base = 0; base < vg->chip.ngpio; base += 32) { 1399 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG); 1400 1401 if (!reg) { 1402 dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base); 1403 continue; 1404 } 1405 1406 raw_spin_lock(&byt_lock); 1407 pending = readl(reg); 1408 raw_spin_unlock(&byt_lock); 1409 for_each_set_bit(pin, &pending, 32) 1410 generic_handle_domain_irq(vg->chip.irq.domain, base + pin); 1411 } 1412 chip->irq_eoi(data); 1413 } 1414 1415 static bool byt_direct_irq_sanity_check(struct intel_pinctrl *vg, int pin, u32 conf0) 1416 { 1417 int direct_irq, ioapic_direct_irq_base; 1418 u8 *match, direct_irq_mux[16]; 1419 u32 trig; 1420 1421 memcpy_fromio(direct_irq_mux, vg->communities->pad_regs + BYT_DIRECT_IRQ_REG, 1422 sizeof(direct_irq_mux)); 1423 match = memchr(direct_irq_mux, pin, sizeof(direct_irq_mux)); 1424 if (!match) { 1425 dev_warn(vg->dev, FW_BUG "Pin %i: DIRECT_IRQ_EN set but no IRQ assigned, clearing\n", pin); 1426 return false; 1427 } 1428 1429 direct_irq = match - direct_irq_mux; 1430 /* Base IO-APIC pin numbers come from atom-e3800-family-datasheet.pdf */ 1431 ioapic_direct_irq_base = (vg->communities->npins == BYT_NGPIO_SCORE) ? 51 : 67; 1432 dev_dbg(vg->dev, "Pin %i: uses direct IRQ %d (IO-APIC %d)\n", pin, 1433 direct_irq, direct_irq + ioapic_direct_irq_base); 1434 1435 /* 1436 * Testing has shown that the way direct IRQs work is that the combination of the 1437 * direct-irq-en flag and the direct IRQ mux connect the output of the GPIO's IRQ 1438 * trigger block, which normally sets the status flag in the IRQ status reg at 1439 * 0x800, to one of the IO-APIC pins according to the mux registers. 1440 * 1441 * This means that: 1442 * 1. The TRIG_MASK bits must be set to configure the GPIO's IRQ trigger block 1443 * 2. The TRIG_LVL bit *must* be set, so that the GPIO's input value is directly 1444 * passed (1:1 or inverted) to the IO-APIC pin, if TRIG_LVL is not set, 1445 * selecting edge mode operation then on the first edge the IO-APIC pin goes 1446 * high, but since no write-to-clear write will be done to the IRQ status reg 1447 * at 0x800, the detected edge condition will never get cleared. 1448 */ 1449 trig = conf0 & BYT_TRIG_MASK; 1450 if (trig != (BYT_TRIG_POS | BYT_TRIG_LVL) && 1451 trig != (BYT_TRIG_NEG | BYT_TRIG_LVL)) { 1452 dev_warn(vg->dev, 1453 FW_BUG "Pin %i: DIRECT_IRQ_EN set without trigger (CONF0: %#08x), clearing\n", 1454 pin, conf0); 1455 return false; 1456 } 1457 1458 return true; 1459 } 1460 1461 static void byt_init_irq_valid_mask(struct gpio_chip *chip, 1462 unsigned long *valid_mask, 1463 unsigned int ngpios) 1464 { 1465 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1466 void __iomem *reg; 1467 u32 value; 1468 int i; 1469 1470 /* 1471 * Clear interrupt triggers for all pins that are GPIOs and 1472 * do not use direct IRQ mode. This will prevent spurious 1473 * interrupts from misconfigured pins. 1474 */ 1475 for (i = 0; i < vg->soc->npins; i++) { 1476 unsigned int pin = vg->soc->pins[i].number; 1477 1478 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1479 if (!reg) { 1480 dev_warn(vg->dev, "Pin %i: could not retrieve CONF0\n", i); 1481 continue; 1482 } 1483 1484 value = readl(reg); 1485 if (value & BYT_DIRECT_IRQ_EN) { 1486 if (byt_direct_irq_sanity_check(vg, i, value)) { 1487 clear_bit(i, valid_mask); 1488 } else { 1489 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | 1490 BYT_TRIG_NEG | BYT_TRIG_LVL); 1491 writel(value, reg); 1492 } 1493 } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) { 1494 byt_gpio_clear_triggering(vg, i); 1495 dev_dbg(vg->dev, "disabling GPIO %d\n", i); 1496 } 1497 } 1498 } 1499 1500 static int byt_gpio_irq_init_hw(struct gpio_chip *chip) 1501 { 1502 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1503 void __iomem *reg; 1504 u32 base, value; 1505 1506 /* clear interrupt status trigger registers */ 1507 for (base = 0; base < vg->soc->npins; base += 32) { 1508 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG); 1509 1510 if (!reg) { 1511 dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base); 1512 continue; 1513 } 1514 1515 writel(0xffffffff, reg); 1516 /* make sure trigger bits are cleared, if not then a pin 1517 might be misconfigured in bios */ 1518 value = readl(reg); 1519 if (value) 1520 dev_err(vg->dev, 1521 "GPIO interrupt error, pins misconfigured. INT_STAT%u: %#08x\n", 1522 base / 32, value); 1523 } 1524 1525 return 0; 1526 } 1527 1528 static int byt_gpio_add_pin_ranges(struct gpio_chip *chip) 1529 { 1530 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1531 struct device *dev = vg->dev; 1532 int ret; 1533 1534 ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins); 1535 if (ret) 1536 dev_err(dev, "failed to add GPIO pin range\n"); 1537 1538 return ret; 1539 } 1540 1541 static int byt_gpio_probe(struct intel_pinctrl *vg) 1542 { 1543 struct platform_device *pdev = to_platform_device(vg->dev); 1544 struct gpio_chip *gc; 1545 int irq, ret; 1546 1547 /* Set up gpio chip */ 1548 vg->chip = byt_gpio_chip; 1549 gc = &vg->chip; 1550 gc->label = dev_name(vg->dev); 1551 gc->base = -1; 1552 gc->can_sleep = false; 1553 gc->add_pin_ranges = byt_gpio_add_pin_ranges; 1554 gc->parent = vg->dev; 1555 gc->ngpio = vg->soc->npins; 1556 1557 #ifdef CONFIG_PM_SLEEP 1558 vg->context.pads = devm_kcalloc(vg->dev, gc->ngpio, sizeof(*vg->context.pads), 1559 GFP_KERNEL); 1560 if (!vg->context.pads) 1561 return -ENOMEM; 1562 #endif 1563 1564 /* set up interrupts */ 1565 irq = platform_get_irq_optional(pdev, 0); 1566 if (irq > 0) { 1567 struct gpio_irq_chip *girq; 1568 1569 girq = &gc->irq; 1570 gpio_irq_chip_set_chip(girq, &byt_gpio_irq_chip); 1571 girq->init_hw = byt_gpio_irq_init_hw; 1572 girq->init_valid_mask = byt_init_irq_valid_mask; 1573 girq->parent_handler = byt_gpio_irq_handler; 1574 girq->num_parents = 1; 1575 girq->parents = devm_kcalloc(vg->dev, girq->num_parents, 1576 sizeof(*girq->parents), GFP_KERNEL); 1577 if (!girq->parents) 1578 return -ENOMEM; 1579 girq->parents[0] = irq; 1580 girq->default_type = IRQ_TYPE_NONE; 1581 girq->handler = handle_bad_irq; 1582 } 1583 1584 ret = devm_gpiochip_add_data(vg->dev, gc, vg); 1585 if (ret) { 1586 dev_err(vg->dev, "failed adding byt-gpio chip\n"); 1587 return ret; 1588 } 1589 1590 return ret; 1591 } 1592 1593 static int byt_set_soc_data(struct intel_pinctrl *vg, 1594 const struct intel_pinctrl_soc_data *soc) 1595 { 1596 struct platform_device *pdev = to_platform_device(vg->dev); 1597 int i; 1598 1599 vg->soc = soc; 1600 1601 vg->ncommunities = vg->soc->ncommunities; 1602 vg->communities = devm_kcalloc(vg->dev, vg->ncommunities, 1603 sizeof(*vg->communities), GFP_KERNEL); 1604 if (!vg->communities) 1605 return -ENOMEM; 1606 1607 for (i = 0; i < vg->soc->ncommunities; i++) { 1608 struct intel_community *comm = vg->communities + i; 1609 1610 *comm = vg->soc->communities[i]; 1611 1612 comm->pad_regs = devm_platform_ioremap_resource(pdev, 0); 1613 if (IS_ERR(comm->pad_regs)) 1614 return PTR_ERR(comm->pad_regs); 1615 } 1616 1617 return 0; 1618 } 1619 1620 static const struct acpi_device_id byt_gpio_acpi_match[] = { 1621 { "INT33B2", (kernel_ulong_t)byt_soc_data }, 1622 { "INT33FC", (kernel_ulong_t)byt_soc_data }, 1623 { } 1624 }; 1625 1626 static int byt_pinctrl_probe(struct platform_device *pdev) 1627 { 1628 const struct intel_pinctrl_soc_data *soc_data; 1629 struct device *dev = &pdev->dev; 1630 struct intel_pinctrl *vg; 1631 int ret; 1632 1633 soc_data = intel_pinctrl_get_soc_data(pdev); 1634 if (IS_ERR(soc_data)) 1635 return PTR_ERR(soc_data); 1636 1637 vg = devm_kzalloc(dev, sizeof(*vg), GFP_KERNEL); 1638 if (!vg) 1639 return -ENOMEM; 1640 1641 vg->dev = dev; 1642 ret = byt_set_soc_data(vg, soc_data); 1643 if (ret) { 1644 dev_err(dev, "failed to set soc data\n"); 1645 return ret; 1646 } 1647 1648 vg->pctldesc = byt_pinctrl_desc; 1649 vg->pctldesc.name = dev_name(dev); 1650 vg->pctldesc.pins = vg->soc->pins; 1651 vg->pctldesc.npins = vg->soc->npins; 1652 1653 vg->pctldev = devm_pinctrl_register(dev, &vg->pctldesc, vg); 1654 if (IS_ERR(vg->pctldev)) { 1655 dev_err(dev, "failed to register pinctrl driver\n"); 1656 return PTR_ERR(vg->pctldev); 1657 } 1658 1659 ret = byt_gpio_probe(vg); 1660 if (ret) 1661 return ret; 1662 1663 platform_set_drvdata(pdev, vg); 1664 pm_runtime_enable(dev); 1665 1666 return 0; 1667 } 1668 1669 static int byt_gpio_suspend(struct device *dev) 1670 { 1671 struct intel_pinctrl *vg = dev_get_drvdata(dev); 1672 unsigned long flags; 1673 int i; 1674 1675 raw_spin_lock_irqsave(&byt_lock, flags); 1676 1677 for (i = 0; i < vg->soc->npins; i++) { 1678 void __iomem *reg; 1679 u32 value; 1680 unsigned int pin = vg->soc->pins[i].number; 1681 1682 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1683 if (!reg) { 1684 dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i); 1685 continue; 1686 } 1687 value = readl(reg) & BYT_CONF0_RESTORE_MASK; 1688 vg->context.pads[i].conf0 = value; 1689 1690 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); 1691 if (!reg) { 1692 dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n", i); 1693 continue; 1694 } 1695 value = readl(reg) & BYT_VAL_RESTORE_MASK; 1696 vg->context.pads[i].val = value; 1697 } 1698 1699 raw_spin_unlock_irqrestore(&byt_lock, flags); 1700 return 0; 1701 } 1702 1703 static int byt_gpio_resume(struct device *dev) 1704 { 1705 struct intel_pinctrl *vg = dev_get_drvdata(dev); 1706 unsigned long flags; 1707 int i; 1708 1709 raw_spin_lock_irqsave(&byt_lock, flags); 1710 1711 for (i = 0; i < vg->soc->npins; i++) { 1712 void __iomem *reg; 1713 u32 value; 1714 unsigned int pin = vg->soc->pins[i].number; 1715 1716 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1717 if (!reg) { 1718 dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i); 1719 continue; 1720 } 1721 value = readl(reg); 1722 if ((value & BYT_CONF0_RESTORE_MASK) != 1723 vg->context.pads[i].conf0) { 1724 value &= ~BYT_CONF0_RESTORE_MASK; 1725 value |= vg->context.pads[i].conf0; 1726 writel(value, reg); 1727 dev_info(dev, "restored pin %d CONF0 %#08x", i, value); 1728 } 1729 1730 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); 1731 if (!reg) { 1732 dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n", i); 1733 continue; 1734 } 1735 value = readl(reg); 1736 if ((value & BYT_VAL_RESTORE_MASK) != 1737 vg->context.pads[i].val) { 1738 u32 v; 1739 1740 v = value & ~BYT_VAL_RESTORE_MASK; 1741 v |= vg->context.pads[i].val; 1742 if (v != value) { 1743 writel(v, reg); 1744 dev_dbg(dev, "restored pin %d VAL %#08x\n", i, v); 1745 } 1746 } 1747 } 1748 1749 raw_spin_unlock_irqrestore(&byt_lock, flags); 1750 return 0; 1751 } 1752 1753 static int byt_gpio_runtime_suspend(struct device *dev) 1754 { 1755 return 0; 1756 } 1757 1758 static int byt_gpio_runtime_resume(struct device *dev) 1759 { 1760 return 0; 1761 } 1762 1763 static const struct dev_pm_ops byt_gpio_pm_ops = { 1764 LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume) 1765 RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume, NULL) 1766 }; 1767 1768 static struct platform_driver byt_gpio_driver = { 1769 .probe = byt_pinctrl_probe, 1770 .driver = { 1771 .name = "byt_gpio", 1772 .pm = pm_ptr(&byt_gpio_pm_ops), 1773 .acpi_match_table = byt_gpio_acpi_match, 1774 .suppress_bind_attrs = true, 1775 }, 1776 }; 1777 1778 static int __init byt_gpio_init(void) 1779 { 1780 return platform_driver_register(&byt_gpio_driver); 1781 } 1782 subsys_initcall(byt_gpio_init); 1783 1784 MODULE_IMPORT_NS(PINCTRL_INTEL); 1785