1 /* 2 * Pinctrl GPIO driver for Intel Baytrail 3 * Copyright (c) 2012-2013, Intel Corporation. 4 * 5 * Author: Mathias Nyman <mathias.nyman@linux.intel.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 */ 16 17 #include <linux/kernel.h> 18 #include <linux/init.h> 19 #include <linux/types.h> 20 #include <linux/bitops.h> 21 #include <linux/interrupt.h> 22 #include <linux/gpio.h> 23 #include <linux/gpio/driver.h> 24 #include <linux/acpi.h> 25 #include <linux/platform_device.h> 26 #include <linux/seq_file.h> 27 #include <linux/io.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/pinctrl/pinctrl.h> 30 #include <linux/pinctrl/pinmux.h> 31 #include <linux/pinctrl/pinconf.h> 32 #include <linux/pinctrl/pinconf-generic.h> 33 34 /* memory mapped register offsets */ 35 #define BYT_CONF0_REG 0x000 36 #define BYT_CONF1_REG 0x004 37 #define BYT_VAL_REG 0x008 38 #define BYT_DFT_REG 0x00c 39 #define BYT_INT_STAT_REG 0x800 40 #define BYT_DEBOUNCE_REG 0x9d0 41 42 /* BYT_CONF0_REG register bits */ 43 #define BYT_IODEN BIT(31) 44 #define BYT_DIRECT_IRQ_EN BIT(27) 45 #define BYT_TRIG_NEG BIT(26) 46 #define BYT_TRIG_POS BIT(25) 47 #define BYT_TRIG_LVL BIT(24) 48 #define BYT_DEBOUNCE_EN BIT(20) 49 #define BYT_GLITCH_FILTER_EN BIT(19) 50 #define BYT_GLITCH_F_SLOW_CLK BIT(17) 51 #define BYT_GLITCH_F_FAST_CLK BIT(16) 52 #define BYT_PULL_STR_SHIFT 9 53 #define BYT_PULL_STR_MASK (3 << BYT_PULL_STR_SHIFT) 54 #define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT) 55 #define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT) 56 #define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT) 57 #define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT) 58 #define BYT_PULL_ASSIGN_SHIFT 7 59 #define BYT_PULL_ASSIGN_MASK (3 << BYT_PULL_ASSIGN_SHIFT) 60 #define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT) 61 #define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT) 62 #define BYT_PIN_MUX 0x07 63 64 /* BYT_VAL_REG register bits */ 65 #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/ 66 #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/ 67 #define BYT_LEVEL BIT(0) 68 69 #define BYT_DIR_MASK (BIT(1) | BIT(2)) 70 #define BYT_TRIG_MASK (BIT(26) | BIT(25) | BIT(24)) 71 72 #define BYT_CONF0_RESTORE_MASK (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | \ 73 BYT_PIN_MUX) 74 #define BYT_VAL_RESTORE_MASK (BYT_DIR_MASK | BYT_LEVEL) 75 76 /* BYT_DEBOUNCE_REG bits */ 77 #define BYT_DEBOUNCE_PULSE_MASK 0x7 78 #define BYT_DEBOUNCE_PULSE_375US 1 79 #define BYT_DEBOUNCE_PULSE_750US 2 80 #define BYT_DEBOUNCE_PULSE_1500US 3 81 #define BYT_DEBOUNCE_PULSE_3MS 4 82 #define BYT_DEBOUNCE_PULSE_6MS 5 83 #define BYT_DEBOUNCE_PULSE_12MS 6 84 #define BYT_DEBOUNCE_PULSE_24MS 7 85 86 #define BYT_NGPIO_SCORE 102 87 #define BYT_NGPIO_NCORE 28 88 #define BYT_NGPIO_SUS 44 89 90 #define BYT_SCORE_ACPI_UID "1" 91 #define BYT_NCORE_ACPI_UID "2" 92 #define BYT_SUS_ACPI_UID "3" 93 94 /* 95 * This is the function value most pins have for GPIO muxing. If the value 96 * differs from the default one, it must be explicitly mentioned. Otherwise, the 97 * pin control implementation will set the muxing value to default GPIO if it 98 * does not find a match for the requested function. 99 */ 100 #define BYT_DEFAULT_GPIO_MUX 0 101 102 struct byt_gpio_pin_context { 103 u32 conf0; 104 u32 val; 105 }; 106 107 struct byt_simple_func_mux { 108 const char *name; 109 unsigned short func; 110 }; 111 112 struct byt_mixed_func_mux { 113 const char *name; 114 const unsigned short *func_values; 115 }; 116 117 struct byt_pingroup { 118 const char *name; 119 const unsigned int *pins; 120 size_t npins; 121 unsigned short has_simple_funcs; 122 union { 123 const struct byt_simple_func_mux *simple_funcs; 124 const struct byt_mixed_func_mux *mixed_funcs; 125 }; 126 size_t nfuncs; 127 }; 128 129 struct byt_function { 130 const char *name; 131 const char * const *groups; 132 size_t ngroups; 133 }; 134 135 struct byt_community { 136 unsigned int pin_base; 137 size_t npins; 138 const unsigned int *pad_map; 139 void __iomem *reg_base; 140 }; 141 142 #define SIMPLE_FUNC(n, f) \ 143 { \ 144 .name = (n), \ 145 .func = (f), \ 146 } 147 #define MIXED_FUNC(n, f) \ 148 { \ 149 .name = (n), \ 150 .func_values = (f), \ 151 } 152 153 #define PIN_GROUP_SIMPLE(n, p, f) \ 154 { \ 155 .name = (n), \ 156 .pins = (p), \ 157 .npins = ARRAY_SIZE((p)), \ 158 .has_simple_funcs = 1, \ 159 { \ 160 .simple_funcs = (f), \ 161 }, \ 162 .nfuncs = ARRAY_SIZE((f)), \ 163 } 164 #define PIN_GROUP_MIXED(n, p, f) \ 165 { \ 166 .name = (n), \ 167 .pins = (p), \ 168 .npins = ARRAY_SIZE((p)), \ 169 .has_simple_funcs = 0, \ 170 { \ 171 .mixed_funcs = (f), \ 172 }, \ 173 .nfuncs = ARRAY_SIZE((f)), \ 174 } 175 176 #define FUNCTION(n, g) \ 177 { \ 178 .name = (n), \ 179 .groups = (g), \ 180 .ngroups = ARRAY_SIZE((g)), \ 181 } 182 183 #define COMMUNITY(p, n, map) \ 184 { \ 185 .pin_base = (p), \ 186 .npins = (n), \ 187 .pad_map = (map),\ 188 } 189 190 struct byt_pinctrl_soc_data { 191 const char *uid; 192 const struct pinctrl_pin_desc *pins; 193 size_t npins; 194 const struct byt_pingroup *groups; 195 size_t ngroups; 196 const struct byt_function *functions; 197 size_t nfunctions; 198 const struct byt_community *communities; 199 size_t ncommunities; 200 }; 201 202 struct byt_gpio { 203 struct gpio_chip chip; 204 struct platform_device *pdev; 205 struct pinctrl_dev *pctl_dev; 206 struct pinctrl_desc pctl_desc; 207 raw_spinlock_t lock; 208 const struct byt_pinctrl_soc_data *soc_data; 209 struct byt_community *communities_copy; 210 struct byt_gpio_pin_context *saved_context; 211 }; 212 213 /* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */ 214 static const struct pinctrl_pin_desc byt_score_pins[] = { 215 PINCTRL_PIN(0, "SATA_GP0"), 216 PINCTRL_PIN(1, "SATA_GP1"), 217 PINCTRL_PIN(2, "SATA_LED#"), 218 PINCTRL_PIN(3, "PCIE_CLKREQ0"), 219 PINCTRL_PIN(4, "PCIE_CLKREQ1"), 220 PINCTRL_PIN(5, "PCIE_CLKREQ2"), 221 PINCTRL_PIN(6, "PCIE_CLKREQ3"), 222 PINCTRL_PIN(7, "SD3_WP"), 223 PINCTRL_PIN(8, "HDA_RST"), 224 PINCTRL_PIN(9, "HDA_SYNC"), 225 PINCTRL_PIN(10, "HDA_CLK"), 226 PINCTRL_PIN(11, "HDA_SDO"), 227 PINCTRL_PIN(12, "HDA_SDI0"), 228 PINCTRL_PIN(13, "HDA_SDI1"), 229 PINCTRL_PIN(14, "GPIO_S0_SC14"), 230 PINCTRL_PIN(15, "GPIO_S0_SC15"), 231 PINCTRL_PIN(16, "MMC1_CLK"), 232 PINCTRL_PIN(17, "MMC1_D0"), 233 PINCTRL_PIN(18, "MMC1_D1"), 234 PINCTRL_PIN(19, "MMC1_D2"), 235 PINCTRL_PIN(20, "MMC1_D3"), 236 PINCTRL_PIN(21, "MMC1_D4"), 237 PINCTRL_PIN(22, "MMC1_D5"), 238 PINCTRL_PIN(23, "MMC1_D6"), 239 PINCTRL_PIN(24, "MMC1_D7"), 240 PINCTRL_PIN(25, "MMC1_CMD"), 241 PINCTRL_PIN(26, "MMC1_RST"), 242 PINCTRL_PIN(27, "SD2_CLK"), 243 PINCTRL_PIN(28, "SD2_D0"), 244 PINCTRL_PIN(29, "SD2_D1"), 245 PINCTRL_PIN(30, "SD2_D2"), 246 PINCTRL_PIN(31, "SD2_D3_CD"), 247 PINCTRL_PIN(32, "SD2_CMD"), 248 PINCTRL_PIN(33, "SD3_CLK"), 249 PINCTRL_PIN(34, "SD3_D0"), 250 PINCTRL_PIN(35, "SD3_D1"), 251 PINCTRL_PIN(36, "SD3_D2"), 252 PINCTRL_PIN(37, "SD3_D3"), 253 PINCTRL_PIN(38, "SD3_CD"), 254 PINCTRL_PIN(39, "SD3_CMD"), 255 PINCTRL_PIN(40, "SD3_1P8EN"), 256 PINCTRL_PIN(41, "SD3_PWREN#"), 257 PINCTRL_PIN(42, "ILB_LPC_AD0"), 258 PINCTRL_PIN(43, "ILB_LPC_AD1"), 259 PINCTRL_PIN(44, "ILB_LPC_AD2"), 260 PINCTRL_PIN(45, "ILB_LPC_AD3"), 261 PINCTRL_PIN(46, "ILB_LPC_FRAME"), 262 PINCTRL_PIN(47, "ILB_LPC_CLK0"), 263 PINCTRL_PIN(48, "ILB_LPC_CLK1"), 264 PINCTRL_PIN(49, "ILB_LPC_CLKRUN"), 265 PINCTRL_PIN(50, "ILB_LPC_SERIRQ"), 266 PINCTRL_PIN(51, "PCU_SMB_DATA"), 267 PINCTRL_PIN(52, "PCU_SMB_CLK"), 268 PINCTRL_PIN(53, "PCU_SMB_ALERT"), 269 PINCTRL_PIN(54, "ILB_8254_SPKR"), 270 PINCTRL_PIN(55, "GPIO_S0_SC55"), 271 PINCTRL_PIN(56, "GPIO_S0_SC56"), 272 PINCTRL_PIN(57, "GPIO_S0_SC57"), 273 PINCTRL_PIN(58, "GPIO_S0_SC58"), 274 PINCTRL_PIN(59, "GPIO_S0_SC59"), 275 PINCTRL_PIN(60, "GPIO_S0_SC60"), 276 PINCTRL_PIN(61, "GPIO_S0_SC61"), 277 PINCTRL_PIN(62, "LPE_I2S2_CLK"), 278 PINCTRL_PIN(63, "LPE_I2S2_FRM"), 279 PINCTRL_PIN(64, "LPE_I2S2_DATAIN"), 280 PINCTRL_PIN(65, "LPE_I2S2_DATAOUT"), 281 PINCTRL_PIN(66, "SIO_SPI_CS"), 282 PINCTRL_PIN(67, "SIO_SPI_MISO"), 283 PINCTRL_PIN(68, "SIO_SPI_MOSI"), 284 PINCTRL_PIN(69, "SIO_SPI_CLK"), 285 PINCTRL_PIN(70, "SIO_UART1_RXD"), 286 PINCTRL_PIN(71, "SIO_UART1_TXD"), 287 PINCTRL_PIN(72, "SIO_UART1_RTS"), 288 PINCTRL_PIN(73, "SIO_UART1_CTS"), 289 PINCTRL_PIN(74, "SIO_UART2_RXD"), 290 PINCTRL_PIN(75, "SIO_UART2_TXD"), 291 PINCTRL_PIN(76, "SIO_UART2_RTS"), 292 PINCTRL_PIN(77, "SIO_UART2_CTS"), 293 PINCTRL_PIN(78, "SIO_I2C0_DATA"), 294 PINCTRL_PIN(79, "SIO_I2C0_CLK"), 295 PINCTRL_PIN(80, "SIO_I2C1_DATA"), 296 PINCTRL_PIN(81, "SIO_I2C1_CLK"), 297 PINCTRL_PIN(82, "SIO_I2C2_DATA"), 298 PINCTRL_PIN(83, "SIO_I2C2_CLK"), 299 PINCTRL_PIN(84, "SIO_I2C3_DATA"), 300 PINCTRL_PIN(85, "SIO_I2C3_CLK"), 301 PINCTRL_PIN(86, "SIO_I2C4_DATA"), 302 PINCTRL_PIN(87, "SIO_I2C4_CLK"), 303 PINCTRL_PIN(88, "SIO_I2C5_DATA"), 304 PINCTRL_PIN(89, "SIO_I2C5_CLK"), 305 PINCTRL_PIN(90, "SIO_I2C6_DATA"), 306 PINCTRL_PIN(91, "SIO_I2C6_CLK"), 307 PINCTRL_PIN(92, "GPIO_S0_SC92"), 308 PINCTRL_PIN(93, "GPIO_S0_SC93"), 309 PINCTRL_PIN(94, "SIO_PWM0"), 310 PINCTRL_PIN(95, "SIO_PWM1"), 311 PINCTRL_PIN(96, "PMC_PLT_CLK0"), 312 PINCTRL_PIN(97, "PMC_PLT_CLK1"), 313 PINCTRL_PIN(98, "PMC_PLT_CLK2"), 314 PINCTRL_PIN(99, "PMC_PLT_CLK3"), 315 PINCTRL_PIN(100, "PMC_PLT_CLK4"), 316 PINCTRL_PIN(101, "PMC_PLT_CLK5"), 317 }; 318 319 static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = { 320 85, 89, 93, 96, 99, 102, 98, 101, 34, 37, 321 36, 38, 39, 35, 40, 84, 62, 61, 64, 59, 322 54, 56, 60, 55, 63, 57, 51, 50, 53, 47, 323 52, 49, 48, 43, 46, 41, 45, 42, 58, 44, 324 95, 105, 70, 68, 67, 66, 69, 71, 65, 72, 325 86, 90, 88, 92, 103, 77, 79, 83, 78, 81, 326 80, 82, 13, 12, 15, 14, 17, 18, 19, 16, 327 2, 1, 0, 4, 6, 7, 9, 8, 33, 32, 328 31, 30, 29, 27, 25, 28, 26, 23, 21, 20, 329 24, 22, 5, 3, 10, 11, 106, 87, 91, 104, 330 97, 100, 331 }; 332 333 /* SCORE groups */ 334 static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 }; 335 static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 }; 336 static const struct byt_simple_func_mux byt_score_uart_mux[] = { 337 SIMPLE_FUNC("uart", 1), 338 }; 339 340 static const unsigned int byt_score_pwm0_pins[] = { 94 }; 341 static const unsigned int byt_score_pwm1_pins[] = { 95 }; 342 static const struct byt_simple_func_mux byt_score_pwm_mux[] = { 343 SIMPLE_FUNC("pwm", 1), 344 }; 345 346 static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 }; 347 static const struct byt_simple_func_mux byt_score_spi_mux[] = { 348 SIMPLE_FUNC("spi", 1), 349 }; 350 351 static const unsigned int byt_score_i2c5_pins[] = { 88, 89 }; 352 static const unsigned int byt_score_i2c6_pins[] = { 90, 91 }; 353 static const unsigned int byt_score_i2c4_pins[] = { 86, 87 }; 354 static const unsigned int byt_score_i2c3_pins[] = { 84, 85 }; 355 static const unsigned int byt_score_i2c2_pins[] = { 82, 83 }; 356 static const unsigned int byt_score_i2c1_pins[] = { 80, 81 }; 357 static const unsigned int byt_score_i2c0_pins[] = { 78, 79 }; 358 static const struct byt_simple_func_mux byt_score_i2c_mux[] = { 359 SIMPLE_FUNC("i2c", 1), 360 }; 361 362 static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 }; 363 static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 }; 364 static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 }; 365 static const struct byt_simple_func_mux byt_score_ssp_mux[] = { 366 SIMPLE_FUNC("ssp", 1), 367 }; 368 369 static const unsigned int byt_score_sdcard_pins[] = { 370 7, 33, 34, 35, 36, 37, 38, 39, 40, 41, 371 }; 372 static const unsigned short byt_score_sdcard_mux_values[] = { 373 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 374 }; 375 static const struct byt_mixed_func_mux byt_score_sdcard_mux[] = { 376 MIXED_FUNC("sdcard", byt_score_sdcard_mux_values), 377 }; 378 379 static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 }; 380 static const struct byt_simple_func_mux byt_score_sdio_mux[] = { 381 SIMPLE_FUNC("sdio", 1), 382 }; 383 384 static const unsigned int byt_score_emmc_pins[] = { 385 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 386 }; 387 static const struct byt_simple_func_mux byt_score_emmc_mux[] = { 388 SIMPLE_FUNC("emmc", 1), 389 }; 390 391 static const unsigned int byt_score_ilb_lpc_pins[] = { 392 42, 43, 44, 45, 46, 47, 48, 49, 50, 393 }; 394 static const struct byt_simple_func_mux byt_score_lpc_mux[] = { 395 SIMPLE_FUNC("lpc", 1), 396 }; 397 398 static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 }; 399 static const struct byt_simple_func_mux byt_score_sata_mux[] = { 400 SIMPLE_FUNC("sata", 1), 401 }; 402 403 static const unsigned int byt_score_plt_clk0_pins[] = { 96 }; 404 static const unsigned int byt_score_plt_clk1_pins[] = { 97 }; 405 static const unsigned int byt_score_plt_clk2_pins[] = { 98 }; 406 static const unsigned int byt_score_plt_clk3_pins[] = { 99 }; 407 static const unsigned int byt_score_plt_clk4_pins[] = { 100 }; 408 static const unsigned int byt_score_plt_clk5_pins[] = { 101 }; 409 static const struct byt_simple_func_mux byt_score_plt_clk_mux[] = { 410 SIMPLE_FUNC("plt_clk", 1), 411 }; 412 413 static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 }; 414 static const struct byt_simple_func_mux byt_score_smbus_mux[] = { 415 SIMPLE_FUNC("smbus", 1), 416 }; 417 418 static const struct byt_pingroup byt_score_groups[] = { 419 PIN_GROUP_SIMPLE("uart1_grp", 420 byt_score_uart1_pins, byt_score_uart_mux), 421 PIN_GROUP_SIMPLE("uart2_grp", 422 byt_score_uart2_pins, byt_score_uart_mux), 423 PIN_GROUP_SIMPLE("pwm0_grp", 424 byt_score_pwm0_pins, byt_score_pwm_mux), 425 PIN_GROUP_SIMPLE("pwm1_grp", 426 byt_score_pwm1_pins, byt_score_pwm_mux), 427 PIN_GROUP_SIMPLE("ssp2_grp", 428 byt_score_ssp2_pins, byt_score_pwm_mux), 429 PIN_GROUP_SIMPLE("sio_spi_grp", 430 byt_score_sio_spi_pins, byt_score_spi_mux), 431 PIN_GROUP_SIMPLE("i2c5_grp", 432 byt_score_i2c5_pins, byt_score_i2c_mux), 433 PIN_GROUP_SIMPLE("i2c6_grp", 434 byt_score_i2c6_pins, byt_score_i2c_mux), 435 PIN_GROUP_SIMPLE("i2c4_grp", 436 byt_score_i2c4_pins, byt_score_i2c_mux), 437 PIN_GROUP_SIMPLE("i2c3_grp", 438 byt_score_i2c3_pins, byt_score_i2c_mux), 439 PIN_GROUP_SIMPLE("i2c2_grp", 440 byt_score_i2c2_pins, byt_score_i2c_mux), 441 PIN_GROUP_SIMPLE("i2c1_grp", 442 byt_score_i2c1_pins, byt_score_i2c_mux), 443 PIN_GROUP_SIMPLE("i2c0_grp", 444 byt_score_i2c0_pins, byt_score_i2c_mux), 445 PIN_GROUP_SIMPLE("ssp0_grp", 446 byt_score_ssp0_pins, byt_score_ssp_mux), 447 PIN_GROUP_SIMPLE("ssp1_grp", 448 byt_score_ssp1_pins, byt_score_ssp_mux), 449 PIN_GROUP_MIXED("sdcard_grp", 450 byt_score_sdcard_pins, byt_score_sdcard_mux), 451 PIN_GROUP_SIMPLE("sdio_grp", 452 byt_score_sdio_pins, byt_score_sdio_mux), 453 PIN_GROUP_SIMPLE("emmc_grp", 454 byt_score_emmc_pins, byt_score_emmc_mux), 455 PIN_GROUP_SIMPLE("lpc_grp", 456 byt_score_ilb_lpc_pins, byt_score_lpc_mux), 457 PIN_GROUP_SIMPLE("sata_grp", 458 byt_score_sata_pins, byt_score_sata_mux), 459 PIN_GROUP_SIMPLE("plt_clk0_grp", 460 byt_score_plt_clk0_pins, byt_score_plt_clk_mux), 461 PIN_GROUP_SIMPLE("plt_clk1_grp", 462 byt_score_plt_clk1_pins, byt_score_plt_clk_mux), 463 PIN_GROUP_SIMPLE("plt_clk2_grp", 464 byt_score_plt_clk2_pins, byt_score_plt_clk_mux), 465 PIN_GROUP_SIMPLE("plt_clk3_grp", 466 byt_score_plt_clk3_pins, byt_score_plt_clk_mux), 467 PIN_GROUP_SIMPLE("plt_clk4_grp", 468 byt_score_plt_clk4_pins, byt_score_plt_clk_mux), 469 PIN_GROUP_SIMPLE("plt_clk5_grp", 470 byt_score_plt_clk5_pins, byt_score_plt_clk_mux), 471 PIN_GROUP_SIMPLE("smbus_grp", 472 byt_score_smbus_pins, byt_score_smbus_mux), 473 }; 474 475 static const char * const byt_score_uart_groups[] = { 476 "uart1_grp", "uart2_grp", 477 }; 478 static const char * const byt_score_pwm_groups[] = { 479 "pwm0_grp", "pwm1_grp", 480 }; 481 static const char * const byt_score_ssp_groups[] = { 482 "ssp0_grp", "ssp1_grp", "ssp2_grp", 483 }; 484 static const char * const byt_score_spi_groups[] = { "sio_spi_grp" }; 485 static const char * const byt_score_i2c_groups[] = { 486 "i2c0_grp", "i2c1_grp", "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", 487 "i2c6_grp", 488 }; 489 static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" }; 490 static const char * const byt_score_sdio_groups[] = { "sdio_grp" }; 491 static const char * const byt_score_emmc_groups[] = { "emmc_grp" }; 492 static const char * const byt_score_lpc_groups[] = { "lpc_grp" }; 493 static const char * const byt_score_sata_groups[] = { "sata_grp" }; 494 static const char * const byt_score_plt_clk_groups[] = { 495 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp", 496 "plt_clk4_grp", "plt_clk5_grp", 497 }; 498 static const char * const byt_score_smbus_groups[] = { "smbus_grp" }; 499 static const char * const byt_score_gpio_groups[] = { 500 "uart1_grp", "uart2_grp", "pwm0_grp", "pwm1_grp", "ssp0_grp", 501 "ssp1_grp", "ssp2_grp", "sio_spi_grp", "i2c0_grp", "i2c1_grp", 502 "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", "i2c6_grp", 503 "sdcard_grp", "sdio_grp", "emmc_grp", "lpc_grp", "sata_grp", 504 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp", 505 "plt_clk4_grp", "plt_clk5_grp", "smbus_grp", 506 507 }; 508 509 static const struct byt_function byt_score_functions[] = { 510 FUNCTION("uart", byt_score_uart_groups), 511 FUNCTION("pwm", byt_score_pwm_groups), 512 FUNCTION("ssp", byt_score_ssp_groups), 513 FUNCTION("spi", byt_score_spi_groups), 514 FUNCTION("i2c", byt_score_i2c_groups), 515 FUNCTION("sdcard", byt_score_sdcard_groups), 516 FUNCTION("sdio", byt_score_sdio_groups), 517 FUNCTION("emmc", byt_score_emmc_groups), 518 FUNCTION("lpc", byt_score_lpc_groups), 519 FUNCTION("sata", byt_score_sata_groups), 520 FUNCTION("plt_clk", byt_score_plt_clk_groups), 521 FUNCTION("smbus", byt_score_smbus_groups), 522 FUNCTION("gpio", byt_score_gpio_groups), 523 }; 524 525 static const struct byt_community byt_score_communities[] = { 526 COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map), 527 }; 528 529 static const struct byt_pinctrl_soc_data byt_score_soc_data = { 530 .uid = BYT_SCORE_ACPI_UID, 531 .pins = byt_score_pins, 532 .npins = ARRAY_SIZE(byt_score_pins), 533 .groups = byt_score_groups, 534 .ngroups = ARRAY_SIZE(byt_score_groups), 535 .functions = byt_score_functions, 536 .nfunctions = ARRAY_SIZE(byt_score_functions), 537 .communities = byt_score_communities, 538 .ncommunities = ARRAY_SIZE(byt_score_communities), 539 }; 540 541 /* SUS pins, aka GPIOS_<pin_no> or GPIO_S5[<pin_no>] */ 542 static const struct pinctrl_pin_desc byt_sus_pins[] = { 543 PINCTRL_PIN(0, "GPIO_S50"), 544 PINCTRL_PIN(1, "GPIO_S51"), 545 PINCTRL_PIN(2, "GPIO_S52"), 546 PINCTRL_PIN(3, "GPIO_S53"), 547 PINCTRL_PIN(4, "GPIO_S54"), 548 PINCTRL_PIN(5, "GPIO_S55"), 549 PINCTRL_PIN(6, "GPIO_S56"), 550 PINCTRL_PIN(7, "GPIO_S57"), 551 PINCTRL_PIN(8, "GPIO_S58"), 552 PINCTRL_PIN(9, "GPIO_S59"), 553 PINCTRL_PIN(10, "GPIO_S510"), 554 PINCTRL_PIN(11, "PMC_SUSPWRDNACK"), 555 PINCTRL_PIN(12, "PMC_SUSCLK0"), 556 PINCTRL_PIN(13, "GPIO_S513"), 557 PINCTRL_PIN(14, "USB_ULPI_RST"), 558 PINCTRL_PIN(15, "PMC_WAKE_PCIE0#"), 559 PINCTRL_PIN(16, "PMC_PWRBTN"), 560 PINCTRL_PIN(17, "GPIO_S517"), 561 PINCTRL_PIN(18, "PMC_SUS_STAT"), 562 PINCTRL_PIN(19, "USB_OC0"), 563 PINCTRL_PIN(20, "USB_OC1"), 564 PINCTRL_PIN(21, "PCU_SPI_CS1"), 565 PINCTRL_PIN(22, "GPIO_S522"), 566 PINCTRL_PIN(23, "GPIO_S523"), 567 PINCTRL_PIN(24, "GPIO_S524"), 568 PINCTRL_PIN(25, "GPIO_S525"), 569 PINCTRL_PIN(26, "GPIO_S526"), 570 PINCTRL_PIN(27, "GPIO_S527"), 571 PINCTRL_PIN(28, "GPIO_S528"), 572 PINCTRL_PIN(29, "GPIO_S529"), 573 PINCTRL_PIN(30, "GPIO_S530"), 574 PINCTRL_PIN(31, "USB_ULPI_CLK"), 575 PINCTRL_PIN(32, "USB_ULPI_DATA0"), 576 PINCTRL_PIN(33, "USB_ULPI_DATA1"), 577 PINCTRL_PIN(34, "USB_ULPI_DATA2"), 578 PINCTRL_PIN(35, "USB_ULPI_DATA3"), 579 PINCTRL_PIN(36, "USB_ULPI_DATA4"), 580 PINCTRL_PIN(37, "USB_ULPI_DATA5"), 581 PINCTRL_PIN(38, "USB_ULPI_DATA6"), 582 PINCTRL_PIN(39, "USB_ULPI_DATA7"), 583 PINCTRL_PIN(40, "USB_ULPI_DIR"), 584 PINCTRL_PIN(41, "USB_ULPI_NXT"), 585 PINCTRL_PIN(42, "USB_ULPI_STP"), 586 PINCTRL_PIN(43, "USB_ULPI_REFCLK"), 587 }; 588 589 static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = { 590 29, 33, 30, 31, 32, 34, 36, 35, 38, 37, 591 18, 7, 11, 20, 17, 1, 8, 10, 19, 12, 592 0, 2, 23, 39, 28, 27, 22, 21, 24, 25, 593 26, 51, 56, 54, 49, 55, 48, 57, 50, 58, 594 52, 53, 59, 40, 595 }; 596 597 static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 }; 598 static const struct byt_simple_func_mux byt_sus_usb_oc_mux[] = { 599 SIMPLE_FUNC("usb", 0), 600 SIMPLE_FUNC("gpio", 1), 601 }; 602 603 static const unsigned int byt_sus_usb_ulpi_pins[] = { 604 14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 605 }; 606 static const unsigned short byt_sus_usb_ulpi_mode_values[] = { 607 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 608 }; 609 static const unsigned short byt_sus_usb_ulpi_gpio_mode_values[] = { 610 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 611 }; 612 static const struct byt_mixed_func_mux byt_sus_usb_ulpi_mux[] = { 613 MIXED_FUNC("usb", byt_sus_usb_ulpi_mode_values), 614 MIXED_FUNC("gpio", byt_sus_usb_ulpi_gpio_mode_values), 615 }; 616 617 static const unsigned int byt_sus_pcu_spi_pins[] = { 21 }; 618 static const struct byt_simple_func_mux byt_sus_pcu_spi_mux[] = { 619 SIMPLE_FUNC("spi", 0), 620 SIMPLE_FUNC("gpio", 1), 621 }; 622 623 static const struct byt_pingroup byt_sus_groups[] = { 624 PIN_GROUP_SIMPLE("usb_oc_grp", 625 byt_sus_usb_over_current_pins, byt_sus_usb_oc_mux), 626 PIN_GROUP_MIXED("usb_ulpi_grp", 627 byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mux), 628 PIN_GROUP_SIMPLE("pcu_spi_grp", 629 byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mux), 630 }; 631 632 static const char * const byt_sus_usb_groups[] = { 633 "usb_oc_grp", "usb_ulpi_grp", 634 }; 635 static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" }; 636 static const char * const byt_sus_gpio_groups[] = { 637 "usb_oc_grp", "usb_ulpi_grp", "pcu_spi_grp", 638 }; 639 640 static const struct byt_function byt_sus_functions[] = { 641 FUNCTION("usb", byt_sus_usb_groups), 642 FUNCTION("spi", byt_sus_spi_groups), 643 FUNCTION("gpio", byt_sus_gpio_groups), 644 }; 645 646 static const struct byt_community byt_sus_communities[] = { 647 COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map), 648 }; 649 650 static const struct byt_pinctrl_soc_data byt_sus_soc_data = { 651 .uid = BYT_SUS_ACPI_UID, 652 .pins = byt_sus_pins, 653 .npins = ARRAY_SIZE(byt_sus_pins), 654 .groups = byt_sus_groups, 655 .ngroups = ARRAY_SIZE(byt_sus_groups), 656 .functions = byt_sus_functions, 657 .nfunctions = ARRAY_SIZE(byt_sus_functions), 658 .communities = byt_sus_communities, 659 .ncommunities = ARRAY_SIZE(byt_sus_communities), 660 }; 661 662 static const struct pinctrl_pin_desc byt_ncore_pins[] = { 663 PINCTRL_PIN(0, "GPIO_NCORE0"), 664 PINCTRL_PIN(1, "GPIO_NCORE1"), 665 PINCTRL_PIN(2, "GPIO_NCORE2"), 666 PINCTRL_PIN(3, "GPIO_NCORE3"), 667 PINCTRL_PIN(4, "GPIO_NCORE4"), 668 PINCTRL_PIN(5, "GPIO_NCORE5"), 669 PINCTRL_PIN(6, "GPIO_NCORE6"), 670 PINCTRL_PIN(7, "GPIO_NCORE7"), 671 PINCTRL_PIN(8, "GPIO_NCORE8"), 672 PINCTRL_PIN(9, "GPIO_NCORE9"), 673 PINCTRL_PIN(10, "GPIO_NCORE10"), 674 PINCTRL_PIN(11, "GPIO_NCORE11"), 675 PINCTRL_PIN(12, "GPIO_NCORE12"), 676 PINCTRL_PIN(13, "GPIO_NCORE13"), 677 PINCTRL_PIN(14, "GPIO_NCORE14"), 678 PINCTRL_PIN(15, "GPIO_NCORE15"), 679 PINCTRL_PIN(16, "GPIO_NCORE16"), 680 PINCTRL_PIN(17, "GPIO_NCORE17"), 681 PINCTRL_PIN(18, "GPIO_NCORE18"), 682 PINCTRL_PIN(19, "GPIO_NCORE19"), 683 PINCTRL_PIN(20, "GPIO_NCORE20"), 684 PINCTRL_PIN(21, "GPIO_NCORE21"), 685 PINCTRL_PIN(22, "GPIO_NCORE22"), 686 PINCTRL_PIN(23, "GPIO_NCORE23"), 687 PINCTRL_PIN(24, "GPIO_NCORE24"), 688 PINCTRL_PIN(25, "GPIO_NCORE25"), 689 PINCTRL_PIN(26, "GPIO_NCORE26"), 690 PINCTRL_PIN(27, "GPIO_NCORE27"), 691 }; 692 693 static unsigned const byt_ncore_pins_map[BYT_NGPIO_NCORE] = { 694 19, 18, 17, 20, 21, 22, 24, 25, 23, 16, 695 14, 15, 12, 26, 27, 1, 4, 8, 11, 0, 696 3, 6, 10, 13, 2, 5, 9, 7, 697 }; 698 699 static const struct byt_community byt_ncore_communities[] = { 700 COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map), 701 }; 702 703 static const struct byt_pinctrl_soc_data byt_ncore_soc_data = { 704 .uid = BYT_NCORE_ACPI_UID, 705 .pins = byt_ncore_pins, 706 .npins = ARRAY_SIZE(byt_ncore_pins), 707 .communities = byt_ncore_communities, 708 .ncommunities = ARRAY_SIZE(byt_ncore_communities), 709 }; 710 711 static const struct byt_pinctrl_soc_data *byt_soc_data[] = { 712 &byt_score_soc_data, 713 &byt_sus_soc_data, 714 &byt_ncore_soc_data, 715 NULL, 716 }; 717 718 static struct byt_community *byt_get_community(struct byt_gpio *vg, 719 unsigned int pin) 720 { 721 struct byt_community *comm; 722 int i; 723 724 for (i = 0; i < vg->soc_data->ncommunities; i++) { 725 comm = vg->communities_copy + i; 726 if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base) 727 return comm; 728 } 729 730 return NULL; 731 } 732 733 static void __iomem *byt_gpio_reg(struct byt_gpio *vg, unsigned int offset, 734 int reg) 735 { 736 struct byt_community *comm = byt_get_community(vg, offset); 737 u32 reg_offset; 738 739 if (!comm) 740 return NULL; 741 742 offset -= comm->pin_base; 743 switch (reg) { 744 case BYT_INT_STAT_REG: 745 reg_offset = (offset / 32) * 4; 746 break; 747 case BYT_DEBOUNCE_REG: 748 reg_offset = 0; 749 break; 750 default: 751 reg_offset = comm->pad_map[offset] * 16; 752 break; 753 } 754 755 return comm->reg_base + reg_offset + reg; 756 } 757 758 static int byt_get_groups_count(struct pinctrl_dev *pctldev) 759 { 760 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); 761 762 return vg->soc_data->ngroups; 763 } 764 765 static const char *byt_get_group_name(struct pinctrl_dev *pctldev, 766 unsigned int selector) 767 { 768 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); 769 770 return vg->soc_data->groups[selector].name; 771 } 772 773 static int byt_get_group_pins(struct pinctrl_dev *pctldev, 774 unsigned int selector, 775 const unsigned int **pins, 776 unsigned int *num_pins) 777 { 778 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); 779 780 *pins = vg->soc_data->groups[selector].pins; 781 *num_pins = vg->soc_data->groups[selector].npins; 782 783 return 0; 784 } 785 786 static const struct pinctrl_ops byt_pinctrl_ops = { 787 .get_groups_count = byt_get_groups_count, 788 .get_group_name = byt_get_group_name, 789 .get_group_pins = byt_get_group_pins, 790 }; 791 792 static int byt_get_functions_count(struct pinctrl_dev *pctldev) 793 { 794 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); 795 796 return vg->soc_data->nfunctions; 797 } 798 799 static const char *byt_get_function_name(struct pinctrl_dev *pctldev, 800 unsigned int selector) 801 { 802 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); 803 804 return vg->soc_data->functions[selector].name; 805 } 806 807 static int byt_get_function_groups(struct pinctrl_dev *pctldev, 808 unsigned int selector, 809 const char * const **groups, 810 unsigned int *num_groups) 811 { 812 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); 813 814 *groups = vg->soc_data->functions[selector].groups; 815 *num_groups = vg->soc_data->functions[selector].ngroups; 816 817 return 0; 818 } 819 820 static int byt_get_group_simple_mux(const struct byt_pingroup group, 821 const char *func_name, 822 unsigned short *func) 823 { 824 int i; 825 826 for (i = 0; i < group.nfuncs; i++) { 827 if (!strcmp(group.simple_funcs[i].name, func_name)) { 828 *func = group.simple_funcs[i].func; 829 return 0; 830 } 831 } 832 833 return 1; 834 } 835 836 static int byt_get_group_mixed_mux(const struct byt_pingroup group, 837 const char *func_name, 838 const unsigned short **func) 839 { 840 int i; 841 842 for (i = 0; i < group.nfuncs; i++) { 843 if (!strcmp(group.mixed_funcs[i].name, func_name)) { 844 *func = group.mixed_funcs[i].func_values; 845 return 0; 846 } 847 } 848 849 return 1; 850 } 851 852 static void byt_set_group_simple_mux(struct byt_gpio *vg, 853 const struct byt_pingroup group, 854 unsigned short func) 855 { 856 unsigned long flags; 857 int i; 858 859 raw_spin_lock_irqsave(&vg->lock, flags); 860 861 for (i = 0; i < group.npins; i++) { 862 void __iomem *padcfg0; 863 u32 value; 864 865 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG); 866 if (!padcfg0) { 867 dev_warn(&vg->pdev->dev, 868 "Group %s, pin %i not muxed (no padcfg0)\n", 869 group.name, i); 870 continue; 871 } 872 873 value = readl(padcfg0); 874 value &= ~BYT_PIN_MUX; 875 value |= func; 876 writel(value, padcfg0); 877 } 878 879 raw_spin_unlock_irqrestore(&vg->lock, flags); 880 } 881 882 static void byt_set_group_mixed_mux(struct byt_gpio *vg, 883 const struct byt_pingroup group, 884 const unsigned short *func) 885 { 886 unsigned long flags; 887 int i; 888 889 raw_spin_lock_irqsave(&vg->lock, flags); 890 891 for (i = 0; i < group.npins; i++) { 892 void __iomem *padcfg0; 893 u32 value; 894 895 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG); 896 if (!padcfg0) { 897 dev_warn(&vg->pdev->dev, 898 "Group %s, pin %i not muxed (no padcfg0)\n", 899 group.name, i); 900 continue; 901 } 902 903 value = readl(padcfg0); 904 value &= ~BYT_PIN_MUX; 905 value |= func[i]; 906 writel(value, padcfg0); 907 } 908 909 raw_spin_unlock_irqrestore(&vg->lock, flags); 910 } 911 912 static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, 913 unsigned int group_selector) 914 { 915 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); 916 const struct byt_function func = vg->soc_data->functions[func_selector]; 917 const struct byt_pingroup group = vg->soc_data->groups[group_selector]; 918 const unsigned short *mixed_func; 919 unsigned short simple_func; 920 int ret = 1; 921 922 if (group.has_simple_funcs) 923 ret = byt_get_group_simple_mux(group, func.name, &simple_func); 924 else 925 ret = byt_get_group_mixed_mux(group, func.name, &mixed_func); 926 927 if (ret) 928 byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX); 929 else if (group.has_simple_funcs) 930 byt_set_group_simple_mux(vg, group, simple_func); 931 else 932 byt_set_group_mixed_mux(vg, group, mixed_func); 933 934 return 0; 935 } 936 937 static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned offset) 938 { 939 /* SCORE pin 92-93 */ 940 if (!strcmp(vg->soc_data->uid, BYT_SCORE_ACPI_UID) && 941 offset >= 92 && offset <= 93) 942 return 1; 943 944 /* SUS pin 11-21 */ 945 if (!strcmp(vg->soc_data->uid, BYT_SUS_ACPI_UID) && 946 offset >= 11 && offset <= 21) 947 return 1; 948 949 return 0; 950 } 951 952 static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned int offset) 953 { 954 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 955 unsigned long flags; 956 u32 value; 957 958 raw_spin_lock_irqsave(&vg->lock, flags); 959 value = readl(reg); 960 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL); 961 writel(value, reg); 962 raw_spin_unlock_irqrestore(&vg->lock, flags); 963 } 964 965 static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev, 966 struct pinctrl_gpio_range *range, 967 unsigned int offset) 968 { 969 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev); 970 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 971 u32 value, gpio_mux; 972 unsigned long flags; 973 974 raw_spin_lock_irqsave(&vg->lock, flags); 975 976 /* 977 * In most cases, func pin mux 000 means GPIO function. 978 * But, some pins may have func pin mux 001 represents 979 * GPIO function. 980 * 981 * Because there are devices out there where some pins were not 982 * configured correctly we allow changing the mux value from 983 * request (but print out warning about that). 984 */ 985 value = readl(reg) & BYT_PIN_MUX; 986 gpio_mux = byt_get_gpio_mux(vg, offset); 987 if (gpio_mux != value) { 988 value = readl(reg) & ~BYT_PIN_MUX; 989 value |= gpio_mux; 990 writel(value, reg); 991 992 dev_warn(&vg->pdev->dev, FW_BUG 993 "pin %u forcibly re-configured as GPIO\n", offset); 994 } 995 996 raw_spin_unlock_irqrestore(&vg->lock, flags); 997 998 pm_runtime_get(&vg->pdev->dev); 999 1000 return 0; 1001 } 1002 1003 static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev, 1004 struct pinctrl_gpio_range *range, 1005 unsigned int offset) 1006 { 1007 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev); 1008 1009 byt_gpio_clear_triggering(vg, offset); 1010 pm_runtime_put(&vg->pdev->dev); 1011 } 1012 1013 static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev, 1014 struct pinctrl_gpio_range *range, 1015 unsigned int offset, 1016 bool input) 1017 { 1018 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev); 1019 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1020 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 1021 unsigned long flags; 1022 u32 value; 1023 1024 raw_spin_lock_irqsave(&vg->lock, flags); 1025 1026 value = readl(val_reg); 1027 value &= ~BYT_DIR_MASK; 1028 if (input) 1029 value |= BYT_OUTPUT_EN; 1030 else 1031 /* 1032 * Before making any direction modifications, do a check if gpio 1033 * is set for direct IRQ. On baytrail, setting GPIO to output 1034 * does not make sense, so let's at least warn the caller before 1035 * they shoot themselves in the foot. 1036 */ 1037 WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN, 1038 "Potential Error: Setting GPIO with direct_irq_en to output"); 1039 writel(value, val_reg); 1040 1041 raw_spin_unlock_irqrestore(&vg->lock, flags); 1042 1043 return 0; 1044 } 1045 1046 static const struct pinmux_ops byt_pinmux_ops = { 1047 .get_functions_count = byt_get_functions_count, 1048 .get_function_name = byt_get_function_name, 1049 .get_function_groups = byt_get_function_groups, 1050 .set_mux = byt_set_mux, 1051 .gpio_request_enable = byt_gpio_request_enable, 1052 .gpio_disable_free = byt_gpio_disable_free, 1053 .gpio_set_direction = byt_gpio_set_direction, 1054 }; 1055 1056 static void byt_get_pull_strength(u32 reg, u16 *strength) 1057 { 1058 switch (reg & BYT_PULL_STR_MASK) { 1059 case BYT_PULL_STR_2K: 1060 *strength = 2000; 1061 break; 1062 case BYT_PULL_STR_10K: 1063 *strength = 10000; 1064 break; 1065 case BYT_PULL_STR_20K: 1066 *strength = 20000; 1067 break; 1068 case BYT_PULL_STR_40K: 1069 *strength = 40000; 1070 break; 1071 } 1072 } 1073 1074 static int byt_set_pull_strength(u32 *reg, u16 strength) 1075 { 1076 *reg &= ~BYT_PULL_STR_MASK; 1077 1078 switch (strength) { 1079 case 2000: 1080 *reg |= BYT_PULL_STR_2K; 1081 break; 1082 case 10000: 1083 *reg |= BYT_PULL_STR_10K; 1084 break; 1085 case 20000: 1086 *reg |= BYT_PULL_STR_20K; 1087 break; 1088 case 40000: 1089 *reg |= BYT_PULL_STR_40K; 1090 break; 1091 default: 1092 return -EINVAL; 1093 } 1094 1095 return 0; 1096 } 1097 1098 static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset, 1099 unsigned long *config) 1100 { 1101 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev); 1102 enum pin_config_param param = pinconf_to_config_param(*config); 1103 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 1104 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1105 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG); 1106 unsigned long flags; 1107 u32 conf, pull, val, debounce; 1108 u16 arg = 0; 1109 1110 raw_spin_lock_irqsave(&vg->lock, flags); 1111 conf = readl(conf_reg); 1112 pull = conf & BYT_PULL_ASSIGN_MASK; 1113 val = readl(val_reg); 1114 raw_spin_unlock_irqrestore(&vg->lock, flags); 1115 1116 switch (param) { 1117 case PIN_CONFIG_BIAS_DISABLE: 1118 if (pull) 1119 return -EINVAL; 1120 break; 1121 case PIN_CONFIG_BIAS_PULL_DOWN: 1122 /* Pull assignment is only applicable in input mode */ 1123 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN) 1124 return -EINVAL; 1125 1126 byt_get_pull_strength(conf, &arg); 1127 1128 break; 1129 case PIN_CONFIG_BIAS_PULL_UP: 1130 /* Pull assignment is only applicable in input mode */ 1131 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP) 1132 return -EINVAL; 1133 1134 byt_get_pull_strength(conf, &arg); 1135 1136 break; 1137 case PIN_CONFIG_INPUT_DEBOUNCE: 1138 if (!(conf & BYT_DEBOUNCE_EN)) 1139 return -EINVAL; 1140 1141 raw_spin_lock_irqsave(&vg->lock, flags); 1142 debounce = readl(db_reg); 1143 raw_spin_unlock_irqrestore(&vg->lock, flags); 1144 1145 switch (debounce & BYT_DEBOUNCE_PULSE_MASK) { 1146 case BYT_DEBOUNCE_PULSE_375US: 1147 arg = 375; 1148 break; 1149 case BYT_DEBOUNCE_PULSE_750US: 1150 arg = 750; 1151 break; 1152 case BYT_DEBOUNCE_PULSE_1500US: 1153 arg = 1500; 1154 break; 1155 case BYT_DEBOUNCE_PULSE_3MS: 1156 arg = 3000; 1157 break; 1158 case BYT_DEBOUNCE_PULSE_6MS: 1159 arg = 6000; 1160 break; 1161 case BYT_DEBOUNCE_PULSE_12MS: 1162 arg = 12000; 1163 break; 1164 case BYT_DEBOUNCE_PULSE_24MS: 1165 arg = 24000; 1166 break; 1167 default: 1168 return -EINVAL; 1169 } 1170 1171 break; 1172 default: 1173 return -ENOTSUPP; 1174 } 1175 1176 *config = pinconf_to_config_packed(param, arg); 1177 1178 return 0; 1179 } 1180 1181 static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, 1182 unsigned int offset, 1183 unsigned long *configs, 1184 unsigned int num_configs) 1185 { 1186 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev); 1187 unsigned int param, arg; 1188 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 1189 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1190 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG); 1191 unsigned long flags; 1192 u32 conf, val, debounce; 1193 int i, ret = 0; 1194 1195 raw_spin_lock_irqsave(&vg->lock, flags); 1196 1197 conf = readl(conf_reg); 1198 val = readl(val_reg); 1199 1200 for (i = 0; i < num_configs; i++) { 1201 param = pinconf_to_config_param(configs[i]); 1202 arg = pinconf_to_config_argument(configs[i]); 1203 1204 switch (param) { 1205 case PIN_CONFIG_BIAS_DISABLE: 1206 conf &= ~BYT_PULL_ASSIGN_MASK; 1207 break; 1208 case PIN_CONFIG_BIAS_PULL_DOWN: 1209 /* Set default strength value in case none is given */ 1210 if (arg == 1) 1211 arg = 2000; 1212 1213 /* 1214 * Pull assignment is only applicable in input mode. If 1215 * chip is not in input mode, set it and warn about it. 1216 */ 1217 if (val & BYT_INPUT_EN) { 1218 val &= ~BYT_INPUT_EN; 1219 writel(val, val_reg); 1220 dev_warn(&vg->pdev->dev, 1221 "pin %u forcibly set to input mode\n", 1222 offset); 1223 } 1224 1225 conf &= ~BYT_PULL_ASSIGN_MASK; 1226 conf |= BYT_PULL_ASSIGN_DOWN; 1227 ret = byt_set_pull_strength(&conf, arg); 1228 1229 break; 1230 case PIN_CONFIG_BIAS_PULL_UP: 1231 /* Set default strength value in case none is given */ 1232 if (arg == 1) 1233 arg = 2000; 1234 1235 /* 1236 * Pull assignment is only applicable in input mode. If 1237 * chip is not in input mode, set it and warn about it. 1238 */ 1239 if (val & BYT_INPUT_EN) { 1240 val &= ~BYT_INPUT_EN; 1241 writel(val, val_reg); 1242 dev_warn(&vg->pdev->dev, 1243 "pin %u forcibly set to input mode\n", 1244 offset); 1245 } 1246 1247 conf &= ~BYT_PULL_ASSIGN_MASK; 1248 conf |= BYT_PULL_ASSIGN_UP; 1249 ret = byt_set_pull_strength(&conf, arg); 1250 1251 break; 1252 case PIN_CONFIG_INPUT_DEBOUNCE: 1253 debounce = readl(db_reg); 1254 debounce &= ~BYT_DEBOUNCE_PULSE_MASK; 1255 1256 if (arg) 1257 conf |= BYT_DEBOUNCE_EN; 1258 else 1259 conf &= ~BYT_DEBOUNCE_EN; 1260 1261 switch (arg) { 1262 case 375: 1263 debounce |= BYT_DEBOUNCE_PULSE_375US; 1264 break; 1265 case 750: 1266 debounce |= BYT_DEBOUNCE_PULSE_750US; 1267 break; 1268 case 1500: 1269 debounce |= BYT_DEBOUNCE_PULSE_1500US; 1270 break; 1271 case 3000: 1272 debounce |= BYT_DEBOUNCE_PULSE_3MS; 1273 break; 1274 case 6000: 1275 debounce |= BYT_DEBOUNCE_PULSE_6MS; 1276 break; 1277 case 12000: 1278 debounce |= BYT_DEBOUNCE_PULSE_12MS; 1279 break; 1280 case 24000: 1281 debounce |= BYT_DEBOUNCE_PULSE_24MS; 1282 break; 1283 default: 1284 if (arg) 1285 ret = -EINVAL; 1286 break; 1287 } 1288 1289 if (!ret) 1290 writel(debounce, db_reg); 1291 break; 1292 default: 1293 ret = -ENOTSUPP; 1294 } 1295 1296 if (ret) 1297 break; 1298 } 1299 1300 if (!ret) 1301 writel(conf, conf_reg); 1302 1303 raw_spin_unlock_irqrestore(&vg->lock, flags); 1304 1305 return ret; 1306 } 1307 1308 static const struct pinconf_ops byt_pinconf_ops = { 1309 .is_generic = true, 1310 .pin_config_get = byt_pin_config_get, 1311 .pin_config_set = byt_pin_config_set, 1312 }; 1313 1314 static const struct pinctrl_desc byt_pinctrl_desc = { 1315 .pctlops = &byt_pinctrl_ops, 1316 .pmxops = &byt_pinmux_ops, 1317 .confops = &byt_pinconf_ops, 1318 .owner = THIS_MODULE, 1319 }; 1320 1321 static int byt_gpio_get(struct gpio_chip *chip, unsigned offset) 1322 { 1323 struct byt_gpio *vg = gpiochip_get_data(chip); 1324 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1325 unsigned long flags; 1326 u32 val; 1327 1328 raw_spin_lock_irqsave(&vg->lock, flags); 1329 val = readl(reg); 1330 raw_spin_unlock_irqrestore(&vg->lock, flags); 1331 1332 return !!(val & BYT_LEVEL); 1333 } 1334 1335 static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 1336 { 1337 struct byt_gpio *vg = gpiochip_get_data(chip); 1338 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1339 unsigned long flags; 1340 u32 old_val; 1341 1342 if (!reg) 1343 return; 1344 1345 raw_spin_lock_irqsave(&vg->lock, flags); 1346 old_val = readl(reg); 1347 if (value) 1348 writel(old_val | BYT_LEVEL, reg); 1349 else 1350 writel(old_val & ~BYT_LEVEL, reg); 1351 raw_spin_unlock_irqrestore(&vg->lock, flags); 1352 } 1353 1354 static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 1355 { 1356 struct byt_gpio *vg = gpiochip_get_data(chip); 1357 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1358 unsigned long flags; 1359 u32 value; 1360 1361 if (!reg) 1362 return -EINVAL; 1363 1364 raw_spin_lock_irqsave(&vg->lock, flags); 1365 value = readl(reg); 1366 raw_spin_unlock_irqrestore(&vg->lock, flags); 1367 1368 if (!(value & BYT_OUTPUT_EN)) 1369 return GPIOF_DIR_OUT; 1370 if (!(value & BYT_INPUT_EN)) 1371 return GPIOF_DIR_IN; 1372 1373 return -EINVAL; 1374 } 1375 1376 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 1377 { 1378 return pinctrl_gpio_direction_input(chip->base + offset); 1379 } 1380 1381 static int byt_gpio_direction_output(struct gpio_chip *chip, 1382 unsigned int offset, int value) 1383 { 1384 int ret = pinctrl_gpio_direction_output(chip->base + offset); 1385 1386 if (ret) 1387 return ret; 1388 1389 byt_gpio_set(chip, offset, value); 1390 1391 return 0; 1392 } 1393 1394 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 1395 { 1396 struct byt_gpio *vg = gpiochip_get_data(chip); 1397 int i; 1398 u32 conf0, val; 1399 1400 for (i = 0; i < vg->soc_data->npins; i++) { 1401 const struct byt_community *comm; 1402 const char *pull_str = NULL; 1403 const char *pull = NULL; 1404 void __iomem *reg; 1405 unsigned long flags; 1406 const char *label; 1407 unsigned int pin; 1408 1409 raw_spin_lock_irqsave(&vg->lock, flags); 1410 pin = vg->soc_data->pins[i].number; 1411 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1412 if (!reg) { 1413 seq_printf(s, 1414 "Could not retrieve pin %i conf0 reg\n", 1415 pin); 1416 raw_spin_unlock_irqrestore(&vg->lock, flags); 1417 continue; 1418 } 1419 conf0 = readl(reg); 1420 1421 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); 1422 if (!reg) { 1423 seq_printf(s, 1424 "Could not retrieve pin %i val reg\n", pin); 1425 raw_spin_unlock_irqrestore(&vg->lock, flags); 1426 continue; 1427 } 1428 val = readl(reg); 1429 raw_spin_unlock_irqrestore(&vg->lock, flags); 1430 1431 comm = byt_get_community(vg, pin); 1432 if (!comm) { 1433 seq_printf(s, 1434 "Could not get community for pin %i\n", pin); 1435 continue; 1436 } 1437 label = gpiochip_is_requested(chip, i); 1438 if (!label) 1439 label = "Unrequested"; 1440 1441 switch (conf0 & BYT_PULL_ASSIGN_MASK) { 1442 case BYT_PULL_ASSIGN_UP: 1443 pull = "up"; 1444 break; 1445 case BYT_PULL_ASSIGN_DOWN: 1446 pull = "down"; 1447 break; 1448 } 1449 1450 switch (conf0 & BYT_PULL_STR_MASK) { 1451 case BYT_PULL_STR_2K: 1452 pull_str = "2k"; 1453 break; 1454 case BYT_PULL_STR_10K: 1455 pull_str = "10k"; 1456 break; 1457 case BYT_PULL_STR_20K: 1458 pull_str = "20k"; 1459 break; 1460 case BYT_PULL_STR_40K: 1461 pull_str = "40k"; 1462 break; 1463 } 1464 1465 seq_printf(s, 1466 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s", 1467 pin, 1468 label, 1469 val & BYT_INPUT_EN ? " " : "in", 1470 val & BYT_OUTPUT_EN ? " " : "out", 1471 val & BYT_LEVEL ? "hi" : "lo", 1472 comm->pad_map[i], comm->pad_map[i] * 16, 1473 conf0 & 0x7, 1474 conf0 & BYT_TRIG_NEG ? " fall" : " ", 1475 conf0 & BYT_TRIG_POS ? " rise" : " ", 1476 conf0 & BYT_TRIG_LVL ? " level" : " "); 1477 1478 if (pull && pull_str) 1479 seq_printf(s, " %-4s %-3s", pull, pull_str); 1480 else 1481 seq_puts(s, " "); 1482 1483 if (conf0 & BYT_IODEN) 1484 seq_puts(s, " open-drain"); 1485 1486 seq_puts(s, "\n"); 1487 } 1488 } 1489 1490 static const struct gpio_chip byt_gpio_chip = { 1491 .owner = THIS_MODULE, 1492 .request = gpiochip_generic_request, 1493 .free = gpiochip_generic_free, 1494 .get_direction = byt_gpio_get_direction, 1495 .direction_input = byt_gpio_direction_input, 1496 .direction_output = byt_gpio_direction_output, 1497 .get = byt_gpio_get, 1498 .set = byt_gpio_set, 1499 .dbg_show = byt_gpio_dbg_show, 1500 }; 1501 1502 static void byt_irq_ack(struct irq_data *d) 1503 { 1504 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1505 struct byt_gpio *vg = gpiochip_get_data(gc); 1506 unsigned offset = irqd_to_hwirq(d); 1507 void __iomem *reg; 1508 1509 reg = byt_gpio_reg(vg, offset, BYT_INT_STAT_REG); 1510 if (!reg) 1511 return; 1512 1513 raw_spin_lock(&vg->lock); 1514 writel(BIT(offset % 32), reg); 1515 raw_spin_unlock(&vg->lock); 1516 } 1517 1518 static void byt_irq_mask(struct irq_data *d) 1519 { 1520 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1521 struct byt_gpio *vg = gpiochip_get_data(gc); 1522 1523 byt_gpio_clear_triggering(vg, irqd_to_hwirq(d)); 1524 } 1525 1526 static void byt_irq_unmask(struct irq_data *d) 1527 { 1528 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1529 struct byt_gpio *vg = gpiochip_get_data(gc); 1530 unsigned offset = irqd_to_hwirq(d); 1531 unsigned long flags; 1532 void __iomem *reg; 1533 u32 value; 1534 1535 reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 1536 if (!reg) 1537 return; 1538 1539 raw_spin_lock_irqsave(&vg->lock, flags); 1540 value = readl(reg); 1541 1542 switch (irqd_get_trigger_type(d)) { 1543 case IRQ_TYPE_LEVEL_HIGH: 1544 value |= BYT_TRIG_LVL; 1545 case IRQ_TYPE_EDGE_RISING: 1546 value |= BYT_TRIG_POS; 1547 break; 1548 case IRQ_TYPE_LEVEL_LOW: 1549 value |= BYT_TRIG_LVL; 1550 case IRQ_TYPE_EDGE_FALLING: 1551 value |= BYT_TRIG_NEG; 1552 break; 1553 case IRQ_TYPE_EDGE_BOTH: 1554 value |= (BYT_TRIG_NEG | BYT_TRIG_POS); 1555 break; 1556 } 1557 1558 writel(value, reg); 1559 1560 raw_spin_unlock_irqrestore(&vg->lock, flags); 1561 } 1562 1563 static int byt_irq_type(struct irq_data *d, unsigned int type) 1564 { 1565 struct byt_gpio *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d)); 1566 u32 offset = irqd_to_hwirq(d); 1567 u32 value; 1568 unsigned long flags; 1569 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 1570 1571 if (!reg || offset >= vg->chip.ngpio) 1572 return -EINVAL; 1573 1574 raw_spin_lock_irqsave(&vg->lock, flags); 1575 value = readl(reg); 1576 1577 WARN(value & BYT_DIRECT_IRQ_EN, 1578 "Bad pad config for io mode, force direct_irq_en bit clearing"); 1579 1580 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits 1581 * are used to indicate high and low level triggering 1582 */ 1583 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG | 1584 BYT_TRIG_LVL); 1585 /* Enable glitch filtering */ 1586 value |= BYT_GLITCH_FILTER_EN | BYT_GLITCH_F_SLOW_CLK | 1587 BYT_GLITCH_F_FAST_CLK; 1588 1589 writel(value, reg); 1590 1591 if (type & IRQ_TYPE_EDGE_BOTH) 1592 irq_set_handler_locked(d, handle_edge_irq); 1593 else if (type & IRQ_TYPE_LEVEL_MASK) 1594 irq_set_handler_locked(d, handle_level_irq); 1595 1596 raw_spin_unlock_irqrestore(&vg->lock, flags); 1597 1598 return 0; 1599 } 1600 1601 static struct irq_chip byt_irqchip = { 1602 .name = "BYT-GPIO", 1603 .irq_ack = byt_irq_ack, 1604 .irq_mask = byt_irq_mask, 1605 .irq_unmask = byt_irq_unmask, 1606 .irq_set_type = byt_irq_type, 1607 .flags = IRQCHIP_SKIP_SET_WAKE, 1608 }; 1609 1610 static void byt_gpio_irq_handler(struct irq_desc *desc) 1611 { 1612 struct irq_data *data = irq_desc_get_irq_data(desc); 1613 struct byt_gpio *vg = gpiochip_get_data( 1614 irq_desc_get_handler_data(desc)); 1615 struct irq_chip *chip = irq_data_get_irq_chip(data); 1616 u32 base, pin; 1617 void __iomem *reg; 1618 unsigned long pending; 1619 unsigned int virq; 1620 1621 /* check from GPIO controller which pin triggered the interrupt */ 1622 for (base = 0; base < vg->chip.ngpio; base += 32) { 1623 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG); 1624 1625 if (!reg) { 1626 dev_warn(&vg->pdev->dev, 1627 "Pin %i: could not retrieve interrupt status register\n", 1628 base); 1629 continue; 1630 } 1631 1632 raw_spin_lock(&vg->lock); 1633 pending = readl(reg); 1634 raw_spin_unlock(&vg->lock); 1635 for_each_set_bit(pin, &pending, 32) { 1636 virq = irq_find_mapping(vg->chip.irq.domain, base + pin); 1637 generic_handle_irq(virq); 1638 } 1639 } 1640 chip->irq_eoi(data); 1641 } 1642 1643 static void byt_gpio_irq_init_hw(struct byt_gpio *vg) 1644 { 1645 struct gpio_chip *gc = &vg->chip; 1646 struct device *dev = &vg->pdev->dev; 1647 void __iomem *reg; 1648 u32 base, value; 1649 int i; 1650 1651 /* 1652 * Clear interrupt triggers for all pins that are GPIOs and 1653 * do not use direct IRQ mode. This will prevent spurious 1654 * interrupts from misconfigured pins. 1655 */ 1656 for (i = 0; i < vg->soc_data->npins; i++) { 1657 unsigned int pin = vg->soc_data->pins[i].number; 1658 1659 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1660 if (!reg) { 1661 dev_warn(&vg->pdev->dev, 1662 "Pin %i: could not retrieve conf0 register\n", 1663 i); 1664 continue; 1665 } 1666 1667 value = readl(reg); 1668 if (value & BYT_DIRECT_IRQ_EN) { 1669 clear_bit(i, gc->irq.valid_mask); 1670 dev_dbg(dev, "excluding GPIO %d from IRQ domain\n", i); 1671 } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) { 1672 byt_gpio_clear_triggering(vg, i); 1673 dev_dbg(dev, "disabling GPIO %d\n", i); 1674 } 1675 } 1676 1677 /* clear interrupt status trigger registers */ 1678 for (base = 0; base < vg->soc_data->npins; base += 32) { 1679 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG); 1680 1681 if (!reg) { 1682 dev_warn(&vg->pdev->dev, 1683 "Pin %i: could not retrieve irq status reg\n", 1684 base); 1685 continue; 1686 } 1687 1688 writel(0xffffffff, reg); 1689 /* make sure trigger bits are cleared, if not then a pin 1690 might be misconfigured in bios */ 1691 value = readl(reg); 1692 if (value) 1693 dev_err(&vg->pdev->dev, 1694 "GPIO interrupt error, pins misconfigured\n"); 1695 } 1696 } 1697 1698 static int byt_gpio_probe(struct byt_gpio *vg) 1699 { 1700 struct gpio_chip *gc; 1701 struct resource *irq_rc; 1702 int ret; 1703 1704 /* Set up gpio chip */ 1705 vg->chip = byt_gpio_chip; 1706 gc = &vg->chip; 1707 gc->label = dev_name(&vg->pdev->dev); 1708 gc->base = -1; 1709 gc->can_sleep = false; 1710 gc->parent = &vg->pdev->dev; 1711 gc->ngpio = vg->soc_data->npins; 1712 gc->irq.need_valid_mask = true; 1713 1714 #ifdef CONFIG_PM_SLEEP 1715 vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio, 1716 sizeof(*vg->saved_context), GFP_KERNEL); 1717 #endif 1718 ret = devm_gpiochip_add_data(&vg->pdev->dev, gc, vg); 1719 if (ret) { 1720 dev_err(&vg->pdev->dev, "failed adding byt-gpio chip\n"); 1721 return ret; 1722 } 1723 1724 ret = gpiochip_add_pin_range(&vg->chip, dev_name(&vg->pdev->dev), 1725 0, 0, vg->soc_data->npins); 1726 if (ret) { 1727 dev_err(&vg->pdev->dev, "failed to add GPIO pin range\n"); 1728 return ret; 1729 } 1730 1731 /* set up interrupts */ 1732 irq_rc = platform_get_resource(vg->pdev, IORESOURCE_IRQ, 0); 1733 if (irq_rc && irq_rc->start) { 1734 byt_gpio_irq_init_hw(vg); 1735 ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0, 1736 handle_bad_irq, IRQ_TYPE_NONE); 1737 if (ret) { 1738 dev_err(&vg->pdev->dev, "failed to add irqchip\n"); 1739 return ret; 1740 } 1741 1742 gpiochip_set_chained_irqchip(gc, &byt_irqchip, 1743 (unsigned)irq_rc->start, 1744 byt_gpio_irq_handler); 1745 } 1746 1747 return ret; 1748 } 1749 1750 static int byt_set_soc_data(struct byt_gpio *vg, 1751 const struct byt_pinctrl_soc_data *soc_data) 1752 { 1753 int i; 1754 1755 vg->soc_data = soc_data; 1756 vg->communities_copy = devm_kcalloc(&vg->pdev->dev, 1757 soc_data->ncommunities, 1758 sizeof(*vg->communities_copy), 1759 GFP_KERNEL); 1760 if (!vg->communities_copy) 1761 return -ENOMEM; 1762 1763 for (i = 0; i < soc_data->ncommunities; i++) { 1764 struct byt_community *comm = vg->communities_copy + i; 1765 struct resource *mem_rc; 1766 1767 *comm = vg->soc_data->communities[i]; 1768 1769 mem_rc = platform_get_resource(vg->pdev, IORESOURCE_MEM, 0); 1770 comm->reg_base = devm_ioremap_resource(&vg->pdev->dev, mem_rc); 1771 if (IS_ERR(comm->reg_base)) 1772 return PTR_ERR(comm->reg_base); 1773 } 1774 1775 return 0; 1776 } 1777 1778 static const struct acpi_device_id byt_gpio_acpi_match[] = { 1779 { "INT33B2", (kernel_ulong_t)byt_soc_data }, 1780 { "INT33FC", (kernel_ulong_t)byt_soc_data }, 1781 { } 1782 }; 1783 MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match); 1784 1785 static int byt_pinctrl_probe(struct platform_device *pdev) 1786 { 1787 const struct byt_pinctrl_soc_data *soc_data = NULL; 1788 const struct byt_pinctrl_soc_data **soc_table; 1789 const struct acpi_device_id *acpi_id; 1790 struct acpi_device *acpi_dev; 1791 struct byt_gpio *vg; 1792 int i, ret; 1793 1794 acpi_dev = ACPI_COMPANION(&pdev->dev); 1795 if (!acpi_dev) 1796 return -ENODEV; 1797 1798 acpi_id = acpi_match_device(byt_gpio_acpi_match, &pdev->dev); 1799 if (!acpi_id) 1800 return -ENODEV; 1801 1802 soc_table = (const struct byt_pinctrl_soc_data **)acpi_id->driver_data; 1803 1804 for (i = 0; soc_table[i]; i++) { 1805 if (!strcmp(acpi_dev->pnp.unique_id, soc_table[i]->uid)) { 1806 soc_data = soc_table[i]; 1807 break; 1808 } 1809 } 1810 1811 if (!soc_data) 1812 return -ENODEV; 1813 1814 vg = devm_kzalloc(&pdev->dev, sizeof(*vg), GFP_KERNEL); 1815 if (!vg) 1816 return -ENOMEM; 1817 1818 vg->pdev = pdev; 1819 ret = byt_set_soc_data(vg, soc_data); 1820 if (ret) { 1821 dev_err(&pdev->dev, "failed to set soc data\n"); 1822 return ret; 1823 } 1824 1825 vg->pctl_desc = byt_pinctrl_desc; 1826 vg->pctl_desc.name = dev_name(&pdev->dev); 1827 vg->pctl_desc.pins = vg->soc_data->pins; 1828 vg->pctl_desc.npins = vg->soc_data->npins; 1829 1830 vg->pctl_dev = devm_pinctrl_register(&pdev->dev, &vg->pctl_desc, vg); 1831 if (IS_ERR(vg->pctl_dev)) { 1832 dev_err(&pdev->dev, "failed to register pinctrl driver\n"); 1833 return PTR_ERR(vg->pctl_dev); 1834 } 1835 1836 raw_spin_lock_init(&vg->lock); 1837 1838 ret = byt_gpio_probe(vg); 1839 if (ret) 1840 return ret; 1841 1842 platform_set_drvdata(pdev, vg); 1843 pm_runtime_enable(&pdev->dev); 1844 1845 return 0; 1846 } 1847 1848 #ifdef CONFIG_PM_SLEEP 1849 static int byt_gpio_suspend(struct device *dev) 1850 { 1851 struct platform_device *pdev = to_platform_device(dev); 1852 struct byt_gpio *vg = platform_get_drvdata(pdev); 1853 int i; 1854 1855 for (i = 0; i < vg->soc_data->npins; i++) { 1856 void __iomem *reg; 1857 u32 value; 1858 unsigned int pin = vg->soc_data->pins[i].number; 1859 1860 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1861 if (!reg) { 1862 dev_warn(&vg->pdev->dev, 1863 "Pin %i: could not retrieve conf0 register\n", 1864 i); 1865 continue; 1866 } 1867 value = readl(reg) & BYT_CONF0_RESTORE_MASK; 1868 vg->saved_context[i].conf0 = value; 1869 1870 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); 1871 value = readl(reg) & BYT_VAL_RESTORE_MASK; 1872 vg->saved_context[i].val = value; 1873 } 1874 1875 return 0; 1876 } 1877 1878 static int byt_gpio_resume(struct device *dev) 1879 { 1880 struct platform_device *pdev = to_platform_device(dev); 1881 struct byt_gpio *vg = platform_get_drvdata(pdev); 1882 int i; 1883 1884 for (i = 0; i < vg->soc_data->npins; i++) { 1885 void __iomem *reg; 1886 u32 value; 1887 unsigned int pin = vg->soc_data->pins[i].number; 1888 1889 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1890 if (!reg) { 1891 dev_warn(&vg->pdev->dev, 1892 "Pin %i: could not retrieve conf0 register\n", 1893 i); 1894 continue; 1895 } 1896 value = readl(reg); 1897 if ((value & BYT_CONF0_RESTORE_MASK) != 1898 vg->saved_context[i].conf0) { 1899 value &= ~BYT_CONF0_RESTORE_MASK; 1900 value |= vg->saved_context[i].conf0; 1901 writel(value, reg); 1902 dev_info(dev, "restored pin %d conf0 %#08x", i, value); 1903 } 1904 1905 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); 1906 value = readl(reg); 1907 if ((value & BYT_VAL_RESTORE_MASK) != 1908 vg->saved_context[i].val) { 1909 u32 v; 1910 1911 v = value & ~BYT_VAL_RESTORE_MASK; 1912 v |= vg->saved_context[i].val; 1913 if (v != value) { 1914 writel(v, reg); 1915 dev_dbg(dev, "restored pin %d val %#08x\n", 1916 i, v); 1917 } 1918 } 1919 } 1920 1921 return 0; 1922 } 1923 #endif 1924 1925 #ifdef CONFIG_PM 1926 static int byt_gpio_runtime_suspend(struct device *dev) 1927 { 1928 return 0; 1929 } 1930 1931 static int byt_gpio_runtime_resume(struct device *dev) 1932 { 1933 return 0; 1934 } 1935 #endif 1936 1937 static const struct dev_pm_ops byt_gpio_pm_ops = { 1938 SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume) 1939 SET_RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume, 1940 NULL) 1941 }; 1942 1943 static struct platform_driver byt_gpio_driver = { 1944 .probe = byt_pinctrl_probe, 1945 .driver = { 1946 .name = "byt_gpio", 1947 .pm = &byt_gpio_pm_ops, 1948 .suppress_bind_attrs = true, 1949 1950 .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match), 1951 }, 1952 }; 1953 1954 static int __init byt_gpio_init(void) 1955 { 1956 return platform_driver_register(&byt_gpio_driver); 1957 } 1958 subsys_initcall(byt_gpio_init); 1959