1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Pinctrl GPIO driver for Intel Baytrail 4 * 5 * Copyright (c) 2012-2013, Intel Corporation 6 * Author: Mathias Nyman <mathias.nyman@linux.intel.com> 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/bitops.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/types.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/property.h> 20 #include <linux/seq_file.h> 21 22 #include <linux/pinctrl/pinctrl.h> 23 #include <linux/pinctrl/pinmux.h> 24 #include <linux/pinctrl/pinconf.h> 25 #include <linux/pinctrl/pinconf-generic.h> 26 27 #include "pinctrl-intel.h" 28 29 /* memory mapped register offsets */ 30 #define BYT_CONF0_REG 0x000 31 #define BYT_CONF1_REG 0x004 32 #define BYT_VAL_REG 0x008 33 #define BYT_DFT_REG 0x00c 34 #define BYT_INT_STAT_REG 0x800 35 #define BYT_DEBOUNCE_REG 0x9d0 36 37 /* BYT_CONF0_REG register bits */ 38 #define BYT_IODEN BIT(31) 39 #define BYT_DIRECT_IRQ_EN BIT(27) 40 #define BYT_TRIG_MASK GENMASK(26, 24) 41 #define BYT_TRIG_NEG BIT(26) 42 #define BYT_TRIG_POS BIT(25) 43 #define BYT_TRIG_LVL BIT(24) 44 #define BYT_DEBOUNCE_EN BIT(20) 45 #define BYT_GLITCH_FILTER_EN BIT(19) 46 #define BYT_GLITCH_F_SLOW_CLK BIT(17) 47 #define BYT_GLITCH_F_FAST_CLK BIT(16) 48 #define BYT_PULL_STR_SHIFT 9 49 #define BYT_PULL_STR_MASK GENMASK(10, 9) 50 #define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT) 51 #define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT) 52 #define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT) 53 #define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT) 54 #define BYT_PULL_ASSIGN_SHIFT 7 55 #define BYT_PULL_ASSIGN_MASK GENMASK(8, 7) 56 #define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT) 57 #define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT) 58 #define BYT_PIN_MUX GENMASK(2, 0) 59 60 /* BYT_VAL_REG register bits */ 61 #define BYT_DIR_MASK GENMASK(2, 1) 62 #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/ 63 #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/ 64 #define BYT_LEVEL BIT(0) 65 66 #define BYT_CONF0_RESTORE_MASK (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | BYT_PIN_MUX) 67 #define BYT_VAL_RESTORE_MASK (BYT_DIR_MASK | BYT_LEVEL) 68 69 /* BYT_DEBOUNCE_REG bits */ 70 #define BYT_DEBOUNCE_PULSE_MASK GENMASK(2, 0) 71 #define BYT_DEBOUNCE_PULSE_375US 1 72 #define BYT_DEBOUNCE_PULSE_750US 2 73 #define BYT_DEBOUNCE_PULSE_1500US 3 74 #define BYT_DEBOUNCE_PULSE_3MS 4 75 #define BYT_DEBOUNCE_PULSE_6MS 5 76 #define BYT_DEBOUNCE_PULSE_12MS 6 77 #define BYT_DEBOUNCE_PULSE_24MS 7 78 79 #define BYT_NGPIO_SCORE 102 80 #define BYT_NGPIO_NCORE 28 81 #define BYT_NGPIO_SUS 44 82 83 #define BYT_SCORE_ACPI_UID "1" 84 #define BYT_NCORE_ACPI_UID "2" 85 #define BYT_SUS_ACPI_UID "3" 86 87 /* 88 * This is the function value most pins have for GPIO muxing. If the value 89 * differs from the default one, it must be explicitly mentioned. Otherwise, the 90 * pin control implementation will set the muxing value to default GPIO if it 91 * does not find a match for the requested function. 92 */ 93 #define BYT_DEFAULT_GPIO_MUX 0 94 #define BYT_ALTER_GPIO_MUX 1 95 96 struct byt_gpio_pin_context { 97 u32 conf0; 98 u32 val; 99 }; 100 101 #define COMMUNITY(p, n, map) \ 102 { \ 103 .pin_base = (p), \ 104 .npins = (n), \ 105 .pad_map = (map),\ 106 } 107 108 struct byt_gpio { 109 struct gpio_chip chip; 110 struct platform_device *pdev; 111 struct pinctrl_dev *pctl_dev; 112 struct pinctrl_desc pctl_desc; 113 raw_spinlock_t lock; 114 const struct intel_pinctrl_soc_data *soc_data; 115 struct intel_community *communities_copy; 116 struct byt_gpio_pin_context *saved_context; 117 }; 118 119 /* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */ 120 static const struct pinctrl_pin_desc byt_score_pins[] = { 121 PINCTRL_PIN(0, "SATA_GP0"), 122 PINCTRL_PIN(1, "SATA_GP1"), 123 PINCTRL_PIN(2, "SATA_LED#"), 124 PINCTRL_PIN(3, "PCIE_CLKREQ0"), 125 PINCTRL_PIN(4, "PCIE_CLKREQ1"), 126 PINCTRL_PIN(5, "PCIE_CLKREQ2"), 127 PINCTRL_PIN(6, "PCIE_CLKREQ3"), 128 PINCTRL_PIN(7, "SD3_WP"), 129 PINCTRL_PIN(8, "HDA_RST"), 130 PINCTRL_PIN(9, "HDA_SYNC"), 131 PINCTRL_PIN(10, "HDA_CLK"), 132 PINCTRL_PIN(11, "HDA_SDO"), 133 PINCTRL_PIN(12, "HDA_SDI0"), 134 PINCTRL_PIN(13, "HDA_SDI1"), 135 PINCTRL_PIN(14, "GPIO_S0_SC14"), 136 PINCTRL_PIN(15, "GPIO_S0_SC15"), 137 PINCTRL_PIN(16, "MMC1_CLK"), 138 PINCTRL_PIN(17, "MMC1_D0"), 139 PINCTRL_PIN(18, "MMC1_D1"), 140 PINCTRL_PIN(19, "MMC1_D2"), 141 PINCTRL_PIN(20, "MMC1_D3"), 142 PINCTRL_PIN(21, "MMC1_D4"), 143 PINCTRL_PIN(22, "MMC1_D5"), 144 PINCTRL_PIN(23, "MMC1_D6"), 145 PINCTRL_PIN(24, "MMC1_D7"), 146 PINCTRL_PIN(25, "MMC1_CMD"), 147 PINCTRL_PIN(26, "MMC1_RST"), 148 PINCTRL_PIN(27, "SD2_CLK"), 149 PINCTRL_PIN(28, "SD2_D0"), 150 PINCTRL_PIN(29, "SD2_D1"), 151 PINCTRL_PIN(30, "SD2_D2"), 152 PINCTRL_PIN(31, "SD2_D3_CD"), 153 PINCTRL_PIN(32, "SD2_CMD"), 154 PINCTRL_PIN(33, "SD3_CLK"), 155 PINCTRL_PIN(34, "SD3_D0"), 156 PINCTRL_PIN(35, "SD3_D1"), 157 PINCTRL_PIN(36, "SD3_D2"), 158 PINCTRL_PIN(37, "SD3_D3"), 159 PINCTRL_PIN(38, "SD3_CD"), 160 PINCTRL_PIN(39, "SD3_CMD"), 161 PINCTRL_PIN(40, "SD3_1P8EN"), 162 PINCTRL_PIN(41, "SD3_PWREN#"), 163 PINCTRL_PIN(42, "ILB_LPC_AD0"), 164 PINCTRL_PIN(43, "ILB_LPC_AD1"), 165 PINCTRL_PIN(44, "ILB_LPC_AD2"), 166 PINCTRL_PIN(45, "ILB_LPC_AD3"), 167 PINCTRL_PIN(46, "ILB_LPC_FRAME"), 168 PINCTRL_PIN(47, "ILB_LPC_CLK0"), 169 PINCTRL_PIN(48, "ILB_LPC_CLK1"), 170 PINCTRL_PIN(49, "ILB_LPC_CLKRUN"), 171 PINCTRL_PIN(50, "ILB_LPC_SERIRQ"), 172 PINCTRL_PIN(51, "PCU_SMB_DATA"), 173 PINCTRL_PIN(52, "PCU_SMB_CLK"), 174 PINCTRL_PIN(53, "PCU_SMB_ALERT"), 175 PINCTRL_PIN(54, "ILB_8254_SPKR"), 176 PINCTRL_PIN(55, "GPIO_S0_SC55"), 177 PINCTRL_PIN(56, "GPIO_S0_SC56"), 178 PINCTRL_PIN(57, "GPIO_S0_SC57"), 179 PINCTRL_PIN(58, "GPIO_S0_SC58"), 180 PINCTRL_PIN(59, "GPIO_S0_SC59"), 181 PINCTRL_PIN(60, "GPIO_S0_SC60"), 182 PINCTRL_PIN(61, "GPIO_S0_SC61"), 183 PINCTRL_PIN(62, "LPE_I2S2_CLK"), 184 PINCTRL_PIN(63, "LPE_I2S2_FRM"), 185 PINCTRL_PIN(64, "LPE_I2S2_DATAIN"), 186 PINCTRL_PIN(65, "LPE_I2S2_DATAOUT"), 187 PINCTRL_PIN(66, "SIO_SPI_CS"), 188 PINCTRL_PIN(67, "SIO_SPI_MISO"), 189 PINCTRL_PIN(68, "SIO_SPI_MOSI"), 190 PINCTRL_PIN(69, "SIO_SPI_CLK"), 191 PINCTRL_PIN(70, "SIO_UART1_RXD"), 192 PINCTRL_PIN(71, "SIO_UART1_TXD"), 193 PINCTRL_PIN(72, "SIO_UART1_RTS"), 194 PINCTRL_PIN(73, "SIO_UART1_CTS"), 195 PINCTRL_PIN(74, "SIO_UART2_RXD"), 196 PINCTRL_PIN(75, "SIO_UART2_TXD"), 197 PINCTRL_PIN(76, "SIO_UART2_RTS"), 198 PINCTRL_PIN(77, "SIO_UART2_CTS"), 199 PINCTRL_PIN(78, "SIO_I2C0_DATA"), 200 PINCTRL_PIN(79, "SIO_I2C0_CLK"), 201 PINCTRL_PIN(80, "SIO_I2C1_DATA"), 202 PINCTRL_PIN(81, "SIO_I2C1_CLK"), 203 PINCTRL_PIN(82, "SIO_I2C2_DATA"), 204 PINCTRL_PIN(83, "SIO_I2C2_CLK"), 205 PINCTRL_PIN(84, "SIO_I2C3_DATA"), 206 PINCTRL_PIN(85, "SIO_I2C3_CLK"), 207 PINCTRL_PIN(86, "SIO_I2C4_DATA"), 208 PINCTRL_PIN(87, "SIO_I2C4_CLK"), 209 PINCTRL_PIN(88, "SIO_I2C5_DATA"), 210 PINCTRL_PIN(89, "SIO_I2C5_CLK"), 211 PINCTRL_PIN(90, "SIO_I2C6_DATA"), 212 PINCTRL_PIN(91, "SIO_I2C6_CLK"), 213 PINCTRL_PIN(92, "GPIO_S0_SC92"), 214 PINCTRL_PIN(93, "GPIO_S0_SC93"), 215 PINCTRL_PIN(94, "SIO_PWM0"), 216 PINCTRL_PIN(95, "SIO_PWM1"), 217 PINCTRL_PIN(96, "PMC_PLT_CLK0"), 218 PINCTRL_PIN(97, "PMC_PLT_CLK1"), 219 PINCTRL_PIN(98, "PMC_PLT_CLK2"), 220 PINCTRL_PIN(99, "PMC_PLT_CLK3"), 221 PINCTRL_PIN(100, "PMC_PLT_CLK4"), 222 PINCTRL_PIN(101, "PMC_PLT_CLK5"), 223 }; 224 225 static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = { 226 85, 89, 93, 96, 99, 102, 98, 101, 34, 37, 227 36, 38, 39, 35, 40, 84, 62, 61, 64, 59, 228 54, 56, 60, 55, 63, 57, 51, 50, 53, 47, 229 52, 49, 48, 43, 46, 41, 45, 42, 58, 44, 230 95, 105, 70, 68, 67, 66, 69, 71, 65, 72, 231 86, 90, 88, 92, 103, 77, 79, 83, 78, 81, 232 80, 82, 13, 12, 15, 14, 17, 18, 19, 16, 233 2, 1, 0, 4, 6, 7, 9, 8, 33, 32, 234 31, 30, 29, 27, 25, 28, 26, 23, 21, 20, 235 24, 22, 5, 3, 10, 11, 106, 87, 91, 104, 236 97, 100, 237 }; 238 239 /* SCORE groups */ 240 static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 }; 241 static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 }; 242 243 static const unsigned int byt_score_pwm0_pins[] = { 94 }; 244 static const unsigned int byt_score_pwm1_pins[] = { 95 }; 245 246 static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 }; 247 248 static const unsigned int byt_score_i2c5_pins[] = { 88, 89 }; 249 static const unsigned int byt_score_i2c6_pins[] = { 90, 91 }; 250 static const unsigned int byt_score_i2c4_pins[] = { 86, 87 }; 251 static const unsigned int byt_score_i2c3_pins[] = { 84, 85 }; 252 static const unsigned int byt_score_i2c2_pins[] = { 82, 83 }; 253 static const unsigned int byt_score_i2c1_pins[] = { 80, 81 }; 254 static const unsigned int byt_score_i2c0_pins[] = { 78, 79 }; 255 256 static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 }; 257 static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 }; 258 static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 }; 259 260 static const unsigned int byt_score_sdcard_pins[] = { 261 7, 33, 34, 35, 36, 37, 38, 39, 40, 41, 262 }; 263 static const unsigned int byt_score_sdcard_mux_values[] = { 264 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 265 }; 266 267 static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 }; 268 269 static const unsigned int byt_score_emmc_pins[] = { 270 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 271 }; 272 273 static const unsigned int byt_score_ilb_lpc_pins[] = { 274 42, 43, 44, 45, 46, 47, 48, 49, 50, 275 }; 276 277 static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 }; 278 279 static const unsigned int byt_score_plt_clk0_pins[] = { 96 }; 280 static const unsigned int byt_score_plt_clk1_pins[] = { 97 }; 281 static const unsigned int byt_score_plt_clk2_pins[] = { 98 }; 282 static const unsigned int byt_score_plt_clk3_pins[] = { 99 }; 283 static const unsigned int byt_score_plt_clk4_pins[] = { 100 }; 284 static const unsigned int byt_score_plt_clk5_pins[] = { 101 }; 285 286 static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 }; 287 288 static const struct intel_pingroup byt_score_groups[] = { 289 PIN_GROUP("uart1_grp", byt_score_uart1_pins, 1), 290 PIN_GROUP("uart2_grp", byt_score_uart2_pins, 1), 291 PIN_GROUP("pwm0_grp", byt_score_pwm0_pins, 1), 292 PIN_GROUP("pwm1_grp", byt_score_pwm1_pins, 1), 293 PIN_GROUP("ssp2_grp", byt_score_ssp2_pins, 1), 294 PIN_GROUP("sio_spi_grp", byt_score_sio_spi_pins, 1), 295 PIN_GROUP("i2c5_grp", byt_score_i2c5_pins, 1), 296 PIN_GROUP("i2c6_grp", byt_score_i2c6_pins, 1), 297 PIN_GROUP("i2c4_grp", byt_score_i2c4_pins, 1), 298 PIN_GROUP("i2c3_grp", byt_score_i2c3_pins, 1), 299 PIN_GROUP("i2c2_grp", byt_score_i2c2_pins, 1), 300 PIN_GROUP("i2c1_grp", byt_score_i2c1_pins, 1), 301 PIN_GROUP("i2c0_grp", byt_score_i2c0_pins, 1), 302 PIN_GROUP("ssp0_grp", byt_score_ssp0_pins, 1), 303 PIN_GROUP("ssp1_grp", byt_score_ssp1_pins, 1), 304 PIN_GROUP("sdcard_grp", byt_score_sdcard_pins, byt_score_sdcard_mux_values), 305 PIN_GROUP("sdio_grp", byt_score_sdio_pins, 1), 306 PIN_GROUP("emmc_grp", byt_score_emmc_pins, 1), 307 PIN_GROUP("lpc_grp", byt_score_ilb_lpc_pins, 1), 308 PIN_GROUP("sata_grp", byt_score_sata_pins, 1), 309 PIN_GROUP("plt_clk0_grp", byt_score_plt_clk0_pins, 1), 310 PIN_GROUP("plt_clk1_grp", byt_score_plt_clk1_pins, 1), 311 PIN_GROUP("plt_clk2_grp", byt_score_plt_clk2_pins, 1), 312 PIN_GROUP("plt_clk3_grp", byt_score_plt_clk3_pins, 1), 313 PIN_GROUP("plt_clk4_grp", byt_score_plt_clk4_pins, 1), 314 PIN_GROUP("plt_clk5_grp", byt_score_plt_clk5_pins, 1), 315 PIN_GROUP("smbus_grp", byt_score_smbus_pins, 1), 316 }; 317 318 static const char * const byt_score_uart_groups[] = { 319 "uart1_grp", "uart2_grp", 320 }; 321 static const char * const byt_score_pwm_groups[] = { 322 "pwm0_grp", "pwm1_grp", 323 }; 324 static const char * const byt_score_ssp_groups[] = { 325 "ssp0_grp", "ssp1_grp", "ssp2_grp", 326 }; 327 static const char * const byt_score_spi_groups[] = { "sio_spi_grp" }; 328 static const char * const byt_score_i2c_groups[] = { 329 "i2c0_grp", "i2c1_grp", "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", 330 "i2c6_grp", 331 }; 332 static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" }; 333 static const char * const byt_score_sdio_groups[] = { "sdio_grp" }; 334 static const char * const byt_score_emmc_groups[] = { "emmc_grp" }; 335 static const char * const byt_score_lpc_groups[] = { "lpc_grp" }; 336 static const char * const byt_score_sata_groups[] = { "sata_grp" }; 337 static const char * const byt_score_plt_clk_groups[] = { 338 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp", 339 "plt_clk4_grp", "plt_clk5_grp", 340 }; 341 static const char * const byt_score_smbus_groups[] = { "smbus_grp" }; 342 static const char * const byt_score_gpio_groups[] = { 343 "uart1_grp", "uart2_grp", "pwm0_grp", "pwm1_grp", "ssp0_grp", 344 "ssp1_grp", "ssp2_grp", "sio_spi_grp", "i2c0_grp", "i2c1_grp", 345 "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", "i2c6_grp", 346 "sdcard_grp", "sdio_grp", "emmc_grp", "lpc_grp", "sata_grp", 347 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp", 348 "plt_clk4_grp", "plt_clk5_grp", "smbus_grp", 349 }; 350 351 static const struct intel_function byt_score_functions[] = { 352 FUNCTION("uart", byt_score_uart_groups), 353 FUNCTION("pwm", byt_score_pwm_groups), 354 FUNCTION("ssp", byt_score_ssp_groups), 355 FUNCTION("spi", byt_score_spi_groups), 356 FUNCTION("i2c", byt_score_i2c_groups), 357 FUNCTION("sdcard", byt_score_sdcard_groups), 358 FUNCTION("sdio", byt_score_sdio_groups), 359 FUNCTION("emmc", byt_score_emmc_groups), 360 FUNCTION("lpc", byt_score_lpc_groups), 361 FUNCTION("sata", byt_score_sata_groups), 362 FUNCTION("plt_clk", byt_score_plt_clk_groups), 363 FUNCTION("smbus", byt_score_smbus_groups), 364 FUNCTION("gpio", byt_score_gpio_groups), 365 }; 366 367 static const struct intel_community byt_score_communities[] = { 368 COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map), 369 }; 370 371 static const struct intel_pinctrl_soc_data byt_score_soc_data = { 372 .uid = BYT_SCORE_ACPI_UID, 373 .pins = byt_score_pins, 374 .npins = ARRAY_SIZE(byt_score_pins), 375 .groups = byt_score_groups, 376 .ngroups = ARRAY_SIZE(byt_score_groups), 377 .functions = byt_score_functions, 378 .nfunctions = ARRAY_SIZE(byt_score_functions), 379 .communities = byt_score_communities, 380 .ncommunities = ARRAY_SIZE(byt_score_communities), 381 }; 382 383 /* SUS pins, aka GPIOS_<pin_no> or GPIO_S5[<pin_no>] */ 384 static const struct pinctrl_pin_desc byt_sus_pins[] = { 385 PINCTRL_PIN(0, "GPIO_S50"), 386 PINCTRL_PIN(1, "GPIO_S51"), 387 PINCTRL_PIN(2, "GPIO_S52"), 388 PINCTRL_PIN(3, "GPIO_S53"), 389 PINCTRL_PIN(4, "GPIO_S54"), 390 PINCTRL_PIN(5, "GPIO_S55"), 391 PINCTRL_PIN(6, "GPIO_S56"), 392 PINCTRL_PIN(7, "GPIO_S57"), 393 PINCTRL_PIN(8, "GPIO_S58"), 394 PINCTRL_PIN(9, "GPIO_S59"), 395 PINCTRL_PIN(10, "GPIO_S510"), 396 PINCTRL_PIN(11, "PMC_SUSPWRDNACK"), 397 PINCTRL_PIN(12, "PMC_SUSCLK0"), 398 PINCTRL_PIN(13, "GPIO_S513"), 399 PINCTRL_PIN(14, "USB_ULPI_RST"), 400 PINCTRL_PIN(15, "PMC_WAKE_PCIE0#"), 401 PINCTRL_PIN(16, "PMC_PWRBTN"), 402 PINCTRL_PIN(17, "GPIO_S517"), 403 PINCTRL_PIN(18, "PMC_SUS_STAT"), 404 PINCTRL_PIN(19, "USB_OC0"), 405 PINCTRL_PIN(20, "USB_OC1"), 406 PINCTRL_PIN(21, "PCU_SPI_CS1"), 407 PINCTRL_PIN(22, "GPIO_S522"), 408 PINCTRL_PIN(23, "GPIO_S523"), 409 PINCTRL_PIN(24, "GPIO_S524"), 410 PINCTRL_PIN(25, "GPIO_S525"), 411 PINCTRL_PIN(26, "GPIO_S526"), 412 PINCTRL_PIN(27, "GPIO_S527"), 413 PINCTRL_PIN(28, "GPIO_S528"), 414 PINCTRL_PIN(29, "GPIO_S529"), 415 PINCTRL_PIN(30, "GPIO_S530"), 416 PINCTRL_PIN(31, "USB_ULPI_CLK"), 417 PINCTRL_PIN(32, "USB_ULPI_DATA0"), 418 PINCTRL_PIN(33, "USB_ULPI_DATA1"), 419 PINCTRL_PIN(34, "USB_ULPI_DATA2"), 420 PINCTRL_PIN(35, "USB_ULPI_DATA3"), 421 PINCTRL_PIN(36, "USB_ULPI_DATA4"), 422 PINCTRL_PIN(37, "USB_ULPI_DATA5"), 423 PINCTRL_PIN(38, "USB_ULPI_DATA6"), 424 PINCTRL_PIN(39, "USB_ULPI_DATA7"), 425 PINCTRL_PIN(40, "USB_ULPI_DIR"), 426 PINCTRL_PIN(41, "USB_ULPI_NXT"), 427 PINCTRL_PIN(42, "USB_ULPI_STP"), 428 PINCTRL_PIN(43, "USB_ULPI_REFCLK"), 429 }; 430 431 static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = { 432 29, 33, 30, 31, 32, 34, 36, 35, 38, 37, 433 18, 7, 11, 20, 17, 1, 8, 10, 19, 12, 434 0, 2, 23, 39, 28, 27, 22, 21, 24, 25, 435 26, 51, 56, 54, 49, 55, 48, 57, 50, 58, 436 52, 53, 59, 40, 437 }; 438 439 static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 }; 440 static const unsigned int byt_sus_usb_over_current_mode_values[] = { 0, 0 }; 441 static const unsigned int byt_sus_usb_over_current_gpio_mode_values[] = { 1, 1 }; 442 443 static const unsigned int byt_sus_usb_ulpi_pins[] = { 444 14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 445 }; 446 static const unsigned int byt_sus_usb_ulpi_mode_values[] = { 447 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 448 }; 449 static const unsigned int byt_sus_usb_ulpi_gpio_mode_values[] = { 450 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 451 }; 452 453 static const unsigned int byt_sus_pcu_spi_pins[] = { 21 }; 454 static const unsigned int byt_sus_pcu_spi_mode_values[] = { 0 }; 455 static const unsigned int byt_sus_pcu_spi_gpio_mode_values[] = { 1 }; 456 457 static const struct intel_pingroup byt_sus_groups[] = { 458 PIN_GROUP("usb_oc_grp", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_mode_values), 459 PIN_GROUP("usb_ulpi_grp", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mode_values), 460 PIN_GROUP("pcu_spi_grp", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mode_values), 461 PIN_GROUP("usb_oc_grp_gpio", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_gpio_mode_values), 462 PIN_GROUP("usb_ulpi_grp_gpio", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_gpio_mode_values), 463 PIN_GROUP("pcu_spi_grp_gpio", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_gpio_mode_values), 464 }; 465 466 static const char * const byt_sus_usb_groups[] = { 467 "usb_oc_grp", "usb_ulpi_grp", 468 }; 469 static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" }; 470 static const char * const byt_sus_gpio_groups[] = { 471 "usb_oc_grp_gpio", "usb_ulpi_grp_gpio", "pcu_spi_grp_gpio", 472 }; 473 474 static const struct intel_function byt_sus_functions[] = { 475 FUNCTION("usb", byt_sus_usb_groups), 476 FUNCTION("spi", byt_sus_spi_groups), 477 FUNCTION("gpio", byt_sus_gpio_groups), 478 }; 479 480 static const struct intel_community byt_sus_communities[] = { 481 COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map), 482 }; 483 484 static const struct intel_pinctrl_soc_data byt_sus_soc_data = { 485 .uid = BYT_SUS_ACPI_UID, 486 .pins = byt_sus_pins, 487 .npins = ARRAY_SIZE(byt_sus_pins), 488 .groups = byt_sus_groups, 489 .ngroups = ARRAY_SIZE(byt_sus_groups), 490 .functions = byt_sus_functions, 491 .nfunctions = ARRAY_SIZE(byt_sus_functions), 492 .communities = byt_sus_communities, 493 .ncommunities = ARRAY_SIZE(byt_sus_communities), 494 }; 495 496 static const struct pinctrl_pin_desc byt_ncore_pins[] = { 497 PINCTRL_PIN(0, "GPIO_NCORE0"), 498 PINCTRL_PIN(1, "GPIO_NCORE1"), 499 PINCTRL_PIN(2, "GPIO_NCORE2"), 500 PINCTRL_PIN(3, "GPIO_NCORE3"), 501 PINCTRL_PIN(4, "GPIO_NCORE4"), 502 PINCTRL_PIN(5, "GPIO_NCORE5"), 503 PINCTRL_PIN(6, "GPIO_NCORE6"), 504 PINCTRL_PIN(7, "GPIO_NCORE7"), 505 PINCTRL_PIN(8, "GPIO_NCORE8"), 506 PINCTRL_PIN(9, "GPIO_NCORE9"), 507 PINCTRL_PIN(10, "GPIO_NCORE10"), 508 PINCTRL_PIN(11, "GPIO_NCORE11"), 509 PINCTRL_PIN(12, "GPIO_NCORE12"), 510 PINCTRL_PIN(13, "GPIO_NCORE13"), 511 PINCTRL_PIN(14, "GPIO_NCORE14"), 512 PINCTRL_PIN(15, "GPIO_NCORE15"), 513 PINCTRL_PIN(16, "GPIO_NCORE16"), 514 PINCTRL_PIN(17, "GPIO_NCORE17"), 515 PINCTRL_PIN(18, "GPIO_NCORE18"), 516 PINCTRL_PIN(19, "GPIO_NCORE19"), 517 PINCTRL_PIN(20, "GPIO_NCORE20"), 518 PINCTRL_PIN(21, "GPIO_NCORE21"), 519 PINCTRL_PIN(22, "GPIO_NCORE22"), 520 PINCTRL_PIN(23, "GPIO_NCORE23"), 521 PINCTRL_PIN(24, "GPIO_NCORE24"), 522 PINCTRL_PIN(25, "GPIO_NCORE25"), 523 PINCTRL_PIN(26, "GPIO_NCORE26"), 524 PINCTRL_PIN(27, "GPIO_NCORE27"), 525 }; 526 527 static const unsigned int byt_ncore_pins_map[BYT_NGPIO_NCORE] = { 528 19, 18, 17, 20, 21, 22, 24, 25, 23, 16, 529 14, 15, 12, 26, 27, 1, 4, 8, 11, 0, 530 3, 6, 10, 13, 2, 5, 9, 7, 531 }; 532 533 static const struct intel_community byt_ncore_communities[] = { 534 COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map), 535 }; 536 537 static const struct intel_pinctrl_soc_data byt_ncore_soc_data = { 538 .uid = BYT_NCORE_ACPI_UID, 539 .pins = byt_ncore_pins, 540 .npins = ARRAY_SIZE(byt_ncore_pins), 541 .communities = byt_ncore_communities, 542 .ncommunities = ARRAY_SIZE(byt_ncore_communities), 543 }; 544 545 static const struct intel_pinctrl_soc_data *byt_soc_data[] = { 546 &byt_score_soc_data, 547 &byt_sus_soc_data, 548 &byt_ncore_soc_data, 549 NULL 550 }; 551 552 static struct intel_community *byt_get_community(struct byt_gpio *vg, 553 unsigned int pin) 554 { 555 struct intel_community *comm; 556 int i; 557 558 for (i = 0; i < vg->soc_data->ncommunities; i++) { 559 comm = vg->communities_copy + i; 560 if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base) 561 return comm; 562 } 563 564 return NULL; 565 } 566 567 static void __iomem *byt_gpio_reg(struct byt_gpio *vg, unsigned int offset, 568 int reg) 569 { 570 struct intel_community *comm = byt_get_community(vg, offset); 571 u32 reg_offset; 572 573 if (!comm) 574 return NULL; 575 576 offset -= comm->pin_base; 577 switch (reg) { 578 case BYT_INT_STAT_REG: 579 reg_offset = (offset / 32) * 4; 580 break; 581 case BYT_DEBOUNCE_REG: 582 reg_offset = 0; 583 break; 584 default: 585 reg_offset = comm->pad_map[offset] * 16; 586 break; 587 } 588 589 return comm->pad_regs + reg_offset + reg; 590 } 591 592 static int byt_get_groups_count(struct pinctrl_dev *pctldev) 593 { 594 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); 595 596 return vg->soc_data->ngroups; 597 } 598 599 static const char *byt_get_group_name(struct pinctrl_dev *pctldev, 600 unsigned int selector) 601 { 602 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); 603 604 return vg->soc_data->groups[selector].name; 605 } 606 607 static int byt_get_group_pins(struct pinctrl_dev *pctldev, 608 unsigned int selector, 609 const unsigned int **pins, 610 unsigned int *num_pins) 611 { 612 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); 613 614 *pins = vg->soc_data->groups[selector].pins; 615 *num_pins = vg->soc_data->groups[selector].npins; 616 617 return 0; 618 } 619 620 static const struct pinctrl_ops byt_pinctrl_ops = { 621 .get_groups_count = byt_get_groups_count, 622 .get_group_name = byt_get_group_name, 623 .get_group_pins = byt_get_group_pins, 624 }; 625 626 static int byt_get_functions_count(struct pinctrl_dev *pctldev) 627 { 628 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); 629 630 return vg->soc_data->nfunctions; 631 } 632 633 static const char *byt_get_function_name(struct pinctrl_dev *pctldev, 634 unsigned int selector) 635 { 636 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); 637 638 return vg->soc_data->functions[selector].name; 639 } 640 641 static int byt_get_function_groups(struct pinctrl_dev *pctldev, 642 unsigned int selector, 643 const char * const **groups, 644 unsigned int *num_groups) 645 { 646 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); 647 648 *groups = vg->soc_data->functions[selector].groups; 649 *num_groups = vg->soc_data->functions[selector].ngroups; 650 651 return 0; 652 } 653 654 static void byt_set_group_simple_mux(struct byt_gpio *vg, 655 const struct intel_pingroup group, 656 unsigned int func) 657 { 658 unsigned long flags; 659 int i; 660 661 raw_spin_lock_irqsave(&vg->lock, flags); 662 663 for (i = 0; i < group.npins; i++) { 664 void __iomem *padcfg0; 665 u32 value; 666 667 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG); 668 if (!padcfg0) { 669 dev_warn(&vg->pdev->dev, 670 "Group %s, pin %i not muxed (no padcfg0)\n", 671 group.name, i); 672 continue; 673 } 674 675 value = readl(padcfg0); 676 value &= ~BYT_PIN_MUX; 677 value |= func; 678 writel(value, padcfg0); 679 } 680 681 raw_spin_unlock_irqrestore(&vg->lock, flags); 682 } 683 684 static void byt_set_group_mixed_mux(struct byt_gpio *vg, 685 const struct intel_pingroup group, 686 const unsigned int *func) 687 { 688 unsigned long flags; 689 int i; 690 691 raw_spin_lock_irqsave(&vg->lock, flags); 692 693 for (i = 0; i < group.npins; i++) { 694 void __iomem *padcfg0; 695 u32 value; 696 697 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG); 698 if (!padcfg0) { 699 dev_warn(&vg->pdev->dev, 700 "Group %s, pin %i not muxed (no padcfg0)\n", 701 group.name, i); 702 continue; 703 } 704 705 value = readl(padcfg0); 706 value &= ~BYT_PIN_MUX; 707 value |= func[i]; 708 writel(value, padcfg0); 709 } 710 711 raw_spin_unlock_irqrestore(&vg->lock, flags); 712 } 713 714 static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, 715 unsigned int group_selector) 716 { 717 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev); 718 const struct intel_function func = vg->soc_data->functions[func_selector]; 719 const struct intel_pingroup group = vg->soc_data->groups[group_selector]; 720 721 if (group.modes) 722 byt_set_group_mixed_mux(vg, group, group.modes); 723 else if (!strcmp(func.name, "gpio")) 724 byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX); 725 else 726 byt_set_group_simple_mux(vg, group, group.mode); 727 728 return 0; 729 } 730 731 static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned int offset) 732 { 733 /* SCORE pin 92-93 */ 734 if (!strcmp(vg->soc_data->uid, BYT_SCORE_ACPI_UID) && 735 offset >= 92 && offset <= 93) 736 return BYT_ALTER_GPIO_MUX; 737 738 /* SUS pin 11-21 */ 739 if (!strcmp(vg->soc_data->uid, BYT_SUS_ACPI_UID) && 740 offset >= 11 && offset <= 21) 741 return BYT_ALTER_GPIO_MUX; 742 743 return BYT_DEFAULT_GPIO_MUX; 744 } 745 746 static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned int offset) 747 { 748 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 749 unsigned long flags; 750 u32 value; 751 752 raw_spin_lock_irqsave(&vg->lock, flags); 753 value = readl(reg); 754 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL); 755 writel(value, reg); 756 raw_spin_unlock_irqrestore(&vg->lock, flags); 757 } 758 759 static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev, 760 struct pinctrl_gpio_range *range, 761 unsigned int offset) 762 { 763 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev); 764 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 765 u32 value, gpio_mux; 766 unsigned long flags; 767 768 raw_spin_lock_irqsave(&vg->lock, flags); 769 770 /* 771 * In most cases, func pin mux 000 means GPIO function. 772 * But, some pins may have func pin mux 001 represents 773 * GPIO function. 774 * 775 * Because there are devices out there where some pins were not 776 * configured correctly we allow changing the mux value from 777 * request (but print out warning about that). 778 */ 779 value = readl(reg) & BYT_PIN_MUX; 780 gpio_mux = byt_get_gpio_mux(vg, offset); 781 if (gpio_mux != value) { 782 value = readl(reg) & ~BYT_PIN_MUX; 783 value |= gpio_mux; 784 writel(value, reg); 785 786 dev_warn(&vg->pdev->dev, FW_BUG 787 "pin %u forcibly re-configured as GPIO\n", offset); 788 } 789 790 raw_spin_unlock_irqrestore(&vg->lock, flags); 791 792 pm_runtime_get(&vg->pdev->dev); 793 794 return 0; 795 } 796 797 static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev, 798 struct pinctrl_gpio_range *range, 799 unsigned int offset) 800 { 801 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev); 802 803 byt_gpio_clear_triggering(vg, offset); 804 pm_runtime_put(&vg->pdev->dev); 805 } 806 807 static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev, 808 struct pinctrl_gpio_range *range, 809 unsigned int offset, 810 bool input) 811 { 812 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev); 813 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 814 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 815 unsigned long flags; 816 u32 value; 817 818 raw_spin_lock_irqsave(&vg->lock, flags); 819 820 value = readl(val_reg); 821 value &= ~BYT_DIR_MASK; 822 if (input) 823 value |= BYT_OUTPUT_EN; 824 else 825 /* 826 * Before making any direction modifications, do a check if gpio 827 * is set for direct IRQ. On baytrail, setting GPIO to output 828 * does not make sense, so let's at least warn the caller before 829 * they shoot themselves in the foot. 830 */ 831 WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN, 832 "Potential Error: Setting GPIO with direct_irq_en to output"); 833 writel(value, val_reg); 834 835 raw_spin_unlock_irqrestore(&vg->lock, flags); 836 837 return 0; 838 } 839 840 static const struct pinmux_ops byt_pinmux_ops = { 841 .get_functions_count = byt_get_functions_count, 842 .get_function_name = byt_get_function_name, 843 .get_function_groups = byt_get_function_groups, 844 .set_mux = byt_set_mux, 845 .gpio_request_enable = byt_gpio_request_enable, 846 .gpio_disable_free = byt_gpio_disable_free, 847 .gpio_set_direction = byt_gpio_set_direction, 848 }; 849 850 static void byt_get_pull_strength(u32 reg, u16 *strength) 851 { 852 switch (reg & BYT_PULL_STR_MASK) { 853 case BYT_PULL_STR_2K: 854 *strength = 2000; 855 break; 856 case BYT_PULL_STR_10K: 857 *strength = 10000; 858 break; 859 case BYT_PULL_STR_20K: 860 *strength = 20000; 861 break; 862 case BYT_PULL_STR_40K: 863 *strength = 40000; 864 break; 865 } 866 } 867 868 static int byt_set_pull_strength(u32 *reg, u16 strength) 869 { 870 *reg &= ~BYT_PULL_STR_MASK; 871 872 switch (strength) { 873 case 2000: 874 *reg |= BYT_PULL_STR_2K; 875 break; 876 case 10000: 877 *reg |= BYT_PULL_STR_10K; 878 break; 879 case 20000: 880 *reg |= BYT_PULL_STR_20K; 881 break; 882 case 40000: 883 *reg |= BYT_PULL_STR_40K; 884 break; 885 default: 886 return -EINVAL; 887 } 888 889 return 0; 890 } 891 892 static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset, 893 unsigned long *config) 894 { 895 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev); 896 enum pin_config_param param = pinconf_to_config_param(*config); 897 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 898 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 899 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG); 900 unsigned long flags; 901 u32 conf, pull, val, debounce; 902 u16 arg = 0; 903 904 raw_spin_lock_irqsave(&vg->lock, flags); 905 conf = readl(conf_reg); 906 pull = conf & BYT_PULL_ASSIGN_MASK; 907 val = readl(val_reg); 908 raw_spin_unlock_irqrestore(&vg->lock, flags); 909 910 switch (param) { 911 case PIN_CONFIG_BIAS_DISABLE: 912 if (pull) 913 return -EINVAL; 914 break; 915 case PIN_CONFIG_BIAS_PULL_DOWN: 916 /* Pull assignment is only applicable in input mode */ 917 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN) 918 return -EINVAL; 919 920 byt_get_pull_strength(conf, &arg); 921 922 break; 923 case PIN_CONFIG_BIAS_PULL_UP: 924 /* Pull assignment is only applicable in input mode */ 925 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP) 926 return -EINVAL; 927 928 byt_get_pull_strength(conf, &arg); 929 930 break; 931 case PIN_CONFIG_INPUT_DEBOUNCE: 932 if (!(conf & BYT_DEBOUNCE_EN)) 933 return -EINVAL; 934 935 raw_spin_lock_irqsave(&vg->lock, flags); 936 debounce = readl(db_reg); 937 raw_spin_unlock_irqrestore(&vg->lock, flags); 938 939 switch (debounce & BYT_DEBOUNCE_PULSE_MASK) { 940 case BYT_DEBOUNCE_PULSE_375US: 941 arg = 375; 942 break; 943 case BYT_DEBOUNCE_PULSE_750US: 944 arg = 750; 945 break; 946 case BYT_DEBOUNCE_PULSE_1500US: 947 arg = 1500; 948 break; 949 case BYT_DEBOUNCE_PULSE_3MS: 950 arg = 3000; 951 break; 952 case BYT_DEBOUNCE_PULSE_6MS: 953 arg = 6000; 954 break; 955 case BYT_DEBOUNCE_PULSE_12MS: 956 arg = 12000; 957 break; 958 case BYT_DEBOUNCE_PULSE_24MS: 959 arg = 24000; 960 break; 961 default: 962 return -EINVAL; 963 } 964 965 break; 966 default: 967 return -ENOTSUPP; 968 } 969 970 *config = pinconf_to_config_packed(param, arg); 971 972 return 0; 973 } 974 975 static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, 976 unsigned int offset, 977 unsigned long *configs, 978 unsigned int num_configs) 979 { 980 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev); 981 unsigned int param, arg; 982 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 983 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 984 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG); 985 unsigned long flags; 986 u32 conf, val, debounce; 987 int i, ret = 0; 988 989 raw_spin_lock_irqsave(&vg->lock, flags); 990 991 conf = readl(conf_reg); 992 val = readl(val_reg); 993 994 for (i = 0; i < num_configs; i++) { 995 param = pinconf_to_config_param(configs[i]); 996 arg = pinconf_to_config_argument(configs[i]); 997 998 switch (param) { 999 case PIN_CONFIG_BIAS_DISABLE: 1000 conf &= ~BYT_PULL_ASSIGN_MASK; 1001 break; 1002 case PIN_CONFIG_BIAS_PULL_DOWN: 1003 /* Set default strength value in case none is given */ 1004 if (arg == 1) 1005 arg = 2000; 1006 1007 /* 1008 * Pull assignment is only applicable in input mode. If 1009 * chip is not in input mode, set it and warn about it. 1010 */ 1011 if (val & BYT_INPUT_EN) { 1012 val &= ~BYT_INPUT_EN; 1013 writel(val, val_reg); 1014 dev_warn(&vg->pdev->dev, 1015 "pin %u forcibly set to input mode\n", 1016 offset); 1017 } 1018 1019 conf &= ~BYT_PULL_ASSIGN_MASK; 1020 conf |= BYT_PULL_ASSIGN_DOWN; 1021 ret = byt_set_pull_strength(&conf, arg); 1022 1023 break; 1024 case PIN_CONFIG_BIAS_PULL_UP: 1025 /* Set default strength value in case none is given */ 1026 if (arg == 1) 1027 arg = 2000; 1028 1029 /* 1030 * Pull assignment is only applicable in input mode. If 1031 * chip is not in input mode, set it and warn about it. 1032 */ 1033 if (val & BYT_INPUT_EN) { 1034 val &= ~BYT_INPUT_EN; 1035 writel(val, val_reg); 1036 dev_warn(&vg->pdev->dev, 1037 "pin %u forcibly set to input mode\n", 1038 offset); 1039 } 1040 1041 conf &= ~BYT_PULL_ASSIGN_MASK; 1042 conf |= BYT_PULL_ASSIGN_UP; 1043 ret = byt_set_pull_strength(&conf, arg); 1044 1045 break; 1046 case PIN_CONFIG_INPUT_DEBOUNCE: 1047 debounce = readl(db_reg); 1048 debounce &= ~BYT_DEBOUNCE_PULSE_MASK; 1049 1050 if (arg) 1051 conf |= BYT_DEBOUNCE_EN; 1052 else 1053 conf &= ~BYT_DEBOUNCE_EN; 1054 1055 switch (arg) { 1056 case 375: 1057 debounce |= BYT_DEBOUNCE_PULSE_375US; 1058 break; 1059 case 750: 1060 debounce |= BYT_DEBOUNCE_PULSE_750US; 1061 break; 1062 case 1500: 1063 debounce |= BYT_DEBOUNCE_PULSE_1500US; 1064 break; 1065 case 3000: 1066 debounce |= BYT_DEBOUNCE_PULSE_3MS; 1067 break; 1068 case 6000: 1069 debounce |= BYT_DEBOUNCE_PULSE_6MS; 1070 break; 1071 case 12000: 1072 debounce |= BYT_DEBOUNCE_PULSE_12MS; 1073 break; 1074 case 24000: 1075 debounce |= BYT_DEBOUNCE_PULSE_24MS; 1076 break; 1077 default: 1078 if (arg) 1079 ret = -EINVAL; 1080 break; 1081 } 1082 1083 if (!ret) 1084 writel(debounce, db_reg); 1085 break; 1086 default: 1087 ret = -ENOTSUPP; 1088 } 1089 1090 if (ret) 1091 break; 1092 } 1093 1094 if (!ret) 1095 writel(conf, conf_reg); 1096 1097 raw_spin_unlock_irqrestore(&vg->lock, flags); 1098 1099 return ret; 1100 } 1101 1102 static const struct pinconf_ops byt_pinconf_ops = { 1103 .is_generic = true, 1104 .pin_config_get = byt_pin_config_get, 1105 .pin_config_set = byt_pin_config_set, 1106 }; 1107 1108 static const struct pinctrl_desc byt_pinctrl_desc = { 1109 .pctlops = &byt_pinctrl_ops, 1110 .pmxops = &byt_pinmux_ops, 1111 .confops = &byt_pinconf_ops, 1112 .owner = THIS_MODULE, 1113 }; 1114 1115 static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset) 1116 { 1117 struct byt_gpio *vg = gpiochip_get_data(chip); 1118 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1119 unsigned long flags; 1120 u32 val; 1121 1122 raw_spin_lock_irqsave(&vg->lock, flags); 1123 val = readl(reg); 1124 raw_spin_unlock_irqrestore(&vg->lock, flags); 1125 1126 return !!(val & BYT_LEVEL); 1127 } 1128 1129 static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 1130 { 1131 struct byt_gpio *vg = gpiochip_get_data(chip); 1132 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1133 unsigned long flags; 1134 u32 old_val; 1135 1136 if (!reg) 1137 return; 1138 1139 raw_spin_lock_irqsave(&vg->lock, flags); 1140 old_val = readl(reg); 1141 if (value) 1142 writel(old_val | BYT_LEVEL, reg); 1143 else 1144 writel(old_val & ~BYT_LEVEL, reg); 1145 raw_spin_unlock_irqrestore(&vg->lock, flags); 1146 } 1147 1148 static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 1149 { 1150 struct byt_gpio *vg = gpiochip_get_data(chip); 1151 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1152 unsigned long flags; 1153 u32 value; 1154 1155 if (!reg) 1156 return -EINVAL; 1157 1158 raw_spin_lock_irqsave(&vg->lock, flags); 1159 value = readl(reg); 1160 raw_spin_unlock_irqrestore(&vg->lock, flags); 1161 1162 if (!(value & BYT_OUTPUT_EN)) 1163 return 0; 1164 if (!(value & BYT_INPUT_EN)) 1165 return 1; 1166 1167 return -EINVAL; 1168 } 1169 1170 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 1171 { 1172 return pinctrl_gpio_direction_input(chip->base + offset); 1173 } 1174 1175 static int byt_gpio_direction_output(struct gpio_chip *chip, 1176 unsigned int offset, int value) 1177 { 1178 int ret = pinctrl_gpio_direction_output(chip->base + offset); 1179 1180 if (ret) 1181 return ret; 1182 1183 byt_gpio_set(chip, offset, value); 1184 1185 return 0; 1186 } 1187 1188 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 1189 { 1190 struct byt_gpio *vg = gpiochip_get_data(chip); 1191 int i; 1192 u32 conf0, val; 1193 1194 for (i = 0; i < vg->soc_data->npins; i++) { 1195 const struct intel_community *comm; 1196 const char *pull_str = NULL; 1197 const char *pull = NULL; 1198 void __iomem *reg; 1199 unsigned long flags; 1200 const char *label; 1201 unsigned int pin; 1202 1203 raw_spin_lock_irqsave(&vg->lock, flags); 1204 pin = vg->soc_data->pins[i].number; 1205 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1206 if (!reg) { 1207 seq_printf(s, 1208 "Could not retrieve pin %i conf0 reg\n", 1209 pin); 1210 raw_spin_unlock_irqrestore(&vg->lock, flags); 1211 continue; 1212 } 1213 conf0 = readl(reg); 1214 1215 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); 1216 if (!reg) { 1217 seq_printf(s, 1218 "Could not retrieve pin %i val reg\n", pin); 1219 raw_spin_unlock_irqrestore(&vg->lock, flags); 1220 continue; 1221 } 1222 val = readl(reg); 1223 raw_spin_unlock_irqrestore(&vg->lock, flags); 1224 1225 comm = byt_get_community(vg, pin); 1226 if (!comm) { 1227 seq_printf(s, 1228 "Could not get community for pin %i\n", pin); 1229 continue; 1230 } 1231 label = gpiochip_is_requested(chip, i); 1232 if (!label) 1233 label = "Unrequested"; 1234 1235 switch (conf0 & BYT_PULL_ASSIGN_MASK) { 1236 case BYT_PULL_ASSIGN_UP: 1237 pull = "up"; 1238 break; 1239 case BYT_PULL_ASSIGN_DOWN: 1240 pull = "down"; 1241 break; 1242 } 1243 1244 switch (conf0 & BYT_PULL_STR_MASK) { 1245 case BYT_PULL_STR_2K: 1246 pull_str = "2k"; 1247 break; 1248 case BYT_PULL_STR_10K: 1249 pull_str = "10k"; 1250 break; 1251 case BYT_PULL_STR_20K: 1252 pull_str = "20k"; 1253 break; 1254 case BYT_PULL_STR_40K: 1255 pull_str = "40k"; 1256 break; 1257 } 1258 1259 seq_printf(s, 1260 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s", 1261 pin, 1262 label, 1263 val & BYT_INPUT_EN ? " " : "in", 1264 val & BYT_OUTPUT_EN ? " " : "out", 1265 val & BYT_LEVEL ? "hi" : "lo", 1266 comm->pad_map[i], comm->pad_map[i] * 16, 1267 conf0 & 0x7, 1268 conf0 & BYT_TRIG_NEG ? " fall" : " ", 1269 conf0 & BYT_TRIG_POS ? " rise" : " ", 1270 conf0 & BYT_TRIG_LVL ? " level" : " "); 1271 1272 if (pull && pull_str) 1273 seq_printf(s, " %-4s %-3s", pull, pull_str); 1274 else 1275 seq_puts(s, " "); 1276 1277 if (conf0 & BYT_IODEN) 1278 seq_puts(s, " open-drain"); 1279 1280 seq_puts(s, "\n"); 1281 } 1282 } 1283 1284 static const struct gpio_chip byt_gpio_chip = { 1285 .owner = THIS_MODULE, 1286 .request = gpiochip_generic_request, 1287 .free = gpiochip_generic_free, 1288 .get_direction = byt_gpio_get_direction, 1289 .direction_input = byt_gpio_direction_input, 1290 .direction_output = byt_gpio_direction_output, 1291 .get = byt_gpio_get, 1292 .set = byt_gpio_set, 1293 .dbg_show = byt_gpio_dbg_show, 1294 }; 1295 1296 static void byt_irq_ack(struct irq_data *d) 1297 { 1298 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1299 struct byt_gpio *vg = gpiochip_get_data(gc); 1300 unsigned int offset = irqd_to_hwirq(d); 1301 void __iomem *reg; 1302 1303 reg = byt_gpio_reg(vg, offset, BYT_INT_STAT_REG); 1304 if (!reg) 1305 return; 1306 1307 raw_spin_lock(&vg->lock); 1308 writel(BIT(offset % 32), reg); 1309 raw_spin_unlock(&vg->lock); 1310 } 1311 1312 static void byt_irq_mask(struct irq_data *d) 1313 { 1314 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1315 struct byt_gpio *vg = gpiochip_get_data(gc); 1316 1317 byt_gpio_clear_triggering(vg, irqd_to_hwirq(d)); 1318 } 1319 1320 static void byt_irq_unmask(struct irq_data *d) 1321 { 1322 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1323 struct byt_gpio *vg = gpiochip_get_data(gc); 1324 unsigned int offset = irqd_to_hwirq(d); 1325 unsigned long flags; 1326 void __iomem *reg; 1327 u32 value; 1328 1329 reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 1330 if (!reg) 1331 return; 1332 1333 raw_spin_lock_irqsave(&vg->lock, flags); 1334 value = readl(reg); 1335 1336 switch (irqd_get_trigger_type(d)) { 1337 case IRQ_TYPE_LEVEL_HIGH: 1338 value |= BYT_TRIG_LVL; 1339 /* fall through */ 1340 case IRQ_TYPE_EDGE_RISING: 1341 value |= BYT_TRIG_POS; 1342 break; 1343 case IRQ_TYPE_LEVEL_LOW: 1344 value |= BYT_TRIG_LVL; 1345 /* fall through */ 1346 case IRQ_TYPE_EDGE_FALLING: 1347 value |= BYT_TRIG_NEG; 1348 break; 1349 case IRQ_TYPE_EDGE_BOTH: 1350 value |= (BYT_TRIG_NEG | BYT_TRIG_POS); 1351 break; 1352 } 1353 1354 writel(value, reg); 1355 1356 raw_spin_unlock_irqrestore(&vg->lock, flags); 1357 } 1358 1359 static int byt_irq_type(struct irq_data *d, unsigned int type) 1360 { 1361 struct byt_gpio *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d)); 1362 u32 offset = irqd_to_hwirq(d); 1363 u32 value; 1364 unsigned long flags; 1365 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 1366 1367 if (!reg || offset >= vg->chip.ngpio) 1368 return -EINVAL; 1369 1370 raw_spin_lock_irqsave(&vg->lock, flags); 1371 value = readl(reg); 1372 1373 WARN(value & BYT_DIRECT_IRQ_EN, 1374 "Bad pad config for io mode, force direct_irq_en bit clearing"); 1375 1376 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits 1377 * are used to indicate high and low level triggering 1378 */ 1379 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG | 1380 BYT_TRIG_LVL); 1381 /* Enable glitch filtering */ 1382 value |= BYT_GLITCH_FILTER_EN | BYT_GLITCH_F_SLOW_CLK | 1383 BYT_GLITCH_F_FAST_CLK; 1384 1385 writel(value, reg); 1386 1387 if (type & IRQ_TYPE_EDGE_BOTH) 1388 irq_set_handler_locked(d, handle_edge_irq); 1389 else if (type & IRQ_TYPE_LEVEL_MASK) 1390 irq_set_handler_locked(d, handle_level_irq); 1391 1392 raw_spin_unlock_irqrestore(&vg->lock, flags); 1393 1394 return 0; 1395 } 1396 1397 static struct irq_chip byt_irqchip = { 1398 .name = "BYT-GPIO", 1399 .irq_ack = byt_irq_ack, 1400 .irq_mask = byt_irq_mask, 1401 .irq_unmask = byt_irq_unmask, 1402 .irq_set_type = byt_irq_type, 1403 .flags = IRQCHIP_SKIP_SET_WAKE, 1404 }; 1405 1406 static void byt_gpio_irq_handler(struct irq_desc *desc) 1407 { 1408 struct irq_data *data = irq_desc_get_irq_data(desc); 1409 struct byt_gpio *vg = gpiochip_get_data( 1410 irq_desc_get_handler_data(desc)); 1411 struct irq_chip *chip = irq_data_get_irq_chip(data); 1412 u32 base, pin; 1413 void __iomem *reg; 1414 unsigned long pending; 1415 unsigned int virq; 1416 1417 /* check from GPIO controller which pin triggered the interrupt */ 1418 for (base = 0; base < vg->chip.ngpio; base += 32) { 1419 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG); 1420 1421 if (!reg) { 1422 dev_warn(&vg->pdev->dev, 1423 "Pin %i: could not retrieve interrupt status register\n", 1424 base); 1425 continue; 1426 } 1427 1428 raw_spin_lock(&vg->lock); 1429 pending = readl(reg); 1430 raw_spin_unlock(&vg->lock); 1431 for_each_set_bit(pin, &pending, 32) { 1432 virq = irq_find_mapping(vg->chip.irq.domain, base + pin); 1433 generic_handle_irq(virq); 1434 } 1435 } 1436 chip->irq_eoi(data); 1437 } 1438 1439 static void byt_init_irq_valid_mask(struct gpio_chip *chip, 1440 unsigned long *valid_mask, 1441 unsigned int ngpios) 1442 { 1443 /* 1444 * FIXME: currently the valid_mask is filled in as part of 1445 * initializing the irq_chip below in byt_gpio_irq_init_hw(). 1446 * when converting this driver to the new way of passing the 1447 * gpio_irq_chip along when adding the gpio_chip, move the 1448 * mask initialization into this callback instead. Right now 1449 * this callback is here to make sure the mask gets allocated. 1450 */ 1451 } 1452 1453 static void byt_gpio_irq_init_hw(struct byt_gpio *vg) 1454 { 1455 struct gpio_chip *gc = &vg->chip; 1456 struct device *dev = &vg->pdev->dev; 1457 void __iomem *reg; 1458 u32 base, value; 1459 int i; 1460 1461 /* 1462 * Clear interrupt triggers for all pins that are GPIOs and 1463 * do not use direct IRQ mode. This will prevent spurious 1464 * interrupts from misconfigured pins. 1465 */ 1466 for (i = 0; i < vg->soc_data->npins; i++) { 1467 unsigned int pin = vg->soc_data->pins[i].number; 1468 1469 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1470 if (!reg) { 1471 dev_warn(&vg->pdev->dev, 1472 "Pin %i: could not retrieve conf0 register\n", 1473 i); 1474 continue; 1475 } 1476 1477 value = readl(reg); 1478 if (value & BYT_DIRECT_IRQ_EN) { 1479 clear_bit(i, gc->irq.valid_mask); 1480 dev_dbg(dev, "excluding GPIO %d from IRQ domain\n", i); 1481 } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) { 1482 byt_gpio_clear_triggering(vg, i); 1483 dev_dbg(dev, "disabling GPIO %d\n", i); 1484 } 1485 } 1486 1487 /* clear interrupt status trigger registers */ 1488 for (base = 0; base < vg->soc_data->npins; base += 32) { 1489 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG); 1490 1491 if (!reg) { 1492 dev_warn(&vg->pdev->dev, 1493 "Pin %i: could not retrieve irq status reg\n", 1494 base); 1495 continue; 1496 } 1497 1498 writel(0xffffffff, reg); 1499 /* make sure trigger bits are cleared, if not then a pin 1500 might be misconfigured in bios */ 1501 value = readl(reg); 1502 if (value) 1503 dev_err(&vg->pdev->dev, 1504 "GPIO interrupt error, pins misconfigured. INT_STAT%u: 0x%08x\n", 1505 base / 32, value); 1506 } 1507 } 1508 1509 static int byt_gpio_probe(struct byt_gpio *vg) 1510 { 1511 struct gpio_chip *gc; 1512 struct resource *irq_rc; 1513 int ret; 1514 1515 /* Set up gpio chip */ 1516 vg->chip = byt_gpio_chip; 1517 gc = &vg->chip; 1518 gc->label = dev_name(&vg->pdev->dev); 1519 gc->base = -1; 1520 gc->can_sleep = false; 1521 gc->parent = &vg->pdev->dev; 1522 gc->ngpio = vg->soc_data->npins; 1523 gc->irq.init_valid_mask = byt_init_irq_valid_mask; 1524 1525 #ifdef CONFIG_PM_SLEEP 1526 vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio, 1527 sizeof(*vg->saved_context), GFP_KERNEL); 1528 if (!vg->saved_context) 1529 return -ENOMEM; 1530 #endif 1531 ret = devm_gpiochip_add_data(&vg->pdev->dev, gc, vg); 1532 if (ret) { 1533 dev_err(&vg->pdev->dev, "failed adding byt-gpio chip\n"); 1534 return ret; 1535 } 1536 1537 ret = gpiochip_add_pin_range(&vg->chip, dev_name(&vg->pdev->dev), 1538 0, 0, vg->soc_data->npins); 1539 if (ret) { 1540 dev_err(&vg->pdev->dev, "failed to add GPIO pin range\n"); 1541 return ret; 1542 } 1543 1544 /* set up interrupts */ 1545 irq_rc = platform_get_resource(vg->pdev, IORESOURCE_IRQ, 0); 1546 if (irq_rc && irq_rc->start) { 1547 byt_gpio_irq_init_hw(vg); 1548 ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0, 1549 handle_bad_irq, IRQ_TYPE_NONE); 1550 if (ret) { 1551 dev_err(&vg->pdev->dev, "failed to add irqchip\n"); 1552 return ret; 1553 } 1554 1555 gpiochip_set_chained_irqchip(gc, &byt_irqchip, 1556 (unsigned)irq_rc->start, 1557 byt_gpio_irq_handler); 1558 } 1559 1560 return ret; 1561 } 1562 1563 static int byt_set_soc_data(struct byt_gpio *vg, 1564 const struct intel_pinctrl_soc_data *soc_data) 1565 { 1566 int i; 1567 1568 vg->soc_data = soc_data; 1569 vg->communities_copy = devm_kcalloc(&vg->pdev->dev, 1570 soc_data->ncommunities, 1571 sizeof(*vg->communities_copy), 1572 GFP_KERNEL); 1573 if (!vg->communities_copy) 1574 return -ENOMEM; 1575 1576 for (i = 0; i < soc_data->ncommunities; i++) { 1577 struct intel_community *comm = vg->communities_copy + i; 1578 1579 *comm = vg->soc_data->communities[i]; 1580 1581 comm->pad_regs = devm_platform_ioremap_resource(vg->pdev, 0); 1582 if (IS_ERR(comm->pad_regs)) 1583 return PTR_ERR(comm->pad_regs); 1584 } 1585 1586 return 0; 1587 } 1588 1589 static const struct acpi_device_id byt_gpio_acpi_match[] = { 1590 { "INT33B2", (kernel_ulong_t)byt_soc_data }, 1591 { "INT33FC", (kernel_ulong_t)byt_soc_data }, 1592 { } 1593 }; 1594 1595 static int byt_pinctrl_probe(struct platform_device *pdev) 1596 { 1597 const struct intel_pinctrl_soc_data *soc_data = NULL; 1598 const struct intel_pinctrl_soc_data **soc_table; 1599 struct acpi_device *acpi_dev; 1600 struct byt_gpio *vg; 1601 int i, ret; 1602 1603 acpi_dev = ACPI_COMPANION(&pdev->dev); 1604 if (!acpi_dev) 1605 return -ENODEV; 1606 1607 soc_table = (const struct intel_pinctrl_soc_data **)device_get_match_data(&pdev->dev); 1608 1609 for (i = 0; soc_table[i]; i++) { 1610 if (!strcmp(acpi_dev->pnp.unique_id, soc_table[i]->uid)) { 1611 soc_data = soc_table[i]; 1612 break; 1613 } 1614 } 1615 1616 if (!soc_data) 1617 return -ENODEV; 1618 1619 vg = devm_kzalloc(&pdev->dev, sizeof(*vg), GFP_KERNEL); 1620 if (!vg) 1621 return -ENOMEM; 1622 1623 vg->pdev = pdev; 1624 ret = byt_set_soc_data(vg, soc_data); 1625 if (ret) { 1626 dev_err(&pdev->dev, "failed to set soc data\n"); 1627 return ret; 1628 } 1629 1630 vg->pctl_desc = byt_pinctrl_desc; 1631 vg->pctl_desc.name = dev_name(&pdev->dev); 1632 vg->pctl_desc.pins = vg->soc_data->pins; 1633 vg->pctl_desc.npins = vg->soc_data->npins; 1634 1635 vg->pctl_dev = devm_pinctrl_register(&pdev->dev, &vg->pctl_desc, vg); 1636 if (IS_ERR(vg->pctl_dev)) { 1637 dev_err(&pdev->dev, "failed to register pinctrl driver\n"); 1638 return PTR_ERR(vg->pctl_dev); 1639 } 1640 1641 raw_spin_lock_init(&vg->lock); 1642 1643 ret = byt_gpio_probe(vg); 1644 if (ret) 1645 return ret; 1646 1647 platform_set_drvdata(pdev, vg); 1648 pm_runtime_enable(&pdev->dev); 1649 1650 return 0; 1651 } 1652 1653 #ifdef CONFIG_PM_SLEEP 1654 static int byt_gpio_suspend(struct device *dev) 1655 { 1656 struct byt_gpio *vg = dev_get_drvdata(dev); 1657 int i; 1658 1659 for (i = 0; i < vg->soc_data->npins; i++) { 1660 void __iomem *reg; 1661 u32 value; 1662 unsigned int pin = vg->soc_data->pins[i].number; 1663 1664 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1665 if (!reg) { 1666 dev_warn(&vg->pdev->dev, 1667 "Pin %i: could not retrieve conf0 register\n", 1668 i); 1669 continue; 1670 } 1671 value = readl(reg) & BYT_CONF0_RESTORE_MASK; 1672 vg->saved_context[i].conf0 = value; 1673 1674 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); 1675 value = readl(reg) & BYT_VAL_RESTORE_MASK; 1676 vg->saved_context[i].val = value; 1677 } 1678 1679 return 0; 1680 } 1681 1682 static int byt_gpio_resume(struct device *dev) 1683 { 1684 struct byt_gpio *vg = dev_get_drvdata(dev); 1685 int i; 1686 1687 for (i = 0; i < vg->soc_data->npins; i++) { 1688 void __iomem *reg; 1689 u32 value; 1690 unsigned int pin = vg->soc_data->pins[i].number; 1691 1692 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1693 if (!reg) { 1694 dev_warn(&vg->pdev->dev, 1695 "Pin %i: could not retrieve conf0 register\n", 1696 i); 1697 continue; 1698 } 1699 value = readl(reg); 1700 if ((value & BYT_CONF0_RESTORE_MASK) != 1701 vg->saved_context[i].conf0) { 1702 value &= ~BYT_CONF0_RESTORE_MASK; 1703 value |= vg->saved_context[i].conf0; 1704 writel(value, reg); 1705 dev_info(dev, "restored pin %d conf0 %#08x", i, value); 1706 } 1707 1708 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); 1709 value = readl(reg); 1710 if ((value & BYT_VAL_RESTORE_MASK) != 1711 vg->saved_context[i].val) { 1712 u32 v; 1713 1714 v = value & ~BYT_VAL_RESTORE_MASK; 1715 v |= vg->saved_context[i].val; 1716 if (v != value) { 1717 writel(v, reg); 1718 dev_dbg(dev, "restored pin %d val %#08x\n", 1719 i, v); 1720 } 1721 } 1722 } 1723 1724 return 0; 1725 } 1726 #endif 1727 1728 #ifdef CONFIG_PM 1729 static int byt_gpio_runtime_suspend(struct device *dev) 1730 { 1731 return 0; 1732 } 1733 1734 static int byt_gpio_runtime_resume(struct device *dev) 1735 { 1736 return 0; 1737 } 1738 #endif 1739 1740 static const struct dev_pm_ops byt_gpio_pm_ops = { 1741 SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume) 1742 SET_RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume, 1743 NULL) 1744 }; 1745 1746 static struct platform_driver byt_gpio_driver = { 1747 .probe = byt_pinctrl_probe, 1748 .driver = { 1749 .name = "byt_gpio", 1750 .pm = &byt_gpio_pm_ops, 1751 .suppress_bind_attrs = true, 1752 1753 .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match), 1754 }, 1755 }; 1756 1757 static int __init byt_gpio_init(void) 1758 { 1759 return platform_driver_register(&byt_gpio_driver); 1760 } 1761 subsys_initcall(byt_gpio_init); 1762