15fae8b86SMika Westerberg /* 25fae8b86SMika Westerberg * Pinctrl GPIO driver for Intel Baytrail 35fae8b86SMika Westerberg * Copyright (c) 2012-2013, Intel Corporation. 45fae8b86SMika Westerberg * 55fae8b86SMika Westerberg * Author: Mathias Nyman <mathias.nyman@linux.intel.com> 65fae8b86SMika Westerberg * 75fae8b86SMika Westerberg * This program is free software; you can redistribute it and/or modify it 85fae8b86SMika Westerberg * under the terms and conditions of the GNU General Public License, 95fae8b86SMika Westerberg * version 2, as published by the Free Software Foundation. 105fae8b86SMika Westerberg * 115fae8b86SMika Westerberg * This program is distributed in the hope it will be useful, but WITHOUT 125fae8b86SMika Westerberg * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 135fae8b86SMika Westerberg * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 145fae8b86SMika Westerberg * more details. 155fae8b86SMika Westerberg * 165fae8b86SMika Westerberg * You should have received a copy of the GNU General Public License along with 175fae8b86SMika Westerberg * this program; if not, write to the Free Software Foundation, Inc., 185fae8b86SMika Westerberg * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 195fae8b86SMika Westerberg * 205fae8b86SMika Westerberg */ 215fae8b86SMika Westerberg 225fae8b86SMika Westerberg #include <linux/kernel.h> 235fae8b86SMika Westerberg #include <linux/module.h> 245fae8b86SMika Westerberg #include <linux/init.h> 255fae8b86SMika Westerberg #include <linux/types.h> 265fae8b86SMika Westerberg #include <linux/bitops.h> 275fae8b86SMika Westerberg #include <linux/interrupt.h> 285fae8b86SMika Westerberg #include <linux/gpio.h> 295fae8b86SMika Westerberg #include <linux/acpi.h> 305fae8b86SMika Westerberg #include <linux/platform_device.h> 315fae8b86SMika Westerberg #include <linux/seq_file.h> 325fae8b86SMika Westerberg #include <linux/io.h> 335fae8b86SMika Westerberg #include <linux/pm_runtime.h> 345fae8b86SMika Westerberg #include <linux/pinctrl/pinctrl.h> 355fae8b86SMika Westerberg 365fae8b86SMika Westerberg /* memory mapped register offsets */ 375fae8b86SMika Westerberg #define BYT_CONF0_REG 0x000 385fae8b86SMika Westerberg #define BYT_CONF1_REG 0x004 395fae8b86SMika Westerberg #define BYT_VAL_REG 0x008 405fae8b86SMika Westerberg #define BYT_DFT_REG 0x00c 415fae8b86SMika Westerberg #define BYT_INT_STAT_REG 0x800 425fae8b86SMika Westerberg 435fae8b86SMika Westerberg /* BYT_CONF0_REG register bits */ 445fae8b86SMika Westerberg #define BYT_IODEN BIT(31) 455fae8b86SMika Westerberg #define BYT_DIRECT_IRQ_EN BIT(27) 465fae8b86SMika Westerberg #define BYT_TRIG_NEG BIT(26) 475fae8b86SMika Westerberg #define BYT_TRIG_POS BIT(25) 485fae8b86SMika Westerberg #define BYT_TRIG_LVL BIT(24) 495fae8b86SMika Westerberg #define BYT_PULL_STR_SHIFT 9 505fae8b86SMika Westerberg #define BYT_PULL_STR_MASK (3 << BYT_PULL_STR_SHIFT) 515fae8b86SMika Westerberg #define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT) 525fae8b86SMika Westerberg #define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT) 535fae8b86SMika Westerberg #define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT) 545fae8b86SMika Westerberg #define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT) 555fae8b86SMika Westerberg #define BYT_PULL_ASSIGN_SHIFT 7 565fae8b86SMika Westerberg #define BYT_PULL_ASSIGN_MASK (3 << BYT_PULL_ASSIGN_SHIFT) 575fae8b86SMika Westerberg #define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT) 585fae8b86SMika Westerberg #define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT) 595fae8b86SMika Westerberg #define BYT_PIN_MUX 0x07 605fae8b86SMika Westerberg 615fae8b86SMika Westerberg /* BYT_VAL_REG register bits */ 625fae8b86SMika Westerberg #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/ 635fae8b86SMika Westerberg #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/ 645fae8b86SMika Westerberg #define BYT_LEVEL BIT(0) 655fae8b86SMika Westerberg 665fae8b86SMika Westerberg #define BYT_DIR_MASK (BIT(1) | BIT(2)) 675fae8b86SMika Westerberg #define BYT_TRIG_MASK (BIT(26) | BIT(25) | BIT(24)) 685fae8b86SMika Westerberg 695fae8b86SMika Westerberg #define BYT_NGPIO_SCORE 102 705fae8b86SMika Westerberg #define BYT_NGPIO_NCORE 28 715fae8b86SMika Westerberg #define BYT_NGPIO_SUS 44 725fae8b86SMika Westerberg 735fae8b86SMika Westerberg #define BYT_SCORE_ACPI_UID "1" 745fae8b86SMika Westerberg #define BYT_NCORE_ACPI_UID "2" 755fae8b86SMika Westerberg #define BYT_SUS_ACPI_UID "3" 765fae8b86SMika Westerberg 775fae8b86SMika Westerberg /* 785fae8b86SMika Westerberg * Baytrail gpio controller consist of three separate sub-controllers called 795fae8b86SMika Westerberg * SCORE, NCORE and SUS. The sub-controllers are identified by their acpi UID. 805fae8b86SMika Westerberg * 815fae8b86SMika Westerberg * GPIO numbering is _not_ ordered meaning that gpio # 0 in ACPI namespace does 825fae8b86SMika Westerberg * _not_ correspond to the first gpio register at controller's gpio base. 835fae8b86SMika Westerberg * There is no logic or pattern in mapping gpio numbers to registers (pads) so 845fae8b86SMika Westerberg * each sub-controller needs to have its own mapping table 855fae8b86SMika Westerberg */ 865fae8b86SMika Westerberg 875fae8b86SMika Westerberg /* score_pins[gpio_nr] = pad_nr */ 885fae8b86SMika Westerberg 895fae8b86SMika Westerberg static unsigned const score_pins[BYT_NGPIO_SCORE] = { 905fae8b86SMika Westerberg 85, 89, 93, 96, 99, 102, 98, 101, 34, 37, 915fae8b86SMika Westerberg 36, 38, 39, 35, 40, 84, 62, 61, 64, 59, 925fae8b86SMika Westerberg 54, 56, 60, 55, 63, 57, 51, 50, 53, 47, 935fae8b86SMika Westerberg 52, 49, 48, 43, 46, 41, 45, 42, 58, 44, 945fae8b86SMika Westerberg 95, 105, 70, 68, 67, 66, 69, 71, 65, 72, 955fae8b86SMika Westerberg 86, 90, 88, 92, 103, 77, 79, 83, 78, 81, 965fae8b86SMika Westerberg 80, 82, 13, 12, 15, 14, 17, 18, 19, 16, 975fae8b86SMika Westerberg 2, 1, 0, 4, 6, 7, 9, 8, 33, 32, 985fae8b86SMika Westerberg 31, 30, 29, 27, 25, 28, 26, 23, 21, 20, 995fae8b86SMika Westerberg 24, 22, 5, 3, 10, 11, 106, 87, 91, 104, 1005fae8b86SMika Westerberg 97, 100, 1015fae8b86SMika Westerberg }; 1025fae8b86SMika Westerberg 1035fae8b86SMika Westerberg static unsigned const ncore_pins[BYT_NGPIO_NCORE] = { 1045fae8b86SMika Westerberg 19, 18, 17, 20, 21, 22, 24, 25, 23, 16, 1055fae8b86SMika Westerberg 14, 15, 12, 26, 27, 1, 4, 8, 11, 0, 1065fae8b86SMika Westerberg 3, 6, 10, 13, 2, 5, 9, 7, 1075fae8b86SMika Westerberg }; 1085fae8b86SMika Westerberg 1095fae8b86SMika Westerberg static unsigned const sus_pins[BYT_NGPIO_SUS] = { 1105fae8b86SMika Westerberg 29, 33, 30, 31, 32, 34, 36, 35, 38, 37, 1115fae8b86SMika Westerberg 18, 7, 11, 20, 17, 1, 8, 10, 19, 12, 1125fae8b86SMika Westerberg 0, 2, 23, 39, 28, 27, 22, 21, 24, 25, 1135fae8b86SMika Westerberg 26, 51, 56, 54, 49, 55, 48, 57, 50, 58, 1145fae8b86SMika Westerberg 52, 53, 59, 40, 1155fae8b86SMika Westerberg }; 1165fae8b86SMika Westerberg 1175fae8b86SMika Westerberg static struct pinctrl_gpio_range byt_ranges[] = { 1185fae8b86SMika Westerberg { 1195fae8b86SMika Westerberg .name = BYT_SCORE_ACPI_UID, /* match with acpi _UID in probe */ 1205fae8b86SMika Westerberg .npins = BYT_NGPIO_SCORE, 1215fae8b86SMika Westerberg .pins = score_pins, 1225fae8b86SMika Westerberg }, 1235fae8b86SMika Westerberg { 1245fae8b86SMika Westerberg .name = BYT_NCORE_ACPI_UID, 1255fae8b86SMika Westerberg .npins = BYT_NGPIO_NCORE, 1265fae8b86SMika Westerberg .pins = ncore_pins, 1275fae8b86SMika Westerberg }, 1285fae8b86SMika Westerberg { 1295fae8b86SMika Westerberg .name = BYT_SUS_ACPI_UID, 1305fae8b86SMika Westerberg .npins = BYT_NGPIO_SUS, 1315fae8b86SMika Westerberg .pins = sus_pins, 1325fae8b86SMika Westerberg }, 1335fae8b86SMika Westerberg { 1345fae8b86SMika Westerberg }, 1355fae8b86SMika Westerberg }; 1365fae8b86SMika Westerberg 1375fae8b86SMika Westerberg struct byt_gpio { 1385fae8b86SMika Westerberg struct gpio_chip chip; 1395fae8b86SMika Westerberg struct platform_device *pdev; 1405fae8b86SMika Westerberg spinlock_t lock; 1415fae8b86SMika Westerberg void __iomem *reg_base; 1425fae8b86SMika Westerberg struct pinctrl_gpio_range *range; 1435fae8b86SMika Westerberg }; 1445fae8b86SMika Westerberg 1455fae8b86SMika Westerberg #define to_byt_gpio(c) container_of(c, struct byt_gpio, chip) 1465fae8b86SMika Westerberg 1475fae8b86SMika Westerberg static void __iomem *byt_gpio_reg(struct gpio_chip *chip, unsigned offset, 1485fae8b86SMika Westerberg int reg) 1495fae8b86SMika Westerberg { 1505fae8b86SMika Westerberg struct byt_gpio *vg = to_byt_gpio(chip); 1515fae8b86SMika Westerberg u32 reg_offset; 1525fae8b86SMika Westerberg 1535fae8b86SMika Westerberg if (reg == BYT_INT_STAT_REG) 1545fae8b86SMika Westerberg reg_offset = (offset / 32) * 4; 1555fae8b86SMika Westerberg else 1565fae8b86SMika Westerberg reg_offset = vg->range->pins[offset] * 16; 1575fae8b86SMika Westerberg 1585fae8b86SMika Westerberg return vg->reg_base + reg_offset + reg; 1595fae8b86SMika Westerberg } 1605fae8b86SMika Westerberg 161f8323b6bSMika Westerberg static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned offset) 1625fae8b86SMika Westerberg { 1635fae8b86SMika Westerberg /* SCORE pin 92-93 */ 1645fae8b86SMika Westerberg if (!strcmp(vg->range->name, BYT_SCORE_ACPI_UID) && 1655fae8b86SMika Westerberg offset >= 92 && offset <= 93) 166f8323b6bSMika Westerberg return 1; 1675fae8b86SMika Westerberg 1685fae8b86SMika Westerberg /* SUS pin 11-21 */ 1695fae8b86SMika Westerberg if (!strcmp(vg->range->name, BYT_SUS_ACPI_UID) && 1705fae8b86SMika Westerberg offset >= 11 && offset <= 21) 171f8323b6bSMika Westerberg return 1; 1725fae8b86SMika Westerberg 173f8323b6bSMika Westerberg return 0; 1745fae8b86SMika Westerberg } 1755fae8b86SMika Westerberg 1765fae8b86SMika Westerberg static int byt_gpio_request(struct gpio_chip *chip, unsigned offset) 1775fae8b86SMika Westerberg { 1785fae8b86SMika Westerberg struct byt_gpio *vg = to_byt_gpio(chip); 1795fae8b86SMika Westerberg void __iomem *reg = byt_gpio_reg(chip, offset, BYT_CONF0_REG); 180f8323b6bSMika Westerberg u32 value, gpio_mux; 1815fae8b86SMika Westerberg 1825fae8b86SMika Westerberg /* 1835fae8b86SMika Westerberg * In most cases, func pin mux 000 means GPIO function. 1845fae8b86SMika Westerberg * But, some pins may have func pin mux 001 represents 185f8323b6bSMika Westerberg * GPIO function. 186f8323b6bSMika Westerberg * 187f8323b6bSMika Westerberg * Because there are devices out there where some pins were not 188f8323b6bSMika Westerberg * configured correctly we allow changing the mux value from 189f8323b6bSMika Westerberg * request (but print out warning about that). 1905fae8b86SMika Westerberg */ 1915fae8b86SMika Westerberg value = readl(reg) & BYT_PIN_MUX; 192f8323b6bSMika Westerberg gpio_mux = byt_get_gpio_mux(vg, offset); 193f8323b6bSMika Westerberg if (WARN_ON(gpio_mux != value)) { 194f8323b6bSMika Westerberg unsigned long flags; 195f8323b6bSMika Westerberg 196f8323b6bSMika Westerberg spin_lock_irqsave(&vg->lock, flags); 197f8323b6bSMika Westerberg value = readl(reg) & ~BYT_PIN_MUX; 198f8323b6bSMika Westerberg value |= gpio_mux; 199f8323b6bSMika Westerberg writel(value, reg); 200f8323b6bSMika Westerberg spin_unlock_irqrestore(&vg->lock, flags); 201f8323b6bSMika Westerberg 202f8323b6bSMika Westerberg dev_warn(&vg->pdev->dev, 203f8323b6bSMika Westerberg "pin %u forcibly re-configured as GPIO\n", offset); 2045fae8b86SMika Westerberg } 2055fae8b86SMika Westerberg 2065fae8b86SMika Westerberg pm_runtime_get(&vg->pdev->dev); 2075fae8b86SMika Westerberg 2085fae8b86SMika Westerberg return 0; 2095fae8b86SMika Westerberg } 2105fae8b86SMika Westerberg 2115fae8b86SMika Westerberg static void byt_gpio_free(struct gpio_chip *chip, unsigned offset) 2125fae8b86SMika Westerberg { 2135fae8b86SMika Westerberg struct byt_gpio *vg = to_byt_gpio(chip); 2145fae8b86SMika Westerberg void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG); 2155fae8b86SMika Westerberg u32 value; 2165fae8b86SMika Westerberg 2175fae8b86SMika Westerberg /* clear interrupt triggering */ 2185fae8b86SMika Westerberg value = readl(reg); 2195fae8b86SMika Westerberg value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL); 2205fae8b86SMika Westerberg writel(value, reg); 2215fae8b86SMika Westerberg 2225fae8b86SMika Westerberg pm_runtime_put(&vg->pdev->dev); 2235fae8b86SMika Westerberg } 2245fae8b86SMika Westerberg 2255fae8b86SMika Westerberg static int byt_irq_type(struct irq_data *d, unsigned type) 2265fae8b86SMika Westerberg { 2275fae8b86SMika Westerberg struct byt_gpio *vg = to_byt_gpio(irq_data_get_irq_chip_data(d)); 2285fae8b86SMika Westerberg u32 offset = irqd_to_hwirq(d); 2295fae8b86SMika Westerberg u32 value; 2305fae8b86SMika Westerberg unsigned long flags; 2315fae8b86SMika Westerberg void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG); 2325fae8b86SMika Westerberg 2335fae8b86SMika Westerberg if (offset >= vg->chip.ngpio) 2345fae8b86SMika Westerberg return -EINVAL; 2355fae8b86SMika Westerberg 2365fae8b86SMika Westerberg spin_lock_irqsave(&vg->lock, flags); 2375fae8b86SMika Westerberg value = readl(reg); 2385fae8b86SMika Westerberg 239c1b30e4dSLinus Torvalds WARN(value & BYT_DIRECT_IRQ_EN, 240c1b30e4dSLinus Torvalds "Bad pad config for io mode, force direct_irq_en bit clearing"); 241c1b30e4dSLinus Torvalds 2425fae8b86SMika Westerberg /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits 2435fae8b86SMika Westerberg * are used to indicate high and low level triggering 2445fae8b86SMika Westerberg */ 245c1b30e4dSLinus Torvalds value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG | 246c1b30e4dSLinus Torvalds BYT_TRIG_LVL); 2475fae8b86SMika Westerberg 2485fae8b86SMika Westerberg switch (type) { 2495fae8b86SMika Westerberg case IRQ_TYPE_LEVEL_HIGH: 2505fae8b86SMika Westerberg value |= BYT_TRIG_LVL; 2515fae8b86SMika Westerberg case IRQ_TYPE_EDGE_RISING: 2525fae8b86SMika Westerberg value |= BYT_TRIG_POS; 2535fae8b86SMika Westerberg break; 2545fae8b86SMika Westerberg case IRQ_TYPE_LEVEL_LOW: 2555fae8b86SMika Westerberg value |= BYT_TRIG_LVL; 2565fae8b86SMika Westerberg case IRQ_TYPE_EDGE_FALLING: 2575fae8b86SMika Westerberg value |= BYT_TRIG_NEG; 2585fae8b86SMika Westerberg break; 2595fae8b86SMika Westerberg case IRQ_TYPE_EDGE_BOTH: 2605fae8b86SMika Westerberg value |= (BYT_TRIG_NEG | BYT_TRIG_POS); 2615fae8b86SMika Westerberg break; 2625fae8b86SMika Westerberg } 2635fae8b86SMika Westerberg writel(value, reg); 2645fae8b86SMika Westerberg 2655fae8b86SMika Westerberg spin_unlock_irqrestore(&vg->lock, flags); 2665fae8b86SMika Westerberg 2675fae8b86SMika Westerberg return 0; 2685fae8b86SMika Westerberg } 2695fae8b86SMika Westerberg 2705fae8b86SMika Westerberg static int byt_gpio_get(struct gpio_chip *chip, unsigned offset) 2715fae8b86SMika Westerberg { 2725fae8b86SMika Westerberg void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG); 2735fae8b86SMika Westerberg return readl(reg) & BYT_LEVEL; 2745fae8b86SMika Westerberg } 2755fae8b86SMika Westerberg 2765fae8b86SMika Westerberg static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 2775fae8b86SMika Westerberg { 2785fae8b86SMika Westerberg struct byt_gpio *vg = to_byt_gpio(chip); 2795fae8b86SMika Westerberg void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG); 2805fae8b86SMika Westerberg unsigned long flags; 2815fae8b86SMika Westerberg u32 old_val; 2825fae8b86SMika Westerberg 2835fae8b86SMika Westerberg spin_lock_irqsave(&vg->lock, flags); 2845fae8b86SMika Westerberg 2855fae8b86SMika Westerberg old_val = readl(reg); 2865fae8b86SMika Westerberg 2875fae8b86SMika Westerberg if (value) 2885fae8b86SMika Westerberg writel(old_val | BYT_LEVEL, reg); 2895fae8b86SMika Westerberg else 2905fae8b86SMika Westerberg writel(old_val & ~BYT_LEVEL, reg); 2915fae8b86SMika Westerberg 2925fae8b86SMika Westerberg spin_unlock_irqrestore(&vg->lock, flags); 2935fae8b86SMika Westerberg } 2945fae8b86SMika Westerberg 2955fae8b86SMika Westerberg static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 2965fae8b86SMika Westerberg { 2975fae8b86SMika Westerberg struct byt_gpio *vg = to_byt_gpio(chip); 2985fae8b86SMika Westerberg void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG); 2995fae8b86SMika Westerberg unsigned long flags; 3005fae8b86SMika Westerberg u32 value; 3015fae8b86SMika Westerberg 3025fae8b86SMika Westerberg spin_lock_irqsave(&vg->lock, flags); 3035fae8b86SMika Westerberg 3045fae8b86SMika Westerberg value = readl(reg) | BYT_DIR_MASK; 3055fae8b86SMika Westerberg value &= ~BYT_INPUT_EN; /* active low */ 3065fae8b86SMika Westerberg writel(value, reg); 3075fae8b86SMika Westerberg 3085fae8b86SMika Westerberg spin_unlock_irqrestore(&vg->lock, flags); 3095fae8b86SMika Westerberg 3105fae8b86SMika Westerberg return 0; 3115fae8b86SMika Westerberg } 3125fae8b86SMika Westerberg 3135fae8b86SMika Westerberg static int byt_gpio_direction_output(struct gpio_chip *chip, 3145fae8b86SMika Westerberg unsigned gpio, int value) 3155fae8b86SMika Westerberg { 3165fae8b86SMika Westerberg struct byt_gpio *vg = to_byt_gpio(chip); 3175fae8b86SMika Westerberg void __iomem *conf_reg = byt_gpio_reg(chip, gpio, BYT_CONF0_REG); 3185fae8b86SMika Westerberg void __iomem *reg = byt_gpio_reg(chip, gpio, BYT_VAL_REG); 3195fae8b86SMika Westerberg unsigned long flags; 3205fae8b86SMika Westerberg u32 reg_val; 3215fae8b86SMika Westerberg 3225fae8b86SMika Westerberg spin_lock_irqsave(&vg->lock, flags); 3235fae8b86SMika Westerberg 3245fae8b86SMika Westerberg /* 3255fae8b86SMika Westerberg * Before making any direction modifications, do a check if gpio 3265fae8b86SMika Westerberg * is set for direct IRQ. On baytrail, setting GPIO to output does 3275fae8b86SMika Westerberg * not make sense, so let's at least warn the caller before they shoot 3285fae8b86SMika Westerberg * themselves in the foot. 3295fae8b86SMika Westerberg */ 3305fae8b86SMika Westerberg WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN, 3315fae8b86SMika Westerberg "Potential Error: Setting GPIO with direct_irq_en to output"); 3325fae8b86SMika Westerberg 3335fae8b86SMika Westerberg reg_val = readl(reg) | BYT_DIR_MASK; 334c1b30e4dSLinus Torvalds reg_val &= ~(BYT_OUTPUT_EN | BYT_INPUT_EN); 3355fae8b86SMika Westerberg 3365fae8b86SMika Westerberg if (value) 3375fae8b86SMika Westerberg writel(reg_val | BYT_LEVEL, reg); 3385fae8b86SMika Westerberg else 3395fae8b86SMika Westerberg writel(reg_val & ~BYT_LEVEL, reg); 3405fae8b86SMika Westerberg 3415fae8b86SMika Westerberg spin_unlock_irqrestore(&vg->lock, flags); 3425fae8b86SMika Westerberg 3435fae8b86SMika Westerberg return 0; 3445fae8b86SMika Westerberg } 3455fae8b86SMika Westerberg 3465fae8b86SMika Westerberg static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 3475fae8b86SMika Westerberg { 3485fae8b86SMika Westerberg struct byt_gpio *vg = to_byt_gpio(chip); 3495fae8b86SMika Westerberg int i; 3505fae8b86SMika Westerberg unsigned long flags; 3515fae8b86SMika Westerberg u32 conf0, val, offs; 3525fae8b86SMika Westerberg 3535fae8b86SMika Westerberg spin_lock_irqsave(&vg->lock, flags); 3545fae8b86SMika Westerberg 3555fae8b86SMika Westerberg for (i = 0; i < vg->chip.ngpio; i++) { 3565fae8b86SMika Westerberg const char *pull_str = NULL; 3575fae8b86SMika Westerberg const char *pull = NULL; 3585fae8b86SMika Westerberg const char *label; 3595fae8b86SMika Westerberg offs = vg->range->pins[i] * 16; 3605fae8b86SMika Westerberg conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG); 3615fae8b86SMika Westerberg val = readl(vg->reg_base + offs + BYT_VAL_REG); 3625fae8b86SMika Westerberg 3635fae8b86SMika Westerberg label = gpiochip_is_requested(chip, i); 3645fae8b86SMika Westerberg if (!label) 3655fae8b86SMika Westerberg label = "Unrequested"; 3665fae8b86SMika Westerberg 3675fae8b86SMika Westerberg switch (conf0 & BYT_PULL_ASSIGN_MASK) { 3685fae8b86SMika Westerberg case BYT_PULL_ASSIGN_UP: 3695fae8b86SMika Westerberg pull = "up"; 3705fae8b86SMika Westerberg break; 3715fae8b86SMika Westerberg case BYT_PULL_ASSIGN_DOWN: 3725fae8b86SMika Westerberg pull = "down"; 3735fae8b86SMika Westerberg break; 3745fae8b86SMika Westerberg } 3755fae8b86SMika Westerberg 3765fae8b86SMika Westerberg switch (conf0 & BYT_PULL_STR_MASK) { 3775fae8b86SMika Westerberg case BYT_PULL_STR_2K: 3785fae8b86SMika Westerberg pull_str = "2k"; 3795fae8b86SMika Westerberg break; 3805fae8b86SMika Westerberg case BYT_PULL_STR_10K: 3815fae8b86SMika Westerberg pull_str = "10k"; 3825fae8b86SMika Westerberg break; 3835fae8b86SMika Westerberg case BYT_PULL_STR_20K: 3845fae8b86SMika Westerberg pull_str = "20k"; 3855fae8b86SMika Westerberg break; 3865fae8b86SMika Westerberg case BYT_PULL_STR_40K: 3875fae8b86SMika Westerberg pull_str = "40k"; 3885fae8b86SMika Westerberg break; 3895fae8b86SMika Westerberg } 3905fae8b86SMika Westerberg 3915fae8b86SMika Westerberg seq_printf(s, 3925fae8b86SMika Westerberg " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s", 3935fae8b86SMika Westerberg i, 3945fae8b86SMika Westerberg label, 3955fae8b86SMika Westerberg val & BYT_INPUT_EN ? " " : "in", 3965fae8b86SMika Westerberg val & BYT_OUTPUT_EN ? " " : "out", 3975fae8b86SMika Westerberg val & BYT_LEVEL ? "hi" : "lo", 3985fae8b86SMika Westerberg vg->range->pins[i], offs, 3995fae8b86SMika Westerberg conf0 & 0x7, 4005fae8b86SMika Westerberg conf0 & BYT_TRIG_NEG ? " fall" : " ", 4015fae8b86SMika Westerberg conf0 & BYT_TRIG_POS ? " rise" : " ", 4025fae8b86SMika Westerberg conf0 & BYT_TRIG_LVL ? " level" : " "); 4035fae8b86SMika Westerberg 4045fae8b86SMika Westerberg if (pull && pull_str) 4055fae8b86SMika Westerberg seq_printf(s, " %-4s %-3s", pull, pull_str); 4065fae8b86SMika Westerberg else 4075fae8b86SMika Westerberg seq_puts(s, " "); 4085fae8b86SMika Westerberg 4095fae8b86SMika Westerberg if (conf0 & BYT_IODEN) 4105fae8b86SMika Westerberg seq_puts(s, " open-drain"); 4115fae8b86SMika Westerberg 4125fae8b86SMika Westerberg seq_puts(s, "\n"); 4135fae8b86SMika Westerberg } 4145fae8b86SMika Westerberg spin_unlock_irqrestore(&vg->lock, flags); 4155fae8b86SMika Westerberg } 4165fae8b86SMika Westerberg 4175fae8b86SMika Westerberg static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc) 4185fae8b86SMika Westerberg { 4195fae8b86SMika Westerberg struct irq_data *data = irq_desc_get_irq_data(desc); 4205fae8b86SMika Westerberg struct byt_gpio *vg = to_byt_gpio(irq_desc_get_handler_data(desc)); 4215fae8b86SMika Westerberg struct irq_chip *chip = irq_data_get_irq_chip(data); 4225fae8b86SMika Westerberg u32 base, pin, mask; 4235fae8b86SMika Westerberg void __iomem *reg; 4245fae8b86SMika Westerberg u32 pending; 4255fae8b86SMika Westerberg unsigned virq; 4265fae8b86SMika Westerberg int looplimit = 0; 4275fae8b86SMika Westerberg 4285fae8b86SMika Westerberg /* check from GPIO controller which pin triggered the interrupt */ 4295fae8b86SMika Westerberg for (base = 0; base < vg->chip.ngpio; base += 32) { 4305fae8b86SMika Westerberg 4315fae8b86SMika Westerberg reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG); 4325fae8b86SMika Westerberg 4335fae8b86SMika Westerberg while ((pending = readl(reg))) { 4345fae8b86SMika Westerberg pin = __ffs(pending); 4355fae8b86SMika Westerberg mask = BIT(pin); 4365fae8b86SMika Westerberg /* Clear before handling so we can't lose an edge */ 4375fae8b86SMika Westerberg writel(mask, reg); 4385fae8b86SMika Westerberg 4395fae8b86SMika Westerberg virq = irq_find_mapping(vg->chip.irqdomain, base + pin); 4405fae8b86SMika Westerberg generic_handle_irq(virq); 4415fae8b86SMika Westerberg 4425fae8b86SMika Westerberg /* In case bios or user sets triggering incorretly a pin 4435fae8b86SMika Westerberg * might remain in "interrupt triggered" state. 4445fae8b86SMika Westerberg */ 4455fae8b86SMika Westerberg if (looplimit++ > 32) { 4465fae8b86SMika Westerberg dev_err(&vg->pdev->dev, 4475fae8b86SMika Westerberg "Gpio %d interrupt flood, disabling\n", 4485fae8b86SMika Westerberg base + pin); 4495fae8b86SMika Westerberg 4505fae8b86SMika Westerberg reg = byt_gpio_reg(&vg->chip, base + pin, 4515fae8b86SMika Westerberg BYT_CONF0_REG); 4525fae8b86SMika Westerberg mask = readl(reg); 4535fae8b86SMika Westerberg mask &= ~(BYT_TRIG_NEG | BYT_TRIG_POS | 4545fae8b86SMika Westerberg BYT_TRIG_LVL); 4555fae8b86SMika Westerberg writel(mask, reg); 4565fae8b86SMika Westerberg mask = readl(reg); /* flush */ 4575fae8b86SMika Westerberg break; 4585fae8b86SMika Westerberg } 4595fae8b86SMika Westerberg } 4605fae8b86SMika Westerberg } 4615fae8b86SMika Westerberg chip->irq_eoi(data); 4625fae8b86SMika Westerberg } 4635fae8b86SMika Westerberg 4645fae8b86SMika Westerberg static void byt_irq_unmask(struct irq_data *d) 4655fae8b86SMika Westerberg { 4665fae8b86SMika Westerberg } 4675fae8b86SMika Westerberg 4685fae8b86SMika Westerberg static void byt_irq_mask(struct irq_data *d) 4695fae8b86SMika Westerberg { 4705fae8b86SMika Westerberg } 4715fae8b86SMika Westerberg 4725fae8b86SMika Westerberg static struct irq_chip byt_irqchip = { 4735fae8b86SMika Westerberg .name = "BYT-GPIO", 4745fae8b86SMika Westerberg .irq_mask = byt_irq_mask, 4755fae8b86SMika Westerberg .irq_unmask = byt_irq_unmask, 4765fae8b86SMika Westerberg .irq_set_type = byt_irq_type, 4775fae8b86SMika Westerberg .flags = IRQCHIP_SKIP_SET_WAKE, 4785fae8b86SMika Westerberg }; 4795fae8b86SMika Westerberg 4805fae8b86SMika Westerberg static void byt_gpio_irq_init_hw(struct byt_gpio *vg) 4815fae8b86SMika Westerberg { 4825fae8b86SMika Westerberg void __iomem *reg; 4835fae8b86SMika Westerberg u32 base, value; 4845fae8b86SMika Westerberg 4855fae8b86SMika Westerberg /* clear interrupt status trigger registers */ 4865fae8b86SMika Westerberg for (base = 0; base < vg->chip.ngpio; base += 32) { 4875fae8b86SMika Westerberg reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG); 4885fae8b86SMika Westerberg writel(0xffffffff, reg); 4895fae8b86SMika Westerberg /* make sure trigger bits are cleared, if not then a pin 4905fae8b86SMika Westerberg might be misconfigured in bios */ 4915fae8b86SMika Westerberg value = readl(reg); 4925fae8b86SMika Westerberg if (value) 4935fae8b86SMika Westerberg dev_err(&vg->pdev->dev, 4945fae8b86SMika Westerberg "GPIO interrupt error, pins misconfigured\n"); 4955fae8b86SMika Westerberg } 4965fae8b86SMika Westerberg } 4975fae8b86SMika Westerberg 4985fae8b86SMika Westerberg static int byt_gpio_probe(struct platform_device *pdev) 4995fae8b86SMika Westerberg { 5005fae8b86SMika Westerberg struct byt_gpio *vg; 5015fae8b86SMika Westerberg struct gpio_chip *gc; 5025fae8b86SMika Westerberg struct resource *mem_rc, *irq_rc; 5035fae8b86SMika Westerberg struct device *dev = &pdev->dev; 5045fae8b86SMika Westerberg struct acpi_device *acpi_dev; 5055fae8b86SMika Westerberg struct pinctrl_gpio_range *range; 5065fae8b86SMika Westerberg acpi_handle handle = ACPI_HANDLE(dev); 5075fae8b86SMika Westerberg int ret; 5085fae8b86SMika Westerberg 5095fae8b86SMika Westerberg if (acpi_bus_get_device(handle, &acpi_dev)) 5105fae8b86SMika Westerberg return -ENODEV; 5115fae8b86SMika Westerberg 5125fae8b86SMika Westerberg vg = devm_kzalloc(dev, sizeof(struct byt_gpio), GFP_KERNEL); 5135fae8b86SMika Westerberg if (!vg) { 5145fae8b86SMika Westerberg dev_err(&pdev->dev, "can't allocate byt_gpio chip data\n"); 5155fae8b86SMika Westerberg return -ENOMEM; 5165fae8b86SMika Westerberg } 5175fae8b86SMika Westerberg 5185fae8b86SMika Westerberg for (range = byt_ranges; range->name; range++) { 5195fae8b86SMika Westerberg if (!strcmp(acpi_dev->pnp.unique_id, range->name)) { 5205fae8b86SMika Westerberg vg->chip.ngpio = range->npins; 5215fae8b86SMika Westerberg vg->range = range; 5225fae8b86SMika Westerberg break; 5235fae8b86SMika Westerberg } 5245fae8b86SMika Westerberg } 5255fae8b86SMika Westerberg 5265fae8b86SMika Westerberg if (!vg->chip.ngpio || !vg->range) 5275fae8b86SMika Westerberg return -ENODEV; 5285fae8b86SMika Westerberg 5295fae8b86SMika Westerberg vg->pdev = pdev; 5305fae8b86SMika Westerberg platform_set_drvdata(pdev, vg); 5315fae8b86SMika Westerberg 5325fae8b86SMika Westerberg mem_rc = platform_get_resource(pdev, IORESOURCE_MEM, 0); 5335fae8b86SMika Westerberg vg->reg_base = devm_ioremap_resource(dev, mem_rc); 5345fae8b86SMika Westerberg if (IS_ERR(vg->reg_base)) 5355fae8b86SMika Westerberg return PTR_ERR(vg->reg_base); 5365fae8b86SMika Westerberg 5375fae8b86SMika Westerberg spin_lock_init(&vg->lock); 5385fae8b86SMika Westerberg 5395fae8b86SMika Westerberg gc = &vg->chip; 5405fae8b86SMika Westerberg gc->label = dev_name(&pdev->dev); 5415fae8b86SMika Westerberg gc->owner = THIS_MODULE; 5425fae8b86SMika Westerberg gc->request = byt_gpio_request; 5435fae8b86SMika Westerberg gc->free = byt_gpio_free; 5445fae8b86SMika Westerberg gc->direction_input = byt_gpio_direction_input; 5455fae8b86SMika Westerberg gc->direction_output = byt_gpio_direction_output; 5465fae8b86SMika Westerberg gc->get = byt_gpio_get; 5475fae8b86SMika Westerberg gc->set = byt_gpio_set; 5485fae8b86SMika Westerberg gc->dbg_show = byt_gpio_dbg_show; 5495fae8b86SMika Westerberg gc->base = -1; 5505fae8b86SMika Westerberg gc->can_sleep = false; 5515fae8b86SMika Westerberg gc->dev = dev; 5525fae8b86SMika Westerberg 5535fae8b86SMika Westerberg ret = gpiochip_add(gc); 5545fae8b86SMika Westerberg if (ret) { 5555fae8b86SMika Westerberg dev_err(&pdev->dev, "failed adding byt-gpio chip\n"); 5565fae8b86SMika Westerberg return ret; 5575fae8b86SMika Westerberg } 5585fae8b86SMika Westerberg 5595fae8b86SMika Westerberg /* set up interrupts */ 5605fae8b86SMika Westerberg irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 5615fae8b86SMika Westerberg if (irq_rc && irq_rc->start) { 5625fae8b86SMika Westerberg byt_gpio_irq_init_hw(vg); 5635fae8b86SMika Westerberg ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0, 5645fae8b86SMika Westerberg handle_simple_irq, IRQ_TYPE_NONE); 5655fae8b86SMika Westerberg if (ret) { 5665fae8b86SMika Westerberg dev_err(dev, "failed to add irqchip\n"); 5675fae8b86SMika Westerberg gpiochip_remove(gc); 5685fae8b86SMika Westerberg return ret; 5695fae8b86SMika Westerberg } 5705fae8b86SMika Westerberg 5715fae8b86SMika Westerberg gpiochip_set_chained_irqchip(gc, &byt_irqchip, 5725fae8b86SMika Westerberg (unsigned)irq_rc->start, 5735fae8b86SMika Westerberg byt_gpio_irq_handler); 5745fae8b86SMika Westerberg } 5755fae8b86SMika Westerberg 5765fae8b86SMika Westerberg pm_runtime_enable(dev); 5775fae8b86SMika Westerberg 5785fae8b86SMika Westerberg return 0; 5795fae8b86SMika Westerberg } 5805fae8b86SMika Westerberg 5815fae8b86SMika Westerberg static int byt_gpio_runtime_suspend(struct device *dev) 5825fae8b86SMika Westerberg { 5835fae8b86SMika Westerberg return 0; 5845fae8b86SMika Westerberg } 5855fae8b86SMika Westerberg 5865fae8b86SMika Westerberg static int byt_gpio_runtime_resume(struct device *dev) 5875fae8b86SMika Westerberg { 5885fae8b86SMika Westerberg return 0; 5895fae8b86SMika Westerberg } 5905fae8b86SMika Westerberg 5915fae8b86SMika Westerberg static const struct dev_pm_ops byt_gpio_pm_ops = { 5925fae8b86SMika Westerberg .runtime_suspend = byt_gpio_runtime_suspend, 5935fae8b86SMika Westerberg .runtime_resume = byt_gpio_runtime_resume, 5945fae8b86SMika Westerberg }; 5955fae8b86SMika Westerberg 5965fae8b86SMika Westerberg static const struct acpi_device_id byt_gpio_acpi_match[] = { 5975fae8b86SMika Westerberg { "INT33B2", 0 }, 5985fae8b86SMika Westerberg { "INT33FC", 0 }, 5995fae8b86SMika Westerberg { } 6005fae8b86SMika Westerberg }; 6015fae8b86SMika Westerberg MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match); 6025fae8b86SMika Westerberg 6035fae8b86SMika Westerberg static int byt_gpio_remove(struct platform_device *pdev) 6045fae8b86SMika Westerberg { 6055fae8b86SMika Westerberg struct byt_gpio *vg = platform_get_drvdata(pdev); 6065fae8b86SMika Westerberg 6075fae8b86SMika Westerberg pm_runtime_disable(&pdev->dev); 6085fae8b86SMika Westerberg gpiochip_remove(&vg->chip); 6095fae8b86SMika Westerberg 6105fae8b86SMika Westerberg return 0; 6115fae8b86SMika Westerberg } 6125fae8b86SMika Westerberg 6135fae8b86SMika Westerberg static struct platform_driver byt_gpio_driver = { 6145fae8b86SMika Westerberg .probe = byt_gpio_probe, 6155fae8b86SMika Westerberg .remove = byt_gpio_remove, 6165fae8b86SMika Westerberg .driver = { 6175fae8b86SMika Westerberg .name = "byt_gpio", 6185fae8b86SMika Westerberg .pm = &byt_gpio_pm_ops, 6195fae8b86SMika Westerberg .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match), 6205fae8b86SMika Westerberg }, 6215fae8b86SMika Westerberg }; 6225fae8b86SMika Westerberg 6235fae8b86SMika Westerberg static int __init byt_gpio_init(void) 6245fae8b86SMika Westerberg { 6255fae8b86SMika Westerberg return platform_driver_register(&byt_gpio_driver); 6265fae8b86SMika Westerberg } 6275fae8b86SMika Westerberg subsys_initcall(byt_gpio_init); 6285fae8b86SMika Westerberg 6295fae8b86SMika Westerberg static void __exit byt_gpio_exit(void) 6305fae8b86SMika Westerberg { 6315fae8b86SMika Westerberg platform_driver_unregister(&byt_gpio_driver); 6325fae8b86SMika Westerberg } 6335fae8b86SMika Westerberg module_exit(byt_gpio_exit); 634