15fae8b86SMika Westerberg /* 25fae8b86SMika Westerberg * Pinctrl GPIO driver for Intel Baytrail 35fae8b86SMika Westerberg * Copyright (c) 2012-2013, Intel Corporation. 45fae8b86SMika Westerberg * 55fae8b86SMika Westerberg * Author: Mathias Nyman <mathias.nyman@linux.intel.com> 65fae8b86SMika Westerberg * 75fae8b86SMika Westerberg * This program is free software; you can redistribute it and/or modify it 85fae8b86SMika Westerberg * under the terms and conditions of the GNU General Public License, 95fae8b86SMika Westerberg * version 2, as published by the Free Software Foundation. 105fae8b86SMika Westerberg * 115fae8b86SMika Westerberg * This program is distributed in the hope it will be useful, but WITHOUT 125fae8b86SMika Westerberg * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 135fae8b86SMika Westerberg * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 145fae8b86SMika Westerberg * more details. 155fae8b86SMika Westerberg */ 165fae8b86SMika Westerberg 175fae8b86SMika Westerberg #include <linux/kernel.h> 185fae8b86SMika Westerberg #include <linux/module.h> 195fae8b86SMika Westerberg #include <linux/init.h> 205fae8b86SMika Westerberg #include <linux/types.h> 215fae8b86SMika Westerberg #include <linux/bitops.h> 225fae8b86SMika Westerberg #include <linux/interrupt.h> 235fae8b86SMika Westerberg #include <linux/gpio.h> 245fae8b86SMika Westerberg #include <linux/acpi.h> 255fae8b86SMika Westerberg #include <linux/platform_device.h> 265fae8b86SMika Westerberg #include <linux/seq_file.h> 275fae8b86SMika Westerberg #include <linux/io.h> 285fae8b86SMika Westerberg #include <linux/pm_runtime.h> 295fae8b86SMika Westerberg #include <linux/pinctrl/pinctrl.h> 305fae8b86SMika Westerberg 315fae8b86SMika Westerberg /* memory mapped register offsets */ 325fae8b86SMika Westerberg #define BYT_CONF0_REG 0x000 335fae8b86SMika Westerberg #define BYT_CONF1_REG 0x004 345fae8b86SMika Westerberg #define BYT_VAL_REG 0x008 355fae8b86SMika Westerberg #define BYT_DFT_REG 0x00c 365fae8b86SMika Westerberg #define BYT_INT_STAT_REG 0x800 375fae8b86SMika Westerberg 385fae8b86SMika Westerberg /* BYT_CONF0_REG register bits */ 395fae8b86SMika Westerberg #define BYT_IODEN BIT(31) 405fae8b86SMika Westerberg #define BYT_DIRECT_IRQ_EN BIT(27) 415fae8b86SMika Westerberg #define BYT_TRIG_NEG BIT(26) 425fae8b86SMika Westerberg #define BYT_TRIG_POS BIT(25) 435fae8b86SMika Westerberg #define BYT_TRIG_LVL BIT(24) 445fae8b86SMika Westerberg #define BYT_PULL_STR_SHIFT 9 455fae8b86SMika Westerberg #define BYT_PULL_STR_MASK (3 << BYT_PULL_STR_SHIFT) 465fae8b86SMika Westerberg #define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT) 475fae8b86SMika Westerberg #define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT) 485fae8b86SMika Westerberg #define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT) 495fae8b86SMika Westerberg #define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT) 505fae8b86SMika Westerberg #define BYT_PULL_ASSIGN_SHIFT 7 515fae8b86SMika Westerberg #define BYT_PULL_ASSIGN_MASK (3 << BYT_PULL_ASSIGN_SHIFT) 525fae8b86SMika Westerberg #define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT) 535fae8b86SMika Westerberg #define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT) 545fae8b86SMika Westerberg #define BYT_PIN_MUX 0x07 555fae8b86SMika Westerberg 565fae8b86SMika Westerberg /* BYT_VAL_REG register bits */ 575fae8b86SMika Westerberg #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/ 585fae8b86SMika Westerberg #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/ 595fae8b86SMika Westerberg #define BYT_LEVEL BIT(0) 605fae8b86SMika Westerberg 615fae8b86SMika Westerberg #define BYT_DIR_MASK (BIT(1) | BIT(2)) 625fae8b86SMika Westerberg #define BYT_TRIG_MASK (BIT(26) | BIT(25) | BIT(24)) 635fae8b86SMika Westerberg 64fcc18debSMika Westerberg #define BYT_CONF0_RESTORE_MASK (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | \ 65fcc18debSMika Westerberg BYT_PIN_MUX) 66fcc18debSMika Westerberg #define BYT_VAL_RESTORE_MASK (BYT_DIR_MASK | BYT_LEVEL) 67fcc18debSMika Westerberg 685fae8b86SMika Westerberg #define BYT_NGPIO_SCORE 102 695fae8b86SMika Westerberg #define BYT_NGPIO_NCORE 28 705fae8b86SMika Westerberg #define BYT_NGPIO_SUS 44 715fae8b86SMika Westerberg 725fae8b86SMika Westerberg #define BYT_SCORE_ACPI_UID "1" 735fae8b86SMika Westerberg #define BYT_NCORE_ACPI_UID "2" 745fae8b86SMika Westerberg #define BYT_SUS_ACPI_UID "3" 755fae8b86SMika Westerberg 765fae8b86SMika Westerberg /* 775fae8b86SMika Westerberg * Baytrail gpio controller consist of three separate sub-controllers called 785fae8b86SMika Westerberg * SCORE, NCORE and SUS. The sub-controllers are identified by their acpi UID. 795fae8b86SMika Westerberg * 805fae8b86SMika Westerberg * GPIO numbering is _not_ ordered meaning that gpio # 0 in ACPI namespace does 815fae8b86SMika Westerberg * _not_ correspond to the first gpio register at controller's gpio base. 825fae8b86SMika Westerberg * There is no logic or pattern in mapping gpio numbers to registers (pads) so 835fae8b86SMika Westerberg * each sub-controller needs to have its own mapping table 845fae8b86SMika Westerberg */ 855fae8b86SMika Westerberg 865fae8b86SMika Westerberg /* score_pins[gpio_nr] = pad_nr */ 875fae8b86SMika Westerberg 885fae8b86SMika Westerberg static unsigned const score_pins[BYT_NGPIO_SCORE] = { 895fae8b86SMika Westerberg 85, 89, 93, 96, 99, 102, 98, 101, 34, 37, 905fae8b86SMika Westerberg 36, 38, 39, 35, 40, 84, 62, 61, 64, 59, 915fae8b86SMika Westerberg 54, 56, 60, 55, 63, 57, 51, 50, 53, 47, 925fae8b86SMika Westerberg 52, 49, 48, 43, 46, 41, 45, 42, 58, 44, 935fae8b86SMika Westerberg 95, 105, 70, 68, 67, 66, 69, 71, 65, 72, 945fae8b86SMika Westerberg 86, 90, 88, 92, 103, 77, 79, 83, 78, 81, 955fae8b86SMika Westerberg 80, 82, 13, 12, 15, 14, 17, 18, 19, 16, 965fae8b86SMika Westerberg 2, 1, 0, 4, 6, 7, 9, 8, 33, 32, 975fae8b86SMika Westerberg 31, 30, 29, 27, 25, 28, 26, 23, 21, 20, 985fae8b86SMika Westerberg 24, 22, 5, 3, 10, 11, 106, 87, 91, 104, 995fae8b86SMika Westerberg 97, 100, 1005fae8b86SMika Westerberg }; 1015fae8b86SMika Westerberg 1025fae8b86SMika Westerberg static unsigned const ncore_pins[BYT_NGPIO_NCORE] = { 1035fae8b86SMika Westerberg 19, 18, 17, 20, 21, 22, 24, 25, 23, 16, 1045fae8b86SMika Westerberg 14, 15, 12, 26, 27, 1, 4, 8, 11, 0, 1055fae8b86SMika Westerberg 3, 6, 10, 13, 2, 5, 9, 7, 1065fae8b86SMika Westerberg }; 1075fae8b86SMika Westerberg 1085fae8b86SMika Westerberg static unsigned const sus_pins[BYT_NGPIO_SUS] = { 1095fae8b86SMika Westerberg 29, 33, 30, 31, 32, 34, 36, 35, 38, 37, 1105fae8b86SMika Westerberg 18, 7, 11, 20, 17, 1, 8, 10, 19, 12, 1115fae8b86SMika Westerberg 0, 2, 23, 39, 28, 27, 22, 21, 24, 25, 1125fae8b86SMika Westerberg 26, 51, 56, 54, 49, 55, 48, 57, 50, 58, 1135fae8b86SMika Westerberg 52, 53, 59, 40, 1145fae8b86SMika Westerberg }; 1155fae8b86SMika Westerberg 1165fae8b86SMika Westerberg static struct pinctrl_gpio_range byt_ranges[] = { 1175fae8b86SMika Westerberg { 1185fae8b86SMika Westerberg .name = BYT_SCORE_ACPI_UID, /* match with acpi _UID in probe */ 1195fae8b86SMika Westerberg .npins = BYT_NGPIO_SCORE, 1205fae8b86SMika Westerberg .pins = score_pins, 1215fae8b86SMika Westerberg }, 1225fae8b86SMika Westerberg { 1235fae8b86SMika Westerberg .name = BYT_NCORE_ACPI_UID, 1245fae8b86SMika Westerberg .npins = BYT_NGPIO_NCORE, 1255fae8b86SMika Westerberg .pins = ncore_pins, 1265fae8b86SMika Westerberg }, 1275fae8b86SMika Westerberg { 1285fae8b86SMika Westerberg .name = BYT_SUS_ACPI_UID, 1295fae8b86SMika Westerberg .npins = BYT_NGPIO_SUS, 1305fae8b86SMika Westerberg .pins = sus_pins, 1315fae8b86SMika Westerberg }, 1325fae8b86SMika Westerberg { 1335fae8b86SMika Westerberg }, 1345fae8b86SMika Westerberg }; 1355fae8b86SMika Westerberg 136fcc18debSMika Westerberg struct byt_gpio_pin_context { 137fcc18debSMika Westerberg u32 conf0; 138fcc18debSMika Westerberg u32 val; 139fcc18debSMika Westerberg }; 140fcc18debSMika Westerberg 1415fae8b86SMika Westerberg struct byt_gpio { 1425fae8b86SMika Westerberg struct gpio_chip chip; 1435fae8b86SMika Westerberg struct platform_device *pdev; 14478e1c896SMika Westerberg raw_spinlock_t lock; 1455fae8b86SMika Westerberg void __iomem *reg_base; 1465fae8b86SMika Westerberg struct pinctrl_gpio_range *range; 147fcc18debSMika Westerberg struct byt_gpio_pin_context *saved_context; 1485fae8b86SMika Westerberg }; 1495fae8b86SMika Westerberg 1505fae8b86SMika Westerberg #define to_byt_gpio(c) container_of(c, struct byt_gpio, chip) 1515fae8b86SMika Westerberg 1525fae8b86SMika Westerberg static void __iomem *byt_gpio_reg(struct gpio_chip *chip, unsigned offset, 1535fae8b86SMika Westerberg int reg) 1545fae8b86SMika Westerberg { 1555fae8b86SMika Westerberg struct byt_gpio *vg = to_byt_gpio(chip); 1565fae8b86SMika Westerberg u32 reg_offset; 1575fae8b86SMika Westerberg 1585fae8b86SMika Westerberg if (reg == BYT_INT_STAT_REG) 1595fae8b86SMika Westerberg reg_offset = (offset / 32) * 4; 1605fae8b86SMika Westerberg else 1615fae8b86SMika Westerberg reg_offset = vg->range->pins[offset] * 16; 1625fae8b86SMika Westerberg 1635fae8b86SMika Westerberg return vg->reg_base + reg_offset + reg; 1645fae8b86SMika Westerberg } 1655fae8b86SMika Westerberg 16695f0972cSMika Westerberg static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned offset) 16795f0972cSMika Westerberg { 16895f0972cSMika Westerberg void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG); 16995f0972cSMika Westerberg unsigned long flags; 17095f0972cSMika Westerberg u32 value; 17195f0972cSMika Westerberg 17278e1c896SMika Westerberg raw_spin_lock_irqsave(&vg->lock, flags); 17395f0972cSMika Westerberg value = readl(reg); 17495f0972cSMika Westerberg value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL); 17595f0972cSMika Westerberg writel(value, reg); 17678e1c896SMika Westerberg raw_spin_unlock_irqrestore(&vg->lock, flags); 17795f0972cSMika Westerberg } 17895f0972cSMika Westerberg 179f8323b6bSMika Westerberg static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned offset) 1805fae8b86SMika Westerberg { 1815fae8b86SMika Westerberg /* SCORE pin 92-93 */ 1825fae8b86SMika Westerberg if (!strcmp(vg->range->name, BYT_SCORE_ACPI_UID) && 1835fae8b86SMika Westerberg offset >= 92 && offset <= 93) 184f8323b6bSMika Westerberg return 1; 1855fae8b86SMika Westerberg 1865fae8b86SMika Westerberg /* SUS pin 11-21 */ 1875fae8b86SMika Westerberg if (!strcmp(vg->range->name, BYT_SUS_ACPI_UID) && 1885fae8b86SMika Westerberg offset >= 11 && offset <= 21) 189f8323b6bSMika Westerberg return 1; 1905fae8b86SMika Westerberg 191f8323b6bSMika Westerberg return 0; 1925fae8b86SMika Westerberg } 1935fae8b86SMika Westerberg 1945fae8b86SMika Westerberg static int byt_gpio_request(struct gpio_chip *chip, unsigned offset) 1955fae8b86SMika Westerberg { 1965fae8b86SMika Westerberg struct byt_gpio *vg = to_byt_gpio(chip); 1975fae8b86SMika Westerberg void __iomem *reg = byt_gpio_reg(chip, offset, BYT_CONF0_REG); 198f8323b6bSMika Westerberg u32 value, gpio_mux; 19939ce8150SMika Westerberg unsigned long flags; 20039ce8150SMika Westerberg 20178e1c896SMika Westerberg raw_spin_lock_irqsave(&vg->lock, flags); 2025fae8b86SMika Westerberg 2035fae8b86SMika Westerberg /* 2045fae8b86SMika Westerberg * In most cases, func pin mux 000 means GPIO function. 2055fae8b86SMika Westerberg * But, some pins may have func pin mux 001 represents 206f8323b6bSMika Westerberg * GPIO function. 207f8323b6bSMika Westerberg * 208f8323b6bSMika Westerberg * Because there are devices out there where some pins were not 209f8323b6bSMika Westerberg * configured correctly we allow changing the mux value from 210f8323b6bSMika Westerberg * request (but print out warning about that). 2115fae8b86SMika Westerberg */ 2125fae8b86SMika Westerberg value = readl(reg) & BYT_PIN_MUX; 213f8323b6bSMika Westerberg gpio_mux = byt_get_gpio_mux(vg, offset); 214f8323b6bSMika Westerberg if (WARN_ON(gpio_mux != value)) { 215f8323b6bSMika Westerberg value = readl(reg) & ~BYT_PIN_MUX; 216f8323b6bSMika Westerberg value |= gpio_mux; 217f8323b6bSMika Westerberg writel(value, reg); 218f8323b6bSMika Westerberg 219f8323b6bSMika Westerberg dev_warn(&vg->pdev->dev, 220f8323b6bSMika Westerberg "pin %u forcibly re-configured as GPIO\n", offset); 2215fae8b86SMika Westerberg } 2225fae8b86SMika Westerberg 22378e1c896SMika Westerberg raw_spin_unlock_irqrestore(&vg->lock, flags); 22439ce8150SMika Westerberg 2255fae8b86SMika Westerberg pm_runtime_get(&vg->pdev->dev); 2265fae8b86SMika Westerberg 2275fae8b86SMika Westerberg return 0; 2285fae8b86SMika Westerberg } 2295fae8b86SMika Westerberg 2305fae8b86SMika Westerberg static void byt_gpio_free(struct gpio_chip *chip, unsigned offset) 2315fae8b86SMika Westerberg { 2325fae8b86SMika Westerberg struct byt_gpio *vg = to_byt_gpio(chip); 2335fae8b86SMika Westerberg 23495f0972cSMika Westerberg byt_gpio_clear_triggering(vg, offset); 2355fae8b86SMika Westerberg pm_runtime_put(&vg->pdev->dev); 2365fae8b86SMika Westerberg } 2375fae8b86SMika Westerberg 2385fae8b86SMika Westerberg static int byt_irq_type(struct irq_data *d, unsigned type) 2395fae8b86SMika Westerberg { 2405fae8b86SMika Westerberg struct byt_gpio *vg = to_byt_gpio(irq_data_get_irq_chip_data(d)); 2415fae8b86SMika Westerberg u32 offset = irqd_to_hwirq(d); 2425fae8b86SMika Westerberg u32 value; 2435fae8b86SMika Westerberg unsigned long flags; 2445fae8b86SMika Westerberg void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG); 2455fae8b86SMika Westerberg 2465fae8b86SMika Westerberg if (offset >= vg->chip.ngpio) 2475fae8b86SMika Westerberg return -EINVAL; 2485fae8b86SMika Westerberg 24978e1c896SMika Westerberg raw_spin_lock_irqsave(&vg->lock, flags); 2505fae8b86SMika Westerberg value = readl(reg); 2515fae8b86SMika Westerberg 252c1b30e4dSLinus Torvalds WARN(value & BYT_DIRECT_IRQ_EN, 253c1b30e4dSLinus Torvalds "Bad pad config for io mode, force direct_irq_en bit clearing"); 254c1b30e4dSLinus Torvalds 2555fae8b86SMika Westerberg /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits 2565fae8b86SMika Westerberg * are used to indicate high and low level triggering 2575fae8b86SMika Westerberg */ 258c1b30e4dSLinus Torvalds value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG | 259c1b30e4dSLinus Torvalds BYT_TRIG_LVL); 2605fae8b86SMika Westerberg 2615fae8b86SMika Westerberg writel(value, reg); 2625fae8b86SMika Westerberg 26331e4329fSMika Westerberg if (type & IRQ_TYPE_EDGE_BOTH) 264f3a085b4SThomas Gleixner irq_set_handler_locked(d, handle_edge_irq); 26531e4329fSMika Westerberg else if (type & IRQ_TYPE_LEVEL_MASK) 266f3a085b4SThomas Gleixner irq_set_handler_locked(d, handle_level_irq); 26731e4329fSMika Westerberg 26878e1c896SMika Westerberg raw_spin_unlock_irqrestore(&vg->lock, flags); 2695fae8b86SMika Westerberg 2705fae8b86SMika Westerberg return 0; 2715fae8b86SMika Westerberg } 2725fae8b86SMika Westerberg 2735fae8b86SMika Westerberg static int byt_gpio_get(struct gpio_chip *chip, unsigned offset) 2745fae8b86SMika Westerberg { 2755fae8b86SMika Westerberg void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG); 27639ce8150SMika Westerberg struct byt_gpio *vg = to_byt_gpio(chip); 27739ce8150SMika Westerberg unsigned long flags; 27839ce8150SMika Westerberg u32 val; 27939ce8150SMika Westerberg 28078e1c896SMika Westerberg raw_spin_lock_irqsave(&vg->lock, flags); 28139ce8150SMika Westerberg val = readl(reg); 28278e1c896SMika Westerberg raw_spin_unlock_irqrestore(&vg->lock, flags); 28339ce8150SMika Westerberg 2843bde8771SLinus Walleij return !!(val & BYT_LEVEL); 2855fae8b86SMika Westerberg } 2865fae8b86SMika Westerberg 2875fae8b86SMika Westerberg static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 2885fae8b86SMika Westerberg { 2895fae8b86SMika Westerberg struct byt_gpio *vg = to_byt_gpio(chip); 2905fae8b86SMika Westerberg void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG); 2915fae8b86SMika Westerberg unsigned long flags; 2925fae8b86SMika Westerberg u32 old_val; 2935fae8b86SMika Westerberg 29478e1c896SMika Westerberg raw_spin_lock_irqsave(&vg->lock, flags); 2955fae8b86SMika Westerberg 2965fae8b86SMika Westerberg old_val = readl(reg); 2975fae8b86SMika Westerberg 2985fae8b86SMika Westerberg if (value) 2995fae8b86SMika Westerberg writel(old_val | BYT_LEVEL, reg); 3005fae8b86SMika Westerberg else 3015fae8b86SMika Westerberg writel(old_val & ~BYT_LEVEL, reg); 3025fae8b86SMika Westerberg 30378e1c896SMika Westerberg raw_spin_unlock_irqrestore(&vg->lock, flags); 3045fae8b86SMika Westerberg } 3055fae8b86SMika Westerberg 3065fae8b86SMika Westerberg static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 3075fae8b86SMika Westerberg { 3085fae8b86SMika Westerberg struct byt_gpio *vg = to_byt_gpio(chip); 3095fae8b86SMika Westerberg void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG); 3105fae8b86SMika Westerberg unsigned long flags; 3115fae8b86SMika Westerberg u32 value; 3125fae8b86SMika Westerberg 31378e1c896SMika Westerberg raw_spin_lock_irqsave(&vg->lock, flags); 3145fae8b86SMika Westerberg 3155fae8b86SMika Westerberg value = readl(reg) | BYT_DIR_MASK; 3165fae8b86SMika Westerberg value &= ~BYT_INPUT_EN; /* active low */ 3175fae8b86SMika Westerberg writel(value, reg); 3185fae8b86SMika Westerberg 31978e1c896SMika Westerberg raw_spin_unlock_irqrestore(&vg->lock, flags); 3205fae8b86SMika Westerberg 3215fae8b86SMika Westerberg return 0; 3225fae8b86SMika Westerberg } 3235fae8b86SMika Westerberg 3245fae8b86SMika Westerberg static int byt_gpio_direction_output(struct gpio_chip *chip, 3255fae8b86SMika Westerberg unsigned gpio, int value) 3265fae8b86SMika Westerberg { 3275fae8b86SMika Westerberg struct byt_gpio *vg = to_byt_gpio(chip); 3285fae8b86SMika Westerberg void __iomem *conf_reg = byt_gpio_reg(chip, gpio, BYT_CONF0_REG); 3295fae8b86SMika Westerberg void __iomem *reg = byt_gpio_reg(chip, gpio, BYT_VAL_REG); 3305fae8b86SMika Westerberg unsigned long flags; 3315fae8b86SMika Westerberg u32 reg_val; 3325fae8b86SMika Westerberg 33378e1c896SMika Westerberg raw_spin_lock_irqsave(&vg->lock, flags); 3345fae8b86SMika Westerberg 3355fae8b86SMika Westerberg /* 3365fae8b86SMika Westerberg * Before making any direction modifications, do a check if gpio 3375fae8b86SMika Westerberg * is set for direct IRQ. On baytrail, setting GPIO to output does 3385fae8b86SMika Westerberg * not make sense, so let's at least warn the caller before they shoot 3395fae8b86SMika Westerberg * themselves in the foot. 3405fae8b86SMika Westerberg */ 3415fae8b86SMika Westerberg WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN, 3425fae8b86SMika Westerberg "Potential Error: Setting GPIO with direct_irq_en to output"); 3435fae8b86SMika Westerberg 3445fae8b86SMika Westerberg reg_val = readl(reg) | BYT_DIR_MASK; 345c1b30e4dSLinus Torvalds reg_val &= ~(BYT_OUTPUT_EN | BYT_INPUT_EN); 3465fae8b86SMika Westerberg 3475fae8b86SMika Westerberg if (value) 3485fae8b86SMika Westerberg writel(reg_val | BYT_LEVEL, reg); 3495fae8b86SMika Westerberg else 3505fae8b86SMika Westerberg writel(reg_val & ~BYT_LEVEL, reg); 3515fae8b86SMika Westerberg 35278e1c896SMika Westerberg raw_spin_unlock_irqrestore(&vg->lock, flags); 3535fae8b86SMika Westerberg 3545fae8b86SMika Westerberg return 0; 3555fae8b86SMika Westerberg } 3565fae8b86SMika Westerberg 3575fae8b86SMika Westerberg static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 3585fae8b86SMika Westerberg { 3595fae8b86SMika Westerberg struct byt_gpio *vg = to_byt_gpio(chip); 3605fae8b86SMika Westerberg int i; 3615fae8b86SMika Westerberg u32 conf0, val, offs; 3625fae8b86SMika Westerberg 3635fae8b86SMika Westerberg for (i = 0; i < vg->chip.ngpio; i++) { 3645fae8b86SMika Westerberg const char *pull_str = NULL; 3655fae8b86SMika Westerberg const char *pull = NULL; 36678e1c896SMika Westerberg unsigned long flags; 3675fae8b86SMika Westerberg const char *label; 3685fae8b86SMika Westerberg offs = vg->range->pins[i] * 16; 36978e1c896SMika Westerberg 37078e1c896SMika Westerberg raw_spin_lock_irqsave(&vg->lock, flags); 3715fae8b86SMika Westerberg conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG); 3725fae8b86SMika Westerberg val = readl(vg->reg_base + offs + BYT_VAL_REG); 37378e1c896SMika Westerberg raw_spin_unlock_irqrestore(&vg->lock, flags); 3745fae8b86SMika Westerberg 3755fae8b86SMika Westerberg label = gpiochip_is_requested(chip, i); 3765fae8b86SMika Westerberg if (!label) 3775fae8b86SMika Westerberg label = "Unrequested"; 3785fae8b86SMika Westerberg 3795fae8b86SMika Westerberg switch (conf0 & BYT_PULL_ASSIGN_MASK) { 3805fae8b86SMika Westerberg case BYT_PULL_ASSIGN_UP: 3815fae8b86SMika Westerberg pull = "up"; 3825fae8b86SMika Westerberg break; 3835fae8b86SMika Westerberg case BYT_PULL_ASSIGN_DOWN: 3845fae8b86SMika Westerberg pull = "down"; 3855fae8b86SMika Westerberg break; 3865fae8b86SMika Westerberg } 3875fae8b86SMika Westerberg 3885fae8b86SMika Westerberg switch (conf0 & BYT_PULL_STR_MASK) { 3895fae8b86SMika Westerberg case BYT_PULL_STR_2K: 3905fae8b86SMika Westerberg pull_str = "2k"; 3915fae8b86SMika Westerberg break; 3925fae8b86SMika Westerberg case BYT_PULL_STR_10K: 3935fae8b86SMika Westerberg pull_str = "10k"; 3945fae8b86SMika Westerberg break; 3955fae8b86SMika Westerberg case BYT_PULL_STR_20K: 3965fae8b86SMika Westerberg pull_str = "20k"; 3975fae8b86SMika Westerberg break; 3985fae8b86SMika Westerberg case BYT_PULL_STR_40K: 3995fae8b86SMika Westerberg pull_str = "40k"; 4005fae8b86SMika Westerberg break; 4015fae8b86SMika Westerberg } 4025fae8b86SMika Westerberg 4035fae8b86SMika Westerberg seq_printf(s, 4045fae8b86SMika Westerberg " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s", 4055fae8b86SMika Westerberg i, 4065fae8b86SMika Westerberg label, 4075fae8b86SMika Westerberg val & BYT_INPUT_EN ? " " : "in", 4085fae8b86SMika Westerberg val & BYT_OUTPUT_EN ? " " : "out", 4095fae8b86SMika Westerberg val & BYT_LEVEL ? "hi" : "lo", 4105fae8b86SMika Westerberg vg->range->pins[i], offs, 4115fae8b86SMika Westerberg conf0 & 0x7, 4125fae8b86SMika Westerberg conf0 & BYT_TRIG_NEG ? " fall" : " ", 4135fae8b86SMika Westerberg conf0 & BYT_TRIG_POS ? " rise" : " ", 4145fae8b86SMika Westerberg conf0 & BYT_TRIG_LVL ? " level" : " "); 4155fae8b86SMika Westerberg 4165fae8b86SMika Westerberg if (pull && pull_str) 4175fae8b86SMika Westerberg seq_printf(s, " %-4s %-3s", pull, pull_str); 4185fae8b86SMika Westerberg else 4195fae8b86SMika Westerberg seq_puts(s, " "); 4205fae8b86SMika Westerberg 4215fae8b86SMika Westerberg if (conf0 & BYT_IODEN) 4225fae8b86SMika Westerberg seq_puts(s, " open-drain"); 4235fae8b86SMika Westerberg 4245fae8b86SMika Westerberg seq_puts(s, "\n"); 4255fae8b86SMika Westerberg } 4265fae8b86SMika Westerberg } 4275fae8b86SMika Westerberg 428bd0b9ac4SThomas Gleixner static void byt_gpio_irq_handler(struct irq_desc *desc) 4295fae8b86SMika Westerberg { 4305fae8b86SMika Westerberg struct irq_data *data = irq_desc_get_irq_data(desc); 4315fae8b86SMika Westerberg struct byt_gpio *vg = to_byt_gpio(irq_desc_get_handler_data(desc)); 4325fae8b86SMika Westerberg struct irq_chip *chip = irq_data_get_irq_chip(data); 43331e4329fSMika Westerberg u32 base, pin; 4345fae8b86SMika Westerberg void __iomem *reg; 43531e4329fSMika Westerberg unsigned long pending; 4365fae8b86SMika Westerberg unsigned virq; 4375fae8b86SMika Westerberg 4385fae8b86SMika Westerberg /* check from GPIO controller which pin triggered the interrupt */ 4395fae8b86SMika Westerberg for (base = 0; base < vg->chip.ngpio; base += 32) { 4405fae8b86SMika Westerberg reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG); 44131e4329fSMika Westerberg pending = readl(reg); 44231e4329fSMika Westerberg for_each_set_bit(pin, &pending, 32) { 4435fae8b86SMika Westerberg virq = irq_find_mapping(vg->chip.irqdomain, base + pin); 4445fae8b86SMika Westerberg generic_handle_irq(virq); 4455fae8b86SMika Westerberg } 4465fae8b86SMika Westerberg } 4475fae8b86SMika Westerberg chip->irq_eoi(data); 4485fae8b86SMika Westerberg } 4495fae8b86SMika Westerberg 45031e4329fSMika Westerberg static void byt_irq_ack(struct irq_data *d) 45131e4329fSMika Westerberg { 45231e4329fSMika Westerberg struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 45331e4329fSMika Westerberg struct byt_gpio *vg = to_byt_gpio(gc); 45431e4329fSMika Westerberg unsigned offset = irqd_to_hwirq(d); 45531e4329fSMika Westerberg void __iomem *reg; 45631e4329fSMika Westerberg 45778e1c896SMika Westerberg raw_spin_lock(&vg->lock); 45831e4329fSMika Westerberg reg = byt_gpio_reg(&vg->chip, offset, BYT_INT_STAT_REG); 45931e4329fSMika Westerberg writel(BIT(offset % 32), reg); 46078e1c896SMika Westerberg raw_spin_unlock(&vg->lock); 46131e4329fSMika Westerberg } 46231e4329fSMika Westerberg 4635fae8b86SMika Westerberg static void byt_irq_unmask(struct irq_data *d) 4645fae8b86SMika Westerberg { 46531e4329fSMika Westerberg struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 46631e4329fSMika Westerberg struct byt_gpio *vg = to_byt_gpio(gc); 46731e4329fSMika Westerberg unsigned offset = irqd_to_hwirq(d); 46831e4329fSMika Westerberg unsigned long flags; 46931e4329fSMika Westerberg void __iomem *reg; 47031e4329fSMika Westerberg u32 value; 47131e4329fSMika Westerberg 47231e4329fSMika Westerberg reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG); 47378e1c896SMika Westerberg 47478e1c896SMika Westerberg raw_spin_lock_irqsave(&vg->lock, flags); 47531e4329fSMika Westerberg value = readl(reg); 47631e4329fSMika Westerberg 47731e4329fSMika Westerberg switch (irqd_get_trigger_type(d)) { 47831e4329fSMika Westerberg case IRQ_TYPE_LEVEL_HIGH: 47931e4329fSMika Westerberg value |= BYT_TRIG_LVL; 48031e4329fSMika Westerberg case IRQ_TYPE_EDGE_RISING: 48131e4329fSMika Westerberg value |= BYT_TRIG_POS; 48231e4329fSMika Westerberg break; 48331e4329fSMika Westerberg case IRQ_TYPE_LEVEL_LOW: 48431e4329fSMika Westerberg value |= BYT_TRIG_LVL; 48531e4329fSMika Westerberg case IRQ_TYPE_EDGE_FALLING: 48631e4329fSMika Westerberg value |= BYT_TRIG_NEG; 48731e4329fSMika Westerberg break; 48831e4329fSMika Westerberg case IRQ_TYPE_EDGE_BOTH: 48931e4329fSMika Westerberg value |= (BYT_TRIG_NEG | BYT_TRIG_POS); 49031e4329fSMika Westerberg break; 49131e4329fSMika Westerberg } 49231e4329fSMika Westerberg 49331e4329fSMika Westerberg writel(value, reg); 49431e4329fSMika Westerberg 49578e1c896SMika Westerberg raw_spin_unlock_irqrestore(&vg->lock, flags); 4965fae8b86SMika Westerberg } 4975fae8b86SMika Westerberg 4985fae8b86SMika Westerberg static void byt_irq_mask(struct irq_data *d) 4995fae8b86SMika Westerberg { 50031e4329fSMika Westerberg struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 50131e4329fSMika Westerberg struct byt_gpio *vg = to_byt_gpio(gc); 50231e4329fSMika Westerberg 50331e4329fSMika Westerberg byt_gpio_clear_triggering(vg, irqd_to_hwirq(d)); 5045fae8b86SMika Westerberg } 5055fae8b86SMika Westerberg 5065fae8b86SMika Westerberg static struct irq_chip byt_irqchip = { 5075fae8b86SMika Westerberg .name = "BYT-GPIO", 50831e4329fSMika Westerberg .irq_ack = byt_irq_ack, 5095fae8b86SMika Westerberg .irq_mask = byt_irq_mask, 5105fae8b86SMika Westerberg .irq_unmask = byt_irq_unmask, 5115fae8b86SMika Westerberg .irq_set_type = byt_irq_type, 5125fae8b86SMika Westerberg .flags = IRQCHIP_SKIP_SET_WAKE, 5135fae8b86SMika Westerberg }; 5145fae8b86SMika Westerberg 5155fae8b86SMika Westerberg static void byt_gpio_irq_init_hw(struct byt_gpio *vg) 5165fae8b86SMika Westerberg { 5175fae8b86SMika Westerberg void __iomem *reg; 5185fae8b86SMika Westerberg u32 base, value; 51995f0972cSMika Westerberg int i; 52095f0972cSMika Westerberg 52195f0972cSMika Westerberg /* 52295f0972cSMika Westerberg * Clear interrupt triggers for all pins that are GPIOs and 52395f0972cSMika Westerberg * do not use direct IRQ mode. This will prevent spurious 52495f0972cSMika Westerberg * interrupts from misconfigured pins. 52595f0972cSMika Westerberg */ 52695f0972cSMika Westerberg for (i = 0; i < vg->chip.ngpio; i++) { 52795f0972cSMika Westerberg value = readl(byt_gpio_reg(&vg->chip, i, BYT_CONF0_REG)); 52895f0972cSMika Westerberg if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i) && 52995f0972cSMika Westerberg !(value & BYT_DIRECT_IRQ_EN)) { 53095f0972cSMika Westerberg byt_gpio_clear_triggering(vg, i); 53195f0972cSMika Westerberg dev_dbg(&vg->pdev->dev, "disabling GPIO %d\n", i); 53295f0972cSMika Westerberg } 53395f0972cSMika Westerberg } 5345fae8b86SMika Westerberg 5355fae8b86SMika Westerberg /* clear interrupt status trigger registers */ 5365fae8b86SMika Westerberg for (base = 0; base < vg->chip.ngpio; base += 32) { 5375fae8b86SMika Westerberg reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG); 5385fae8b86SMika Westerberg writel(0xffffffff, reg); 5395fae8b86SMika Westerberg /* make sure trigger bits are cleared, if not then a pin 5405fae8b86SMika Westerberg might be misconfigured in bios */ 5415fae8b86SMika Westerberg value = readl(reg); 5425fae8b86SMika Westerberg if (value) 5435fae8b86SMika Westerberg dev_err(&vg->pdev->dev, 5445fae8b86SMika Westerberg "GPIO interrupt error, pins misconfigured\n"); 5455fae8b86SMika Westerberg } 5465fae8b86SMika Westerberg } 5475fae8b86SMika Westerberg 5485fae8b86SMika Westerberg static int byt_gpio_probe(struct platform_device *pdev) 5495fae8b86SMika Westerberg { 5505fae8b86SMika Westerberg struct byt_gpio *vg; 5515fae8b86SMika Westerberg struct gpio_chip *gc; 5525fae8b86SMika Westerberg struct resource *mem_rc, *irq_rc; 5535fae8b86SMika Westerberg struct device *dev = &pdev->dev; 5545fae8b86SMika Westerberg struct acpi_device *acpi_dev; 5555fae8b86SMika Westerberg struct pinctrl_gpio_range *range; 5565fae8b86SMika Westerberg acpi_handle handle = ACPI_HANDLE(dev); 5575fae8b86SMika Westerberg int ret; 5585fae8b86SMika Westerberg 5595fae8b86SMika Westerberg if (acpi_bus_get_device(handle, &acpi_dev)) 5605fae8b86SMika Westerberg return -ENODEV; 5615fae8b86SMika Westerberg 5625fae8b86SMika Westerberg vg = devm_kzalloc(dev, sizeof(struct byt_gpio), GFP_KERNEL); 5635fae8b86SMika Westerberg if (!vg) { 5645fae8b86SMika Westerberg dev_err(&pdev->dev, "can't allocate byt_gpio chip data\n"); 5655fae8b86SMika Westerberg return -ENOMEM; 5665fae8b86SMika Westerberg } 5675fae8b86SMika Westerberg 5685fae8b86SMika Westerberg for (range = byt_ranges; range->name; range++) { 5695fae8b86SMika Westerberg if (!strcmp(acpi_dev->pnp.unique_id, range->name)) { 5705fae8b86SMika Westerberg vg->chip.ngpio = range->npins; 5715fae8b86SMika Westerberg vg->range = range; 5725fae8b86SMika Westerberg break; 5735fae8b86SMika Westerberg } 5745fae8b86SMika Westerberg } 5755fae8b86SMika Westerberg 5765fae8b86SMika Westerberg if (!vg->chip.ngpio || !vg->range) 5775fae8b86SMika Westerberg return -ENODEV; 5785fae8b86SMika Westerberg 5795fae8b86SMika Westerberg vg->pdev = pdev; 5805fae8b86SMika Westerberg platform_set_drvdata(pdev, vg); 5815fae8b86SMika Westerberg 5825fae8b86SMika Westerberg mem_rc = platform_get_resource(pdev, IORESOURCE_MEM, 0); 5835fae8b86SMika Westerberg vg->reg_base = devm_ioremap_resource(dev, mem_rc); 5845fae8b86SMika Westerberg if (IS_ERR(vg->reg_base)) 5855fae8b86SMika Westerberg return PTR_ERR(vg->reg_base); 5865fae8b86SMika Westerberg 58778e1c896SMika Westerberg raw_spin_lock_init(&vg->lock); 5885fae8b86SMika Westerberg 5895fae8b86SMika Westerberg gc = &vg->chip; 5905fae8b86SMika Westerberg gc->label = dev_name(&pdev->dev); 5915fae8b86SMika Westerberg gc->owner = THIS_MODULE; 5925fae8b86SMika Westerberg gc->request = byt_gpio_request; 5935fae8b86SMika Westerberg gc->free = byt_gpio_free; 5945fae8b86SMika Westerberg gc->direction_input = byt_gpio_direction_input; 5955fae8b86SMika Westerberg gc->direction_output = byt_gpio_direction_output; 5965fae8b86SMika Westerberg gc->get = byt_gpio_get; 5975fae8b86SMika Westerberg gc->set = byt_gpio_set; 5985fae8b86SMika Westerberg gc->dbg_show = byt_gpio_dbg_show; 5995fae8b86SMika Westerberg gc->base = -1; 6005fae8b86SMika Westerberg gc->can_sleep = false; 60158383c78SLinus Walleij gc->parent = dev; 6025fae8b86SMika Westerberg 603fcc18debSMika Westerberg #ifdef CONFIG_PM_SLEEP 604fcc18debSMika Westerberg vg->saved_context = devm_kcalloc(&pdev->dev, gc->ngpio, 605fcc18debSMika Westerberg sizeof(*vg->saved_context), GFP_KERNEL); 606fcc18debSMika Westerberg #endif 607fcc18debSMika Westerberg 6085fae8b86SMika Westerberg ret = gpiochip_add(gc); 6095fae8b86SMika Westerberg if (ret) { 6105fae8b86SMika Westerberg dev_err(&pdev->dev, "failed adding byt-gpio chip\n"); 6115fae8b86SMika Westerberg return ret; 6125fae8b86SMika Westerberg } 6135fae8b86SMika Westerberg 6145fae8b86SMika Westerberg /* set up interrupts */ 6155fae8b86SMika Westerberg irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 6165fae8b86SMika Westerberg if (irq_rc && irq_rc->start) { 6175fae8b86SMika Westerberg byt_gpio_irq_init_hw(vg); 6185fae8b86SMika Westerberg ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0, 6195fae8b86SMika Westerberg handle_simple_irq, IRQ_TYPE_NONE); 6205fae8b86SMika Westerberg if (ret) { 6215fae8b86SMika Westerberg dev_err(dev, "failed to add irqchip\n"); 6225fae8b86SMika Westerberg gpiochip_remove(gc); 6235fae8b86SMika Westerberg return ret; 6245fae8b86SMika Westerberg } 6255fae8b86SMika Westerberg 6265fae8b86SMika Westerberg gpiochip_set_chained_irqchip(gc, &byt_irqchip, 6275fae8b86SMika Westerberg (unsigned)irq_rc->start, 6285fae8b86SMika Westerberg byt_gpio_irq_handler); 6295fae8b86SMika Westerberg } 6305fae8b86SMika Westerberg 6315fae8b86SMika Westerberg pm_runtime_enable(dev); 6325fae8b86SMika Westerberg 6335fae8b86SMika Westerberg return 0; 6345fae8b86SMika Westerberg } 6355fae8b86SMika Westerberg 636fcc18debSMika Westerberg #ifdef CONFIG_PM_SLEEP 637fcc18debSMika Westerberg static int byt_gpio_suspend(struct device *dev) 638fcc18debSMika Westerberg { 639fcc18debSMika Westerberg struct platform_device *pdev = to_platform_device(dev); 640fcc18debSMika Westerberg struct byt_gpio *vg = platform_get_drvdata(pdev); 641fcc18debSMika Westerberg int i; 642fcc18debSMika Westerberg 643fcc18debSMika Westerberg for (i = 0; i < vg->chip.ngpio; i++) { 644fcc18debSMika Westerberg void __iomem *reg; 645fcc18debSMika Westerberg u32 value; 646fcc18debSMika Westerberg 647fcc18debSMika Westerberg reg = byt_gpio_reg(&vg->chip, i, BYT_CONF0_REG); 648fcc18debSMika Westerberg value = readl(reg) & BYT_CONF0_RESTORE_MASK; 649fcc18debSMika Westerberg vg->saved_context[i].conf0 = value; 650fcc18debSMika Westerberg 651fcc18debSMika Westerberg reg = byt_gpio_reg(&vg->chip, i, BYT_VAL_REG); 652fcc18debSMika Westerberg value = readl(reg) & BYT_VAL_RESTORE_MASK; 653fcc18debSMika Westerberg vg->saved_context[i].val = value; 654fcc18debSMika Westerberg } 655fcc18debSMika Westerberg 656fcc18debSMika Westerberg return 0; 657fcc18debSMika Westerberg } 658fcc18debSMika Westerberg 659fcc18debSMika Westerberg static int byt_gpio_resume(struct device *dev) 660fcc18debSMika Westerberg { 661fcc18debSMika Westerberg struct platform_device *pdev = to_platform_device(dev); 662fcc18debSMika Westerberg struct byt_gpio *vg = platform_get_drvdata(pdev); 663fcc18debSMika Westerberg int i; 664fcc18debSMika Westerberg 665fcc18debSMika Westerberg for (i = 0; i < vg->chip.ngpio; i++) { 666fcc18debSMika Westerberg void __iomem *reg; 667fcc18debSMika Westerberg u32 value; 668fcc18debSMika Westerberg 669fcc18debSMika Westerberg reg = byt_gpio_reg(&vg->chip, i, BYT_CONF0_REG); 670fcc18debSMika Westerberg value = readl(reg); 671fcc18debSMika Westerberg if ((value & BYT_CONF0_RESTORE_MASK) != 672fcc18debSMika Westerberg vg->saved_context[i].conf0) { 673fcc18debSMika Westerberg value &= ~BYT_CONF0_RESTORE_MASK; 674fcc18debSMika Westerberg value |= vg->saved_context[i].conf0; 675fcc18debSMika Westerberg writel(value, reg); 676fcc18debSMika Westerberg dev_info(dev, "restored pin %d conf0 %#08x", i, value); 677fcc18debSMika Westerberg } 678fcc18debSMika Westerberg 679fcc18debSMika Westerberg reg = byt_gpio_reg(&vg->chip, i, BYT_VAL_REG); 680fcc18debSMika Westerberg value = readl(reg); 681fcc18debSMika Westerberg if ((value & BYT_VAL_RESTORE_MASK) != 682fcc18debSMika Westerberg vg->saved_context[i].val) { 683fcc18debSMika Westerberg u32 v; 684fcc18debSMika Westerberg 685fcc18debSMika Westerberg v = value & ~BYT_VAL_RESTORE_MASK; 686fcc18debSMika Westerberg v |= vg->saved_context[i].val; 687fcc18debSMika Westerberg if (v != value) { 688fcc18debSMika Westerberg writel(v, reg); 689fcc18debSMika Westerberg dev_dbg(dev, "restored pin %d val %#08x\n", 690fcc18debSMika Westerberg i, v); 691fcc18debSMika Westerberg } 692fcc18debSMika Westerberg } 693fcc18debSMika Westerberg } 694fcc18debSMika Westerberg 695fcc18debSMika Westerberg return 0; 696fcc18debSMika Westerberg } 697fcc18debSMika Westerberg #endif 698fcc18debSMika Westerberg 699ec879f12SMika Westerberg #ifdef CONFIG_PM 7005fae8b86SMika Westerberg static int byt_gpio_runtime_suspend(struct device *dev) 7015fae8b86SMika Westerberg { 7025fae8b86SMika Westerberg return 0; 7035fae8b86SMika Westerberg } 7045fae8b86SMika Westerberg 7055fae8b86SMika Westerberg static int byt_gpio_runtime_resume(struct device *dev) 7065fae8b86SMika Westerberg { 7075fae8b86SMika Westerberg return 0; 7085fae8b86SMika Westerberg } 709ec879f12SMika Westerberg #endif 7105fae8b86SMika Westerberg 7115fae8b86SMika Westerberg static const struct dev_pm_ops byt_gpio_pm_ops = { 712fcc18debSMika Westerberg SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume) 713fcc18debSMika Westerberg SET_RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume, 714fcc18debSMika Westerberg NULL) 7155fae8b86SMika Westerberg }; 7165fae8b86SMika Westerberg 7175fae8b86SMika Westerberg static const struct acpi_device_id byt_gpio_acpi_match[] = { 7185fae8b86SMika Westerberg { "INT33B2", 0 }, 7195fae8b86SMika Westerberg { "INT33FC", 0 }, 7205fae8b86SMika Westerberg { } 7215fae8b86SMika Westerberg }; 7225fae8b86SMika Westerberg MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match); 7235fae8b86SMika Westerberg 7245fae8b86SMika Westerberg static int byt_gpio_remove(struct platform_device *pdev) 7255fae8b86SMika Westerberg { 7265fae8b86SMika Westerberg struct byt_gpio *vg = platform_get_drvdata(pdev); 7275fae8b86SMika Westerberg 7285fae8b86SMika Westerberg pm_runtime_disable(&pdev->dev); 7295fae8b86SMika Westerberg gpiochip_remove(&vg->chip); 7305fae8b86SMika Westerberg 7315fae8b86SMika Westerberg return 0; 7325fae8b86SMika Westerberg } 7335fae8b86SMika Westerberg 7345fae8b86SMika Westerberg static struct platform_driver byt_gpio_driver = { 7355fae8b86SMika Westerberg .probe = byt_gpio_probe, 7365fae8b86SMika Westerberg .remove = byt_gpio_remove, 7375fae8b86SMika Westerberg .driver = { 7385fae8b86SMika Westerberg .name = "byt_gpio", 7395fae8b86SMika Westerberg .pm = &byt_gpio_pm_ops, 7405fae8b86SMika Westerberg .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match), 7415fae8b86SMika Westerberg }, 7425fae8b86SMika Westerberg }; 7435fae8b86SMika Westerberg 7445fae8b86SMika Westerberg static int __init byt_gpio_init(void) 7455fae8b86SMika Westerberg { 7465fae8b86SMika Westerberg return platform_driver_register(&byt_gpio_driver); 7475fae8b86SMika Westerberg } 7485fae8b86SMika Westerberg subsys_initcall(byt_gpio_init); 7495fae8b86SMika Westerberg 7505fae8b86SMika Westerberg static void __exit byt_gpio_exit(void) 7515fae8b86SMika Westerberg { 7525fae8b86SMika Westerberg platform_driver_unregister(&byt_gpio_driver); 7535fae8b86SMika Westerberg } 7545fae8b86SMika Westerberg module_exit(byt_gpio_exit); 755