1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/of_address.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/slab.h> 22 23 #include <dt-bindings/phy/phy.h> 24 25 #include "phy-qcom-qmp.h" 26 27 /* QPHY_SW_RESET bit */ 28 #define SW_RESET BIT(0) 29 /* QPHY_POWER_DOWN_CONTROL */ 30 #define SW_PWRDN BIT(0) 31 /* QPHY_START_CONTROL bits */ 32 #define SERDES_START BIT(0) 33 #define PCS_START BIT(1) 34 /* QPHY_PCS_STATUS bit */ 35 #define PHYSTATUS BIT(6) 36 37 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ 38 /* DP PHY soft reset */ 39 #define SW_DPPHY_RESET BIT(0) 40 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */ 41 #define SW_DPPHY_RESET_MUX BIT(1) 42 /* USB3 PHY soft reset */ 43 #define SW_USB3PHY_RESET BIT(2) 44 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ 45 #define SW_USB3PHY_RESET_MUX BIT(3) 46 47 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ 48 #define USB3_MODE BIT(0) /* enables USB3 mode */ 49 #define DP_MODE BIT(1) /* enables DP mode */ 50 51 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ 52 #define ARCVR_DTCT_EN BIT(0) 53 #define ALFPS_DTCT_EN BIT(1) 54 #define ARCVR_DTCT_EVENT_SEL BIT(4) 55 56 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ 57 #define IRQ_CLEAR BIT(0) 58 59 /* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */ 60 #define RCVR_DETECT BIT(0) 61 62 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ 63 #define CLAMP_EN BIT(0) /* enables i/o clamp_n */ 64 65 #define PHY_INIT_COMPLETE_TIMEOUT 10000 66 #define POWER_DOWN_DELAY_US_MIN 10 67 #define POWER_DOWN_DELAY_US_MAX 11 68 69 struct qmp_phy_init_tbl { 70 unsigned int offset; 71 unsigned int val; 72 /* 73 * register part of layout ? 74 * if yes, then offset gives index in the reg-layout 75 */ 76 bool in_layout; 77 /* 78 * mask of lanes for which this register is written 79 * for cases when second lane needs different values 80 */ 81 u8 lane_mask; 82 }; 83 84 #define QMP_PHY_INIT_CFG(o, v) \ 85 { \ 86 .offset = o, \ 87 .val = v, \ 88 .lane_mask = 0xff, \ 89 } 90 91 #define QMP_PHY_INIT_CFG_L(o, v) \ 92 { \ 93 .offset = o, \ 94 .val = v, \ 95 .in_layout = true, \ 96 .lane_mask = 0xff, \ 97 } 98 99 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ 100 { \ 101 .offset = o, \ 102 .val = v, \ 103 .lane_mask = l, \ 104 } 105 106 /* set of registers with offsets different per-PHY */ 107 enum qphy_reg_layout { 108 /* PCS registers */ 109 QPHY_SW_RESET, 110 QPHY_START_CTRL, 111 QPHY_PCS_STATUS, 112 QPHY_PCS_AUTONOMOUS_MODE_CTRL, 113 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, 114 QPHY_PCS_LFPS_RXTERM_IRQ_STATUS, 115 QPHY_PCS_POWER_DOWN_CONTROL, 116 /* Keep last to ensure regs_layout arrays are properly initialized */ 117 QPHY_LAYOUT_SIZE 118 }; 119 120 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 121 [QPHY_SW_RESET] = 0x00, 122 [QPHY_START_CTRL] = 0x08, 123 [QPHY_PCS_STATUS] = 0x174, 124 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8, 125 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc, 126 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170, 127 }; 128 129 static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 130 [QPHY_SW_RESET] = 0x00, 131 [QPHY_START_CTRL] = 0x44, 132 [QPHY_PCS_STATUS] = 0x14, 133 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, 134 135 /* In PCS_USB */ 136 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x008, 137 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x014, 138 }; 139 140 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { 141 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 142 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 143 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 144 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 145 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 146 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 147 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16), 148 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 149 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 150 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 151 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 152 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 153 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 154 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 155 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 156 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 157 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 158 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 159 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 160 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 161 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 162 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 163 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 164 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 165 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 166 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 167 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 168 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 169 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), 170 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 171 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 172 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 173 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 174 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 175 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 176 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 177 }; 178 179 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { 180 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 181 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 182 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), 183 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 184 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 185 }; 186 187 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = { 188 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 189 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37), 190 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 191 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e), 192 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 193 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 194 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02), 195 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00), 196 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 197 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 198 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 199 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 200 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), 201 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 202 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), 203 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), 204 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f), 205 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 206 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 207 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 208 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 209 }; 210 211 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = { 212 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c), 213 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 214 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 215 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 216 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f), 217 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08), 218 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 219 }; 220 221 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = { 222 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04), 223 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 224 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 225 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 226 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f), 227 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e), 228 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 229 }; 230 231 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = { 232 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 233 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c), 234 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00), 235 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a), 236 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f), 237 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c), 238 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 239 }; 240 241 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = { 242 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03), 243 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 244 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 245 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 246 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f), 247 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a), 248 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08), 249 }; 250 251 static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = { 252 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), 253 QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), 254 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 255 QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), 256 QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), 257 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), 258 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), 259 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 260 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), 261 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), 262 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a), 263 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38), 264 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20), 265 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 266 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), 267 }; 268 269 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { 270 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 271 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 272 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 273 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 274 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 275 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 276 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 277 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 278 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 279 }; 280 281 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { 282 /* FLL settings */ 283 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 284 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 285 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 286 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 287 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 288 289 /* Lock Det settings */ 290 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 291 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 292 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 293 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 294 295 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), 296 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 297 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 298 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 299 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 300 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 301 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 302 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 303 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 304 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 305 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 306 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 307 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 308 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 309 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 310 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 311 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 312 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 313 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 314 315 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 316 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 317 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 318 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 319 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 320 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 321 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 322 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 323 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 324 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 325 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 326 }; 327 328 static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = { 329 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 330 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 331 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 332 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 333 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 334 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), 335 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), 336 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), 337 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), 338 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 339 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 340 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 341 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 342 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 343 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 344 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), 345 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 346 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), 347 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), 348 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), 349 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), 350 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 351 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), 352 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), 353 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), 354 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), 355 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 356 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 357 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), 358 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 359 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 360 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), 361 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), 362 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 363 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 364 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 365 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 366 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 367 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 368 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 369 }; 370 371 static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = { 372 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00), 373 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00), 374 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 375 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 376 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 377 }; 378 379 static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = { 380 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), 381 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 382 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 383 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 384 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 385 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 386 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 387 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 388 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 389 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 390 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 391 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e), 392 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 393 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 394 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 395 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 396 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 397 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 398 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 399 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 400 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 401 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf), 402 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f), 403 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 404 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94), 405 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 406 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 407 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 408 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), 409 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), 410 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 411 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 412 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 413 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 414 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 415 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 416 }; 417 418 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = { 419 /* Lock Det settings */ 420 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 421 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 422 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 423 424 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 425 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 426 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 427 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 428 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 429 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 430 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 431 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 432 }; 433 434 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = { 435 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 436 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 437 }; 438 439 static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = { 440 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60), 441 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60), 442 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 443 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), 444 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 445 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 446 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1), 447 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2), 448 }; 449 450 static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = { 451 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), 452 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 453 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 454 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 455 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 456 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 457 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 458 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 459 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 460 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 461 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 462 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 463 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 464 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 465 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 466 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 467 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 468 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 469 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 470 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 471 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1), 472 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2), 473 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1), 474 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2), 475 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f), 476 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 477 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97), 478 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 479 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 480 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 481 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 482 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 483 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 484 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 485 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 486 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 487 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 488 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 489 }; 490 491 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = { 492 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 493 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 494 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 495 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 496 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 497 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), 498 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 499 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 500 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 501 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 502 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 503 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 504 }; 505 506 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = { 507 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 508 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 509 }; 510 511 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = { 512 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), 513 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), 514 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), 515 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), 516 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), 517 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), 518 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 519 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 520 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 521 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 522 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), 523 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 524 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 525 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00), 526 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), 527 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), 528 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), 529 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), 530 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), 531 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), 532 }; 533 534 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = { 535 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05), 536 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 537 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 538 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 539 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f), 540 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08), 541 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 542 }; 543 544 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = { 545 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03), 546 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 547 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 548 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 549 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f), 550 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e), 551 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 552 }; 553 554 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = { 555 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 556 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c), 557 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00), 558 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a), 559 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f), 560 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c), 561 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 562 }; 563 564 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = { 565 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00), 566 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 567 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 568 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 569 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f), 570 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a), 571 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 572 }; 573 574 static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = { 575 QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40), 576 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 577 QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b), 578 QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f), 579 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03), 580 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f), 581 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 582 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00), 583 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 584 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 585 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4), 586 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a), 587 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a), 588 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20), 589 }; 590 591 static const struct qmp_phy_init_tbl qmp_v5_dp_serdes_tbl[] = { 592 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), 593 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), 594 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), 595 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), 596 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), 597 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), 598 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 599 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 600 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 601 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 602 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 603 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 604 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 605 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), 606 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 607 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 608 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 609 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), 610 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), 611 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), 612 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), 613 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), 614 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), 615 }; 616 617 static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx_tbl[] = { 618 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x51), 619 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 0x1a), 620 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_VMODE_CTRL1, 0x40), 621 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PRE_STALL_LDO_BOOST_EN, 0x0), 622 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_INTERFACE_SELECT, 0xff), 623 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_CLKBUF_ENABLE, 0x0f), 624 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RESET_TSYNC_EN, 0x03), 625 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRAN_DRVR_EMP_EN, 0xf), 626 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 627 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 628 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 629 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TX_BAND, 0x01), 630 }; 631 632 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = { 633 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 634 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 635 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 636 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xfd), 637 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x0d), 638 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xfd), 639 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0d), 640 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a), 641 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x02), 642 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x02), 643 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 644 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 645 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 646 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 647 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a), 648 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04), 649 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14), 650 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34), 651 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34), 652 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82), 653 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x04), 654 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE0, 0x01), 655 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x04), 656 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE1, 0x01), 657 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 658 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xd5), 659 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x05), 660 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 661 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xd5), 662 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 663 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 664 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0xd4), 665 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE0, 0x00), 666 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xd4), 667 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x00), 668 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x13), 669 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 670 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 671 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 672 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 673 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x76), 674 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0xff), 675 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0x20), 676 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0x20), 677 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00), 678 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAXVAL2, 0x01), 679 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SVS_MODE_CLK_SEL, 0x0a), 680 }; 681 682 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_tx_tbl[] = { 683 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_1, 0x05), 684 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_2, 0xc2), 685 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x10), 686 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 687 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x0a), 688 }; 689 690 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_rx_tbl[] = { 691 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_CNTRL, 0x04), 692 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 693 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_ENABLES, 0x00), 694 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B0, 0xd2), 695 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B1, 0xd2), 696 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B2, 0xdb), 697 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B3, 0x21), 698 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B4, 0x3f), 699 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B5, 0x80), 700 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B6, 0x45), 701 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B7, 0x00), 702 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B0, 0x6b), 703 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B1, 0x63), 704 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B2, 0xb6), 705 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B3, 0x23), 706 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B4, 0x35), 707 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B5, 0x30), 708 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B6, 0x8e), 709 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B7, 0x00), 710 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CODE_OVERRIDE, 0x00), 711 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL2, 0x80), 712 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_SUMMER_CAL_SPD_MODE, 0x1b), 713 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 714 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_PI_CONTROLS, 0x15), 715 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE2, 0x0a), 716 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c), 717 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_CNTRL1, 0x00), 718 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_MAN_VAL, 0x0d), 719 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_DAC_ENABLE1, 0x00), 720 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_3, 0x45), 721 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_GM_CAL, 0x09), 722 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE2, 0x09), 723 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE2, 0x05), 724 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x3f), 725 }; 726 727 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_pcs_tbl[] = { 728 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 729 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 730 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0), 731 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07), 732 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20), 733 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13), 734 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21), 735 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa), 736 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_CONFIG, 0x0a), 737 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88), 738 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13), 739 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c), 740 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b), 741 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10), 742 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 743 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 744 }; 745 746 /* list of regulators */ 747 struct qmp_regulator_data { 748 const char *name; 749 unsigned int enable_load; 750 }; 751 752 static struct qmp_regulator_data qmp_phy_vreg_l[] = { 753 { .name = "vdda-phy", .enable_load = 21800 }, 754 { .name = "vdda-pll", .enable_load = 36000 }, 755 }; 756 757 static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = { 758 { 0x00, 0x0c, 0x15, 0x1a }, 759 { 0x02, 0x0e, 0x16, 0xff }, 760 { 0x02, 0x11, 0xff, 0xff }, 761 { 0x04, 0xff, 0xff, 0xff } 762 }; 763 764 static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = { 765 { 0x02, 0x12, 0x16, 0x1a }, 766 { 0x09, 0x19, 0x1f, 0xff }, 767 { 0x10, 0x1f, 0xff, 0xff }, 768 { 0x1f, 0xff, 0xff, 0xff } 769 }; 770 771 static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = { 772 { 0x00, 0x0c, 0x14, 0x19 }, 773 { 0x00, 0x0b, 0x12, 0xff }, 774 { 0x00, 0x0b, 0xff, 0xff }, 775 { 0x04, 0xff, 0xff, 0xff } 776 }; 777 778 static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { 779 { 0x08, 0x0f, 0x16, 0x1f }, 780 { 0x11, 0x1e, 0x1f, 0xff }, 781 { 0x19, 0x1f, 0xff, 0xff }, 782 { 0x1f, 0xff, 0xff, 0xff } 783 }; 784 785 static const u8 qmp_dp_v5_pre_emphasis_hbr3_hbr2[4][4] = { 786 { 0x20, 0x2c, 0x35, 0x3b }, 787 { 0x22, 0x2e, 0x36, 0xff }, 788 { 0x22, 0x31, 0xff, 0xff }, 789 { 0x24, 0xff, 0xff, 0xff } 790 }; 791 792 static const u8 qmp_dp_v5_voltage_swing_hbr3_hbr2[4][4] = { 793 { 0x22, 0x32, 0x36, 0x3a }, 794 { 0x29, 0x39, 0x3f, 0xff }, 795 { 0x30, 0x3f, 0xff, 0xff }, 796 { 0x3f, 0xff, 0xff, 0xff } 797 }; 798 799 static const u8 qmp_dp_v5_pre_emphasis_hbr_rbr[4][4] = { 800 { 0x20, 0x2d, 0x34, 0x3a }, 801 { 0x20, 0x2e, 0x35, 0xff }, 802 { 0x20, 0x2e, 0xff, 0xff }, 803 { 0x24, 0xff, 0xff, 0xff } 804 }; 805 806 static const u8 qmp_dp_v5_voltage_swing_hbr_rbr[4][4] = { 807 { 0x28, 0x2f, 0x36, 0x3f }, 808 { 0x31, 0x3e, 0x3f, 0xff }, 809 { 0x36, 0x3f, 0xff, 0xff }, 810 { 0x3f, 0xff, 0xff, 0xff } 811 }; 812 813 struct qmp_phy; 814 815 /* struct qmp_phy_cfg - per-PHY initialization config */ 816 struct qmp_phy_cfg { 817 /* phy-type - PCIE/UFS/USB */ 818 unsigned int type; 819 int lanes; 820 821 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 822 const struct qmp_phy_init_tbl *serdes_tbl; 823 int serdes_tbl_num; 824 const struct qmp_phy_init_tbl *tx_tbl; 825 int tx_tbl_num; 826 const struct qmp_phy_init_tbl *rx_tbl; 827 int rx_tbl_num; 828 const struct qmp_phy_init_tbl *pcs_tbl; 829 int pcs_tbl_num; 830 const struct qmp_phy_init_tbl *pcs_usb_tbl; 831 int pcs_usb_tbl_num; 832 833 /* Init sequence for DP PHY block link rates */ 834 const struct qmp_phy_init_tbl *serdes_tbl_rbr; 835 int serdes_tbl_rbr_num; 836 const struct qmp_phy_init_tbl *serdes_tbl_hbr; 837 int serdes_tbl_hbr_num; 838 const struct qmp_phy_init_tbl *serdes_tbl_hbr2; 839 int serdes_tbl_hbr2_num; 840 const struct qmp_phy_init_tbl *serdes_tbl_hbr3; 841 int serdes_tbl_hbr3_num; 842 843 /* DP PHY swing and pre_emphasis tables */ 844 const u8 (*swing_hbr_rbr)[4][4]; 845 const u8 (*swing_hbr3_hbr2)[4][4]; 846 const u8 (*pre_emphasis_hbr_rbr)[4][4]; 847 const u8 (*pre_emphasis_hbr3_hbr2)[4][4]; 848 849 /* DP PHY callbacks */ 850 int (*configure_dp_phy)(struct qmp_phy *qphy); 851 void (*configure_dp_tx)(struct qmp_phy *qphy); 852 int (*calibrate_dp_phy)(struct qmp_phy *qphy); 853 void (*dp_aux_init)(struct qmp_phy *qphy); 854 855 /* clock ids to be requested */ 856 const char * const *clk_list; 857 int num_clks; 858 /* resets to be requested */ 859 const char * const *reset_list; 860 int num_resets; 861 /* regulators to be requested */ 862 const struct qmp_regulator_data *vreg_list; 863 int num_vregs; 864 865 /* array of registers with different offsets */ 866 const unsigned int *regs; 867 868 unsigned int start_ctrl; 869 unsigned int pwrdn_ctrl; 870 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ 871 unsigned int phy_status; 872 873 /* true, if PHY needs delay after POWER_DOWN */ 874 bool has_pwrdn_delay; 875 /* power_down delay in usec */ 876 int pwrdn_delay_min; 877 int pwrdn_delay_max; 878 879 /* Offset from PCS to PCS_USB region */ 880 unsigned int pcs_usb_offset; 881 882 }; 883 884 struct qmp_phy_combo_cfg { 885 const struct qmp_phy_cfg *usb_cfg; 886 const struct qmp_phy_cfg *dp_cfg; 887 }; 888 889 /** 890 * struct qmp_phy - per-lane phy descriptor 891 * 892 * @phy: generic phy 893 * @cfg: phy specific configuration 894 * @serdes: iomapped memory space for phy's serdes (i.e. PLL) 895 * @tx: iomapped memory space for lane's tx 896 * @rx: iomapped memory space for lane's rx 897 * @pcs: iomapped memory space for lane's pcs 898 * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) 899 * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) 900 * @pcs_misc: iomapped memory space for lane's pcs_misc 901 * @pcs_usb: iomapped memory space for lane's pcs_usb 902 * @pipe_clk: pipe clock 903 * @qmp: QMP phy to which this lane belongs 904 * @mode: current PHY mode 905 * @dp_aux_cfg: Display port aux config 906 * @dp_opts: Display port optional config 907 * @dp_clks: Display port clocks 908 */ 909 struct qmp_phy { 910 struct phy *phy; 911 const struct qmp_phy_cfg *cfg; 912 void __iomem *serdes; 913 void __iomem *tx; 914 void __iomem *rx; 915 void __iomem *pcs; 916 void __iomem *tx2; 917 void __iomem *rx2; 918 void __iomem *pcs_misc; 919 void __iomem *pcs_usb; 920 struct clk *pipe_clk; 921 struct qcom_qmp *qmp; 922 enum phy_mode mode; 923 unsigned int dp_aux_cfg; 924 struct phy_configure_opts_dp dp_opts; 925 struct qmp_phy_dp_clks *dp_clks; 926 }; 927 928 struct qmp_phy_dp_clks { 929 struct qmp_phy *qphy; 930 struct clk_hw dp_link_hw; 931 struct clk_hw dp_pixel_hw; 932 }; 933 934 /** 935 * struct qcom_qmp - structure holding QMP phy block attributes 936 * 937 * @dev: device 938 * @dp_com: iomapped memory space for phy's dp_com control block 939 * 940 * @clks: array of clocks required by phy 941 * @resets: array of resets required by phy 942 * @vregs: regulator supplies bulk data 943 * 944 * @phys: array of per-lane phy descriptors 945 * @phy_mutex: mutex lock for PHY common block initialization 946 * @init_count: phy common block initialization count 947 * @ufs_reset: optional UFS PHY reset handle 948 */ 949 struct qcom_qmp { 950 struct device *dev; 951 void __iomem *dp_com; 952 953 struct clk_bulk_data *clks; 954 struct reset_control_bulk_data *resets; 955 struct regulator_bulk_data *vregs; 956 957 struct qmp_phy **phys; 958 959 struct mutex phy_mutex; 960 int init_count; 961 962 struct reset_control *ufs_reset; 963 }; 964 965 static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy); 966 static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy); 967 static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy); 968 static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy); 969 970 static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy); 971 static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy); 972 static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy); 973 static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy); 974 975 static int qcom_qmp_v5_phy_configure_dp_phy(struct qmp_phy *qphy); 976 977 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 978 { 979 u32 reg; 980 981 reg = readl(base + offset); 982 reg |= val; 983 writel(reg, base + offset); 984 985 /* ensure that above write is through */ 986 readl(base + offset); 987 } 988 989 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 990 { 991 u32 reg; 992 993 reg = readl(base + offset); 994 reg &= ~val; 995 writel(reg, base + offset); 996 997 /* ensure that above write is through */ 998 readl(base + offset); 999 } 1000 1001 /* list of clocks required by phy */ 1002 static const char * const qmp_v3_phy_clk_l[] = { 1003 "aux", "cfg_ahb", "ref", "com_aux", 1004 }; 1005 1006 static const char * const qmp_v4_phy_clk_l[] = { 1007 "aux", "ref_clk_src", "ref", "com_aux", 1008 }; 1009 1010 /* the primary usb3 phy on sm8250 doesn't have a ref clock */ 1011 static const char * const qmp_v4_sm8250_usbphy_clk_l[] = { 1012 "aux", "ref_clk_src", "com_aux" 1013 }; 1014 1015 /* list of resets */ 1016 static const char * const msm8996_usb3phy_reset_l[] = { 1017 "phy", "common", 1018 }; 1019 1020 static const char * const sc7180_usb3phy_reset_l[] = { 1021 "phy", 1022 }; 1023 1024 static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { 1025 .type = PHY_TYPE_USB3, 1026 .lanes = 2, 1027 1028 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1029 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1030 .tx_tbl = qmp_v3_usb3_tx_tbl, 1031 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1032 .rx_tbl = qmp_v3_usb3_rx_tbl, 1033 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 1034 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 1035 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 1036 .clk_list = qmp_v3_phy_clk_l, 1037 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 1038 .reset_list = sc7180_usb3phy_reset_l, 1039 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), 1040 .vreg_list = qmp_phy_vreg_l, 1041 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1042 .regs = qmp_v3_usb3phy_regs_layout, 1043 1044 .start_ctrl = SERDES_START | PCS_START, 1045 .pwrdn_ctrl = SW_PWRDN, 1046 .phy_status = PHYSTATUS, 1047 1048 .has_pwrdn_delay = true, 1049 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1050 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1051 }; 1052 1053 static const struct qmp_phy_cfg sc7180_dpphy_cfg = { 1054 .type = PHY_TYPE_DP, 1055 .lanes = 2, 1056 1057 .serdes_tbl = qmp_v3_dp_serdes_tbl, 1058 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 1059 .tx_tbl = qmp_v3_dp_tx_tbl, 1060 .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 1061 1062 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 1063 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 1064 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 1065 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 1066 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 1067 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 1068 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 1069 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 1070 1071 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1072 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1073 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1074 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1075 1076 .clk_list = qmp_v3_phy_clk_l, 1077 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 1078 .reset_list = sc7180_usb3phy_reset_l, 1079 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), 1080 .vreg_list = qmp_phy_vreg_l, 1081 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1082 .regs = qmp_v3_usb3phy_regs_layout, 1083 1084 .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init, 1085 .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx, 1086 .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy, 1087 .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate, 1088 }; 1089 1090 static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = { 1091 .usb_cfg = &sc7180_usb3phy_cfg, 1092 .dp_cfg = &sc7180_dpphy_cfg, 1093 }; 1094 1095 static const struct qmp_phy_cfg sdm845_usb3phy_cfg = { 1096 .type = PHY_TYPE_USB3, 1097 .lanes = 2, 1098 1099 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1100 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1101 .tx_tbl = qmp_v3_usb3_tx_tbl, 1102 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1103 .rx_tbl = qmp_v3_usb3_rx_tbl, 1104 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 1105 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 1106 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 1107 .clk_list = qmp_v3_phy_clk_l, 1108 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 1109 .reset_list = msm8996_usb3phy_reset_l, 1110 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1111 .vreg_list = qmp_phy_vreg_l, 1112 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1113 .regs = qmp_v3_usb3phy_regs_layout, 1114 1115 .start_ctrl = SERDES_START | PCS_START, 1116 .pwrdn_ctrl = SW_PWRDN, 1117 .phy_status = PHYSTATUS, 1118 1119 .has_pwrdn_delay = true, 1120 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1121 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1122 }; 1123 1124 static const struct qmp_phy_combo_cfg sdm845_usb3dpphy_cfg = { 1125 .usb_cfg = &sdm845_usb3phy_cfg, 1126 .dp_cfg = &sc7180_dpphy_cfg, 1127 }; 1128 1129 static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { 1130 .type = PHY_TYPE_USB3, 1131 .lanes = 2, 1132 1133 .serdes_tbl = sm8150_usb3_serdes_tbl, 1134 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1135 .tx_tbl = sm8150_usb3_tx_tbl, 1136 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl), 1137 .rx_tbl = sm8150_usb3_rx_tbl, 1138 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl), 1139 .pcs_tbl = sm8150_usb3_pcs_tbl, 1140 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl), 1141 .pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl, 1142 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl), 1143 .clk_list = qmp_v4_phy_clk_l, 1144 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1145 .reset_list = msm8996_usb3phy_reset_l, 1146 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1147 .vreg_list = qmp_phy_vreg_l, 1148 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1149 .regs = qmp_v4_usb3phy_regs_layout, 1150 .pcs_usb_offset = 0x300, 1151 1152 .start_ctrl = SERDES_START | PCS_START, 1153 .pwrdn_ctrl = SW_PWRDN, 1154 .phy_status = PHYSTATUS, 1155 1156 1157 .has_pwrdn_delay = true, 1158 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1159 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1160 }; 1161 1162 static const struct qmp_phy_cfg sc8180x_dpphy_cfg = { 1163 .type = PHY_TYPE_DP, 1164 .lanes = 2, 1165 1166 .serdes_tbl = qmp_v4_dp_serdes_tbl, 1167 .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 1168 .tx_tbl = qmp_v4_dp_tx_tbl, 1169 .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 1170 1171 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1172 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1173 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1174 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1175 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1176 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1177 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1178 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1179 1180 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1181 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1182 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1183 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1184 1185 .clk_list = qmp_v3_phy_clk_l, 1186 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 1187 .reset_list = sc7180_usb3phy_reset_l, 1188 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), 1189 .vreg_list = qmp_phy_vreg_l, 1190 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1191 .regs = qmp_v3_usb3phy_regs_layout, 1192 1193 .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, 1194 .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, 1195 .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy, 1196 .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate, 1197 }; 1198 1199 static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = { 1200 .usb_cfg = &sm8150_usb3phy_cfg, 1201 .dp_cfg = &sc8180x_dpphy_cfg, 1202 }; 1203 1204 static const struct qmp_phy_cfg sc8280xp_usb43dp_usb_cfg = { 1205 .type = PHY_TYPE_USB3, 1206 .lanes = 2, 1207 1208 .serdes_tbl = sc8280xp_usb43dp_serdes_tbl, 1209 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_serdes_tbl), 1210 .tx_tbl = sc8280xp_usb43dp_tx_tbl, 1211 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_tx_tbl), 1212 .rx_tbl = sc8280xp_usb43dp_rx_tbl, 1213 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_rx_tbl), 1214 .pcs_tbl = sc8280xp_usb43dp_pcs_tbl, 1215 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_pcs_tbl), 1216 .clk_list = qmp_v4_phy_clk_l, 1217 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1218 .reset_list = msm8996_usb3phy_reset_l, 1219 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1220 .vreg_list = qmp_phy_vreg_l, 1221 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1222 .regs = qmp_v4_usb3phy_regs_layout, 1223 .pcs_usb_offset = 0x300, 1224 1225 .start_ctrl = SERDES_START | PCS_START, 1226 .pwrdn_ctrl = SW_PWRDN, 1227 .phy_status = PHYSTATUS, 1228 1229 .has_pwrdn_delay = true, 1230 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1231 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1232 }; 1233 1234 static const struct qmp_phy_cfg sc8280xp_usb43dp_dp_cfg = { 1235 .type = PHY_TYPE_DP, 1236 .lanes = 2, 1237 1238 .serdes_tbl = qmp_v5_dp_serdes_tbl, 1239 .serdes_tbl_num = ARRAY_SIZE(qmp_v5_dp_serdes_tbl), 1240 .tx_tbl = qmp_v5_5nm_dp_tx_tbl, 1241 .tx_tbl_num = ARRAY_SIZE(qmp_v5_5nm_dp_tx_tbl), 1242 1243 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1244 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1245 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1246 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1247 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1248 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1249 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1250 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1251 1252 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 1253 .pre_emphasis_hbr_rbr = &qmp_dp_v5_pre_emphasis_hbr_rbr, 1254 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 1255 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 1256 1257 .clk_list = qmp_v4_phy_clk_l, 1258 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1259 .reset_list = msm8996_usb3phy_reset_l, 1260 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1261 .vreg_list = qmp_phy_vreg_l, 1262 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1263 .regs = qmp_v4_usb3phy_regs_layout, 1264 1265 .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, 1266 .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, 1267 .configure_dp_phy = qcom_qmp_v5_phy_configure_dp_phy, 1268 .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate, 1269 }; 1270 1271 static const struct qmp_phy_combo_cfg sc8280xp_usb43dpphy_combo_cfg = { 1272 .usb_cfg = &sc8280xp_usb43dp_usb_cfg, 1273 .dp_cfg = &sc8280xp_usb43dp_dp_cfg, 1274 }; 1275 1276 static const struct qmp_phy_cfg sm8250_usb3phy_cfg = { 1277 .type = PHY_TYPE_USB3, 1278 .lanes = 2, 1279 1280 .serdes_tbl = sm8150_usb3_serdes_tbl, 1281 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1282 .tx_tbl = sm8250_usb3_tx_tbl, 1283 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl), 1284 .rx_tbl = sm8250_usb3_rx_tbl, 1285 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl), 1286 .pcs_tbl = sm8250_usb3_pcs_tbl, 1287 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl), 1288 .pcs_usb_tbl = sm8250_usb3_pcs_usb_tbl, 1289 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl), 1290 .clk_list = qmp_v4_sm8250_usbphy_clk_l, 1291 .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), 1292 .reset_list = msm8996_usb3phy_reset_l, 1293 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1294 .vreg_list = qmp_phy_vreg_l, 1295 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1296 .regs = qmp_v4_usb3phy_regs_layout, 1297 .pcs_usb_offset = 0x300, 1298 1299 .start_ctrl = SERDES_START | PCS_START, 1300 .pwrdn_ctrl = SW_PWRDN, 1301 .phy_status = PHYSTATUS, 1302 1303 .has_pwrdn_delay = true, 1304 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1305 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1306 }; 1307 1308 static const struct qmp_phy_cfg sm8250_dpphy_cfg = { 1309 .type = PHY_TYPE_DP, 1310 .lanes = 2, 1311 1312 .serdes_tbl = qmp_v4_dp_serdes_tbl, 1313 .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 1314 .tx_tbl = qmp_v4_dp_tx_tbl, 1315 .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 1316 1317 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1318 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1319 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1320 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1321 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1322 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1323 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1324 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1325 1326 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1327 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1328 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1329 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1330 1331 .clk_list = qmp_v4_phy_clk_l, 1332 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1333 .reset_list = msm8996_usb3phy_reset_l, 1334 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1335 .vreg_list = qmp_phy_vreg_l, 1336 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1337 .regs = qmp_v4_usb3phy_regs_layout, 1338 1339 .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, 1340 .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, 1341 .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy, 1342 .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate, 1343 }; 1344 1345 static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = { 1346 .usb_cfg = &sm8250_usb3phy_cfg, 1347 .dp_cfg = &sm8250_dpphy_cfg, 1348 }; 1349 1350 static void qmp_combo_configure_lane(void __iomem *base, 1351 const unsigned int *regs, 1352 const struct qmp_phy_init_tbl tbl[], 1353 int num, 1354 u8 lane_mask) 1355 { 1356 int i; 1357 const struct qmp_phy_init_tbl *t = tbl; 1358 1359 if (!t) 1360 return; 1361 1362 for (i = 0; i < num; i++, t++) { 1363 if (!(t->lane_mask & lane_mask)) 1364 continue; 1365 1366 if (t->in_layout) 1367 writel(t->val, base + regs[t->offset]); 1368 else 1369 writel(t->val, base + t->offset); 1370 } 1371 } 1372 1373 static void qmp_combo_configure(void __iomem *base, 1374 const unsigned int *regs, 1375 const struct qmp_phy_init_tbl tbl[], 1376 int num) 1377 { 1378 qmp_combo_configure_lane(base, regs, tbl, num, 0xff); 1379 } 1380 1381 static int qmp_combo_serdes_init(struct qmp_phy *qphy) 1382 { 1383 const struct qmp_phy_cfg *cfg = qphy->cfg; 1384 void __iomem *serdes = qphy->serdes; 1385 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; 1386 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; 1387 int serdes_tbl_num = cfg->serdes_tbl_num; 1388 1389 qmp_combo_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); 1390 1391 if (cfg->type == PHY_TYPE_DP) { 1392 switch (dp_opts->link_rate) { 1393 case 1620: 1394 qmp_combo_configure(serdes, cfg->regs, 1395 cfg->serdes_tbl_rbr, 1396 cfg->serdes_tbl_rbr_num); 1397 break; 1398 case 2700: 1399 qmp_combo_configure(serdes, cfg->regs, 1400 cfg->serdes_tbl_hbr, 1401 cfg->serdes_tbl_hbr_num); 1402 break; 1403 case 5400: 1404 qmp_combo_configure(serdes, cfg->regs, 1405 cfg->serdes_tbl_hbr2, 1406 cfg->serdes_tbl_hbr2_num); 1407 break; 1408 case 8100: 1409 qmp_combo_configure(serdes, cfg->regs, 1410 cfg->serdes_tbl_hbr3, 1411 cfg->serdes_tbl_hbr3_num); 1412 break; 1413 default: 1414 /* Other link rates aren't supported */ 1415 return -EINVAL; 1416 } 1417 } 1418 1419 return 0; 1420 } 1421 1422 static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy) 1423 { 1424 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 1425 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 1426 qphy->pcs + QSERDES_DP_PHY_PD_CTL); 1427 1428 /* Turn on BIAS current for PHY/PLL */ 1429 writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | 1430 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL, 1431 qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); 1432 1433 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); 1434 1435 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 1436 DP_PHY_PD_CTL_LANE_0_1_PWRDN | 1437 DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | 1438 DP_PHY_PD_CTL_DP_CLAMP_EN, 1439 qphy->pcs + QSERDES_DP_PHY_PD_CTL); 1440 1441 writel(QSERDES_V3_COM_BIAS_EN | 1442 QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN | 1443 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL | 1444 QSERDES_V3_COM_CLKBUF_RX_DRIVE_L, 1445 qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); 1446 1447 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); 1448 writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); 1449 writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); 1450 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); 1451 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); 1452 writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); 1453 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); 1454 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); 1455 writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); 1456 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); 1457 qphy->dp_aux_cfg = 0; 1458 1459 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 1460 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 1461 PHY_AUX_REQ_ERR_MASK, 1462 qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); 1463 } 1464 1465 static int qmp_combo_configure_dp_swing(struct qmp_phy *qphy, 1466 unsigned int drv_lvl_reg, unsigned int emp_post_reg) 1467 { 1468 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; 1469 const struct qmp_phy_cfg *cfg = qphy->cfg; 1470 unsigned int v_level = 0, p_level = 0; 1471 u8 voltage_swing_cfg, pre_emphasis_cfg; 1472 int i; 1473 1474 for (i = 0; i < dp_opts->lanes; i++) { 1475 v_level = max(v_level, dp_opts->voltage[i]); 1476 p_level = max(p_level, dp_opts->pre[i]); 1477 } 1478 1479 if (dp_opts->link_rate <= 2700) { 1480 voltage_swing_cfg = (*cfg->swing_hbr_rbr)[v_level][p_level]; 1481 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr_rbr)[v_level][p_level]; 1482 } else { 1483 voltage_swing_cfg = (*cfg->swing_hbr3_hbr2)[v_level][p_level]; 1484 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr3_hbr2)[v_level][p_level]; 1485 } 1486 1487 /* TODO: Move check to config check */ 1488 if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF) 1489 return -EINVAL; 1490 1491 /* Enable MUX to use Cursor values from these registers */ 1492 voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; 1493 pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; 1494 1495 writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg); 1496 writel(pre_emphasis_cfg, qphy->tx + emp_post_reg); 1497 writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg); 1498 writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg); 1499 1500 return 0; 1501 } 1502 1503 static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy) 1504 { 1505 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; 1506 u32 bias_en, drvr_en; 1507 1508 if (qmp_combo_configure_dp_swing(qphy, QSERDES_V3_TX_TX_DRV_LVL, 1509 QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0) 1510 return; 1511 1512 if (dp_opts->lanes == 1) { 1513 bias_en = 0x3e; 1514 drvr_en = 0x13; 1515 } else { 1516 bias_en = 0x3f; 1517 drvr_en = 0x10; 1518 } 1519 1520 writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); 1521 writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 1522 writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); 1523 writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 1524 } 1525 1526 static bool qmp_combo_configure_dp_mode(struct qmp_phy *qphy) 1527 { 1528 u32 val; 1529 bool reverse = false; 1530 1531 val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 1532 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN; 1533 1534 /* 1535 * TODO: Assume orientation is CC1 for now and two lanes, need to 1536 * use type-c connector to understand orientation and lanes. 1537 * 1538 * Otherwise val changes to be like below if this code understood 1539 * the orientation of the type-c cable. 1540 * 1541 * if (lane_cnt == 4 || orientation == ORIENTATION_CC2) 1542 * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN; 1543 * if (lane_cnt == 4 || orientation == ORIENTATION_CC1) 1544 * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; 1545 * if (orientation == ORIENTATION_CC2) 1546 * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE); 1547 */ 1548 val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; 1549 writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL); 1550 1551 writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE); 1552 1553 return reverse; 1554 } 1555 1556 static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy) 1557 { 1558 const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; 1559 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; 1560 u32 phy_vco_div, status; 1561 unsigned long pixel_freq; 1562 1563 qmp_combo_configure_dp_mode(qphy); 1564 1565 writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); 1566 writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); 1567 1568 switch (dp_opts->link_rate) { 1569 case 1620: 1570 phy_vco_div = 0x1; 1571 pixel_freq = 1620000000UL / 2; 1572 break; 1573 case 2700: 1574 phy_vco_div = 0x1; 1575 pixel_freq = 2700000000UL / 2; 1576 break; 1577 case 5400: 1578 phy_vco_div = 0x2; 1579 pixel_freq = 5400000000UL / 4; 1580 break; 1581 case 8100: 1582 phy_vco_div = 0x0; 1583 pixel_freq = 8100000000UL / 6; 1584 break; 1585 default: 1586 /* Other link rates aren't supported */ 1587 return -EINVAL; 1588 } 1589 writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV); 1590 1591 clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); 1592 clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); 1593 1594 writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); 1595 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); 1596 writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); 1597 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); 1598 writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); 1599 1600 writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL); 1601 1602 if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS, 1603 status, 1604 ((status & BIT(0)) > 0), 1605 500, 1606 10000)) 1607 return -ETIMEDOUT; 1608 1609 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); 1610 1611 if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, 1612 status, 1613 ((status & BIT(1)) > 0), 1614 500, 1615 10000)) 1616 return -ETIMEDOUT; 1617 1618 writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); 1619 udelay(2000); 1620 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); 1621 1622 return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, 1623 status, 1624 ((status & BIT(1)) > 0), 1625 500, 1626 10000); 1627 } 1628 1629 /* 1630 * We need to calibrate the aux setting here as many times 1631 * as the caller tries 1632 */ 1633 static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy) 1634 { 1635 static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d }; 1636 u8 val; 1637 1638 qphy->dp_aux_cfg++; 1639 qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 1640 val = cfg1_settings[qphy->dp_aux_cfg]; 1641 1642 writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); 1643 1644 return 0; 1645 } 1646 1647 static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy) 1648 { 1649 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 1650 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 1651 qphy->pcs + QSERDES_DP_PHY_PD_CTL); 1652 1653 /* Turn on BIAS current for PHY/PLL */ 1654 writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); 1655 1656 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); 1657 writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); 1658 writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); 1659 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); 1660 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); 1661 writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); 1662 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); 1663 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); 1664 writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); 1665 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); 1666 qphy->dp_aux_cfg = 0; 1667 1668 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 1669 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 1670 PHY_AUX_REQ_ERR_MASK, 1671 qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); 1672 } 1673 1674 static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy) 1675 { 1676 /* Program default values before writing proper values */ 1677 writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); 1678 writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); 1679 1680 writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); 1681 writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); 1682 1683 qmp_combo_configure_dp_swing(qphy, QSERDES_V4_TX_TX_DRV_LVL, 1684 QSERDES_V4_TX_TX_EMP_POST1_LVL); 1685 } 1686 1687 static int qcom_qmp_v45_phy_configure_dp_phy(struct qmp_phy *qphy) 1688 { 1689 const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; 1690 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; 1691 u32 phy_vco_div, status; 1692 unsigned long pixel_freq; 1693 1694 writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1); 1695 1696 qmp_combo_configure_dp_mode(qphy); 1697 1698 writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); 1699 writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); 1700 1701 writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); 1702 writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); 1703 1704 switch (dp_opts->link_rate) { 1705 case 1620: 1706 phy_vco_div = 0x1; 1707 pixel_freq = 1620000000UL / 2; 1708 break; 1709 case 2700: 1710 phy_vco_div = 0x1; 1711 pixel_freq = 2700000000UL / 2; 1712 break; 1713 case 5400: 1714 phy_vco_div = 0x2; 1715 pixel_freq = 5400000000UL / 4; 1716 break; 1717 case 8100: 1718 phy_vco_div = 0x0; 1719 pixel_freq = 8100000000UL / 6; 1720 break; 1721 default: 1722 /* Other link rates aren't supported */ 1723 return -EINVAL; 1724 } 1725 writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV); 1726 1727 clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); 1728 clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); 1729 1730 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); 1731 writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); 1732 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); 1733 writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); 1734 1735 writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL); 1736 1737 if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS, 1738 status, 1739 ((status & BIT(0)) > 0), 1740 500, 1741 10000)) 1742 return -ETIMEDOUT; 1743 1744 if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS, 1745 status, 1746 ((status & BIT(0)) > 0), 1747 500, 1748 10000)) 1749 return -ETIMEDOUT; 1750 1751 if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS, 1752 status, 1753 ((status & BIT(1)) > 0), 1754 500, 1755 10000)) 1756 return -ETIMEDOUT; 1757 1758 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); 1759 1760 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, 1761 status, 1762 ((status & BIT(0)) > 0), 1763 500, 1764 10000)) 1765 return -ETIMEDOUT; 1766 1767 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, 1768 status, 1769 ((status & BIT(1)) > 0), 1770 500, 1771 10000)) 1772 return -ETIMEDOUT; 1773 1774 return 0; 1775 } 1776 1777 static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy) 1778 { 1779 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; 1780 u32 bias0_en, drvr0_en, bias1_en, drvr1_en; 1781 bool reverse = false; 1782 u32 status; 1783 int ret; 1784 1785 ret = qcom_qmp_v45_phy_configure_dp_phy(qphy); 1786 if (ret < 0) 1787 return ret; 1788 1789 /* 1790 * At least for 7nm DP PHY this has to be done after enabling link 1791 * clock. 1792 */ 1793 1794 if (dp_opts->lanes == 1) { 1795 bias0_en = reverse ? 0x3e : 0x15; 1796 bias1_en = reverse ? 0x15 : 0x3e; 1797 drvr0_en = reverse ? 0x13 : 0x10; 1798 drvr1_en = reverse ? 0x10 : 0x13; 1799 } else if (dp_opts->lanes == 2) { 1800 bias0_en = reverse ? 0x3f : 0x15; 1801 bias1_en = reverse ? 0x15 : 0x3f; 1802 drvr0_en = 0x10; 1803 drvr1_en = 0x10; 1804 } else { 1805 bias0_en = 0x3f; 1806 bias1_en = 0x3f; 1807 drvr0_en = 0x10; 1808 drvr1_en = 0x10; 1809 } 1810 1811 writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN); 1812 writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); 1813 writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN); 1814 writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); 1815 1816 writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); 1817 udelay(2000); 1818 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); 1819 1820 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, 1821 status, 1822 ((status & BIT(1)) > 0), 1823 500, 1824 10000)) 1825 return -ETIMEDOUT; 1826 1827 writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV); 1828 writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV); 1829 1830 writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); 1831 writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); 1832 1833 writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); 1834 writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); 1835 1836 return 0; 1837 } 1838 1839 static int qcom_qmp_v5_phy_configure_dp_phy(struct qmp_phy *qphy) 1840 { 1841 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; 1842 u32 bias0_en, drvr0_en, bias1_en, drvr1_en; 1843 bool reverse = false; 1844 u32 status; 1845 int ret; 1846 1847 ret = qcom_qmp_v45_phy_configure_dp_phy(qphy); 1848 if (ret < 0) 1849 return ret; 1850 1851 if (dp_opts->lanes == 1) { 1852 bias0_en = reverse ? 0x3e : 0x1a; 1853 drvr0_en = reverse ? 0x13 : 0x10; 1854 bias1_en = reverse ? 0x15 : 0x3e; 1855 drvr1_en = reverse ? 0x10 : 0x13; 1856 } else if (dp_opts->lanes == 2) { 1857 bias0_en = reverse ? 0x3f : 0x15; 1858 drvr0_en = 0x10; 1859 bias1_en = reverse ? 0x15 : 0x3f; 1860 drvr1_en = 0x10; 1861 } else { 1862 bias0_en = 0x3f; 1863 bias1_en = 0x3f; 1864 drvr0_en = 0x10; 1865 drvr1_en = 0x10; 1866 } 1867 1868 writel(drvr0_en, qphy->tx + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN); 1869 writel(bias0_en, qphy->tx + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN); 1870 writel(drvr1_en, qphy->tx2 + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN); 1871 writel(bias1_en, qphy->tx2 + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN); 1872 1873 writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); 1874 udelay(2000); 1875 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); 1876 1877 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, 1878 status, 1879 ((status & BIT(1)) > 0), 1880 500, 1881 10000)) 1882 return -ETIMEDOUT; 1883 1884 writel(0x0a, qphy->tx + QSERDES_V5_5NM_TX_TX_POL_INV); 1885 writel(0x0a, qphy->tx2 + QSERDES_V5_5NM_TX_TX_POL_INV); 1886 1887 writel(0x27, qphy->tx + QSERDES_V5_5NM_TX_TX_DRV_LVL); 1888 writel(0x27, qphy->tx2 + QSERDES_V5_5NM_TX_TX_DRV_LVL); 1889 1890 writel(0x20, qphy->tx + QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL); 1891 writel(0x20, qphy->tx2 + QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL); 1892 1893 return 0; 1894 } 1895 1896 /* 1897 * We need to calibrate the aux setting here as many times 1898 * as the caller tries 1899 */ 1900 static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy) 1901 { 1902 static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d }; 1903 u8 val; 1904 1905 qphy->dp_aux_cfg++; 1906 qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 1907 val = cfg1_settings[qphy->dp_aux_cfg]; 1908 1909 writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); 1910 1911 return 0; 1912 } 1913 1914 static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) 1915 { 1916 const struct phy_configure_opts_dp *dp_opts = &opts->dp; 1917 struct qmp_phy *qphy = phy_get_drvdata(phy); 1918 const struct qmp_phy_cfg *cfg = qphy->cfg; 1919 1920 memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts)); 1921 if (qphy->dp_opts.set_voltages) { 1922 cfg->configure_dp_tx(qphy); 1923 qphy->dp_opts.set_voltages = 0; 1924 } 1925 1926 return 0; 1927 } 1928 1929 static int qcom_qmp_dp_phy_calibrate(struct phy *phy) 1930 { 1931 struct qmp_phy *qphy = phy_get_drvdata(phy); 1932 const struct qmp_phy_cfg *cfg = qphy->cfg; 1933 1934 if (cfg->calibrate_dp_phy) 1935 return cfg->calibrate_dp_phy(qphy); 1936 1937 return 0; 1938 } 1939 1940 static int qmp_combo_com_init(struct qmp_phy *qphy) 1941 { 1942 struct qcom_qmp *qmp = qphy->qmp; 1943 const struct qmp_phy_cfg *cfg = qphy->cfg; 1944 void __iomem *pcs = qphy->pcs; 1945 void __iomem *dp_com = qmp->dp_com; 1946 int ret; 1947 1948 mutex_lock(&qmp->phy_mutex); 1949 if (qmp->init_count++) { 1950 mutex_unlock(&qmp->phy_mutex); 1951 return 0; 1952 } 1953 1954 /* turn on regulator supplies */ 1955 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 1956 if (ret) { 1957 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 1958 goto err_unlock; 1959 } 1960 1961 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1962 if (ret) { 1963 dev_err(qmp->dev, "reset assert failed\n"); 1964 goto err_disable_regulators; 1965 } 1966 1967 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 1968 if (ret) { 1969 dev_err(qmp->dev, "reset deassert failed\n"); 1970 goto err_disable_regulators; 1971 } 1972 1973 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 1974 if (ret) 1975 goto err_assert_reset; 1976 1977 qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, SW_PWRDN); 1978 1979 /* override hardware control for reset of qmp phy */ 1980 qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 1981 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 1982 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 1983 1984 /* Default type-c orientation, i.e CC1 */ 1985 qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02); 1986 1987 qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL, USB3_MODE | DP_MODE); 1988 1989 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ 1990 qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 1991 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 1992 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 1993 1994 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); 1995 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); 1996 1997 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) 1998 qphy_setbits(pcs, 1999 cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2000 cfg->pwrdn_ctrl); 2001 else 2002 qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, 2003 cfg->pwrdn_ctrl); 2004 2005 mutex_unlock(&qmp->phy_mutex); 2006 2007 return 0; 2008 2009 err_assert_reset: 2010 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2011 err_disable_regulators: 2012 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2013 err_unlock: 2014 mutex_unlock(&qmp->phy_mutex); 2015 2016 return ret; 2017 } 2018 2019 static int qmp_combo_com_exit(struct qmp_phy *qphy) 2020 { 2021 struct qcom_qmp *qmp = qphy->qmp; 2022 const struct qmp_phy_cfg *cfg = qphy->cfg; 2023 2024 mutex_lock(&qmp->phy_mutex); 2025 if (--qmp->init_count) { 2026 mutex_unlock(&qmp->phy_mutex); 2027 return 0; 2028 } 2029 2030 reset_control_assert(qmp->ufs_reset); 2031 2032 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2033 2034 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2035 2036 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2037 2038 mutex_unlock(&qmp->phy_mutex); 2039 2040 return 0; 2041 } 2042 2043 static int qmp_combo_init(struct phy *phy) 2044 { 2045 struct qmp_phy *qphy = phy_get_drvdata(phy); 2046 struct qcom_qmp *qmp = qphy->qmp; 2047 const struct qmp_phy_cfg *cfg = qphy->cfg; 2048 int ret; 2049 dev_vdbg(qmp->dev, "Initializing QMP phy\n"); 2050 2051 ret = qmp_combo_com_init(qphy); 2052 if (ret) 2053 return ret; 2054 2055 if (cfg->type == PHY_TYPE_DP) 2056 cfg->dp_aux_init(qphy); 2057 2058 return 0; 2059 } 2060 2061 static int qmp_combo_power_on(struct phy *phy) 2062 { 2063 struct qmp_phy *qphy = phy_get_drvdata(phy); 2064 struct qcom_qmp *qmp = qphy->qmp; 2065 const struct qmp_phy_cfg *cfg = qphy->cfg; 2066 void __iomem *tx = qphy->tx; 2067 void __iomem *rx = qphy->rx; 2068 void __iomem *pcs = qphy->pcs; 2069 void __iomem *status; 2070 unsigned int mask, val, ready; 2071 int ret; 2072 2073 qmp_combo_serdes_init(qphy); 2074 2075 ret = clk_prepare_enable(qphy->pipe_clk); 2076 if (ret) { 2077 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 2078 return ret; 2079 } 2080 2081 /* Tx, Rx, and PCS configurations */ 2082 qmp_combo_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1); 2083 2084 if (cfg->lanes >= 2) { 2085 qmp_combo_configure_lane(qphy->tx2, cfg->regs, cfg->tx_tbl, 2086 cfg->tx_tbl_num, 2); 2087 } 2088 2089 /* Configure special DP tx tunings */ 2090 if (cfg->type == PHY_TYPE_DP) 2091 cfg->configure_dp_tx(qphy); 2092 2093 qmp_combo_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1); 2094 2095 if (cfg->lanes >= 2) { 2096 qmp_combo_configure_lane(qphy->rx2, cfg->regs, cfg->rx_tbl, 2097 cfg->rx_tbl_num, 2); 2098 } 2099 2100 /* Configure link rate, swing, etc. */ 2101 if (cfg->type == PHY_TYPE_DP) 2102 cfg->configure_dp_phy(qphy); 2103 else 2104 qmp_combo_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); 2105 2106 ret = reset_control_deassert(qmp->ufs_reset); 2107 if (ret) 2108 goto err_disable_pipe_clk; 2109 2110 if (cfg->has_pwrdn_delay) 2111 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); 2112 2113 if (cfg->type != PHY_TYPE_DP) { 2114 /* Pull PHY out of reset state */ 2115 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2116 /* start SerDes and Phy-Coding-Sublayer */ 2117 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 2118 2119 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 2120 mask = cfg->phy_status; 2121 ready = 0; 2122 2123 ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, 2124 PHY_INIT_COMPLETE_TIMEOUT); 2125 if (ret) { 2126 dev_err(qmp->dev, "phy initialization timed-out\n"); 2127 goto err_disable_pipe_clk; 2128 } 2129 } 2130 return 0; 2131 2132 err_disable_pipe_clk: 2133 clk_disable_unprepare(qphy->pipe_clk); 2134 2135 return ret; 2136 } 2137 2138 static int qmp_combo_power_off(struct phy *phy) 2139 { 2140 struct qmp_phy *qphy = phy_get_drvdata(phy); 2141 const struct qmp_phy_cfg *cfg = qphy->cfg; 2142 2143 clk_disable_unprepare(qphy->pipe_clk); 2144 2145 if (cfg->type == PHY_TYPE_DP) { 2146 /* Assert DP PHY power down */ 2147 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); 2148 } else { 2149 /* PHY reset */ 2150 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2151 2152 /* stop SerDes and Phy-Coding-Sublayer */ 2153 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 2154 2155 /* Put PHY into POWER DOWN state: active low */ 2156 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { 2157 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2158 cfg->pwrdn_ctrl); 2159 } else { 2160 qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, 2161 cfg->pwrdn_ctrl); 2162 } 2163 } 2164 2165 return 0; 2166 } 2167 2168 static int qmp_combo_exit(struct phy *phy) 2169 { 2170 struct qmp_phy *qphy = phy_get_drvdata(phy); 2171 2172 qmp_combo_com_exit(qphy); 2173 2174 return 0; 2175 } 2176 2177 static int qmp_combo_enable(struct phy *phy) 2178 { 2179 int ret; 2180 2181 ret = qmp_combo_init(phy); 2182 if (ret) 2183 return ret; 2184 2185 ret = qmp_combo_power_on(phy); 2186 if (ret) 2187 qmp_combo_exit(phy); 2188 2189 return ret; 2190 } 2191 2192 static int qmp_combo_disable(struct phy *phy) 2193 { 2194 int ret; 2195 2196 ret = qmp_combo_power_off(phy); 2197 if (ret) 2198 return ret; 2199 return qmp_combo_exit(phy); 2200 } 2201 2202 static int qmp_combo_set_mode(struct phy *phy, enum phy_mode mode, int submode) 2203 { 2204 struct qmp_phy *qphy = phy_get_drvdata(phy); 2205 2206 qphy->mode = mode; 2207 2208 return 0; 2209 } 2210 2211 static void qmp_combo_enable_autonomous_mode(struct qmp_phy *qphy) 2212 { 2213 const struct qmp_phy_cfg *cfg = qphy->cfg; 2214 void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs; 2215 void __iomem *pcs_misc = qphy->pcs_misc; 2216 u32 intr_mask; 2217 2218 if (qphy->mode == PHY_MODE_USB_HOST_SS || 2219 qphy->mode == PHY_MODE_USB_DEVICE_SS) 2220 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; 2221 else 2222 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; 2223 2224 /* Clear any pending interrupts status */ 2225 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2226 /* Writing 1 followed by 0 clears the interrupt */ 2227 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2228 2229 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 2230 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); 2231 2232 /* Enable required PHY autonomous mode interrupts */ 2233 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); 2234 2235 /* Enable i/o clamp_n for autonomous mode */ 2236 if (pcs_misc) 2237 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 2238 } 2239 2240 static void qmp_combo_disable_autonomous_mode(struct qmp_phy *qphy) 2241 { 2242 const struct qmp_phy_cfg *cfg = qphy->cfg; 2243 void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs_usb; 2244 void __iomem *pcs_misc = qphy->pcs_misc; 2245 2246 /* Disable i/o clamp_n on resume for normal mode */ 2247 if (pcs_misc) 2248 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 2249 2250 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 2251 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); 2252 2253 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2254 /* Writing 1 followed by 0 clears the interrupt */ 2255 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2256 } 2257 2258 static int __maybe_unused qmp_combo_runtime_suspend(struct device *dev) 2259 { 2260 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2261 struct qmp_phy *qphy = qmp->phys[0]; 2262 const struct qmp_phy_cfg *cfg = qphy->cfg; 2263 2264 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode); 2265 2266 /* Supported only for USB3 PHY and luckily USB3 is the first phy */ 2267 if (cfg->type != PHY_TYPE_USB3) 2268 return 0; 2269 2270 if (!qmp->init_count) { 2271 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2272 return 0; 2273 } 2274 2275 qmp_combo_enable_autonomous_mode(qphy); 2276 2277 clk_disable_unprepare(qphy->pipe_clk); 2278 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2279 2280 return 0; 2281 } 2282 2283 static int __maybe_unused qmp_combo_runtime_resume(struct device *dev) 2284 { 2285 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2286 struct qmp_phy *qphy = qmp->phys[0]; 2287 const struct qmp_phy_cfg *cfg = qphy->cfg; 2288 int ret = 0; 2289 2290 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode); 2291 2292 /* Supported only for USB3 PHY and luckily USB3 is the first phy */ 2293 if (cfg->type != PHY_TYPE_USB3) 2294 return 0; 2295 2296 if (!qmp->init_count) { 2297 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2298 return 0; 2299 } 2300 2301 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 2302 if (ret) 2303 return ret; 2304 2305 ret = clk_prepare_enable(qphy->pipe_clk); 2306 if (ret) { 2307 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); 2308 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2309 return ret; 2310 } 2311 2312 qmp_combo_disable_autonomous_mode(qphy); 2313 2314 return 0; 2315 } 2316 2317 static int qmp_combo_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2318 { 2319 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2320 int num = cfg->num_vregs; 2321 int ret, i; 2322 2323 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 2324 if (!qmp->vregs) 2325 return -ENOMEM; 2326 2327 for (i = 0; i < num; i++) 2328 qmp->vregs[i].supply = cfg->vreg_list[i].name; 2329 2330 ret = devm_regulator_bulk_get(dev, num, qmp->vregs); 2331 if (ret) { 2332 dev_err(dev, "failed at devm_regulator_bulk_get\n"); 2333 return ret; 2334 } 2335 2336 for (i = 0; i < num; i++) { 2337 ret = regulator_set_load(qmp->vregs[i].consumer, 2338 cfg->vreg_list[i].enable_load); 2339 if (ret) { 2340 dev_err(dev, "failed to set load at %s\n", 2341 qmp->vregs[i].supply); 2342 return ret; 2343 } 2344 } 2345 2346 return 0; 2347 } 2348 2349 static int qmp_combo_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2350 { 2351 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2352 int i; 2353 int ret; 2354 2355 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 2356 sizeof(*qmp->resets), GFP_KERNEL); 2357 if (!qmp->resets) 2358 return -ENOMEM; 2359 2360 for (i = 0; i < cfg->num_resets; i++) 2361 qmp->resets[i].id = cfg->reset_list[i]; 2362 2363 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 2364 if (ret) 2365 return dev_err_probe(dev, ret, "failed to get resets\n"); 2366 2367 return 0; 2368 } 2369 2370 static int qmp_combo_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2371 { 2372 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2373 int num = cfg->num_clks; 2374 int i; 2375 2376 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 2377 if (!qmp->clks) 2378 return -ENOMEM; 2379 2380 for (i = 0; i < num; i++) 2381 qmp->clks[i].id = cfg->clk_list[i]; 2382 2383 return devm_clk_bulk_get(dev, num, qmp->clks); 2384 } 2385 2386 static void phy_clk_release_provider(void *res) 2387 { 2388 of_clk_del_provider(res); 2389 } 2390 2391 /* 2392 * Register a fixed rate pipe clock. 2393 * 2394 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 2395 * controls it. The <s>_pipe_clk coming out of the GCC is requested 2396 * by the PHY driver for its operations. 2397 * We register the <s>_pipe_clksrc here. The gcc driver takes care 2398 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 2399 * Below picture shows this relationship. 2400 * 2401 * +---------------+ 2402 * | PHY block |<<---------------------------------------+ 2403 * | | | 2404 * | +-------+ | +-----+ | 2405 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 2406 * clk | +-------+ | +-----+ 2407 * +---------------+ 2408 */ 2409 static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) 2410 { 2411 struct clk_fixed_rate *fixed; 2412 struct clk_init_data init = { }; 2413 int ret; 2414 2415 ret = of_property_read_string(np, "clock-output-names", &init.name); 2416 if (ret) { 2417 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 2418 return ret; 2419 } 2420 2421 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); 2422 if (!fixed) 2423 return -ENOMEM; 2424 2425 init.ops = &clk_fixed_rate_ops; 2426 2427 /* controllers using QMP phys use 125MHz pipe clock interface */ 2428 fixed->fixed_rate = 125000000; 2429 fixed->hw.init = &init; 2430 2431 ret = devm_clk_hw_register(qmp->dev, &fixed->hw); 2432 if (ret) 2433 return ret; 2434 2435 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); 2436 if (ret) 2437 return ret; 2438 2439 /* 2440 * Roll a devm action because the clock provider is the child node, but 2441 * the child node is not actually a device. 2442 */ 2443 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 2444 } 2445 2446 /* 2447 * Display Port PLL driver block diagram for branch clocks 2448 * 2449 * +------------------------------+ 2450 * | DP_VCO_CLK | 2451 * | | 2452 * | +-------------------+ | 2453 * | | (DP PLL/VCO) | | 2454 * | +---------+---------+ | 2455 * | v | 2456 * | +----------+-----------+ | 2457 * | | hsclk_divsel_clk_src | | 2458 * | +----------+-----------+ | 2459 * +------------------------------+ 2460 * | 2461 * +---------<---------v------------>----------+ 2462 * | | 2463 * +--------v----------------+ | 2464 * | dp_phy_pll_link_clk | | 2465 * | link_clk | | 2466 * +--------+----------------+ | 2467 * | | 2468 * | | 2469 * v v 2470 * Input to DISPCC block | 2471 * for link clk, crypto clk | 2472 * and interface clock | 2473 * | 2474 * | 2475 * +--------<------------+-----------------+---<---+ 2476 * | | | 2477 * +----v---------+ +--------v-----+ +--------v------+ 2478 * | vco_divided | | vco_divided | | vco_divided | 2479 * | _clk_src | | _clk_src | | _clk_src | 2480 * | | | | | | 2481 * |divsel_six | | divsel_two | | divsel_four | 2482 * +-------+------+ +-----+--------+ +--------+------+ 2483 * | | | 2484 * v---->----------v-------------<------v 2485 * | 2486 * +----------+-----------------+ 2487 * | dp_phy_pll_vco_div_clk | 2488 * +---------+------------------+ 2489 * | 2490 * v 2491 * Input to DISPCC block 2492 * for DP pixel clock 2493 * 2494 */ 2495 static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, 2496 struct clk_rate_request *req) 2497 { 2498 switch (req->rate) { 2499 case 1620000000UL / 2: 2500 case 2700000000UL / 2: 2501 /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ 2502 return 0; 2503 default: 2504 return -EINVAL; 2505 } 2506 } 2507 2508 static unsigned long 2509 qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 2510 { 2511 const struct qmp_phy_dp_clks *dp_clks; 2512 const struct qmp_phy *qphy; 2513 const struct phy_configure_opts_dp *dp_opts; 2514 2515 dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw); 2516 qphy = dp_clks->qphy; 2517 dp_opts = &qphy->dp_opts; 2518 2519 switch (dp_opts->link_rate) { 2520 case 1620: 2521 return 1620000000UL / 2; 2522 case 2700: 2523 return 2700000000UL / 2; 2524 case 5400: 2525 return 5400000000UL / 4; 2526 case 8100: 2527 return 8100000000UL / 6; 2528 default: 2529 return 0; 2530 } 2531 } 2532 2533 static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = { 2534 .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate, 2535 .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate, 2536 }; 2537 2538 static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw, 2539 struct clk_rate_request *req) 2540 { 2541 switch (req->rate) { 2542 case 162000000: 2543 case 270000000: 2544 case 540000000: 2545 case 810000000: 2546 return 0; 2547 default: 2548 return -EINVAL; 2549 } 2550 } 2551 2552 static unsigned long 2553 qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 2554 { 2555 const struct qmp_phy_dp_clks *dp_clks; 2556 const struct qmp_phy *qphy; 2557 const struct phy_configure_opts_dp *dp_opts; 2558 2559 dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw); 2560 qphy = dp_clks->qphy; 2561 dp_opts = &qphy->dp_opts; 2562 2563 switch (dp_opts->link_rate) { 2564 case 1620: 2565 case 2700: 2566 case 5400: 2567 case 8100: 2568 return dp_opts->link_rate * 100000; 2569 default: 2570 return 0; 2571 } 2572 } 2573 2574 static const struct clk_ops qcom_qmp_dp_link_clk_ops = { 2575 .determine_rate = qcom_qmp_dp_link_clk_determine_rate, 2576 .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate, 2577 }; 2578 2579 static struct clk_hw * 2580 qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) 2581 { 2582 struct qmp_phy_dp_clks *dp_clks = data; 2583 unsigned int idx = clkspec->args[0]; 2584 2585 if (idx >= 2) { 2586 pr_err("%s: invalid index %u\n", __func__, idx); 2587 return ERR_PTR(-EINVAL); 2588 } 2589 2590 if (idx == 0) 2591 return &dp_clks->dp_link_hw; 2592 2593 return &dp_clks->dp_pixel_hw; 2594 } 2595 2596 static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy, 2597 struct device_node *np) 2598 { 2599 struct clk_init_data init = { }; 2600 struct qmp_phy_dp_clks *dp_clks; 2601 char name[64]; 2602 int ret; 2603 2604 dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL); 2605 if (!dp_clks) 2606 return -ENOMEM; 2607 2608 dp_clks->qphy = qphy; 2609 qphy->dp_clks = dp_clks; 2610 2611 snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); 2612 init.ops = &qcom_qmp_dp_link_clk_ops; 2613 init.name = name; 2614 dp_clks->dp_link_hw.init = &init; 2615 ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw); 2616 if (ret) 2617 return ret; 2618 2619 snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); 2620 init.ops = &qcom_qmp_dp_pixel_clk_ops; 2621 init.name = name; 2622 dp_clks->dp_pixel_hw.init = &init; 2623 ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw); 2624 if (ret) 2625 return ret; 2626 2627 ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks); 2628 if (ret) 2629 return ret; 2630 2631 /* 2632 * Roll a devm action because the clock provider is the child node, but 2633 * the child node is not actually a device. 2634 */ 2635 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 2636 } 2637 2638 static const struct phy_ops qmp_combo_usb_ops = { 2639 .init = qmp_combo_enable, 2640 .exit = qmp_combo_disable, 2641 .set_mode = qmp_combo_set_mode, 2642 .owner = THIS_MODULE, 2643 }; 2644 2645 static const struct phy_ops qmp_combo_dp_ops = { 2646 .init = qmp_combo_init, 2647 .configure = qcom_qmp_dp_phy_configure, 2648 .power_on = qmp_combo_power_on, 2649 .calibrate = qcom_qmp_dp_phy_calibrate, 2650 .power_off = qmp_combo_power_off, 2651 .exit = qmp_combo_exit, 2652 .set_mode = qmp_combo_set_mode, 2653 .owner = THIS_MODULE, 2654 }; 2655 2656 static int qmp_combo_create(struct device *dev, struct device_node *np, int id, 2657 void __iomem *serdes, const struct qmp_phy_cfg *cfg) 2658 { 2659 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2660 struct phy *generic_phy; 2661 struct qmp_phy *qphy; 2662 const struct phy_ops *ops; 2663 int ret; 2664 2665 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); 2666 if (!qphy) 2667 return -ENOMEM; 2668 2669 qphy->cfg = cfg; 2670 qphy->serdes = serdes; 2671 /* 2672 * Get memory resources for each phy lane: 2673 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 2674 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 2675 * For single lane PHYs: pcs_misc (optional) -> 3. 2676 */ 2677 qphy->tx = devm_of_iomap(dev, np, 0, NULL); 2678 if (IS_ERR(qphy->tx)) 2679 return PTR_ERR(qphy->tx); 2680 2681 qphy->rx = devm_of_iomap(dev, np, 1, NULL); 2682 if (IS_ERR(qphy->rx)) 2683 return PTR_ERR(qphy->rx); 2684 2685 qphy->pcs = devm_of_iomap(dev, np, 2, NULL); 2686 if (IS_ERR(qphy->pcs)) 2687 return PTR_ERR(qphy->pcs); 2688 2689 if (cfg->pcs_usb_offset) 2690 qphy->pcs_usb = qphy->pcs + cfg->pcs_usb_offset; 2691 2692 if (cfg->lanes >= 2) { 2693 qphy->tx2 = devm_of_iomap(dev, np, 3, NULL); 2694 if (IS_ERR(qphy->tx2)) 2695 return PTR_ERR(qphy->tx2); 2696 2697 qphy->rx2 = devm_of_iomap(dev, np, 4, NULL); 2698 if (IS_ERR(qphy->rx2)) 2699 return PTR_ERR(qphy->rx2); 2700 2701 qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 2702 } else { 2703 qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 2704 } 2705 2706 if (IS_ERR(qphy->pcs_misc)) { 2707 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 2708 qphy->pcs_misc = NULL; 2709 } 2710 2711 /* 2712 * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3 2713 * based phys, so they essentially have pipe clock. So, 2714 * we return error in case phy is USB3 or PIPE type. 2715 * Otherwise, we initialize pipe clock to NULL for 2716 * all phys that don't need this. 2717 */ 2718 qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 2719 if (IS_ERR(qphy->pipe_clk)) { 2720 if (cfg->type == PHY_TYPE_USB3) 2721 return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk), 2722 "failed to get lane%d pipe_clk\n", 2723 id); 2724 qphy->pipe_clk = NULL; 2725 } 2726 2727 if (cfg->type == PHY_TYPE_DP) 2728 ops = &qmp_combo_dp_ops; 2729 else 2730 ops = &qmp_combo_usb_ops; 2731 2732 generic_phy = devm_phy_create(dev, np, ops); 2733 if (IS_ERR(generic_phy)) { 2734 ret = PTR_ERR(generic_phy); 2735 dev_err(dev, "failed to create qphy %d\n", ret); 2736 return ret; 2737 } 2738 2739 qphy->phy = generic_phy; 2740 qphy->qmp = qmp; 2741 qmp->phys[id] = qphy; 2742 phy_set_drvdata(generic_phy, qphy); 2743 2744 return 0; 2745 } 2746 2747 static const struct of_device_id qmp_combo_of_match_table[] = { 2748 { 2749 .compatible = "qcom,sc7180-qmp-usb3-dp-phy", 2750 .data = &sc7180_usb3dpphy_cfg, 2751 }, 2752 { 2753 .compatible = "qcom,sdm845-qmp-usb3-dp-phy", 2754 .data = &sdm845_usb3dpphy_cfg, 2755 }, 2756 { 2757 .compatible = "qcom,sm8250-qmp-usb3-dp-phy", 2758 .data = &sm8250_usb3dpphy_cfg, 2759 }, 2760 { 2761 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", 2762 .data = &sc8180x_usb3dpphy_cfg, 2763 }, 2764 { 2765 .compatible = "qcom,sc8280xp-qmp-usb43dp-phy", 2766 .data = &sc8280xp_usb43dpphy_combo_cfg, 2767 }, 2768 { } 2769 }; 2770 MODULE_DEVICE_TABLE(of, qmp_combo_of_match_table); 2771 2772 static const struct dev_pm_ops qmp_combo_pm_ops = { 2773 SET_RUNTIME_PM_OPS(qmp_combo_runtime_suspend, 2774 qmp_combo_runtime_resume, NULL) 2775 }; 2776 2777 static int qmp_combo_probe(struct platform_device *pdev) 2778 { 2779 struct qcom_qmp *qmp; 2780 struct device *dev = &pdev->dev; 2781 struct device_node *child; 2782 struct phy_provider *phy_provider; 2783 void __iomem *serdes; 2784 void __iomem *usb_serdes; 2785 void __iomem *dp_serdes = NULL; 2786 const struct qmp_phy_combo_cfg *combo_cfg = NULL; 2787 const struct qmp_phy_cfg *cfg = NULL; 2788 const struct qmp_phy_cfg *usb_cfg = NULL; 2789 const struct qmp_phy_cfg *dp_cfg = NULL; 2790 int num, id, expected_phys; 2791 int ret; 2792 2793 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 2794 if (!qmp) 2795 return -ENOMEM; 2796 2797 qmp->dev = dev; 2798 dev_set_drvdata(dev, qmp); 2799 2800 /* Get the specific init parameters of QMP phy */ 2801 combo_cfg = of_device_get_match_data(dev); 2802 if (!combo_cfg) 2803 return -EINVAL; 2804 2805 usb_cfg = combo_cfg->usb_cfg; 2806 cfg = usb_cfg; /* Setup clks and regulators */ 2807 2808 /* per PHY serdes; usually located at base address */ 2809 usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0); 2810 if (IS_ERR(serdes)) 2811 return PTR_ERR(serdes); 2812 2813 qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); 2814 if (IS_ERR(qmp->dp_com)) 2815 return PTR_ERR(qmp->dp_com); 2816 2817 /* Only two serdes for combo PHY */ 2818 dp_serdes = devm_platform_ioremap_resource(pdev, 2); 2819 if (IS_ERR(dp_serdes)) 2820 return PTR_ERR(dp_serdes); 2821 2822 dp_cfg = combo_cfg->dp_cfg; 2823 expected_phys = 2; 2824 2825 mutex_init(&qmp->phy_mutex); 2826 2827 ret = qmp_combo_clk_init(dev, cfg); 2828 if (ret) 2829 return ret; 2830 2831 ret = qmp_combo_reset_init(dev, cfg); 2832 if (ret) 2833 return ret; 2834 2835 ret = qmp_combo_vreg_init(dev, cfg); 2836 if (ret) 2837 return dev_err_probe(dev, ret, 2838 "failed to get regulator supplies\n"); 2839 2840 num = of_get_available_child_count(dev->of_node); 2841 /* do we have a rogue child node ? */ 2842 if (num > expected_phys) 2843 return -EINVAL; 2844 2845 qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); 2846 if (!qmp->phys) 2847 return -ENOMEM; 2848 2849 pm_runtime_set_active(dev); 2850 ret = devm_pm_runtime_enable(dev); 2851 if (ret) 2852 return ret; 2853 /* 2854 * Prevent runtime pm from being ON by default. Users can enable 2855 * it using power/control in sysfs. 2856 */ 2857 pm_runtime_forbid(dev); 2858 2859 id = 0; 2860 for_each_available_child_of_node(dev->of_node, child) { 2861 if (of_node_name_eq(child, "dp-phy")) { 2862 cfg = dp_cfg; 2863 serdes = dp_serdes; 2864 2865 /* Create per-lane phy */ 2866 ret = qmp_combo_create(dev, child, id, serdes, cfg); 2867 if (ret) { 2868 dev_err(dev, "failed to create lane%d phy, %d\n", 2869 id, ret); 2870 goto err_node_put; 2871 } 2872 2873 ret = phy_dp_clks_register(qmp, qmp->phys[id], child); 2874 if (ret) { 2875 dev_err(qmp->dev, 2876 "failed to register DP clock source\n"); 2877 goto err_node_put; 2878 } 2879 } else if (of_node_name_eq(child, "usb3-phy")) { 2880 cfg = usb_cfg; 2881 serdes = usb_serdes; 2882 2883 /* Create per-lane phy */ 2884 ret = qmp_combo_create(dev, child, id, serdes, cfg); 2885 if (ret) { 2886 dev_err(dev, "failed to create lane%d phy, %d\n", 2887 id, ret); 2888 goto err_node_put; 2889 } 2890 2891 /* 2892 * Register the pipe clock provided by phy. 2893 * See function description to see details of this pipe clock. 2894 */ 2895 ret = phy_pipe_clk_register(qmp, child); 2896 if (ret) { 2897 dev_err(qmp->dev, 2898 "failed to register pipe clock source\n"); 2899 goto err_node_put; 2900 } 2901 } 2902 2903 id++; 2904 } 2905 2906 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2907 2908 return PTR_ERR_OR_ZERO(phy_provider); 2909 2910 err_node_put: 2911 of_node_put(child); 2912 return ret; 2913 } 2914 2915 static struct platform_driver qmp_combo_driver = { 2916 .probe = qmp_combo_probe, 2917 .driver = { 2918 .name = "qcom-qmp-combo-phy", 2919 .pm = &qmp_combo_pm_ops, 2920 .of_match_table = qmp_combo_of_match_table, 2921 }, 2922 }; 2923 2924 module_platform_driver(qmp_combo_driver); 2925 2926 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 2927 MODULE_DESCRIPTION("Qualcomm QMP USB+DP combo PHY driver"); 2928 MODULE_LICENSE("GPL v2"); 2929