1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/phy/phy.h> 17 #include <linux/platform_device.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/reset.h> 20 #include <linux/slab.h> 21 #include <linux/usb/typec.h> 22 #include <linux/usb/typec_mux.h> 23 24 #include <drm/drm_bridge.h> 25 26 #include <dt-bindings/phy/phy-qcom-qmp.h> 27 28 #include "phy-qcom-qmp.h" 29 #include "phy-qcom-qmp-pcs-misc-v3.h" 30 #include "phy-qcom-qmp-pcs-usb-v4.h" 31 #include "phy-qcom-qmp-pcs-usb-v5.h" 32 #include "phy-qcom-qmp-pcs-usb-v6.h" 33 34 /* QPHY_SW_RESET bit */ 35 #define SW_RESET BIT(0) 36 /* QPHY_POWER_DOWN_CONTROL */ 37 #define SW_PWRDN BIT(0) 38 /* QPHY_START_CONTROL bits */ 39 #define SERDES_START BIT(0) 40 #define PCS_START BIT(1) 41 /* QPHY_PCS_STATUS bit */ 42 #define PHYSTATUS BIT(6) 43 44 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ 45 /* DP PHY soft reset */ 46 #define SW_DPPHY_RESET BIT(0) 47 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */ 48 #define SW_DPPHY_RESET_MUX BIT(1) 49 /* USB3 PHY soft reset */ 50 #define SW_USB3PHY_RESET BIT(2) 51 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ 52 #define SW_USB3PHY_RESET_MUX BIT(3) 53 54 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ 55 #define USB3_MODE BIT(0) /* enables USB3 mode */ 56 #define DP_MODE BIT(1) /* enables DP mode */ 57 58 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ 59 #define ARCVR_DTCT_EN BIT(0) 60 #define ALFPS_DTCT_EN BIT(1) 61 #define ARCVR_DTCT_EVENT_SEL BIT(4) 62 63 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ 64 #define IRQ_CLEAR BIT(0) 65 66 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ 67 #define CLAMP_EN BIT(0) /* enables i/o clamp_n */ 68 69 /* QPHY_V3_DP_COM_TYPEC_CTRL register bits */ 70 #define SW_PORTSELECT_VAL BIT(0) 71 #define SW_PORTSELECT_MUX BIT(1) 72 73 #define PHY_INIT_COMPLETE_TIMEOUT 10000 74 75 struct qmp_phy_init_tbl { 76 unsigned int offset; 77 unsigned int val; 78 /* 79 * mask of lanes for which this register is written 80 * for cases when second lane needs different values 81 */ 82 u8 lane_mask; 83 }; 84 85 #define QMP_PHY_INIT_CFG(o, v) \ 86 { \ 87 .offset = o, \ 88 .val = v, \ 89 .lane_mask = 0xff, \ 90 } 91 92 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ 93 { \ 94 .offset = o, \ 95 .val = v, \ 96 .lane_mask = l, \ 97 } 98 99 /* set of registers with offsets different per-PHY */ 100 enum qphy_reg_layout { 101 /* PCS registers */ 102 QPHY_SW_RESET, 103 QPHY_START_CTRL, 104 QPHY_PCS_STATUS, 105 QPHY_PCS_AUTONOMOUS_MODE_CTRL, 106 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, 107 QPHY_PCS_POWER_DOWN_CONTROL, 108 109 QPHY_COM_RESETSM_CNTRL, 110 QPHY_COM_C_READY_STATUS, 111 QPHY_COM_CMN_STATUS, 112 QPHY_COM_BIAS_EN_CLKBUFLR_EN, 113 114 QPHY_DP_PHY_STATUS, 115 116 QPHY_TX_TX_POL_INV, 117 QPHY_TX_TX_DRV_LVL, 118 QPHY_TX_TX_EMP_POST1_LVL, 119 QPHY_TX_HIGHZ_DRVR_EN, 120 QPHY_TX_TRANSCEIVER_BIAS_EN, 121 122 /* Keep last to ensure regs_layout arrays are properly initialized */ 123 QPHY_LAYOUT_SIZE 124 }; 125 126 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 127 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, 128 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, 129 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, 130 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, 131 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL, 132 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR, 133 134 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V3_COM_RESETSM_CNTRL, 135 [QPHY_COM_C_READY_STATUS] = QSERDES_V3_COM_C_READY_STATUS, 136 [QPHY_COM_CMN_STATUS] = QSERDES_V3_COM_CMN_STATUS, 137 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 138 139 [QPHY_DP_PHY_STATUS] = QSERDES_V3_DP_PHY_STATUS, 140 141 [QPHY_TX_TX_POL_INV] = QSERDES_V3_TX_TX_POL_INV, 142 [QPHY_TX_TX_DRV_LVL] = QSERDES_V3_TX_TX_DRV_LVL, 143 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V3_TX_TX_EMP_POST1_LVL, 144 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V3_TX_HIGHZ_DRVR_EN, 145 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 146 }; 147 148 static const unsigned int qmp_v45_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 149 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, 150 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, 151 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, 152 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, 153 154 /* In PCS_USB */ 155 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL, 156 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 157 158 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V4_COM_RESETSM_CNTRL, 159 [QPHY_COM_C_READY_STATUS] = QSERDES_V4_COM_C_READY_STATUS, 160 [QPHY_COM_CMN_STATUS] = QSERDES_V4_COM_CMN_STATUS, 161 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 162 163 [QPHY_DP_PHY_STATUS] = QSERDES_V4_DP_PHY_STATUS, 164 165 [QPHY_TX_TX_POL_INV] = QSERDES_V4_TX_TX_POL_INV, 166 [QPHY_TX_TX_DRV_LVL] = QSERDES_V4_TX_TX_DRV_LVL, 167 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V4_TX_TX_EMP_POST1_LVL, 168 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V4_TX_HIGHZ_DRVR_EN, 169 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V4_TX_TRANSCEIVER_BIAS_EN, 170 }; 171 172 static const unsigned int qmp_v5_5nm_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 173 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, 174 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, 175 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, 176 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, 177 178 /* In PCS_USB */ 179 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL, 180 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 181 182 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V5_COM_RESETSM_CNTRL, 183 [QPHY_COM_C_READY_STATUS] = QSERDES_V5_COM_C_READY_STATUS, 184 [QPHY_COM_CMN_STATUS] = QSERDES_V5_COM_CMN_STATUS, 185 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 186 187 [QPHY_DP_PHY_STATUS] = QSERDES_V5_DP_PHY_STATUS, 188 189 [QPHY_TX_TX_POL_INV] = QSERDES_V5_5NM_TX_TX_POL_INV, 190 [QPHY_TX_TX_DRV_LVL] = QSERDES_V5_5NM_TX_TX_DRV_LVL, 191 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL, 192 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN, 193 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 194 }; 195 196 static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 197 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, 198 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, 199 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, 200 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, 201 202 /* In PCS_USB */ 203 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL, 204 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 205 206 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V6_COM_RESETSM_CNTRL, 207 [QPHY_COM_C_READY_STATUS] = QSERDES_V6_COM_C_READY_STATUS, 208 [QPHY_COM_CMN_STATUS] = QSERDES_V6_COM_CMN_STATUS, 209 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 210 211 [QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS, 212 213 [QPHY_TX_TX_POL_INV] = QSERDES_V6_TX_TX_POL_INV, 214 [QPHY_TX_TX_DRV_LVL] = QSERDES_V6_TX_TX_DRV_LVL, 215 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V6_TX_TX_EMP_POST1_LVL, 216 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V6_TX_HIGHZ_DRVR_EN, 217 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V6_TX_TRANSCEIVER_BIAS_EN, 218 }; 219 220 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { 221 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 222 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 223 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 224 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 225 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 226 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 227 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16), 228 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 229 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 230 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 231 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 232 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 233 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 234 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 235 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 236 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 237 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 238 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 239 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 240 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 241 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 242 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 243 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 244 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 245 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 246 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 247 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 248 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 249 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), 250 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 251 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 252 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 253 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 254 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 255 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 256 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 257 }; 258 259 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { 260 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 261 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 262 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), 263 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 264 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 265 }; 266 267 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = { 268 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 269 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37), 270 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 271 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e), 272 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 273 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 274 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02), 275 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00), 276 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 277 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 278 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 279 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 280 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), 281 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 282 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), 283 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), 284 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f), 285 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 286 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 287 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 288 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 289 }; 290 291 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = { 292 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c), 293 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 294 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 295 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 296 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f), 297 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08), 298 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 299 }; 300 301 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = { 302 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04), 303 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 304 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 305 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 306 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f), 307 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e), 308 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 309 }; 310 311 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = { 312 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 313 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c), 314 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00), 315 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a), 316 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f), 317 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c), 318 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 319 }; 320 321 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = { 322 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03), 323 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 324 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 325 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 326 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f), 327 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a), 328 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08), 329 }; 330 331 static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = { 332 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), 333 QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), 334 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 335 QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), 336 QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), 337 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), 338 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), 339 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 340 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), 341 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), 342 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a), 343 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38), 344 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20), 345 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 346 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), 347 }; 348 349 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { 350 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 351 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 352 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 353 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 354 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 355 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 356 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 357 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 358 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 359 }; 360 361 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { 362 /* FLL settings */ 363 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 364 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 365 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 366 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 367 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 368 369 /* Lock Det settings */ 370 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 371 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 372 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 373 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 374 375 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), 376 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 377 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 378 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 379 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 380 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 381 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 382 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 383 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 384 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 385 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 386 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 387 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 388 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 389 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 390 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 391 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 392 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 393 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 394 395 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 396 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 397 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 398 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 399 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 400 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 401 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 402 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 403 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 404 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 405 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 406 }; 407 408 static const struct qmp_phy_init_tbl sm6350_usb3_rx_tbl[] = { 409 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 410 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 411 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 412 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 413 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 414 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 415 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 416 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 417 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), 418 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 419 }; 420 421 static const struct qmp_phy_init_tbl sm6350_usb3_pcs_tbl[] = { 422 /* FLL settings */ 423 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 424 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 425 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 426 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 427 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 428 429 /* Lock Det settings */ 430 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 431 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 432 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 433 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 434 435 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xcc), 436 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 437 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 438 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 439 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 440 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 441 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 442 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 443 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 444 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 445 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 446 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 447 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 448 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 449 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 450 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 451 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 452 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 453 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 454 455 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 456 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 457 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 458 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 459 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 460 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 461 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 462 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 463 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 464 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 465 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 466 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL, 0x04), 467 468 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21), 469 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), 470 }; 471 472 static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = { 473 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 474 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 475 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 476 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 477 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 478 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), 479 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), 480 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), 481 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), 482 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 483 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 484 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 485 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 486 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 487 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 488 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), 489 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 490 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), 491 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), 492 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), 493 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), 494 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 495 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), 496 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), 497 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), 498 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), 499 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 500 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 501 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), 502 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 503 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 504 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), 505 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), 506 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 507 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 508 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 509 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 510 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 511 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 512 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 513 }; 514 515 static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = { 516 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00), 517 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00), 518 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 519 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 520 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 521 }; 522 523 static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = { 524 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), 525 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 526 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 527 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 528 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 529 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 530 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 531 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 532 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 533 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 534 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 535 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e), 536 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 537 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 538 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 539 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 540 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 541 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 542 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 543 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 544 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 545 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf), 546 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f), 547 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 548 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94), 549 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 550 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 551 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 552 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), 553 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), 554 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 555 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 556 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 557 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 558 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 559 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 560 }; 561 562 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = { 563 /* Lock Det settings */ 564 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 565 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 566 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 567 568 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 569 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 570 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 571 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 572 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 573 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 574 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 575 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 576 }; 577 578 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = { 579 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 580 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 581 }; 582 583 static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = { 584 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60), 585 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60), 586 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 587 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), 588 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 589 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 590 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1), 591 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2), 592 }; 593 594 static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = { 595 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), 596 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 597 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 598 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 599 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 600 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 601 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 602 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 603 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 604 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 605 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 606 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 607 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 608 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 609 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 610 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 611 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 612 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 613 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 614 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 615 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1), 616 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2), 617 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1), 618 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2), 619 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f), 620 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 621 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97), 622 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 623 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 624 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 625 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 626 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 627 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 628 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 629 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 630 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 631 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 632 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 633 }; 634 635 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = { 636 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 637 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 638 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 639 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 640 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 641 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), 642 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 643 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 644 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 645 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 646 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 647 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 648 }; 649 650 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = { 651 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 652 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 653 }; 654 655 static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = { 656 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00), 657 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00), 658 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), 659 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 660 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35), 661 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 662 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f), 663 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f), 664 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12), 665 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 666 }; 667 668 static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = { 669 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), 670 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 671 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 672 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 673 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 674 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 675 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 676 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 677 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 678 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 679 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 680 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 681 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 682 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 683 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 684 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 685 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 686 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 687 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 688 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 689 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 690 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb), 691 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b), 692 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb), 693 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1), 694 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2), 695 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), 696 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 697 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 698 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2), 699 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13), 700 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 701 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04), 702 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 703 QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 704 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), 705 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 706 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10), 707 }; 708 709 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = { 710 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 711 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 712 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 713 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 714 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 715 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 716 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 717 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 718 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 719 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 720 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 721 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 722 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 723 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 724 }; 725 726 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] = { 727 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 728 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 729 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 730 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 731 }; 732 733 static const struct qmp_phy_init_tbl sm8550_usb3_serdes_tbl[] = { 734 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc0), 735 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01), 736 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 737 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 738 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 739 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 740 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16), 741 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41), 742 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x41), 743 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00), 744 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 745 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x75), 746 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01), 747 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 748 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25), 749 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02), 750 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c), 751 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f), 752 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c), 753 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f), 754 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc0), 755 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 756 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 757 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 758 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 759 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08), 760 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a), 761 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 762 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00), 763 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55), 764 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x75), 765 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 766 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25), 767 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02), 768 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 769 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 770 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 771 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 772 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0c), 773 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a), 774 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14), 775 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 776 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20), 777 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 778 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), 779 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b), 780 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37), 781 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c), 782 }; 783 784 static const struct qmp_phy_init_tbl sm8550_usb3_tx_tbl[] = { 785 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00), 786 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00), 787 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 788 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 789 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5), 790 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f), 791 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f), 792 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f), 793 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x12), 794 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x21, 1), 795 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x05, 2), 796 }; 797 798 static const struct qmp_phy_init_tbl sm8550_usb3_rx_tbl[] = { 799 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a), 800 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06), 801 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 802 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 803 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 804 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 805 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99), 806 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), 807 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08), 808 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00), 809 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x0a), 810 QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 811 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54), 812 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f), 813 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13), 814 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 815 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 816 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 817 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07), 818 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 819 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 820 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04), 821 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 822 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc), 823 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c), 824 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c), 825 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d), 826 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09), 827 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04), 828 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 829 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c), 830 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10), 831 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14), 832 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08), 833 834 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f, 1), 835 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 1), 836 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff, 1), 837 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 1), 838 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xed, 1), 839 840 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0xbf, 2), 841 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 2), 842 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf, 2), 843 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 2), 844 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xfd, 2), 845 }; 846 847 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_tbl[] = { 848 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4), 849 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG2, 0x89), 850 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG3, 0x20), 851 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG6, 0x13), 852 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_REFGEN_REQ_CONFIG1, 0x21), 853 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_RX_SIGDET_LVL, 0x99), 854 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 855 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 856 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_CDR_RESET_TIME, 0x0a), 857 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88), 858 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13), 859 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_PCS_TX_RX_CONFIG, 0x0c), 860 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_EQ_CONFIG1, 0x4b), 861 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_EQ_CONFIG5, 0x10), 862 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_POWER_STATE_CONFIG1, 0x68), 863 }; 864 865 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_usb_tbl[] = { 866 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 867 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 868 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 869 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 870 }; 871 872 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = { 873 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), 874 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), 875 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), 876 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), 877 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), 878 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), 879 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 880 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 881 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 882 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 883 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), 884 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 885 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 886 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00), 887 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), 888 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), 889 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), 890 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), 891 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), 892 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), 893 }; 894 895 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = { 896 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05), 897 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 898 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 899 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 900 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f), 901 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08), 902 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 903 }; 904 905 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = { 906 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03), 907 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 908 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 909 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 910 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f), 911 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e), 912 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 913 }; 914 915 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = { 916 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 917 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c), 918 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00), 919 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a), 920 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f), 921 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c), 922 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 923 }; 924 925 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = { 926 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00), 927 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 928 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 929 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 930 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f), 931 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a), 932 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 933 }; 934 935 static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = { 936 QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40), 937 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 938 QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b), 939 QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f), 940 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03), 941 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f), 942 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 943 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00), 944 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 945 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 946 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4), 947 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a), 948 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a), 949 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20), 950 }; 951 952 static const struct qmp_phy_init_tbl qmp_v5_dp_serdes_tbl[] = { 953 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), 954 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), 955 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), 956 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), 957 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), 958 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), 959 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 960 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 961 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 962 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 963 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 964 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 965 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 966 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), 967 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 968 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 969 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 970 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), 971 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), 972 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), 973 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), 974 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), 975 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), 976 }; 977 978 static const struct qmp_phy_init_tbl qmp_v5_dp_tx_tbl[] = { 979 QMP_PHY_INIT_CFG(QSERDES_V5_TX_VMODE_CTRL1, 0x40), 980 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 981 QMP_PHY_INIT_CFG(QSERDES_V5_TX_INTERFACE_SELECT, 0x3b), 982 QMP_PHY_INIT_CFG(QSERDES_V5_TX_CLKBUF_ENABLE, 0x0f), 983 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RESET_TSYNC_EN, 0x03), 984 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0f), 985 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 986 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_INTERFACE_MODE, 0x00), 987 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 988 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 989 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_BAND, 0x04), 990 }; 991 992 static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx_tbl[] = { 993 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x51), 994 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 0x1a), 995 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_VMODE_CTRL1, 0x40), 996 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PRE_STALL_LDO_BOOST_EN, 0x0), 997 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_INTERFACE_SELECT, 0xff), 998 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_CLKBUF_ENABLE, 0x0f), 999 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RESET_TSYNC_EN, 0x03), 1000 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRAN_DRVR_EMP_EN, 0xf), 1001 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1002 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1003 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 1004 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TX_BAND, 0x01), 1005 }; 1006 1007 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl[] = { 1008 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15), 1009 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b), 1010 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02), 1011 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c), 1012 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06), 1013 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30), 1014 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 1015 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1016 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1017 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 1018 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00), 1019 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12), 1020 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1021 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1022 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00), 1023 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1024 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14), 1025 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00), 1026 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17), 1027 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f), 1028 }; 1029 1030 static const struct qmp_phy_init_tbl qmp_v6_dp_tx_tbl[] = { 1031 QMP_PHY_INIT_CFG(QSERDES_V6_TX_VMODE_CTRL1, 0x40), 1032 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 1033 QMP_PHY_INIT_CFG(QSERDES_V6_TX_INTERFACE_SELECT, 0x3b), 1034 QMP_PHY_INIT_CFG(QSERDES_V6_TX_CLKBUF_ENABLE, 0x0f), 1035 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RESET_TSYNC_EN, 0x03), 1036 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TRAN_DRVR_EMP_EN, 0x0f), 1037 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1038 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_INTERFACE_MODE, 0x00), 1039 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x0c), 1040 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1041 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_BAND, 0x4), 1042 }; 1043 1044 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_rbr[] = { 1045 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05), 1046 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1047 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1048 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1049 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x37), 1050 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04), 1051 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04), 1052 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1053 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1054 }; 1055 1056 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr[] = { 1057 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03), 1058 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1059 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1060 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1061 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x07), 1062 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07), 1063 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1064 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1065 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1066 }; 1067 1068 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr2[] = { 1069 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 1070 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46), 1071 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x00), 1072 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05), 1073 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f), 1074 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e), 1075 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1076 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x97), 1077 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10), 1078 }; 1079 1080 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr3[] = { 1081 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00), 1082 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1083 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1084 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1085 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x17), 1086 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x15), 1087 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1088 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1089 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1090 }; 1091 1092 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = { 1093 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 1094 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1095 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1096 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xfd), 1097 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x0d), 1098 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xfd), 1099 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0d), 1100 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a), 1101 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x02), 1102 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x02), 1103 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1104 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1105 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1106 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1107 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a), 1108 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04), 1109 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14), 1110 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34), 1111 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34), 1112 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82), 1113 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x04), 1114 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE0, 0x01), 1115 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x04), 1116 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE1, 0x01), 1117 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1118 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xd5), 1119 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x05), 1120 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 1121 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xd5), 1122 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 1123 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1124 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0xd4), 1125 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE0, 0x00), 1126 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xd4), 1127 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x00), 1128 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x13), 1129 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1130 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 1131 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 1132 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 1133 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x76), 1134 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0xff), 1135 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0x20), 1136 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0x20), 1137 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00), 1138 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAXVAL2, 0x01), 1139 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SVS_MODE_CLK_SEL, 0x0a), 1140 }; 1141 1142 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_tx_tbl[] = { 1143 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_1, 0x05), 1144 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_2, 0xc2), 1145 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x10), 1146 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 1147 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x0a), 1148 }; 1149 1150 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_rx_tbl[] = { 1151 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_CNTRL, 0x04), 1152 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1153 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_ENABLES, 0x00), 1154 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B0, 0xd2), 1155 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B1, 0xd2), 1156 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B2, 0xdb), 1157 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B3, 0x21), 1158 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B4, 0x3f), 1159 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B5, 0x80), 1160 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B6, 0x45), 1161 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B7, 0x00), 1162 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B0, 0x6b), 1163 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B1, 0x63), 1164 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B2, 0xb6), 1165 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B3, 0x23), 1166 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B4, 0x35), 1167 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B5, 0x30), 1168 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B6, 0x8e), 1169 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B7, 0x00), 1170 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CODE_OVERRIDE, 0x00), 1171 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL2, 0x80), 1172 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_SUMMER_CAL_SPD_MODE, 0x1b), 1173 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1174 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_PI_CONTROLS, 0x15), 1175 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE2, 0x0a), 1176 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c), 1177 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_CNTRL1, 0x00), 1178 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_MAN_VAL, 0x0d), 1179 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_DAC_ENABLE1, 0x00), 1180 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_3, 0x45), 1181 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_GM_CAL, 0x09), 1182 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE2, 0x09), 1183 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE2, 0x05), 1184 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x3f), 1185 }; 1186 1187 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_pcs_tbl[] = { 1188 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1189 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1190 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1191 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07), 1192 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20), 1193 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13), 1194 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21), 1195 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa), 1196 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_CONFIG, 0x0a), 1197 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1198 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1199 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c), 1200 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b), 1201 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10), 1202 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1203 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1204 }; 1205 1206 /* list of regulators */ 1207 struct qmp_regulator_data { 1208 const char *name; 1209 unsigned int enable_load; 1210 }; 1211 1212 static struct qmp_regulator_data qmp_phy_vreg_l[] = { 1213 { .name = "vdda-phy", .enable_load = 21800 }, 1214 { .name = "vdda-pll", .enable_load = 36000 }, 1215 }; 1216 1217 static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = { 1218 { 0x00, 0x0c, 0x15, 0x1a }, 1219 { 0x02, 0x0e, 0x16, 0xff }, 1220 { 0x02, 0x11, 0xff, 0xff }, 1221 { 0x04, 0xff, 0xff, 0xff } 1222 }; 1223 1224 static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = { 1225 { 0x02, 0x12, 0x16, 0x1a }, 1226 { 0x09, 0x19, 0x1f, 0xff }, 1227 { 0x10, 0x1f, 0xff, 0xff }, 1228 { 0x1f, 0xff, 0xff, 0xff } 1229 }; 1230 1231 static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = { 1232 { 0x00, 0x0c, 0x14, 0x19 }, 1233 { 0x00, 0x0b, 0x12, 0xff }, 1234 { 0x00, 0x0b, 0xff, 0xff }, 1235 { 0x04, 0xff, 0xff, 0xff } 1236 }; 1237 1238 static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { 1239 { 0x08, 0x0f, 0x16, 0x1f }, 1240 { 0x11, 0x1e, 0x1f, 0xff }, 1241 { 0x19, 0x1f, 0xff, 0xff }, 1242 { 0x1f, 0xff, 0xff, 0xff } 1243 }; 1244 1245 static const u8 qmp_dp_v4_pre_emphasis_hbr3_hbr2[4][4] = { 1246 { 0x00, 0x0c, 0x15, 0x1b }, 1247 { 0x02, 0x0e, 0x16, 0xff }, 1248 { 0x02, 0x11, 0xff, 0xff }, 1249 { 0x04, 0xff, 0xff, 0xff } 1250 }; 1251 1252 static const u8 qmp_dp_v4_pre_emphasis_hbr_rbr[4][4] = { 1253 { 0x00, 0x0d, 0x14, 0x1a }, 1254 { 0x00, 0x0e, 0x15, 0xff }, 1255 { 0x00, 0x0d, 0xff, 0xff }, 1256 { 0x03, 0xff, 0xff, 0xff } 1257 }; 1258 1259 static const u8 qmp_dp_v4_voltage_swing_hbr_rbr[4][4] = { 1260 { 0x08, 0x0f, 0x16, 0x1f }, 1261 { 0x11, 0x1e, 0x1f, 0xff }, 1262 { 0x16, 0x1f, 0xff, 0xff }, 1263 { 0x1f, 0xff, 0xff, 0xff } 1264 }; 1265 1266 static const u8 qmp_dp_v5_pre_emphasis_hbr3_hbr2[4][4] = { 1267 { 0x20, 0x2c, 0x35, 0x3b }, 1268 { 0x22, 0x2e, 0x36, 0xff }, 1269 { 0x22, 0x31, 0xff, 0xff }, 1270 { 0x24, 0xff, 0xff, 0xff } 1271 }; 1272 1273 static const u8 qmp_dp_v5_voltage_swing_hbr3_hbr2[4][4] = { 1274 { 0x22, 0x32, 0x36, 0x3a }, 1275 { 0x29, 0x39, 0x3f, 0xff }, 1276 { 0x30, 0x3f, 0xff, 0xff }, 1277 { 0x3f, 0xff, 0xff, 0xff } 1278 }; 1279 1280 static const u8 qmp_dp_v5_pre_emphasis_hbr_rbr[4][4] = { 1281 { 0x20, 0x2d, 0x34, 0x3a }, 1282 { 0x20, 0x2e, 0x35, 0xff }, 1283 { 0x20, 0x2e, 0xff, 0xff }, 1284 { 0x24, 0xff, 0xff, 0xff } 1285 }; 1286 1287 static const u8 qmp_dp_v5_voltage_swing_hbr_rbr[4][4] = { 1288 { 0x28, 0x2f, 0x36, 0x3f }, 1289 { 0x31, 0x3e, 0x3f, 0xff }, 1290 { 0x36, 0x3f, 0xff, 0xff }, 1291 { 0x3f, 0xff, 0xff, 0xff } 1292 }; 1293 1294 static const u8 qmp_dp_v6_pre_emphasis_hbr_rbr[4][4] = { 1295 { 0x20, 0x2d, 0x34, 0x3a }, 1296 { 0x20, 0x2e, 0x35, 0xff }, 1297 { 0x20, 0x2e, 0xff, 0xff }, 1298 { 0x22, 0xff, 0xff, 0xff } 1299 }; 1300 1301 struct qmp_combo; 1302 1303 struct qmp_combo_offsets { 1304 u16 com; 1305 u16 txa; 1306 u16 rxa; 1307 u16 txb; 1308 u16 rxb; 1309 u16 usb3_serdes; 1310 u16 usb3_pcs_misc; 1311 u16 usb3_pcs; 1312 u16 usb3_pcs_usb; 1313 u16 dp_serdes; 1314 u16 dp_txa; 1315 u16 dp_txb; 1316 u16 dp_dp_phy; 1317 }; 1318 1319 struct qmp_phy_cfg { 1320 const struct qmp_combo_offsets *offsets; 1321 1322 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 1323 const struct qmp_phy_init_tbl *serdes_tbl; 1324 int serdes_tbl_num; 1325 const struct qmp_phy_init_tbl *tx_tbl; 1326 int tx_tbl_num; 1327 const struct qmp_phy_init_tbl *rx_tbl; 1328 int rx_tbl_num; 1329 const struct qmp_phy_init_tbl *pcs_tbl; 1330 int pcs_tbl_num; 1331 const struct qmp_phy_init_tbl *pcs_usb_tbl; 1332 int pcs_usb_tbl_num; 1333 1334 const struct qmp_phy_init_tbl *dp_serdes_tbl; 1335 int dp_serdes_tbl_num; 1336 const struct qmp_phy_init_tbl *dp_tx_tbl; 1337 int dp_tx_tbl_num; 1338 1339 /* Init sequence for DP PHY block link rates */ 1340 const struct qmp_phy_init_tbl *serdes_tbl_rbr; 1341 int serdes_tbl_rbr_num; 1342 const struct qmp_phy_init_tbl *serdes_tbl_hbr; 1343 int serdes_tbl_hbr_num; 1344 const struct qmp_phy_init_tbl *serdes_tbl_hbr2; 1345 int serdes_tbl_hbr2_num; 1346 const struct qmp_phy_init_tbl *serdes_tbl_hbr3; 1347 int serdes_tbl_hbr3_num; 1348 1349 /* DP PHY swing and pre_emphasis tables */ 1350 const u8 (*swing_hbr_rbr)[4][4]; 1351 const u8 (*swing_hbr3_hbr2)[4][4]; 1352 const u8 (*pre_emphasis_hbr_rbr)[4][4]; 1353 const u8 (*pre_emphasis_hbr3_hbr2)[4][4]; 1354 1355 /* DP PHY callbacks */ 1356 int (*configure_dp_phy)(struct qmp_combo *qmp); 1357 void (*configure_dp_tx)(struct qmp_combo *qmp); 1358 int (*calibrate_dp_phy)(struct qmp_combo *qmp); 1359 void (*dp_aux_init)(struct qmp_combo *qmp); 1360 1361 /* clock ids to be requested */ 1362 const char * const *clk_list; 1363 int num_clks; 1364 /* resets to be requested */ 1365 const char * const *reset_list; 1366 int num_resets; 1367 /* regulators to be requested */ 1368 const struct qmp_regulator_data *vreg_list; 1369 int num_vregs; 1370 1371 /* array of registers with different offsets */ 1372 const unsigned int *regs; 1373 1374 /* true, if PHY needs delay after POWER_DOWN */ 1375 bool has_pwrdn_delay; 1376 1377 /* Offset from PCS to PCS_USB region */ 1378 unsigned int pcs_usb_offset; 1379 1380 }; 1381 1382 struct qmp_combo { 1383 struct device *dev; 1384 1385 const struct qmp_phy_cfg *cfg; 1386 1387 void __iomem *com; 1388 1389 void __iomem *serdes; 1390 void __iomem *tx; 1391 void __iomem *rx; 1392 void __iomem *pcs; 1393 void __iomem *tx2; 1394 void __iomem *rx2; 1395 void __iomem *pcs_misc; 1396 void __iomem *pcs_usb; 1397 1398 void __iomem *dp_serdes; 1399 void __iomem *dp_tx; 1400 void __iomem *dp_tx2; 1401 void __iomem *dp_dp_phy; 1402 1403 struct clk *pipe_clk; 1404 struct clk_bulk_data *clks; 1405 struct reset_control_bulk_data *resets; 1406 struct regulator_bulk_data *vregs; 1407 1408 struct mutex phy_mutex; 1409 int init_count; 1410 1411 struct phy *usb_phy; 1412 enum phy_mode mode; 1413 unsigned int usb_init_count; 1414 1415 struct phy *dp_phy; 1416 unsigned int dp_aux_cfg; 1417 struct phy_configure_opts_dp dp_opts; 1418 unsigned int dp_init_count; 1419 1420 struct clk_fixed_rate pipe_clk_fixed; 1421 struct clk_hw dp_link_hw; 1422 struct clk_hw dp_pixel_hw; 1423 1424 struct drm_bridge bridge; 1425 1426 struct typec_switch_dev *sw; 1427 enum typec_orientation orientation; 1428 }; 1429 1430 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp); 1431 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp); 1432 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp); 1433 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp); 1434 1435 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp); 1436 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp); 1437 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp); 1438 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp); 1439 1440 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 1441 { 1442 u32 reg; 1443 1444 reg = readl(base + offset); 1445 reg |= val; 1446 writel(reg, base + offset); 1447 1448 /* ensure that above write is through */ 1449 readl(base + offset); 1450 } 1451 1452 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 1453 { 1454 u32 reg; 1455 1456 reg = readl(base + offset); 1457 reg &= ~val; 1458 writel(reg, base + offset); 1459 1460 /* ensure that above write is through */ 1461 readl(base + offset); 1462 } 1463 1464 /* list of clocks required by phy */ 1465 static const char * const qmp_v3_phy_clk_l[] = { 1466 "aux", "cfg_ahb", "ref", "com_aux", 1467 }; 1468 1469 static const char * const qmp_v4_phy_clk_l[] = { 1470 "aux", "ref", "com_aux", 1471 }; 1472 1473 /* the primary usb3 phy on sm8250 doesn't have a ref clock */ 1474 static const char * const qmp_v4_sm8250_usbphy_clk_l[] = { 1475 "aux", "ref_clk_src", "com_aux" 1476 }; 1477 1478 /* list of resets */ 1479 static const char * const msm8996_usb3phy_reset_l[] = { 1480 "phy", "common", 1481 }; 1482 1483 static const char * const sc7180_usb3phy_reset_l[] = { 1484 "phy", 1485 }; 1486 1487 static const struct qmp_combo_offsets qmp_combo_offsets_v3 = { 1488 .com = 0x0000, 1489 .txa = 0x1200, 1490 .rxa = 0x1400, 1491 .txb = 0x1600, 1492 .rxb = 0x1800, 1493 .usb3_serdes = 0x1000, 1494 .usb3_pcs_misc = 0x1a00, 1495 .usb3_pcs = 0x1c00, 1496 .usb3_pcs_usb = 0x1f00, 1497 .dp_serdes = 0x2000, 1498 .dp_txa = 0x2200, 1499 .dp_txb = 0x2600, 1500 .dp_dp_phy = 0x2a00, 1501 }; 1502 1503 static const struct qmp_combo_offsets qmp_combo_offsets_v5 = { 1504 .com = 0x0000, 1505 .txa = 0x0400, 1506 .rxa = 0x0600, 1507 .txb = 0x0a00, 1508 .rxb = 0x0c00, 1509 .usb3_serdes = 0x1000, 1510 .usb3_pcs_misc = 0x1200, 1511 .usb3_pcs = 0x1400, 1512 .usb3_pcs_usb = 0x1700, 1513 .dp_serdes = 0x2000, 1514 .dp_dp_phy = 0x2200, 1515 }; 1516 1517 static const struct qmp_phy_cfg sc7180_usb3dpphy_cfg = { 1518 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1519 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1520 .tx_tbl = qmp_v3_usb3_tx_tbl, 1521 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1522 .rx_tbl = qmp_v3_usb3_rx_tbl, 1523 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 1524 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 1525 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 1526 1527 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 1528 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 1529 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 1530 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 1531 1532 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 1533 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 1534 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 1535 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 1536 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 1537 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 1538 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 1539 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 1540 1541 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1542 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1543 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1544 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1545 1546 .dp_aux_init = qmp_v3_dp_aux_init, 1547 .configure_dp_tx = qmp_v3_configure_dp_tx, 1548 .configure_dp_phy = qmp_v3_configure_dp_phy, 1549 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 1550 1551 .clk_list = qmp_v3_phy_clk_l, 1552 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 1553 .reset_list = sc7180_usb3phy_reset_l, 1554 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), 1555 .vreg_list = qmp_phy_vreg_l, 1556 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1557 .regs = qmp_v3_usb3phy_regs_layout, 1558 1559 .has_pwrdn_delay = true, 1560 }; 1561 1562 static const struct qmp_phy_cfg sdm845_usb3dpphy_cfg = { 1563 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1564 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1565 .tx_tbl = qmp_v3_usb3_tx_tbl, 1566 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1567 .rx_tbl = qmp_v3_usb3_rx_tbl, 1568 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 1569 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 1570 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 1571 1572 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 1573 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 1574 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 1575 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 1576 1577 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 1578 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 1579 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 1580 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 1581 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 1582 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 1583 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 1584 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 1585 1586 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1587 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1588 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1589 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1590 1591 .dp_aux_init = qmp_v3_dp_aux_init, 1592 .configure_dp_tx = qmp_v3_configure_dp_tx, 1593 .configure_dp_phy = qmp_v3_configure_dp_phy, 1594 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 1595 1596 .clk_list = qmp_v3_phy_clk_l, 1597 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 1598 .reset_list = msm8996_usb3phy_reset_l, 1599 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1600 .vreg_list = qmp_phy_vreg_l, 1601 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1602 .regs = qmp_v3_usb3phy_regs_layout, 1603 1604 .has_pwrdn_delay = true, 1605 }; 1606 1607 static const struct qmp_phy_cfg sc8180x_usb3dpphy_cfg = { 1608 .serdes_tbl = sm8150_usb3_serdes_tbl, 1609 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1610 .tx_tbl = sm8150_usb3_tx_tbl, 1611 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl), 1612 .rx_tbl = sm8150_usb3_rx_tbl, 1613 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl), 1614 .pcs_tbl = sm8150_usb3_pcs_tbl, 1615 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl), 1616 .pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl, 1617 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl), 1618 1619 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 1620 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 1621 .dp_tx_tbl = qmp_v4_dp_tx_tbl, 1622 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 1623 1624 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1625 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1626 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1627 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1628 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1629 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1630 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1631 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1632 1633 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1634 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1635 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1636 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1637 1638 .dp_aux_init = qmp_v4_dp_aux_init, 1639 .configure_dp_tx = qmp_v4_configure_dp_tx, 1640 .configure_dp_phy = qmp_v4_configure_dp_phy, 1641 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1642 1643 .clk_list = qmp_v4_phy_clk_l, 1644 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1645 .reset_list = msm8996_usb3phy_reset_l, 1646 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1647 .vreg_list = qmp_phy_vreg_l, 1648 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1649 .regs = qmp_v45_usb3phy_regs_layout, 1650 .pcs_usb_offset = 0x300, 1651 1652 .has_pwrdn_delay = true, 1653 }; 1654 1655 static const struct qmp_phy_cfg sc8280xp_usb43dpphy_cfg = { 1656 .offsets = &qmp_combo_offsets_v5, 1657 1658 .serdes_tbl = sc8280xp_usb43dp_serdes_tbl, 1659 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_serdes_tbl), 1660 .tx_tbl = sc8280xp_usb43dp_tx_tbl, 1661 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_tx_tbl), 1662 .rx_tbl = sc8280xp_usb43dp_rx_tbl, 1663 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_rx_tbl), 1664 .pcs_tbl = sc8280xp_usb43dp_pcs_tbl, 1665 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_pcs_tbl), 1666 1667 .dp_serdes_tbl = qmp_v5_dp_serdes_tbl, 1668 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v5_dp_serdes_tbl), 1669 .dp_tx_tbl = qmp_v5_5nm_dp_tx_tbl, 1670 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_5nm_dp_tx_tbl), 1671 1672 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1673 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1674 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1675 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1676 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1677 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1678 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1679 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1680 1681 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 1682 .pre_emphasis_hbr_rbr = &qmp_dp_v5_pre_emphasis_hbr_rbr, 1683 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 1684 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 1685 1686 .dp_aux_init = qmp_v4_dp_aux_init, 1687 .configure_dp_tx = qmp_v4_configure_dp_tx, 1688 .configure_dp_phy = qmp_v4_configure_dp_phy, 1689 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1690 1691 .clk_list = qmp_v4_phy_clk_l, 1692 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1693 .reset_list = msm8996_usb3phy_reset_l, 1694 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1695 .vreg_list = qmp_phy_vreg_l, 1696 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1697 .regs = qmp_v5_5nm_usb3phy_regs_layout, 1698 }; 1699 1700 static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = { 1701 .offsets = &qmp_combo_offsets_v3, 1702 1703 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1704 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1705 .tx_tbl = qmp_v3_usb3_tx_tbl, 1706 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1707 .rx_tbl = sm6350_usb3_rx_tbl, 1708 .rx_tbl_num = ARRAY_SIZE(sm6350_usb3_rx_tbl), 1709 .pcs_tbl = sm6350_usb3_pcs_tbl, 1710 .pcs_tbl_num = ARRAY_SIZE(sm6350_usb3_pcs_tbl), 1711 1712 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 1713 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 1714 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 1715 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 1716 1717 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 1718 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 1719 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 1720 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 1721 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 1722 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 1723 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 1724 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 1725 1726 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1727 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1728 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1729 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1730 1731 .dp_aux_init = qmp_v3_dp_aux_init, 1732 .configure_dp_tx = qmp_v3_configure_dp_tx, 1733 .configure_dp_phy = qmp_v3_configure_dp_phy, 1734 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 1735 1736 .clk_list = qmp_v4_phy_clk_l, 1737 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1738 .reset_list = msm8996_usb3phy_reset_l, 1739 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1740 .vreg_list = qmp_phy_vreg_l, 1741 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1742 .regs = qmp_v3_usb3phy_regs_layout, 1743 }; 1744 1745 static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = { 1746 .serdes_tbl = sm8150_usb3_serdes_tbl, 1747 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1748 .tx_tbl = sm8250_usb3_tx_tbl, 1749 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl), 1750 .rx_tbl = sm8250_usb3_rx_tbl, 1751 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl), 1752 .pcs_tbl = sm8250_usb3_pcs_tbl, 1753 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl), 1754 .pcs_usb_tbl = sm8250_usb3_pcs_usb_tbl, 1755 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl), 1756 1757 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 1758 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 1759 .dp_tx_tbl = qmp_v4_dp_tx_tbl, 1760 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 1761 1762 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1763 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1764 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1765 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1766 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1767 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1768 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1769 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1770 1771 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1772 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1773 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1774 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1775 1776 .dp_aux_init = qmp_v4_dp_aux_init, 1777 .configure_dp_tx = qmp_v4_configure_dp_tx, 1778 .configure_dp_phy = qmp_v4_configure_dp_phy, 1779 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1780 1781 .clk_list = qmp_v4_sm8250_usbphy_clk_l, 1782 .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), 1783 .reset_list = msm8996_usb3phy_reset_l, 1784 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1785 .vreg_list = qmp_phy_vreg_l, 1786 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1787 .regs = qmp_v45_usb3phy_regs_layout, 1788 .pcs_usb_offset = 0x300, 1789 1790 .has_pwrdn_delay = true, 1791 }; 1792 1793 static const struct qmp_phy_cfg sm8350_usb3dpphy_cfg = { 1794 .offsets = &qmp_combo_offsets_v3, 1795 1796 .serdes_tbl = sm8150_usb3_serdes_tbl, 1797 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1798 .tx_tbl = sm8350_usb3_tx_tbl, 1799 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl), 1800 .rx_tbl = sm8350_usb3_rx_tbl, 1801 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl), 1802 .pcs_tbl = sm8350_usb3_pcs_tbl, 1803 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl), 1804 .pcs_usb_tbl = sm8350_usb3_pcs_usb_tbl, 1805 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_usb_tbl), 1806 1807 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 1808 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 1809 .dp_tx_tbl = qmp_v5_dp_tx_tbl, 1810 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_dp_tx_tbl), 1811 1812 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1813 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1814 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1815 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1816 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1817 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1818 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1819 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1820 1821 .swing_hbr_rbr = &qmp_dp_v4_voltage_swing_hbr_rbr, 1822 .pre_emphasis_hbr_rbr = &qmp_dp_v4_pre_emphasis_hbr_rbr, 1823 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1824 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v4_pre_emphasis_hbr3_hbr2, 1825 1826 .dp_aux_init = qmp_v4_dp_aux_init, 1827 .configure_dp_tx = qmp_v4_configure_dp_tx, 1828 .configure_dp_phy = qmp_v4_configure_dp_phy, 1829 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1830 1831 .clk_list = qmp_v4_phy_clk_l, 1832 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1833 .reset_list = msm8996_usb3phy_reset_l, 1834 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1835 .vreg_list = qmp_phy_vreg_l, 1836 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1837 .regs = qmp_v45_usb3phy_regs_layout, 1838 1839 .has_pwrdn_delay = true, 1840 }; 1841 1842 static const struct qmp_phy_cfg sm8550_usb3dpphy_cfg = { 1843 .offsets = &qmp_combo_offsets_v3, 1844 1845 .serdes_tbl = sm8550_usb3_serdes_tbl, 1846 .serdes_tbl_num = ARRAY_SIZE(sm8550_usb3_serdes_tbl), 1847 .tx_tbl = sm8550_usb3_tx_tbl, 1848 .tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl), 1849 .rx_tbl = sm8550_usb3_rx_tbl, 1850 .rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl), 1851 .pcs_tbl = sm8550_usb3_pcs_tbl, 1852 .pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl), 1853 .pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl, 1854 .pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl), 1855 1856 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl, 1857 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl), 1858 .dp_tx_tbl = qmp_v6_dp_tx_tbl, 1859 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), 1860 1861 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr, 1862 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), 1863 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr, 1864 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), 1865 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2, 1866 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), 1867 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3, 1868 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), 1869 1870 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 1871 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 1872 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 1873 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 1874 1875 .dp_aux_init = qmp_v4_dp_aux_init, 1876 .configure_dp_tx = qmp_v4_configure_dp_tx, 1877 .configure_dp_phy = qmp_v4_configure_dp_phy, 1878 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1879 1880 .regs = qmp_v6_usb3phy_regs_layout, 1881 .clk_list = qmp_v4_phy_clk_l, 1882 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1883 .reset_list = msm8996_usb3phy_reset_l, 1884 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1885 .vreg_list = qmp_phy_vreg_l, 1886 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1887 }; 1888 1889 static void qmp_combo_configure_lane(void __iomem *base, 1890 const struct qmp_phy_init_tbl tbl[], 1891 int num, 1892 u8 lane_mask) 1893 { 1894 int i; 1895 const struct qmp_phy_init_tbl *t = tbl; 1896 1897 if (!t) 1898 return; 1899 1900 for (i = 0; i < num; i++, t++) { 1901 if (!(t->lane_mask & lane_mask)) 1902 continue; 1903 1904 writel(t->val, base + t->offset); 1905 } 1906 } 1907 1908 static void qmp_combo_configure(void __iomem *base, 1909 const struct qmp_phy_init_tbl tbl[], 1910 int num) 1911 { 1912 qmp_combo_configure_lane(base, tbl, num, 0xff); 1913 } 1914 1915 static int qmp_combo_dp_serdes_init(struct qmp_combo *qmp) 1916 { 1917 const struct qmp_phy_cfg *cfg = qmp->cfg; 1918 void __iomem *serdes = qmp->dp_serdes; 1919 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 1920 1921 qmp_combo_configure(serdes, cfg->dp_serdes_tbl, cfg->dp_serdes_tbl_num); 1922 1923 switch (dp_opts->link_rate) { 1924 case 1620: 1925 qmp_combo_configure(serdes, cfg->serdes_tbl_rbr, 1926 cfg->serdes_tbl_rbr_num); 1927 break; 1928 case 2700: 1929 qmp_combo_configure(serdes, cfg->serdes_tbl_hbr, 1930 cfg->serdes_tbl_hbr_num); 1931 break; 1932 case 5400: 1933 qmp_combo_configure(serdes, cfg->serdes_tbl_hbr2, 1934 cfg->serdes_tbl_hbr2_num); 1935 break; 1936 case 8100: 1937 qmp_combo_configure(serdes, cfg->serdes_tbl_hbr3, 1938 cfg->serdes_tbl_hbr3_num); 1939 break; 1940 default: 1941 /* Other link rates aren't supported */ 1942 return -EINVAL; 1943 } 1944 1945 return 0; 1946 } 1947 1948 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp) 1949 { 1950 const struct qmp_phy_cfg *cfg = qmp->cfg; 1951 1952 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 1953 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 1954 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 1955 1956 /* Turn on BIAS current for PHY/PLL */ 1957 writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | 1958 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL, 1959 qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 1960 1961 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 1962 1963 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 1964 DP_PHY_PD_CTL_LANE_0_1_PWRDN | 1965 DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | 1966 DP_PHY_PD_CTL_DP_CLAMP_EN, 1967 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 1968 1969 writel(QSERDES_V3_COM_BIAS_EN | 1970 QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN | 1971 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL | 1972 QSERDES_V3_COM_CLKBUF_RX_DRIVE_L, 1973 qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 1974 1975 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 1976 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 1977 writel(0x24, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 1978 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 1979 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 1980 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 1981 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 1982 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 1983 writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 1984 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 1985 qmp->dp_aux_cfg = 0; 1986 1987 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 1988 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 1989 PHY_AUX_REQ_ERR_MASK, 1990 qmp->dp_dp_phy + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); 1991 } 1992 1993 static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp) 1994 { 1995 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 1996 const struct qmp_phy_cfg *cfg = qmp->cfg; 1997 unsigned int v_level = 0, p_level = 0; 1998 u8 voltage_swing_cfg, pre_emphasis_cfg; 1999 int i; 2000 2001 for (i = 0; i < dp_opts->lanes; i++) { 2002 v_level = max(v_level, dp_opts->voltage[i]); 2003 p_level = max(p_level, dp_opts->pre[i]); 2004 } 2005 2006 if (dp_opts->link_rate <= 2700) { 2007 voltage_swing_cfg = (*cfg->swing_hbr_rbr)[v_level][p_level]; 2008 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr_rbr)[v_level][p_level]; 2009 } else { 2010 voltage_swing_cfg = (*cfg->swing_hbr3_hbr2)[v_level][p_level]; 2011 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr3_hbr2)[v_level][p_level]; 2012 } 2013 2014 /* TODO: Move check to config check */ 2015 if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF) 2016 return -EINVAL; 2017 2018 /* Enable MUX to use Cursor values from these registers */ 2019 voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; 2020 pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; 2021 2022 writel(voltage_swing_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2023 writel(pre_emphasis_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2024 writel(voltage_swing_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2025 writel(pre_emphasis_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2026 2027 return 0; 2028 } 2029 2030 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp) 2031 { 2032 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2033 u32 bias_en, drvr_en; 2034 2035 if (qmp_combo_configure_dp_swing(qmp) < 0) 2036 return; 2037 2038 if (dp_opts->lanes == 1) { 2039 bias_en = 0x3e; 2040 drvr_en = 0x13; 2041 } else { 2042 bias_en = 0x3f; 2043 drvr_en = 0x10; 2044 } 2045 2046 writel(drvr_en, qmp->dp_tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); 2047 writel(bias_en, qmp->dp_tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 2048 writel(drvr_en, qmp->dp_tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); 2049 writel(bias_en, qmp->dp_tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 2050 } 2051 2052 static bool qmp_combo_configure_dp_mode(struct qmp_combo *qmp) 2053 { 2054 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); 2055 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2056 u32 val; 2057 2058 val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 2059 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN; 2060 2061 if (dp_opts->lanes == 4 || reverse) 2062 val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN; 2063 if (dp_opts->lanes == 4 || !reverse) 2064 val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; 2065 2066 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2067 2068 if (reverse) 2069 writel(0x4c, qmp->pcs + QSERDES_DP_PHY_MODE); 2070 else 2071 writel(0x5c, qmp->pcs + QSERDES_DP_PHY_MODE); 2072 2073 return reverse; 2074 } 2075 2076 static int qmp_combo_configure_dp_clocks(struct qmp_combo *qmp) 2077 { 2078 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2079 u32 phy_vco_div; 2080 unsigned long pixel_freq; 2081 2082 switch (dp_opts->link_rate) { 2083 case 1620: 2084 phy_vco_div = 0x1; 2085 pixel_freq = 1620000000UL / 2; 2086 break; 2087 case 2700: 2088 phy_vco_div = 0x1; 2089 pixel_freq = 2700000000UL / 2; 2090 break; 2091 case 5400: 2092 phy_vco_div = 0x2; 2093 pixel_freq = 5400000000UL / 4; 2094 break; 2095 case 8100: 2096 phy_vco_div = 0x0; 2097 pixel_freq = 8100000000UL / 6; 2098 break; 2099 default: 2100 /* Other link rates aren't supported */ 2101 return -EINVAL; 2102 } 2103 writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_VCO_DIV); 2104 2105 clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000); 2106 clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq); 2107 2108 return 0; 2109 } 2110 2111 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp) 2112 { 2113 const struct qmp_phy_cfg *cfg = qmp->cfg; 2114 u32 status; 2115 int ret; 2116 2117 qmp_combo_configure_dp_mode(qmp); 2118 2119 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); 2120 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); 2121 2122 ret = qmp_combo_configure_dp_clocks(qmp); 2123 if (ret) 2124 return ret; 2125 2126 writel(0x04, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2127 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2128 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2129 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2130 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2131 2132 writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); 2133 2134 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS], 2135 status, 2136 ((status & BIT(0)) > 0), 2137 500, 2138 10000)) 2139 return -ETIMEDOUT; 2140 2141 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2142 2143 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2144 status, 2145 ((status & BIT(1)) > 0), 2146 500, 2147 10000)) 2148 return -ETIMEDOUT; 2149 2150 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2151 udelay(2000); 2152 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2153 2154 return readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2155 status, 2156 ((status & BIT(1)) > 0), 2157 500, 2158 10000); 2159 } 2160 2161 /* 2162 * We need to calibrate the aux setting here as many times 2163 * as the caller tries 2164 */ 2165 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp) 2166 { 2167 static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d }; 2168 u8 val; 2169 2170 qmp->dp_aux_cfg++; 2171 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 2172 val = cfg1_settings[qmp->dp_aux_cfg]; 2173 2174 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2175 2176 return 0; 2177 } 2178 2179 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp) 2180 { 2181 const struct qmp_phy_cfg *cfg = qmp->cfg; 2182 2183 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 2184 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 2185 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2186 2187 /* Turn on BIAS current for PHY/PLL */ 2188 writel(0x17, qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 2189 2190 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 2191 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2192 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2193 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 2194 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 2195 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 2196 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 2197 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 2198 writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 2199 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 2200 qmp->dp_aux_cfg = 0; 2201 2202 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 2203 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 2204 PHY_AUX_REQ_ERR_MASK, 2205 qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); 2206 } 2207 2208 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp) 2209 { 2210 const struct qmp_phy_cfg *cfg = qmp->cfg; 2211 2212 /* Program default values before writing proper values */ 2213 writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2214 writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2215 2216 writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2217 writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2218 2219 qmp_combo_configure_dp_swing(qmp); 2220 } 2221 2222 static int qmp_v456_configure_dp_phy(struct qmp_combo *qmp) 2223 { 2224 const struct qmp_phy_cfg *cfg = qmp->cfg; 2225 u32 status; 2226 int ret; 2227 2228 writel(0x0f, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_CFG_1); 2229 2230 qmp_combo_configure_dp_mode(qmp); 2231 2232 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2233 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2234 2235 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); 2236 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); 2237 2238 ret = qmp_combo_configure_dp_clocks(qmp); 2239 if (ret) 2240 return ret; 2241 2242 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2243 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2244 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2245 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2246 2247 writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); 2248 2249 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS], 2250 status, 2251 ((status & BIT(0)) > 0), 2252 500, 2253 10000)) 2254 return -ETIMEDOUT; 2255 2256 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], 2257 status, 2258 ((status & BIT(0)) > 0), 2259 500, 2260 10000)) 2261 return -ETIMEDOUT; 2262 2263 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], 2264 status, 2265 ((status & BIT(1)) > 0), 2266 500, 2267 10000)) 2268 return -ETIMEDOUT; 2269 2270 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2271 2272 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2273 status, 2274 ((status & BIT(0)) > 0), 2275 500, 2276 10000)) 2277 return -ETIMEDOUT; 2278 2279 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2280 status, 2281 ((status & BIT(1)) > 0), 2282 500, 2283 10000)) 2284 return -ETIMEDOUT; 2285 2286 return 0; 2287 } 2288 2289 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp) 2290 { 2291 const struct qmp_phy_cfg *cfg = qmp->cfg; 2292 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); 2293 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2294 u32 bias0_en, drvr0_en, bias1_en, drvr1_en; 2295 u32 status; 2296 int ret; 2297 2298 ret = qmp_v456_configure_dp_phy(qmp); 2299 if (ret < 0) 2300 return ret; 2301 2302 /* 2303 * At least for 7nm DP PHY this has to be done after enabling link 2304 * clock. 2305 */ 2306 2307 if (dp_opts->lanes == 1) { 2308 bias0_en = reverse ? 0x3e : 0x15; 2309 bias1_en = reverse ? 0x15 : 0x3e; 2310 drvr0_en = reverse ? 0x13 : 0x10; 2311 drvr1_en = reverse ? 0x10 : 0x13; 2312 } else if (dp_opts->lanes == 2) { 2313 bias0_en = reverse ? 0x3f : 0x15; 2314 bias1_en = reverse ? 0x15 : 0x3f; 2315 drvr0_en = 0x10; 2316 drvr1_en = 0x10; 2317 } else { 2318 bias0_en = 0x3f; 2319 bias1_en = 0x3f; 2320 drvr0_en = 0x10; 2321 drvr1_en = 0x10; 2322 } 2323 2324 writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 2325 writel(bias0_en, qmp->dp_tx + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 2326 writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 2327 writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 2328 2329 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2330 udelay(2000); 2331 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2332 2333 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2334 status, 2335 ((status & BIT(1)) > 0), 2336 500, 2337 10000)) 2338 return -ETIMEDOUT; 2339 2340 writel(0x0a, qmp->dp_tx + cfg->regs[QPHY_TX_TX_POL_INV]); 2341 writel(0x0a, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_POL_INV]); 2342 2343 writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2344 writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2345 2346 writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2347 writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2348 2349 return 0; 2350 2351 return 0; 2352 } 2353 2354 /* 2355 * We need to calibrate the aux setting here as many times 2356 * as the caller tries 2357 */ 2358 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp) 2359 { 2360 static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d }; 2361 u8 val; 2362 2363 qmp->dp_aux_cfg++; 2364 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 2365 val = cfg1_settings[qmp->dp_aux_cfg]; 2366 2367 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2368 2369 return 0; 2370 } 2371 2372 static int qmp_combo_dp_configure(struct phy *phy, union phy_configure_opts *opts) 2373 { 2374 const struct phy_configure_opts_dp *dp_opts = &opts->dp; 2375 struct qmp_combo *qmp = phy_get_drvdata(phy); 2376 const struct qmp_phy_cfg *cfg = qmp->cfg; 2377 2378 mutex_lock(&qmp->phy_mutex); 2379 2380 memcpy(&qmp->dp_opts, dp_opts, sizeof(*dp_opts)); 2381 if (qmp->dp_opts.set_voltages) { 2382 cfg->configure_dp_tx(qmp); 2383 qmp->dp_opts.set_voltages = 0; 2384 } 2385 2386 mutex_unlock(&qmp->phy_mutex); 2387 2388 return 0; 2389 } 2390 2391 static int qmp_combo_dp_calibrate(struct phy *phy) 2392 { 2393 struct qmp_combo *qmp = phy_get_drvdata(phy); 2394 const struct qmp_phy_cfg *cfg = qmp->cfg; 2395 int ret = 0; 2396 2397 mutex_lock(&qmp->phy_mutex); 2398 2399 if (cfg->calibrate_dp_phy) 2400 ret = cfg->calibrate_dp_phy(qmp); 2401 2402 mutex_unlock(&qmp->phy_mutex); 2403 2404 return ret; 2405 } 2406 2407 static int qmp_combo_com_init(struct qmp_combo *qmp, bool force) 2408 { 2409 const struct qmp_phy_cfg *cfg = qmp->cfg; 2410 void __iomem *com = qmp->com; 2411 int ret; 2412 u32 val; 2413 2414 if (!force && qmp->init_count++) 2415 return 0; 2416 2417 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 2418 if (ret) { 2419 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 2420 goto err_decrement_count; 2421 } 2422 2423 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2424 if (ret) { 2425 dev_err(qmp->dev, "reset assert failed\n"); 2426 goto err_disable_regulators; 2427 } 2428 2429 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 2430 if (ret) { 2431 dev_err(qmp->dev, "reset deassert failed\n"); 2432 goto err_disable_regulators; 2433 } 2434 2435 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 2436 if (ret) 2437 goto err_assert_reset; 2438 2439 qphy_setbits(com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, SW_PWRDN); 2440 2441 /* override hardware control for reset of qmp phy */ 2442 qphy_setbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 2443 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 2444 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 2445 2446 /* Use software based port select and switch on typec orientation */ 2447 val = SW_PORTSELECT_MUX; 2448 if (qmp->orientation == TYPEC_ORIENTATION_REVERSE) 2449 val |= SW_PORTSELECT_VAL; 2450 writel(val, com + QPHY_V3_DP_COM_TYPEC_CTRL); 2451 writel(USB3_MODE | DP_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL); 2452 2453 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ 2454 qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 2455 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 2456 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 2457 2458 qphy_clrbits(com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); 2459 qphy_clrbits(com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); 2460 2461 qphy_setbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2462 SW_PWRDN); 2463 2464 return 0; 2465 2466 err_assert_reset: 2467 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2468 err_disable_regulators: 2469 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2470 err_decrement_count: 2471 qmp->init_count--; 2472 2473 return ret; 2474 } 2475 2476 static int qmp_combo_com_exit(struct qmp_combo *qmp, bool force) 2477 { 2478 const struct qmp_phy_cfg *cfg = qmp->cfg; 2479 2480 if (!force && --qmp->init_count) 2481 return 0; 2482 2483 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2484 2485 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2486 2487 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2488 2489 return 0; 2490 } 2491 2492 static int qmp_combo_dp_init(struct phy *phy) 2493 { 2494 struct qmp_combo *qmp = phy_get_drvdata(phy); 2495 const struct qmp_phy_cfg *cfg = qmp->cfg; 2496 int ret; 2497 2498 mutex_lock(&qmp->phy_mutex); 2499 2500 ret = qmp_combo_com_init(qmp, false); 2501 if (ret) 2502 goto out_unlock; 2503 2504 cfg->dp_aux_init(qmp); 2505 2506 qmp->dp_init_count++; 2507 2508 out_unlock: 2509 mutex_unlock(&qmp->phy_mutex); 2510 return ret; 2511 } 2512 2513 static int qmp_combo_dp_exit(struct phy *phy) 2514 { 2515 struct qmp_combo *qmp = phy_get_drvdata(phy); 2516 2517 mutex_lock(&qmp->phy_mutex); 2518 2519 qmp_combo_com_exit(qmp, false); 2520 2521 qmp->dp_init_count--; 2522 2523 mutex_unlock(&qmp->phy_mutex); 2524 2525 return 0; 2526 } 2527 2528 static int qmp_combo_dp_power_on(struct phy *phy) 2529 { 2530 struct qmp_combo *qmp = phy_get_drvdata(phy); 2531 const struct qmp_phy_cfg *cfg = qmp->cfg; 2532 void __iomem *tx = qmp->dp_tx; 2533 void __iomem *tx2 = qmp->dp_tx2; 2534 2535 mutex_lock(&qmp->phy_mutex); 2536 2537 qmp_combo_dp_serdes_init(qmp); 2538 2539 qmp_combo_configure_lane(tx, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 1); 2540 qmp_combo_configure_lane(tx2, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 2); 2541 2542 /* Configure special DP tx tunings */ 2543 cfg->configure_dp_tx(qmp); 2544 2545 /* Configure link rate, swing, etc. */ 2546 cfg->configure_dp_phy(qmp); 2547 2548 mutex_unlock(&qmp->phy_mutex); 2549 2550 return 0; 2551 } 2552 2553 static int qmp_combo_dp_power_off(struct phy *phy) 2554 { 2555 struct qmp_combo *qmp = phy_get_drvdata(phy); 2556 2557 mutex_lock(&qmp->phy_mutex); 2558 2559 /* Assert DP PHY power down */ 2560 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2561 2562 mutex_unlock(&qmp->phy_mutex); 2563 2564 return 0; 2565 } 2566 2567 static int qmp_combo_usb_power_on(struct phy *phy) 2568 { 2569 struct qmp_combo *qmp = phy_get_drvdata(phy); 2570 const struct qmp_phy_cfg *cfg = qmp->cfg; 2571 void __iomem *serdes = qmp->serdes; 2572 void __iomem *tx = qmp->tx; 2573 void __iomem *rx = qmp->rx; 2574 void __iomem *tx2 = qmp->tx2; 2575 void __iomem *rx2 = qmp->rx2; 2576 void __iomem *pcs = qmp->pcs; 2577 void __iomem *status; 2578 unsigned int val; 2579 int ret; 2580 2581 qmp_combo_configure(serdes, cfg->serdes_tbl, cfg->serdes_tbl_num); 2582 2583 ret = clk_prepare_enable(qmp->pipe_clk); 2584 if (ret) { 2585 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 2586 return ret; 2587 } 2588 2589 /* Tx, Rx, and PCS configurations */ 2590 qmp_combo_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); 2591 qmp_combo_configure_lane(tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); 2592 2593 qmp_combo_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); 2594 qmp_combo_configure_lane(rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); 2595 2596 qmp_combo_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); 2597 2598 if (cfg->has_pwrdn_delay) 2599 usleep_range(10, 20); 2600 2601 /* Pull PHY out of reset state */ 2602 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2603 2604 /* start SerDes and Phy-Coding-Sublayer */ 2605 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 2606 2607 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 2608 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200, 2609 PHY_INIT_COMPLETE_TIMEOUT); 2610 if (ret) { 2611 dev_err(qmp->dev, "phy initialization timed-out\n"); 2612 goto err_disable_pipe_clk; 2613 } 2614 2615 return 0; 2616 2617 err_disable_pipe_clk: 2618 clk_disable_unprepare(qmp->pipe_clk); 2619 2620 return ret; 2621 } 2622 2623 static int qmp_combo_usb_power_off(struct phy *phy) 2624 { 2625 struct qmp_combo *qmp = phy_get_drvdata(phy); 2626 const struct qmp_phy_cfg *cfg = qmp->cfg; 2627 2628 clk_disable_unprepare(qmp->pipe_clk); 2629 2630 /* PHY reset */ 2631 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2632 2633 /* stop SerDes and Phy-Coding-Sublayer */ 2634 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 2635 SERDES_START | PCS_START); 2636 2637 /* Put PHY into POWER DOWN state: active low */ 2638 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2639 SW_PWRDN); 2640 2641 return 0; 2642 } 2643 2644 static int qmp_combo_usb_init(struct phy *phy) 2645 { 2646 struct qmp_combo *qmp = phy_get_drvdata(phy); 2647 int ret; 2648 2649 mutex_lock(&qmp->phy_mutex); 2650 ret = qmp_combo_com_init(qmp, false); 2651 if (ret) 2652 goto out_unlock; 2653 2654 ret = qmp_combo_usb_power_on(phy); 2655 if (ret) { 2656 qmp_combo_com_exit(qmp, false); 2657 goto out_unlock; 2658 } 2659 2660 qmp->usb_init_count++; 2661 2662 out_unlock: 2663 mutex_unlock(&qmp->phy_mutex); 2664 return ret; 2665 } 2666 2667 static int qmp_combo_usb_exit(struct phy *phy) 2668 { 2669 struct qmp_combo *qmp = phy_get_drvdata(phy); 2670 int ret; 2671 2672 mutex_lock(&qmp->phy_mutex); 2673 ret = qmp_combo_usb_power_off(phy); 2674 if (ret) 2675 goto out_unlock; 2676 2677 ret = qmp_combo_com_exit(qmp, false); 2678 if (ret) 2679 goto out_unlock; 2680 2681 qmp->usb_init_count--; 2682 2683 out_unlock: 2684 mutex_unlock(&qmp->phy_mutex); 2685 return ret; 2686 } 2687 2688 static int qmp_combo_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode) 2689 { 2690 struct qmp_combo *qmp = phy_get_drvdata(phy); 2691 2692 qmp->mode = mode; 2693 2694 return 0; 2695 } 2696 2697 static const struct phy_ops qmp_combo_usb_phy_ops = { 2698 .init = qmp_combo_usb_init, 2699 .exit = qmp_combo_usb_exit, 2700 .set_mode = qmp_combo_usb_set_mode, 2701 .owner = THIS_MODULE, 2702 }; 2703 2704 static const struct phy_ops qmp_combo_dp_phy_ops = { 2705 .init = qmp_combo_dp_init, 2706 .configure = qmp_combo_dp_configure, 2707 .power_on = qmp_combo_dp_power_on, 2708 .calibrate = qmp_combo_dp_calibrate, 2709 .power_off = qmp_combo_dp_power_off, 2710 .exit = qmp_combo_dp_exit, 2711 .owner = THIS_MODULE, 2712 }; 2713 2714 static void qmp_combo_enable_autonomous_mode(struct qmp_combo *qmp) 2715 { 2716 const struct qmp_phy_cfg *cfg = qmp->cfg; 2717 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 2718 void __iomem *pcs_misc = qmp->pcs_misc; 2719 u32 intr_mask; 2720 2721 if (qmp->mode == PHY_MODE_USB_HOST_SS || 2722 qmp->mode == PHY_MODE_USB_DEVICE_SS) 2723 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; 2724 else 2725 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; 2726 2727 /* Clear any pending interrupts status */ 2728 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2729 /* Writing 1 followed by 0 clears the interrupt */ 2730 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2731 2732 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 2733 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); 2734 2735 /* Enable required PHY autonomous mode interrupts */ 2736 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); 2737 2738 /* Enable i/o clamp_n for autonomous mode */ 2739 if (pcs_misc) 2740 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 2741 } 2742 2743 static void qmp_combo_disable_autonomous_mode(struct qmp_combo *qmp) 2744 { 2745 const struct qmp_phy_cfg *cfg = qmp->cfg; 2746 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 2747 void __iomem *pcs_misc = qmp->pcs_misc; 2748 2749 /* Disable i/o clamp_n on resume for normal mode */ 2750 if (pcs_misc) 2751 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 2752 2753 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 2754 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); 2755 2756 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2757 /* Writing 1 followed by 0 clears the interrupt */ 2758 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2759 } 2760 2761 static int __maybe_unused qmp_combo_runtime_suspend(struct device *dev) 2762 { 2763 struct qmp_combo *qmp = dev_get_drvdata(dev); 2764 const struct qmp_phy_cfg *cfg = qmp->cfg; 2765 2766 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode); 2767 2768 if (!qmp->init_count) { 2769 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2770 return 0; 2771 } 2772 2773 qmp_combo_enable_autonomous_mode(qmp); 2774 2775 clk_disable_unprepare(qmp->pipe_clk); 2776 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2777 2778 return 0; 2779 } 2780 2781 static int __maybe_unused qmp_combo_runtime_resume(struct device *dev) 2782 { 2783 struct qmp_combo *qmp = dev_get_drvdata(dev); 2784 const struct qmp_phy_cfg *cfg = qmp->cfg; 2785 int ret = 0; 2786 2787 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode); 2788 2789 if (!qmp->init_count) { 2790 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2791 return 0; 2792 } 2793 2794 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 2795 if (ret) 2796 return ret; 2797 2798 ret = clk_prepare_enable(qmp->pipe_clk); 2799 if (ret) { 2800 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); 2801 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2802 return ret; 2803 } 2804 2805 qmp_combo_disable_autonomous_mode(qmp); 2806 2807 return 0; 2808 } 2809 2810 static const struct dev_pm_ops qmp_combo_pm_ops = { 2811 SET_RUNTIME_PM_OPS(qmp_combo_runtime_suspend, 2812 qmp_combo_runtime_resume, NULL) 2813 }; 2814 2815 static int qmp_combo_vreg_init(struct qmp_combo *qmp) 2816 { 2817 const struct qmp_phy_cfg *cfg = qmp->cfg; 2818 struct device *dev = qmp->dev; 2819 int num = cfg->num_vregs; 2820 int ret, i; 2821 2822 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 2823 if (!qmp->vregs) 2824 return -ENOMEM; 2825 2826 for (i = 0; i < num; i++) 2827 qmp->vregs[i].supply = cfg->vreg_list[i].name; 2828 2829 ret = devm_regulator_bulk_get(dev, num, qmp->vregs); 2830 if (ret) { 2831 dev_err(dev, "failed at devm_regulator_bulk_get\n"); 2832 return ret; 2833 } 2834 2835 for (i = 0; i < num; i++) { 2836 ret = regulator_set_load(qmp->vregs[i].consumer, 2837 cfg->vreg_list[i].enable_load); 2838 if (ret) { 2839 dev_err(dev, "failed to set load at %s\n", 2840 qmp->vregs[i].supply); 2841 return ret; 2842 } 2843 } 2844 2845 return 0; 2846 } 2847 2848 static int qmp_combo_reset_init(struct qmp_combo *qmp) 2849 { 2850 const struct qmp_phy_cfg *cfg = qmp->cfg; 2851 struct device *dev = qmp->dev; 2852 int i; 2853 int ret; 2854 2855 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 2856 sizeof(*qmp->resets), GFP_KERNEL); 2857 if (!qmp->resets) 2858 return -ENOMEM; 2859 2860 for (i = 0; i < cfg->num_resets; i++) 2861 qmp->resets[i].id = cfg->reset_list[i]; 2862 2863 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 2864 if (ret) 2865 return dev_err_probe(dev, ret, "failed to get resets\n"); 2866 2867 return 0; 2868 } 2869 2870 static int qmp_combo_clk_init(struct qmp_combo *qmp) 2871 { 2872 const struct qmp_phy_cfg *cfg = qmp->cfg; 2873 struct device *dev = qmp->dev; 2874 int num = cfg->num_clks; 2875 int i; 2876 2877 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 2878 if (!qmp->clks) 2879 return -ENOMEM; 2880 2881 for (i = 0; i < num; i++) 2882 qmp->clks[i].id = cfg->clk_list[i]; 2883 2884 return devm_clk_bulk_get(dev, num, qmp->clks); 2885 } 2886 2887 static void phy_clk_release_provider(void *res) 2888 { 2889 of_clk_del_provider(res); 2890 } 2891 2892 /* 2893 * Register a fixed rate pipe clock. 2894 * 2895 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 2896 * controls it. The <s>_pipe_clk coming out of the GCC is requested 2897 * by the PHY driver for its operations. 2898 * We register the <s>_pipe_clksrc here. The gcc driver takes care 2899 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 2900 * Below picture shows this relationship. 2901 * 2902 * +---------------+ 2903 * | PHY block |<<---------------------------------------+ 2904 * | | | 2905 * | +-------+ | +-----+ | 2906 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 2907 * clk | +-------+ | +-----+ 2908 * +---------------+ 2909 */ 2910 static int phy_pipe_clk_register(struct qmp_combo *qmp, struct device_node *np) 2911 { 2912 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 2913 struct clk_init_data init = { }; 2914 char name[64]; 2915 2916 snprintf(name, sizeof(name), "%s::pipe_clk", dev_name(qmp->dev)); 2917 init.name = name; 2918 init.ops = &clk_fixed_rate_ops; 2919 2920 /* controllers using QMP phys use 125MHz pipe clock interface */ 2921 fixed->fixed_rate = 125000000; 2922 fixed->hw.init = &init; 2923 2924 return devm_clk_hw_register(qmp->dev, &fixed->hw); 2925 } 2926 2927 /* 2928 * Display Port PLL driver block diagram for branch clocks 2929 * 2930 * +------------------------------+ 2931 * | DP_VCO_CLK | 2932 * | | 2933 * | +-------------------+ | 2934 * | | (DP PLL/VCO) | | 2935 * | +---------+---------+ | 2936 * | v | 2937 * | +----------+-----------+ | 2938 * | | hsclk_divsel_clk_src | | 2939 * | +----------+-----------+ | 2940 * +------------------------------+ 2941 * | 2942 * +---------<---------v------------>----------+ 2943 * | | 2944 * +--------v----------------+ | 2945 * | dp_phy_pll_link_clk | | 2946 * | link_clk | | 2947 * +--------+----------------+ | 2948 * | | 2949 * | | 2950 * v v 2951 * Input to DISPCC block | 2952 * for link clk, crypto clk | 2953 * and interface clock | 2954 * | 2955 * | 2956 * +--------<------------+-----------------+---<---+ 2957 * | | | 2958 * +----v---------+ +--------v-----+ +--------v------+ 2959 * | vco_divided | | vco_divided | | vco_divided | 2960 * | _clk_src | | _clk_src | | _clk_src | 2961 * | | | | | | 2962 * |divsel_six | | divsel_two | | divsel_four | 2963 * +-------+------+ +-----+--------+ +--------+------+ 2964 * | | | 2965 * v---->----------v-------------<------v 2966 * | 2967 * +----------+-----------------+ 2968 * | dp_phy_pll_vco_div_clk | 2969 * +---------+------------------+ 2970 * | 2971 * v 2972 * Input to DISPCC block 2973 * for DP pixel clock 2974 * 2975 */ 2976 static int qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 2977 { 2978 switch (req->rate) { 2979 case 1620000000UL / 2: 2980 case 2700000000UL / 2: 2981 /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ 2982 return 0; 2983 default: 2984 return -EINVAL; 2985 } 2986 } 2987 2988 static unsigned long qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 2989 { 2990 const struct qmp_combo *qmp; 2991 const struct phy_configure_opts_dp *dp_opts; 2992 2993 qmp = container_of(hw, struct qmp_combo, dp_pixel_hw); 2994 dp_opts = &qmp->dp_opts; 2995 2996 switch (dp_opts->link_rate) { 2997 case 1620: 2998 return 1620000000UL / 2; 2999 case 2700: 3000 return 2700000000UL / 2; 3001 case 5400: 3002 return 5400000000UL / 4; 3003 case 8100: 3004 return 8100000000UL / 6; 3005 default: 3006 return 0; 3007 } 3008 } 3009 3010 static const struct clk_ops qmp_dp_pixel_clk_ops = { 3011 .determine_rate = qmp_dp_pixel_clk_determine_rate, 3012 .recalc_rate = qmp_dp_pixel_clk_recalc_rate, 3013 }; 3014 3015 static int qmp_dp_link_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 3016 { 3017 switch (req->rate) { 3018 case 162000000: 3019 case 270000000: 3020 case 540000000: 3021 case 810000000: 3022 return 0; 3023 default: 3024 return -EINVAL; 3025 } 3026 } 3027 3028 static unsigned long qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 3029 { 3030 const struct qmp_combo *qmp; 3031 const struct phy_configure_opts_dp *dp_opts; 3032 3033 qmp = container_of(hw, struct qmp_combo, dp_link_hw); 3034 dp_opts = &qmp->dp_opts; 3035 3036 switch (dp_opts->link_rate) { 3037 case 1620: 3038 case 2700: 3039 case 5400: 3040 case 8100: 3041 return dp_opts->link_rate * 100000; 3042 default: 3043 return 0; 3044 } 3045 } 3046 3047 static const struct clk_ops qmp_dp_link_clk_ops = { 3048 .determine_rate = qmp_dp_link_clk_determine_rate, 3049 .recalc_rate = qmp_dp_link_clk_recalc_rate, 3050 }; 3051 3052 static struct clk_hw *qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) 3053 { 3054 struct qmp_combo *qmp = data; 3055 unsigned int idx = clkspec->args[0]; 3056 3057 if (idx >= 2) { 3058 pr_err("%s: invalid index %u\n", __func__, idx); 3059 return ERR_PTR(-EINVAL); 3060 } 3061 3062 if (idx == 0) 3063 return &qmp->dp_link_hw; 3064 3065 return &qmp->dp_pixel_hw; 3066 } 3067 3068 static int phy_dp_clks_register(struct qmp_combo *qmp, struct device_node *np) 3069 { 3070 struct clk_init_data init = { }; 3071 char name[64]; 3072 int ret; 3073 3074 snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); 3075 init.ops = &qmp_dp_link_clk_ops; 3076 init.name = name; 3077 qmp->dp_link_hw.init = &init; 3078 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_link_hw); 3079 if (ret) 3080 return ret; 3081 3082 snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); 3083 init.ops = &qmp_dp_pixel_clk_ops; 3084 init.name = name; 3085 qmp->dp_pixel_hw.init = &init; 3086 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_pixel_hw); 3087 if (ret) 3088 return ret; 3089 3090 return 0; 3091 } 3092 3093 static struct clk_hw *qmp_combo_clk_hw_get(struct of_phandle_args *clkspec, void *data) 3094 { 3095 struct qmp_combo *qmp = data; 3096 3097 switch (clkspec->args[0]) { 3098 case QMP_USB43DP_USB3_PIPE_CLK: 3099 return &qmp->pipe_clk_fixed.hw; 3100 case QMP_USB43DP_DP_LINK_CLK: 3101 return &qmp->dp_link_hw; 3102 case QMP_USB43DP_DP_VCO_DIV_CLK: 3103 return &qmp->dp_pixel_hw; 3104 } 3105 3106 return ERR_PTR(-EINVAL); 3107 } 3108 3109 static int qmp_combo_register_clocks(struct qmp_combo *qmp, struct device_node *usb_np, 3110 struct device_node *dp_np) 3111 { 3112 int ret; 3113 3114 ret = phy_pipe_clk_register(qmp, usb_np); 3115 if (ret) 3116 return ret; 3117 3118 ret = phy_dp_clks_register(qmp, dp_np); 3119 if (ret) 3120 return ret; 3121 3122 /* 3123 * Register a single provider for bindings without child nodes. 3124 */ 3125 if (usb_np == qmp->dev->of_node) 3126 return devm_of_clk_add_hw_provider(qmp->dev, qmp_combo_clk_hw_get, qmp); 3127 3128 /* 3129 * Register multiple providers for legacy bindings with child nodes. 3130 */ 3131 ret = of_clk_add_hw_provider(usb_np, of_clk_hw_simple_get, 3132 &qmp->pipe_clk_fixed.hw); 3133 if (ret) 3134 return ret; 3135 3136 /* 3137 * Roll a devm action because the clock provider is the child node, but 3138 * the child node is not actually a device. 3139 */ 3140 ret = devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, usb_np); 3141 if (ret) 3142 return ret; 3143 3144 ret = of_clk_add_hw_provider(dp_np, qmp_dp_clks_hw_get, qmp); 3145 if (ret) 3146 return ret; 3147 3148 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, dp_np); 3149 } 3150 3151 #if IS_ENABLED(CONFIG_TYPEC) 3152 static int qmp_combo_typec_switch_set(struct typec_switch_dev *sw, 3153 enum typec_orientation orientation) 3154 { 3155 struct qmp_combo *qmp = typec_switch_get_drvdata(sw); 3156 const struct qmp_phy_cfg *cfg = qmp->cfg; 3157 3158 if (orientation == qmp->orientation || orientation == TYPEC_ORIENTATION_NONE) 3159 return 0; 3160 3161 mutex_lock(&qmp->phy_mutex); 3162 qmp->orientation = orientation; 3163 3164 if (qmp->init_count) { 3165 if (qmp->usb_init_count) 3166 qmp_combo_usb_power_off(qmp->usb_phy); 3167 qmp_combo_com_exit(qmp, true); 3168 3169 qmp_combo_com_init(qmp, true); 3170 if (qmp->usb_init_count) 3171 qmp_combo_usb_power_on(qmp->usb_phy); 3172 if (qmp->dp_init_count) 3173 cfg->dp_aux_init(qmp); 3174 } 3175 mutex_unlock(&qmp->phy_mutex); 3176 3177 return 0; 3178 } 3179 3180 static void qmp_combo_typec_unregister(void *data) 3181 { 3182 struct qmp_combo *qmp = data; 3183 3184 typec_switch_unregister(qmp->sw); 3185 } 3186 3187 static int qmp_combo_typec_switch_register(struct qmp_combo *qmp) 3188 { 3189 struct typec_switch_desc sw_desc = {}; 3190 struct device *dev = qmp->dev; 3191 3192 sw_desc.drvdata = qmp; 3193 sw_desc.fwnode = dev->fwnode; 3194 sw_desc.set = qmp_combo_typec_switch_set; 3195 qmp->sw = typec_switch_register(dev, &sw_desc); 3196 if (IS_ERR(qmp->sw)) { 3197 dev_err(dev, "Unable to register typec switch: %pe\n", qmp->sw); 3198 return PTR_ERR(qmp->sw); 3199 } 3200 3201 return devm_add_action_or_reset(dev, qmp_combo_typec_unregister, qmp); 3202 } 3203 #else 3204 static int qmp_combo_typec_switch_register(struct qmp_combo *qmp) 3205 { 3206 return 0; 3207 } 3208 #endif 3209 3210 #if IS_ENABLED(CONFIG_DRM) 3211 static int qmp_combo_bridge_attach(struct drm_bridge *bridge, 3212 enum drm_bridge_attach_flags flags) 3213 { 3214 struct qmp_combo *qmp = container_of(bridge, struct qmp_combo, bridge); 3215 struct drm_bridge *next_bridge; 3216 3217 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 3218 return -EINVAL; 3219 3220 next_bridge = devm_drm_of_get_bridge(qmp->dev, qmp->dev->of_node, 0, 0); 3221 if (IS_ERR(next_bridge)) { 3222 dev_err(qmp->dev, "failed to acquire drm_bridge: %pe\n", next_bridge); 3223 return PTR_ERR(next_bridge); 3224 } 3225 3226 return drm_bridge_attach(bridge->encoder, next_bridge, bridge, 3227 DRM_BRIDGE_ATTACH_NO_CONNECTOR); 3228 } 3229 3230 static const struct drm_bridge_funcs qmp_combo_bridge_funcs = { 3231 .attach = qmp_combo_bridge_attach, 3232 }; 3233 3234 static int qmp_combo_dp_register_bridge(struct qmp_combo *qmp) 3235 { 3236 qmp->bridge.funcs = &qmp_combo_bridge_funcs; 3237 qmp->bridge.of_node = qmp->dev->of_node; 3238 3239 return devm_drm_bridge_add(qmp->dev, &qmp->bridge); 3240 } 3241 #else 3242 static int qmp_combo_dp_register_bridge(struct qmp_combo *qmp) 3243 { 3244 return 0; 3245 } 3246 #endif 3247 3248 static int qmp_combo_parse_dt_lecacy_dp(struct qmp_combo *qmp, struct device_node *np) 3249 { 3250 struct device *dev = qmp->dev; 3251 3252 /* 3253 * Get memory resources from the DP child node: 3254 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; 3255 * tx2 -> 3; rx2 -> 4 3256 * 3257 * Note that only tx/tx2 and pcs (dp_phy) are used by the DP 3258 * implementation. 3259 */ 3260 qmp->dp_tx = devm_of_iomap(dev, np, 0, NULL); 3261 if (IS_ERR(qmp->dp_tx)) 3262 return PTR_ERR(qmp->dp_tx); 3263 3264 qmp->dp_dp_phy = devm_of_iomap(dev, np, 2, NULL); 3265 if (IS_ERR(qmp->dp_dp_phy)) 3266 return PTR_ERR(qmp->dp_dp_phy); 3267 3268 qmp->dp_tx2 = devm_of_iomap(dev, np, 3, NULL); 3269 if (IS_ERR(qmp->dp_tx2)) 3270 return PTR_ERR(qmp->dp_tx2); 3271 3272 return 0; 3273 } 3274 3275 static int qmp_combo_parse_dt_lecacy_usb(struct qmp_combo *qmp, struct device_node *np) 3276 { 3277 const struct qmp_phy_cfg *cfg = qmp->cfg; 3278 struct device *dev = qmp->dev; 3279 3280 /* 3281 * Get memory resources from the USB child node: 3282 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; 3283 * tx2 -> 3; rx2 -> 4; pcs_misc (optional) -> 5 3284 */ 3285 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 3286 if (IS_ERR(qmp->tx)) 3287 return PTR_ERR(qmp->tx); 3288 3289 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 3290 if (IS_ERR(qmp->rx)) 3291 return PTR_ERR(qmp->rx); 3292 3293 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 3294 if (IS_ERR(qmp->pcs)) 3295 return PTR_ERR(qmp->pcs); 3296 3297 if (cfg->pcs_usb_offset) 3298 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset; 3299 3300 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 3301 if (IS_ERR(qmp->tx2)) 3302 return PTR_ERR(qmp->tx2); 3303 3304 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 3305 if (IS_ERR(qmp->rx2)) 3306 return PTR_ERR(qmp->rx2); 3307 3308 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 3309 if (IS_ERR(qmp->pcs_misc)) { 3310 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 3311 qmp->pcs_misc = NULL; 3312 } 3313 3314 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 3315 if (IS_ERR(qmp->pipe_clk)) { 3316 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 3317 "failed to get pipe clock\n"); 3318 } 3319 3320 return 0; 3321 } 3322 3323 static int qmp_combo_parse_dt_legacy(struct qmp_combo *qmp, struct device_node *usb_np, 3324 struct device_node *dp_np) 3325 { 3326 struct platform_device *pdev = to_platform_device(qmp->dev); 3327 int ret; 3328 3329 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 3330 if (IS_ERR(qmp->serdes)) 3331 return PTR_ERR(qmp->serdes); 3332 3333 qmp->com = devm_platform_ioremap_resource(pdev, 1); 3334 if (IS_ERR(qmp->com)) 3335 return PTR_ERR(qmp->com); 3336 3337 qmp->dp_serdes = devm_platform_ioremap_resource(pdev, 2); 3338 if (IS_ERR(qmp->dp_serdes)) 3339 return PTR_ERR(qmp->dp_serdes); 3340 3341 ret = qmp_combo_parse_dt_lecacy_usb(qmp, usb_np); 3342 if (ret) 3343 return ret; 3344 3345 ret = qmp_combo_parse_dt_lecacy_dp(qmp, dp_np); 3346 if (ret) 3347 return ret; 3348 3349 return 0; 3350 } 3351 3352 static int qmp_combo_parse_dt(struct qmp_combo *qmp) 3353 { 3354 struct platform_device *pdev = to_platform_device(qmp->dev); 3355 const struct qmp_phy_cfg *cfg = qmp->cfg; 3356 const struct qmp_combo_offsets *offs = cfg->offsets; 3357 struct device *dev = qmp->dev; 3358 void __iomem *base; 3359 3360 if (!offs) 3361 return -EINVAL; 3362 3363 base = devm_platform_ioremap_resource(pdev, 0); 3364 if (IS_ERR(base)) 3365 return PTR_ERR(base); 3366 3367 qmp->com = base + offs->com; 3368 qmp->tx = base + offs->txa; 3369 qmp->rx = base + offs->rxa; 3370 qmp->tx2 = base + offs->txb; 3371 qmp->rx2 = base + offs->rxb; 3372 3373 qmp->serdes = base + offs->usb3_serdes; 3374 qmp->pcs_misc = base + offs->usb3_pcs_misc; 3375 qmp->pcs = base + offs->usb3_pcs; 3376 qmp->pcs_usb = base + offs->usb3_pcs_usb; 3377 3378 qmp->dp_serdes = base + offs->dp_serdes; 3379 if (offs->dp_txa) { 3380 qmp->dp_tx = base + offs->dp_txa; 3381 qmp->dp_tx2 = base + offs->dp_txb; 3382 } else { 3383 qmp->dp_tx = base + offs->txa; 3384 qmp->dp_tx2 = base + offs->txb; 3385 } 3386 qmp->dp_dp_phy = base + offs->dp_dp_phy; 3387 3388 qmp->pipe_clk = devm_clk_get(dev, "usb3_pipe"); 3389 if (IS_ERR(qmp->pipe_clk)) { 3390 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 3391 "failed to get usb3_pipe clock\n"); 3392 } 3393 3394 return 0; 3395 } 3396 3397 static struct phy *qmp_combo_phy_xlate(struct device *dev, struct of_phandle_args *args) 3398 { 3399 struct qmp_combo *qmp = dev_get_drvdata(dev); 3400 3401 if (args->args_count == 0) 3402 return ERR_PTR(-EINVAL); 3403 3404 switch (args->args[0]) { 3405 case QMP_USB43DP_USB3_PHY: 3406 return qmp->usb_phy; 3407 case QMP_USB43DP_DP_PHY: 3408 return qmp->dp_phy; 3409 } 3410 3411 return ERR_PTR(-EINVAL); 3412 } 3413 3414 static int qmp_combo_probe(struct platform_device *pdev) 3415 { 3416 struct qmp_combo *qmp; 3417 struct device *dev = &pdev->dev; 3418 struct device_node *dp_np, *usb_np; 3419 struct phy_provider *phy_provider; 3420 int ret; 3421 3422 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 3423 if (!qmp) 3424 return -ENOMEM; 3425 3426 qmp->dev = dev; 3427 3428 qmp->orientation = TYPEC_ORIENTATION_NORMAL; 3429 3430 qmp->cfg = of_device_get_match_data(dev); 3431 if (!qmp->cfg) 3432 return -EINVAL; 3433 3434 mutex_init(&qmp->phy_mutex); 3435 3436 ret = qmp_combo_clk_init(qmp); 3437 if (ret) 3438 return ret; 3439 3440 ret = qmp_combo_reset_init(qmp); 3441 if (ret) 3442 return ret; 3443 3444 ret = qmp_combo_vreg_init(qmp); 3445 if (ret) 3446 return ret; 3447 3448 ret = qmp_combo_typec_switch_register(qmp); 3449 if (ret) 3450 return ret; 3451 3452 ret = qmp_combo_dp_register_bridge(qmp); 3453 if (ret) 3454 return ret; 3455 3456 /* Check for legacy binding with child nodes. */ 3457 usb_np = of_get_child_by_name(dev->of_node, "usb3-phy"); 3458 if (usb_np) { 3459 dp_np = of_get_child_by_name(dev->of_node, "dp-phy"); 3460 if (!dp_np) { 3461 of_node_put(usb_np); 3462 return -EINVAL; 3463 } 3464 3465 ret = qmp_combo_parse_dt_legacy(qmp, usb_np, dp_np); 3466 } else { 3467 usb_np = of_node_get(dev->of_node); 3468 dp_np = of_node_get(dev->of_node); 3469 3470 ret = qmp_combo_parse_dt(qmp); 3471 } 3472 if (ret) 3473 goto err_node_put; 3474 3475 pm_runtime_set_active(dev); 3476 ret = devm_pm_runtime_enable(dev); 3477 if (ret) 3478 goto err_node_put; 3479 /* 3480 * Prevent runtime pm from being ON by default. Users can enable 3481 * it using power/control in sysfs. 3482 */ 3483 pm_runtime_forbid(dev); 3484 3485 ret = qmp_combo_register_clocks(qmp, usb_np, dp_np); 3486 if (ret) 3487 goto err_node_put; 3488 3489 qmp->usb_phy = devm_phy_create(dev, usb_np, &qmp_combo_usb_phy_ops); 3490 if (IS_ERR(qmp->usb_phy)) { 3491 ret = PTR_ERR(qmp->usb_phy); 3492 dev_err(dev, "failed to create USB PHY: %d\n", ret); 3493 goto err_node_put; 3494 } 3495 3496 phy_set_drvdata(qmp->usb_phy, qmp); 3497 3498 qmp->dp_phy = devm_phy_create(dev, dp_np, &qmp_combo_dp_phy_ops); 3499 if (IS_ERR(qmp->dp_phy)) { 3500 ret = PTR_ERR(qmp->dp_phy); 3501 dev_err(dev, "failed to create DP PHY: %d\n", ret); 3502 goto err_node_put; 3503 } 3504 3505 phy_set_drvdata(qmp->dp_phy, qmp); 3506 3507 dev_set_drvdata(dev, qmp); 3508 3509 if (usb_np == dev->of_node) 3510 phy_provider = devm_of_phy_provider_register(dev, qmp_combo_phy_xlate); 3511 else 3512 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 3513 3514 of_node_put(usb_np); 3515 of_node_put(dp_np); 3516 3517 return PTR_ERR_OR_ZERO(phy_provider); 3518 3519 err_node_put: 3520 of_node_put(usb_np); 3521 of_node_put(dp_np); 3522 return ret; 3523 } 3524 3525 static const struct of_device_id qmp_combo_of_match_table[] = { 3526 { 3527 .compatible = "qcom,sc7180-qmp-usb3-dp-phy", 3528 .data = &sc7180_usb3dpphy_cfg, 3529 }, 3530 { 3531 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", 3532 .data = &sc8180x_usb3dpphy_cfg, 3533 }, 3534 { 3535 .compatible = "qcom,sc8280xp-qmp-usb43dp-phy", 3536 .data = &sc8280xp_usb43dpphy_cfg, 3537 }, 3538 { 3539 .compatible = "qcom,sdm845-qmp-usb3-dp-phy", 3540 .data = &sdm845_usb3dpphy_cfg, 3541 }, 3542 { 3543 .compatible = "qcom,sm6350-qmp-usb3-dp-phy", 3544 .data = &sm6350_usb3dpphy_cfg, 3545 }, 3546 { 3547 .compatible = "qcom,sm8150-qmp-usb3-dp-phy", 3548 .data = &sc8180x_usb3dpphy_cfg, 3549 }, 3550 { 3551 .compatible = "qcom,sm8250-qmp-usb3-dp-phy", 3552 .data = &sm8250_usb3dpphy_cfg, 3553 }, 3554 { 3555 .compatible = "qcom,sm8350-qmp-usb3-dp-phy", 3556 .data = &sm8350_usb3dpphy_cfg, 3557 }, 3558 { 3559 .compatible = "qcom,sm8450-qmp-usb3-dp-phy", 3560 .data = &sm8350_usb3dpphy_cfg, 3561 }, 3562 { 3563 .compatible = "qcom,sm8550-qmp-usb3-dp-phy", 3564 .data = &sm8550_usb3dpphy_cfg, 3565 }, 3566 { } 3567 }; 3568 MODULE_DEVICE_TABLE(of, qmp_combo_of_match_table); 3569 3570 static struct platform_driver qmp_combo_driver = { 3571 .probe = qmp_combo_probe, 3572 .driver = { 3573 .name = "qcom-qmp-combo-phy", 3574 .pm = &qmp_combo_pm_ops, 3575 .of_match_table = qmp_combo_of_match_table, 3576 }, 3577 }; 3578 3579 module_platform_driver(qmp_combo_driver); 3580 3581 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 3582 MODULE_DESCRIPTION("Qualcomm QMP USB+DP combo PHY driver"); 3583 MODULE_LICENSE("GPL v2"); 3584