xref: /openbmc/linux/drivers/pci/setup-res.c (revision d2999e1b)
1 /*
2  *	drivers/pci/setup-res.c
3  *
4  * Extruded from code written by
5  *      Dave Rusling (david.rusling@reo.mts.dec.com)
6  *      David Mosberger (davidm@cs.arizona.edu)
7  *	David Miller (davem@redhat.com)
8  *
9  * Support routines for initializing a PCI subsystem.
10  */
11 
12 /* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
13 
14 /*
15  * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16  *	     Resource sorting
17  */
18 
19 #include <linux/kernel.h>
20 #include <linux/export.h>
21 #include <linux/pci.h>
22 #include <linux/errno.h>
23 #include <linux/ioport.h>
24 #include <linux/cache.h>
25 #include <linux/slab.h>
26 #include "pci.h"
27 
28 
29 void pci_update_resource(struct pci_dev *dev, int resno)
30 {
31 	struct pci_bus_region region;
32 	bool disable;
33 	u16 cmd;
34 	u32 new, check, mask;
35 	int reg;
36 	enum pci_bar_type type;
37 	struct resource *res = dev->resource + resno;
38 
39 	/*
40 	 * Ignore resources for unimplemented BARs and unused resource slots
41 	 * for 64 bit BARs.
42 	 */
43 	if (!res->flags)
44 		return;
45 
46 	if (res->flags & IORESOURCE_UNSET)
47 		return;
48 
49 	/*
50 	 * Ignore non-moveable resources.  This might be legacy resources for
51 	 * which no functional BAR register exists or another important
52 	 * system resource we shouldn't move around.
53 	 */
54 	if (res->flags & IORESOURCE_PCI_FIXED)
55 		return;
56 
57 	pcibios_resource_to_bus(dev->bus, &region, res);
58 
59 	new = region.start | (res->flags & PCI_REGION_FLAG_MASK);
60 	if (res->flags & IORESOURCE_IO)
61 		mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
62 	else
63 		mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
64 
65 	reg = pci_resource_bar(dev, resno, &type);
66 	if (!reg)
67 		return;
68 	if (type != pci_bar_unknown) {
69 		if (!(res->flags & IORESOURCE_ROM_ENABLE))
70 			return;
71 		new |= PCI_ROM_ADDRESS_ENABLE;
72 	}
73 
74 	/*
75 	 * We can't update a 64-bit BAR atomically, so when possible,
76 	 * disable decoding so that a half-updated BAR won't conflict
77 	 * with another device.
78 	 */
79 	disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
80 	if (disable) {
81 		pci_read_config_word(dev, PCI_COMMAND, &cmd);
82 		pci_write_config_word(dev, PCI_COMMAND,
83 				      cmd & ~PCI_COMMAND_MEMORY);
84 	}
85 
86 	pci_write_config_dword(dev, reg, new);
87 	pci_read_config_dword(dev, reg, &check);
88 
89 	if ((new ^ check) & mask) {
90 		dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
91 			resno, new, check);
92 	}
93 
94 	if (res->flags & IORESOURCE_MEM_64) {
95 		new = region.start >> 16 >> 16;
96 		pci_write_config_dword(dev, reg + 4, new);
97 		pci_read_config_dword(dev, reg + 4, &check);
98 		if (check != new) {
99 			dev_err(&dev->dev, "BAR %d: error updating (high %#08x != %#08x)\n",
100 				resno, new, check);
101 		}
102 	}
103 
104 	if (disable)
105 		pci_write_config_word(dev, PCI_COMMAND, cmd);
106 }
107 
108 int pci_claim_resource(struct pci_dev *dev, int resource)
109 {
110 	struct resource *res = &dev->resource[resource];
111 	struct resource *root, *conflict;
112 
113 	if (res->flags & IORESOURCE_UNSET) {
114 		dev_info(&dev->dev, "can't claim BAR %d %pR: no address assigned\n",
115 			 resource, res);
116 		return -EINVAL;
117 	}
118 
119 	root = pci_find_parent_resource(dev, res);
120 	if (!root) {
121 		dev_info(&dev->dev, "can't claim BAR %d %pR: no compatible bridge window\n",
122 			 resource, res);
123 		return -EINVAL;
124 	}
125 
126 	conflict = request_resource_conflict(root, res);
127 	if (conflict) {
128 		dev_info(&dev->dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
129 			 resource, res, conflict->name, conflict);
130 		return -EBUSY;
131 	}
132 
133 	return 0;
134 }
135 EXPORT_SYMBOL(pci_claim_resource);
136 
137 void pci_disable_bridge_window(struct pci_dev *dev)
138 {
139 	dev_info(&dev->dev, "disabling bridge mem windows\n");
140 
141 	/* MMIO Base/Limit */
142 	pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
143 
144 	/* Prefetchable MMIO Base/Limit */
145 	pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
146 	pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
147 	pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
148 }
149 
150 /*
151  * Generic function that returns a value indicating that the device's
152  * original BIOS BAR address was not saved and so is not available for
153  * reinstatement.
154  *
155  * Can be over-ridden by architecture specific code that implements
156  * reinstatement functionality rather than leaving it disabled when
157  * normal allocation attempts fail.
158  */
159 resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
160 {
161 	return 0;
162 }
163 
164 static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
165 		int resno, resource_size_t size)
166 {
167 	struct resource *root, *conflict;
168 	resource_size_t fw_addr, start, end;
169 	int ret = 0;
170 
171 	fw_addr = pcibios_retrieve_fw_addr(dev, resno);
172 	if (!fw_addr)
173 		return 1;
174 
175 	start = res->start;
176 	end = res->end;
177 	res->start = fw_addr;
178 	res->end = res->start + size - 1;
179 
180 	root = pci_find_parent_resource(dev, res);
181 	if (!root) {
182 		if (res->flags & IORESOURCE_IO)
183 			root = &ioport_resource;
184 		else
185 			root = &iomem_resource;
186 	}
187 
188 	dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
189 		 resno, res);
190 	conflict = request_resource_conflict(root, res);
191 	if (conflict) {
192 		dev_info(&dev->dev,
193 			 "BAR %d: %pR conflicts with %s %pR\n", resno,
194 			 res, conflict->name, conflict);
195 		res->start = start;
196 		res->end = end;
197 		ret = 1;
198 	}
199 	return ret;
200 }
201 
202 static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
203 		int resno, resource_size_t size, resource_size_t align)
204 {
205 	struct resource *res = dev->resource + resno;
206 	resource_size_t min;
207 	int ret;
208 
209 	min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
210 
211 	/*
212 	 * First, try exact prefetching match.  Even if a 64-bit
213 	 * prefetchable bridge window is below 4GB, we can't put a 32-bit
214 	 * prefetchable resource in it because pbus_size_mem() assumes a
215 	 * 64-bit window will contain no 32-bit resources.  If we assign
216 	 * things differently than they were sized, not everything will fit.
217 	 */
218 	ret = pci_bus_alloc_resource(bus, res, size, align, min,
219 				     IORESOURCE_PREFETCH | IORESOURCE_MEM_64,
220 				     pcibios_align_resource, dev);
221 	if (ret == 0)
222 		return 0;
223 
224 	/*
225 	 * If the prefetchable window is only 32 bits wide, we can put
226 	 * 64-bit prefetchable resources in it.
227 	 */
228 	if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) ==
229 	     (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) {
230 		ret = pci_bus_alloc_resource(bus, res, size, align, min,
231 					     IORESOURCE_PREFETCH,
232 					     pcibios_align_resource, dev);
233 		if (ret == 0)
234 			return 0;
235 	}
236 
237 	/*
238 	 * If we didn't find a better match, we can put any memory resource
239 	 * in a non-prefetchable window.  If this resource is 32 bits and
240 	 * non-prefetchable, the first call already tried the only possibility
241 	 * so we don't need to try again.
242 	 */
243 	if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64))
244 		ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
245 					     pcibios_align_resource, dev);
246 
247 	return ret;
248 }
249 
250 static int _pci_assign_resource(struct pci_dev *dev, int resno,
251 				resource_size_t size, resource_size_t min_align)
252 {
253 	struct resource *res = dev->resource + resno;
254 	struct pci_bus *bus;
255 	int ret;
256 	char *type;
257 
258 	bus = dev->bus;
259 	while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
260 		if (!bus->parent || !bus->self->transparent)
261 			break;
262 		bus = bus->parent;
263 	}
264 
265 	if (ret) {
266 		if (res->flags & IORESOURCE_MEM)
267 			if (res->flags & IORESOURCE_PREFETCH)
268 				type = "mem pref";
269 			else
270 				type = "mem";
271 		else if (res->flags & IORESOURCE_IO)
272 			type = "io";
273 		else
274 			type = "unknown";
275 		dev_info(&dev->dev,
276 			 "BAR %d: can't assign %s (size %#llx)\n",
277 			 resno, type, (unsigned long long) resource_size(res));
278 	}
279 
280 	return ret;
281 }
282 
283 int pci_assign_resource(struct pci_dev *dev, int resno)
284 {
285 	struct resource *res = dev->resource + resno;
286 	resource_size_t align, size;
287 	int ret;
288 
289 	res->flags |= IORESOURCE_UNSET;
290 	align = pci_resource_alignment(dev, res);
291 	if (!align) {
292 		dev_info(&dev->dev, "BAR %d: can't assign %pR (bogus alignment)\n",
293 			 resno, res);
294 		return -EINVAL;
295 	}
296 
297 	size = resource_size(res);
298 	ret = _pci_assign_resource(dev, resno, size, align);
299 
300 	/*
301 	 * If we failed to assign anything, let's try the address
302 	 * where firmware left it.  That at least has a chance of
303 	 * working, which is better than just leaving it disabled.
304 	 */
305 	if (ret < 0)
306 		ret = pci_revert_fw_address(res, dev, resno, size);
307 
308 	if (!ret) {
309 		res->flags &= ~IORESOURCE_UNSET;
310 		res->flags &= ~IORESOURCE_STARTALIGN;
311 		dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
312 		if (resno < PCI_BRIDGE_RESOURCES)
313 			pci_update_resource(dev, resno);
314 	}
315 	return ret;
316 }
317 EXPORT_SYMBOL(pci_assign_resource);
318 
319 int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
320 			resource_size_t min_align)
321 {
322 	struct resource *res = dev->resource + resno;
323 	resource_size_t new_size;
324 	int ret;
325 
326 	res->flags |= IORESOURCE_UNSET;
327 	if (!res->parent) {
328 		dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR\n",
329 			 resno, res);
330 		return -EINVAL;
331 	}
332 
333 	/* already aligned with min_align */
334 	new_size = resource_size(res) + addsize;
335 	ret = _pci_assign_resource(dev, resno, new_size, min_align);
336 	if (!ret) {
337 		res->flags &= ~IORESOURCE_UNSET;
338 		res->flags &= ~IORESOURCE_STARTALIGN;
339 		dev_info(&dev->dev, "BAR %d: reassigned %pR\n", resno, res);
340 		if (resno < PCI_BRIDGE_RESOURCES)
341 			pci_update_resource(dev, resno);
342 	}
343 	return ret;
344 }
345 
346 int pci_enable_resources(struct pci_dev *dev, int mask)
347 {
348 	u16 cmd, old_cmd;
349 	int i;
350 	struct resource *r;
351 
352 	pci_read_config_word(dev, PCI_COMMAND, &cmd);
353 	old_cmd = cmd;
354 
355 	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
356 		if (!(mask & (1 << i)))
357 			continue;
358 
359 		r = &dev->resource[i];
360 
361 		if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
362 			continue;
363 		if ((i == PCI_ROM_RESOURCE) &&
364 				(!(r->flags & IORESOURCE_ROM_ENABLE)))
365 			continue;
366 
367 		if (r->flags & IORESOURCE_UNSET) {
368 			dev_err(&dev->dev, "can't enable device: BAR %d %pR not assigned\n",
369 				i, r);
370 			return -EINVAL;
371 		}
372 
373 		if (!r->parent) {
374 			dev_err(&dev->dev, "can't enable device: BAR %d %pR not claimed\n",
375 				i, r);
376 			return -EINVAL;
377 		}
378 
379 		if (r->flags & IORESOURCE_IO)
380 			cmd |= PCI_COMMAND_IO;
381 		if (r->flags & IORESOURCE_MEM)
382 			cmd |= PCI_COMMAND_MEMORY;
383 	}
384 
385 	if (cmd != old_cmd) {
386 		dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
387 			 old_cmd, cmd);
388 		pci_write_config_word(dev, PCI_COMMAND, cmd);
389 	}
390 	return 0;
391 }
392