1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * drivers/pci/setup-res.c 4 * 5 * Extruded from code written by 6 * Dave Rusling (david.rusling@reo.mts.dec.com) 7 * David Mosberger (davidm@cs.arizona.edu) 8 * David Miller (davem@redhat.com) 9 * 10 * Support routines for initializing a PCI subsystem. 11 */ 12 13 /* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */ 14 15 /* 16 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> 17 * Resource sorting 18 */ 19 20 #include <linux/kernel.h> 21 #include <linux/export.h> 22 #include <linux/pci.h> 23 #include <linux/errno.h> 24 #include <linux/ioport.h> 25 #include <linux/cache.h> 26 #include <linux/slab.h> 27 #include "pci.h" 28 29 static void pci_std_update_resource(struct pci_dev *dev, int resno) 30 { 31 struct pci_bus_region region; 32 bool disable; 33 u16 cmd; 34 u32 new, check, mask; 35 int reg; 36 struct resource *res = dev->resource + resno; 37 38 /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */ 39 if (dev->is_virtfn) 40 return; 41 42 /* 43 * Ignore resources for unimplemented BARs and unused resource slots 44 * for 64 bit BARs. 45 */ 46 if (!res->flags) 47 return; 48 49 if (res->flags & IORESOURCE_UNSET) 50 return; 51 52 /* 53 * Ignore non-moveable resources. This might be legacy resources for 54 * which no functional BAR register exists or another important 55 * system resource we shouldn't move around. 56 */ 57 if (res->flags & IORESOURCE_PCI_FIXED) 58 return; 59 60 pcibios_resource_to_bus(dev->bus, ®ion, res); 61 new = region.start; 62 63 if (res->flags & IORESOURCE_IO) { 64 mask = (u32)PCI_BASE_ADDRESS_IO_MASK; 65 new |= res->flags & ~PCI_BASE_ADDRESS_IO_MASK; 66 } else if (resno == PCI_ROM_RESOURCE) { 67 mask = PCI_ROM_ADDRESS_MASK; 68 } else { 69 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; 70 new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK; 71 } 72 73 if (resno < PCI_ROM_RESOURCE) { 74 reg = PCI_BASE_ADDRESS_0 + 4 * resno; 75 } else if (resno == PCI_ROM_RESOURCE) { 76 77 /* 78 * Apparently some Matrox devices have ROM BARs that read 79 * as zero when disabled, so don't update ROM BARs unless 80 * they're enabled. See https://lkml.org/lkml/2005/8/30/138. 81 */ 82 if (!(res->flags & IORESOURCE_ROM_ENABLE)) 83 return; 84 85 reg = dev->rom_base_reg; 86 new |= PCI_ROM_ADDRESS_ENABLE; 87 } else 88 return; 89 90 /* 91 * We can't update a 64-bit BAR atomically, so when possible, 92 * disable decoding so that a half-updated BAR won't conflict 93 * with another device. 94 */ 95 disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on; 96 if (disable) { 97 pci_read_config_word(dev, PCI_COMMAND, &cmd); 98 pci_write_config_word(dev, PCI_COMMAND, 99 cmd & ~PCI_COMMAND_MEMORY); 100 } 101 102 pci_write_config_dword(dev, reg, new); 103 pci_read_config_dword(dev, reg, &check); 104 105 if ((new ^ check) & mask) { 106 pci_err(dev, "BAR %d: error updating (%#08x != %#08x)\n", 107 resno, new, check); 108 } 109 110 if (res->flags & IORESOURCE_MEM_64) { 111 new = region.start >> 16 >> 16; 112 pci_write_config_dword(dev, reg + 4, new); 113 pci_read_config_dword(dev, reg + 4, &check); 114 if (check != new) { 115 pci_err(dev, "BAR %d: error updating (high %#08x != %#08x)\n", 116 resno, new, check); 117 } 118 } 119 120 if (disable) 121 pci_write_config_word(dev, PCI_COMMAND, cmd); 122 } 123 124 void pci_update_resource(struct pci_dev *dev, int resno) 125 { 126 if (resno <= PCI_ROM_RESOURCE) 127 pci_std_update_resource(dev, resno); 128 #ifdef CONFIG_PCI_IOV 129 else if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) 130 pci_iov_update_resource(dev, resno); 131 #endif 132 } 133 134 int pci_claim_resource(struct pci_dev *dev, int resource) 135 { 136 struct resource *res = &dev->resource[resource]; 137 struct resource *root, *conflict; 138 139 if (res->flags & IORESOURCE_UNSET) { 140 pci_info(dev, "can't claim BAR %d %pR: no address assigned\n", 141 resource, res); 142 return -EINVAL; 143 } 144 145 /* 146 * If we have a shadow copy in RAM, the PCI device doesn't respond 147 * to the shadow range, so we don't need to claim it, and upstream 148 * bridges don't need to route the range to the device. 149 */ 150 if (res->flags & IORESOURCE_ROM_SHADOW) 151 return 0; 152 153 root = pci_find_parent_resource(dev, res); 154 if (!root) { 155 pci_info(dev, "can't claim BAR %d %pR: no compatible bridge window\n", 156 resource, res); 157 res->flags |= IORESOURCE_UNSET; 158 return -EINVAL; 159 } 160 161 conflict = request_resource_conflict(root, res); 162 if (conflict) { 163 pci_info(dev, "can't claim BAR %d %pR: address conflict with %s %pR\n", 164 resource, res, conflict->name, conflict); 165 res->flags |= IORESOURCE_UNSET; 166 return -EBUSY; 167 } 168 169 return 0; 170 } 171 EXPORT_SYMBOL(pci_claim_resource); 172 173 void pci_disable_bridge_window(struct pci_dev *dev) 174 { 175 pci_info(dev, "disabling bridge mem windows\n"); 176 177 /* MMIO Base/Limit */ 178 pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0); 179 180 /* Prefetchable MMIO Base/Limit */ 181 pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0); 182 pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0); 183 pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff); 184 } 185 186 /* 187 * Generic function that returns a value indicating that the device's 188 * original BIOS BAR address was not saved and so is not available for 189 * reinstatement. 190 * 191 * Can be over-ridden by architecture specific code that implements 192 * reinstatement functionality rather than leaving it disabled when 193 * normal allocation attempts fail. 194 */ 195 resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx) 196 { 197 return 0; 198 } 199 200 static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev, 201 int resno, resource_size_t size) 202 { 203 struct resource *root, *conflict; 204 resource_size_t fw_addr, start, end; 205 206 fw_addr = pcibios_retrieve_fw_addr(dev, resno); 207 if (!fw_addr) 208 return -ENOMEM; 209 210 start = res->start; 211 end = res->end; 212 res->start = fw_addr; 213 res->end = res->start + size - 1; 214 res->flags &= ~IORESOURCE_UNSET; 215 216 root = pci_find_parent_resource(dev, res); 217 if (!root) { 218 if (res->flags & IORESOURCE_IO) 219 root = &ioport_resource; 220 else 221 root = &iomem_resource; 222 } 223 224 pci_info(dev, "BAR %d: trying firmware assignment %pR\n", 225 resno, res); 226 conflict = request_resource_conflict(root, res); 227 if (conflict) { 228 pci_info(dev, "BAR %d: %pR conflicts with %s %pR\n", 229 resno, res, conflict->name, conflict); 230 res->start = start; 231 res->end = end; 232 res->flags |= IORESOURCE_UNSET; 233 return -EBUSY; 234 } 235 return 0; 236 } 237 238 /* 239 * We don't have to worry about legacy ISA devices, so nothing to do here. 240 * This is marked as __weak because multiple architectures define it; it should 241 * eventually go away. 242 */ 243 resource_size_t __weak pcibios_align_resource(void *data, 244 const struct resource *res, 245 resource_size_t size, 246 resource_size_t align) 247 { 248 return res->start; 249 } 250 251 static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev, 252 int resno, resource_size_t size, resource_size_t align) 253 { 254 struct resource *res = dev->resource + resno; 255 resource_size_t min; 256 int ret; 257 258 min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM; 259 260 /* 261 * First, try exact prefetching match. Even if a 64-bit 262 * prefetchable bridge window is below 4GB, we can't put a 32-bit 263 * prefetchable resource in it because pbus_size_mem() assumes a 264 * 64-bit window will contain no 32-bit resources. If we assign 265 * things differently than they were sized, not everything will fit. 266 */ 267 ret = pci_bus_alloc_resource(bus, res, size, align, min, 268 IORESOURCE_PREFETCH | IORESOURCE_MEM_64, 269 pcibios_align_resource, dev); 270 if (ret == 0) 271 return 0; 272 273 /* 274 * If the prefetchable window is only 32 bits wide, we can put 275 * 64-bit prefetchable resources in it. 276 */ 277 if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) == 278 (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) { 279 ret = pci_bus_alloc_resource(bus, res, size, align, min, 280 IORESOURCE_PREFETCH, 281 pcibios_align_resource, dev); 282 if (ret == 0) 283 return 0; 284 } 285 286 /* 287 * If we didn't find a better match, we can put any memory resource 288 * in a non-prefetchable window. If this resource is 32 bits and 289 * non-prefetchable, the first call already tried the only possibility 290 * so we don't need to try again. 291 */ 292 if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) 293 ret = pci_bus_alloc_resource(bus, res, size, align, min, 0, 294 pcibios_align_resource, dev); 295 296 return ret; 297 } 298 299 static int _pci_assign_resource(struct pci_dev *dev, int resno, 300 resource_size_t size, resource_size_t min_align) 301 { 302 struct pci_bus *bus; 303 int ret; 304 305 bus = dev->bus; 306 while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) { 307 if (!bus->parent || !bus->self->transparent) 308 break; 309 bus = bus->parent; 310 } 311 312 return ret; 313 } 314 315 int pci_assign_resource(struct pci_dev *dev, int resno) 316 { 317 struct resource *res = dev->resource + resno; 318 resource_size_t align, size; 319 int ret; 320 321 if (res->flags & IORESOURCE_PCI_FIXED) 322 return 0; 323 324 res->flags |= IORESOURCE_UNSET; 325 align = pci_resource_alignment(dev, res); 326 if (!align) { 327 pci_info(dev, "BAR %d: can't assign %pR (bogus alignment)\n", 328 resno, res); 329 return -EINVAL; 330 } 331 332 size = resource_size(res); 333 ret = _pci_assign_resource(dev, resno, size, align); 334 335 /* 336 * If we failed to assign anything, let's try the address 337 * where firmware left it. That at least has a chance of 338 * working, which is better than just leaving it disabled. 339 */ 340 if (ret < 0) { 341 pci_info(dev, "BAR %d: no space for %pR\n", resno, res); 342 ret = pci_revert_fw_address(res, dev, resno, size); 343 } 344 345 if (ret < 0) { 346 pci_info(dev, "BAR %d: failed to assign %pR\n", resno, res); 347 return ret; 348 } 349 350 res->flags &= ~IORESOURCE_UNSET; 351 res->flags &= ~IORESOURCE_STARTALIGN; 352 pci_info(dev, "BAR %d: assigned %pR\n", resno, res); 353 if (resno < PCI_BRIDGE_RESOURCES) 354 pci_update_resource(dev, resno); 355 356 return 0; 357 } 358 EXPORT_SYMBOL(pci_assign_resource); 359 360 int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize, 361 resource_size_t min_align) 362 { 363 struct resource *res = dev->resource + resno; 364 unsigned long flags; 365 resource_size_t new_size; 366 int ret; 367 368 if (res->flags & IORESOURCE_PCI_FIXED) 369 return 0; 370 371 flags = res->flags; 372 res->flags |= IORESOURCE_UNSET; 373 if (!res->parent) { 374 pci_info(dev, "BAR %d: can't reassign an unassigned resource %pR\n", 375 resno, res); 376 return -EINVAL; 377 } 378 379 /* already aligned with min_align */ 380 new_size = resource_size(res) + addsize; 381 ret = _pci_assign_resource(dev, resno, new_size, min_align); 382 if (ret) { 383 res->flags = flags; 384 pci_info(dev, "BAR %d: %pR (failed to expand by %#llx)\n", 385 resno, res, (unsigned long long) addsize); 386 return ret; 387 } 388 389 res->flags &= ~IORESOURCE_UNSET; 390 res->flags &= ~IORESOURCE_STARTALIGN; 391 pci_info(dev, "BAR %d: reassigned %pR (expanded by %#llx)\n", 392 resno, res, (unsigned long long) addsize); 393 if (resno < PCI_BRIDGE_RESOURCES) 394 pci_update_resource(dev, resno); 395 396 return 0; 397 } 398 399 void pci_release_resource(struct pci_dev *dev, int resno) 400 { 401 struct resource *res = dev->resource + resno; 402 403 pci_info(dev, "BAR %d: releasing %pR\n", resno, res); 404 405 if (!res->parent) 406 return; 407 408 release_resource(res); 409 res->end = resource_size(res) - 1; 410 res->start = 0; 411 res->flags |= IORESOURCE_UNSET; 412 } 413 EXPORT_SYMBOL(pci_release_resource); 414 415 int pci_resize_resource(struct pci_dev *dev, int resno, int size) 416 { 417 struct resource *res = dev->resource + resno; 418 int old, ret; 419 u32 sizes; 420 u16 cmd; 421 422 /* Make sure the resource isn't assigned before resizing it. */ 423 if (!(res->flags & IORESOURCE_UNSET)) 424 return -EBUSY; 425 426 pci_read_config_word(dev, PCI_COMMAND, &cmd); 427 if (cmd & PCI_COMMAND_MEMORY) 428 return -EBUSY; 429 430 sizes = pci_rebar_get_possible_sizes(dev, resno); 431 if (!sizes) 432 return -ENOTSUPP; 433 434 if (!(sizes & BIT(size))) 435 return -EINVAL; 436 437 old = pci_rebar_get_current_size(dev, resno); 438 if (old < 0) 439 return old; 440 441 ret = pci_rebar_set_size(dev, resno, size); 442 if (ret) 443 return ret; 444 445 res->end = res->start + pci_rebar_size_to_bytes(size) - 1; 446 447 /* Check if the new config works by trying to assign everything. */ 448 ret = pci_reassign_bridge_resources(dev->bus->self, res->flags); 449 if (ret) 450 goto error_resize; 451 452 return 0; 453 454 error_resize: 455 pci_rebar_set_size(dev, resno, old); 456 res->end = res->start + pci_rebar_size_to_bytes(old) - 1; 457 return ret; 458 } 459 EXPORT_SYMBOL(pci_resize_resource); 460 461 int pci_enable_resources(struct pci_dev *dev, int mask) 462 { 463 u16 cmd, old_cmd; 464 int i; 465 struct resource *r; 466 467 pci_read_config_word(dev, PCI_COMMAND, &cmd); 468 old_cmd = cmd; 469 470 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 471 if (!(mask & (1 << i))) 472 continue; 473 474 r = &dev->resource[i]; 475 476 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) 477 continue; 478 if ((i == PCI_ROM_RESOURCE) && 479 (!(r->flags & IORESOURCE_ROM_ENABLE))) 480 continue; 481 482 if (r->flags & IORESOURCE_UNSET) { 483 pci_err(dev, "can't enable device: BAR %d %pR not assigned\n", 484 i, r); 485 return -EINVAL; 486 } 487 488 if (!r->parent) { 489 pci_err(dev, "can't enable device: BAR %d %pR not claimed\n", 490 i, r); 491 return -EINVAL; 492 } 493 494 if (r->flags & IORESOURCE_IO) 495 cmd |= PCI_COMMAND_IO; 496 if (r->flags & IORESOURCE_MEM) 497 cmd |= PCI_COMMAND_MEMORY; 498 } 499 500 if (cmd != old_cmd) { 501 pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd); 502 pci_write_config_word(dev, PCI_COMMAND, cmd); 503 } 504 return 0; 505 } 506