1 /* 2 * drivers/pci/setup-res.c 3 * 4 * Extruded from code written by 5 * Dave Rusling (david.rusling@reo.mts.dec.com) 6 * David Mosberger (davidm@cs.arizona.edu) 7 * David Miller (davem@redhat.com) 8 * 9 * Support routines for initializing a PCI subsystem. 10 */ 11 12 /* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */ 13 14 /* 15 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> 16 * Resource sorting 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/export.h> 21 #include <linux/pci.h> 22 #include <linux/errno.h> 23 #include <linux/ioport.h> 24 #include <linux/cache.h> 25 #include <linux/slab.h> 26 #include "pci.h" 27 28 29 void pci_update_resource(struct pci_dev *dev, int resno) 30 { 31 struct pci_bus_region region; 32 bool disable; 33 u16 cmd; 34 u32 new, check, mask; 35 int reg; 36 enum pci_bar_type type; 37 struct resource *res = dev->resource + resno; 38 39 if (dev->is_virtfn) { 40 dev_warn(&dev->dev, "can't update VF BAR%d\n", resno); 41 return; 42 } 43 44 /* 45 * Ignore resources for unimplemented BARs and unused resource slots 46 * for 64 bit BARs. 47 */ 48 if (!res->flags) 49 return; 50 51 if (res->flags & IORESOURCE_UNSET) 52 return; 53 54 /* 55 * Ignore non-moveable resources. This might be legacy resources for 56 * which no functional BAR register exists or another important 57 * system resource we shouldn't move around. 58 */ 59 if (res->flags & IORESOURCE_PCI_FIXED) 60 return; 61 62 pcibios_resource_to_bus(dev->bus, ®ion, res); 63 64 new = region.start | (res->flags & PCI_REGION_FLAG_MASK); 65 if (res->flags & IORESOURCE_IO) 66 mask = (u32)PCI_BASE_ADDRESS_IO_MASK; 67 else 68 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; 69 70 reg = pci_resource_bar(dev, resno, &type); 71 if (!reg) 72 return; 73 if (type != pci_bar_unknown) { 74 if (!(res->flags & IORESOURCE_ROM_ENABLE)) 75 return; 76 new |= PCI_ROM_ADDRESS_ENABLE; 77 } 78 79 /* 80 * We can't update a 64-bit BAR atomically, so when possible, 81 * disable decoding so that a half-updated BAR won't conflict 82 * with another device. 83 */ 84 disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on; 85 if (disable) { 86 pci_read_config_word(dev, PCI_COMMAND, &cmd); 87 pci_write_config_word(dev, PCI_COMMAND, 88 cmd & ~PCI_COMMAND_MEMORY); 89 } 90 91 pci_write_config_dword(dev, reg, new); 92 pci_read_config_dword(dev, reg, &check); 93 94 if ((new ^ check) & mask) { 95 dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n", 96 resno, new, check); 97 } 98 99 if (res->flags & IORESOURCE_MEM_64) { 100 new = region.start >> 16 >> 16; 101 pci_write_config_dword(dev, reg + 4, new); 102 pci_read_config_dword(dev, reg + 4, &check); 103 if (check != new) { 104 dev_err(&dev->dev, "BAR %d: error updating (high %#08x != %#08x)\n", 105 resno, new, check); 106 } 107 } 108 109 if (disable) 110 pci_write_config_word(dev, PCI_COMMAND, cmd); 111 } 112 113 int pci_claim_resource(struct pci_dev *dev, int resource) 114 { 115 struct resource *res = &dev->resource[resource]; 116 struct resource *root, *conflict; 117 118 if (res->flags & IORESOURCE_UNSET) { 119 dev_info(&dev->dev, "can't claim BAR %d %pR: no address assigned\n", 120 resource, res); 121 return -EINVAL; 122 } 123 124 /* 125 * If we have a shadow copy in RAM, the PCI device doesn't respond 126 * to the shadow range, so we don't need to claim it, and upstream 127 * bridges don't need to route the range to the device. 128 */ 129 if (res->flags & IORESOURCE_ROM_SHADOW) 130 return 0; 131 132 root = pci_find_parent_resource(dev, res); 133 if (!root) { 134 dev_info(&dev->dev, "can't claim BAR %d %pR: no compatible bridge window\n", 135 resource, res); 136 res->flags |= IORESOURCE_UNSET; 137 return -EINVAL; 138 } 139 140 conflict = request_resource_conflict(root, res); 141 if (conflict) { 142 dev_info(&dev->dev, "can't claim BAR %d %pR: address conflict with %s %pR\n", 143 resource, res, conflict->name, conflict); 144 res->flags |= IORESOURCE_UNSET; 145 return -EBUSY; 146 } 147 148 return 0; 149 } 150 EXPORT_SYMBOL(pci_claim_resource); 151 152 void pci_disable_bridge_window(struct pci_dev *dev) 153 { 154 dev_info(&dev->dev, "disabling bridge mem windows\n"); 155 156 /* MMIO Base/Limit */ 157 pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0); 158 159 /* Prefetchable MMIO Base/Limit */ 160 pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0); 161 pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0); 162 pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff); 163 } 164 165 /* 166 * Generic function that returns a value indicating that the device's 167 * original BIOS BAR address was not saved and so is not available for 168 * reinstatement. 169 * 170 * Can be over-ridden by architecture specific code that implements 171 * reinstatement functionality rather than leaving it disabled when 172 * normal allocation attempts fail. 173 */ 174 resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx) 175 { 176 return 0; 177 } 178 179 static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev, 180 int resno, resource_size_t size) 181 { 182 struct resource *root, *conflict; 183 resource_size_t fw_addr, start, end; 184 185 fw_addr = pcibios_retrieve_fw_addr(dev, resno); 186 if (!fw_addr) 187 return -ENOMEM; 188 189 start = res->start; 190 end = res->end; 191 res->start = fw_addr; 192 res->end = res->start + size - 1; 193 res->flags &= ~IORESOURCE_UNSET; 194 195 root = pci_find_parent_resource(dev, res); 196 if (!root) { 197 if (res->flags & IORESOURCE_IO) 198 root = &ioport_resource; 199 else 200 root = &iomem_resource; 201 } 202 203 dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n", 204 resno, res); 205 conflict = request_resource_conflict(root, res); 206 if (conflict) { 207 dev_info(&dev->dev, "BAR %d: %pR conflicts with %s %pR\n", 208 resno, res, conflict->name, conflict); 209 res->start = start; 210 res->end = end; 211 res->flags |= IORESOURCE_UNSET; 212 return -EBUSY; 213 } 214 return 0; 215 } 216 217 static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev, 218 int resno, resource_size_t size, resource_size_t align) 219 { 220 struct resource *res = dev->resource + resno; 221 resource_size_t min; 222 int ret; 223 224 min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM; 225 226 /* 227 * First, try exact prefetching match. Even if a 64-bit 228 * prefetchable bridge window is below 4GB, we can't put a 32-bit 229 * prefetchable resource in it because pbus_size_mem() assumes a 230 * 64-bit window will contain no 32-bit resources. If we assign 231 * things differently than they were sized, not everything will fit. 232 */ 233 ret = pci_bus_alloc_resource(bus, res, size, align, min, 234 IORESOURCE_PREFETCH | IORESOURCE_MEM_64, 235 pcibios_align_resource, dev); 236 if (ret == 0) 237 return 0; 238 239 /* 240 * If the prefetchable window is only 32 bits wide, we can put 241 * 64-bit prefetchable resources in it. 242 */ 243 if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) == 244 (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) { 245 ret = pci_bus_alloc_resource(bus, res, size, align, min, 246 IORESOURCE_PREFETCH, 247 pcibios_align_resource, dev); 248 if (ret == 0) 249 return 0; 250 } 251 252 /* 253 * If we didn't find a better match, we can put any memory resource 254 * in a non-prefetchable window. If this resource is 32 bits and 255 * non-prefetchable, the first call already tried the only possibility 256 * so we don't need to try again. 257 */ 258 if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) 259 ret = pci_bus_alloc_resource(bus, res, size, align, min, 0, 260 pcibios_align_resource, dev); 261 262 return ret; 263 } 264 265 static int _pci_assign_resource(struct pci_dev *dev, int resno, 266 resource_size_t size, resource_size_t min_align) 267 { 268 struct pci_bus *bus; 269 int ret; 270 271 bus = dev->bus; 272 while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) { 273 if (!bus->parent || !bus->self->transparent) 274 break; 275 bus = bus->parent; 276 } 277 278 return ret; 279 } 280 281 int pci_assign_resource(struct pci_dev *dev, int resno) 282 { 283 struct resource *res = dev->resource + resno; 284 resource_size_t align, size; 285 int ret; 286 287 if (res->flags & IORESOURCE_PCI_FIXED) 288 return 0; 289 290 res->flags |= IORESOURCE_UNSET; 291 align = pci_resource_alignment(dev, res); 292 if (!align) { 293 dev_info(&dev->dev, "BAR %d: can't assign %pR (bogus alignment)\n", 294 resno, res); 295 return -EINVAL; 296 } 297 298 size = resource_size(res); 299 ret = _pci_assign_resource(dev, resno, size, align); 300 301 /* 302 * If we failed to assign anything, let's try the address 303 * where firmware left it. That at least has a chance of 304 * working, which is better than just leaving it disabled. 305 */ 306 if (ret < 0) { 307 dev_info(&dev->dev, "BAR %d: no space for %pR\n", resno, res); 308 ret = pci_revert_fw_address(res, dev, resno, size); 309 } 310 311 if (ret < 0) { 312 dev_info(&dev->dev, "BAR %d: failed to assign %pR\n", resno, 313 res); 314 return ret; 315 } 316 317 res->flags &= ~IORESOURCE_UNSET; 318 res->flags &= ~IORESOURCE_STARTALIGN; 319 dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res); 320 if (resno < PCI_BRIDGE_RESOURCES) 321 pci_update_resource(dev, resno); 322 323 return 0; 324 } 325 EXPORT_SYMBOL(pci_assign_resource); 326 327 int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize, 328 resource_size_t min_align) 329 { 330 struct resource *res = dev->resource + resno; 331 unsigned long flags; 332 resource_size_t new_size; 333 int ret; 334 335 if (res->flags & IORESOURCE_PCI_FIXED) 336 return 0; 337 338 flags = res->flags; 339 res->flags |= IORESOURCE_UNSET; 340 if (!res->parent) { 341 dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR\n", 342 resno, res); 343 return -EINVAL; 344 } 345 346 /* already aligned with min_align */ 347 new_size = resource_size(res) + addsize; 348 ret = _pci_assign_resource(dev, resno, new_size, min_align); 349 if (ret) { 350 res->flags = flags; 351 dev_info(&dev->dev, "BAR %d: %pR (failed to expand by %#llx)\n", 352 resno, res, (unsigned long long) addsize); 353 return ret; 354 } 355 356 res->flags &= ~IORESOURCE_UNSET; 357 res->flags &= ~IORESOURCE_STARTALIGN; 358 dev_info(&dev->dev, "BAR %d: reassigned %pR (expanded by %#llx)\n", 359 resno, res, (unsigned long long) addsize); 360 if (resno < PCI_BRIDGE_RESOURCES) 361 pci_update_resource(dev, resno); 362 363 return 0; 364 } 365 366 int pci_enable_resources(struct pci_dev *dev, int mask) 367 { 368 u16 cmd, old_cmd; 369 int i; 370 struct resource *r; 371 372 pci_read_config_word(dev, PCI_COMMAND, &cmd); 373 old_cmd = cmd; 374 375 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 376 if (!(mask & (1 << i))) 377 continue; 378 379 r = &dev->resource[i]; 380 381 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) 382 continue; 383 if ((i == PCI_ROM_RESOURCE) && 384 (!(r->flags & IORESOURCE_ROM_ENABLE))) 385 continue; 386 387 if (r->flags & IORESOURCE_UNSET) { 388 dev_err(&dev->dev, "can't enable device: BAR %d %pR not assigned\n", 389 i, r); 390 return -EINVAL; 391 } 392 393 if (!r->parent) { 394 dev_err(&dev->dev, "can't enable device: BAR %d %pR not claimed\n", 395 i, r); 396 return -EINVAL; 397 } 398 399 if (r->flags & IORESOURCE_IO) 400 cmd |= PCI_COMMAND_IO; 401 if (r->flags & IORESOURCE_MEM) 402 cmd |= PCI_COMMAND_MEMORY; 403 } 404 405 if (cmd != old_cmd) { 406 dev_info(&dev->dev, "enabling device (%04x -> %04x)\n", 407 old_cmd, cmd); 408 pci_write_config_word(dev, PCI_COMMAND, cmd); 409 } 410 return 0; 411 } 412