xref: /openbmc/linux/drivers/pci/setup-res.c (revision 8ee90c5c)
1 /*
2  *	drivers/pci/setup-res.c
3  *
4  * Extruded from code written by
5  *      Dave Rusling (david.rusling@reo.mts.dec.com)
6  *      David Mosberger (davidm@cs.arizona.edu)
7  *	David Miller (davem@redhat.com)
8  *
9  * Support routines for initializing a PCI subsystem.
10  */
11 
12 /* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
13 
14 /*
15  * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16  *	     Resource sorting
17  */
18 
19 #include <linux/kernel.h>
20 #include <linux/export.h>
21 #include <linux/pci.h>
22 #include <linux/errno.h>
23 #include <linux/ioport.h>
24 #include <linux/cache.h>
25 #include <linux/slab.h>
26 #include "pci.h"
27 
28 static void pci_std_update_resource(struct pci_dev *dev, int resno)
29 {
30 	struct pci_bus_region region;
31 	bool disable;
32 	u16 cmd;
33 	u32 new, check, mask;
34 	int reg;
35 	struct resource *res = dev->resource + resno;
36 
37 	/* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */
38 	if (dev->is_virtfn)
39 		return;
40 
41 	/*
42 	 * Ignore resources for unimplemented BARs and unused resource slots
43 	 * for 64 bit BARs.
44 	 */
45 	if (!res->flags)
46 		return;
47 
48 	if (res->flags & IORESOURCE_UNSET)
49 		return;
50 
51 	/*
52 	 * Ignore non-moveable resources.  This might be legacy resources for
53 	 * which no functional BAR register exists or another important
54 	 * system resource we shouldn't move around.
55 	 */
56 	if (res->flags & IORESOURCE_PCI_FIXED)
57 		return;
58 
59 	pcibios_resource_to_bus(dev->bus, &region, res);
60 	new = region.start;
61 
62 	if (res->flags & IORESOURCE_IO) {
63 		mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
64 		new |= res->flags & ~PCI_BASE_ADDRESS_IO_MASK;
65 	} else if (resno == PCI_ROM_RESOURCE) {
66 		mask = PCI_ROM_ADDRESS_MASK;
67 	} else {
68 		mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
69 		new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK;
70 	}
71 
72 	if (resno < PCI_ROM_RESOURCE) {
73 		reg = PCI_BASE_ADDRESS_0 + 4 * resno;
74 	} else if (resno == PCI_ROM_RESOURCE) {
75 
76 		/*
77 		 * Apparently some Matrox devices have ROM BARs that read
78 		 * as zero when disabled, so don't update ROM BARs unless
79 		 * they're enabled.  See https://lkml.org/lkml/2005/8/30/138.
80 		 */
81 		if (!(res->flags & IORESOURCE_ROM_ENABLE))
82 			return;
83 
84 		reg = dev->rom_base_reg;
85 		new |= PCI_ROM_ADDRESS_ENABLE;
86 	} else
87 		return;
88 
89 	/*
90 	 * We can't update a 64-bit BAR atomically, so when possible,
91 	 * disable decoding so that a half-updated BAR won't conflict
92 	 * with another device.
93 	 */
94 	disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
95 	if (disable) {
96 		pci_read_config_word(dev, PCI_COMMAND, &cmd);
97 		pci_write_config_word(dev, PCI_COMMAND,
98 				      cmd & ~PCI_COMMAND_MEMORY);
99 	}
100 
101 	pci_write_config_dword(dev, reg, new);
102 	pci_read_config_dword(dev, reg, &check);
103 
104 	if ((new ^ check) & mask) {
105 		dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
106 			resno, new, check);
107 	}
108 
109 	if (res->flags & IORESOURCE_MEM_64) {
110 		new = region.start >> 16 >> 16;
111 		pci_write_config_dword(dev, reg + 4, new);
112 		pci_read_config_dword(dev, reg + 4, &check);
113 		if (check != new) {
114 			dev_err(&dev->dev, "BAR %d: error updating (high %#08x != %#08x)\n",
115 				resno, new, check);
116 		}
117 	}
118 
119 	if (disable)
120 		pci_write_config_word(dev, PCI_COMMAND, cmd);
121 }
122 
123 void pci_update_resource(struct pci_dev *dev, int resno)
124 {
125 	if (resno <= PCI_ROM_RESOURCE)
126 		pci_std_update_resource(dev, resno);
127 #ifdef CONFIG_PCI_IOV
128 	else if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
129 		pci_iov_update_resource(dev, resno);
130 #endif
131 }
132 
133 int pci_claim_resource(struct pci_dev *dev, int resource)
134 {
135 	struct resource *res = &dev->resource[resource];
136 	struct resource *root, *conflict;
137 
138 	if (res->flags & IORESOURCE_UNSET) {
139 		dev_info(&dev->dev, "can't claim BAR %d %pR: no address assigned\n",
140 			 resource, res);
141 		return -EINVAL;
142 	}
143 
144 	/*
145 	 * If we have a shadow copy in RAM, the PCI device doesn't respond
146 	 * to the shadow range, so we don't need to claim it, and upstream
147 	 * bridges don't need to route the range to the device.
148 	 */
149 	if (res->flags & IORESOURCE_ROM_SHADOW)
150 		return 0;
151 
152 	root = pci_find_parent_resource(dev, res);
153 	if (!root) {
154 		dev_info(&dev->dev, "can't claim BAR %d %pR: no compatible bridge window\n",
155 			 resource, res);
156 		res->flags |= IORESOURCE_UNSET;
157 		return -EINVAL;
158 	}
159 
160 	conflict = request_resource_conflict(root, res);
161 	if (conflict) {
162 		dev_info(&dev->dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
163 			 resource, res, conflict->name, conflict);
164 		res->flags |= IORESOURCE_UNSET;
165 		return -EBUSY;
166 	}
167 
168 	return 0;
169 }
170 EXPORT_SYMBOL(pci_claim_resource);
171 
172 void pci_disable_bridge_window(struct pci_dev *dev)
173 {
174 	dev_info(&dev->dev, "disabling bridge mem windows\n");
175 
176 	/* MMIO Base/Limit */
177 	pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
178 
179 	/* Prefetchable MMIO Base/Limit */
180 	pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
181 	pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
182 	pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
183 }
184 
185 /*
186  * Generic function that returns a value indicating that the device's
187  * original BIOS BAR address was not saved and so is not available for
188  * reinstatement.
189  *
190  * Can be over-ridden by architecture specific code that implements
191  * reinstatement functionality rather than leaving it disabled when
192  * normal allocation attempts fail.
193  */
194 resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
195 {
196 	return 0;
197 }
198 
199 static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
200 		int resno, resource_size_t size)
201 {
202 	struct resource *root, *conflict;
203 	resource_size_t fw_addr, start, end;
204 
205 	fw_addr = pcibios_retrieve_fw_addr(dev, resno);
206 	if (!fw_addr)
207 		return -ENOMEM;
208 
209 	start = res->start;
210 	end = res->end;
211 	res->start = fw_addr;
212 	res->end = res->start + size - 1;
213 	res->flags &= ~IORESOURCE_UNSET;
214 
215 	root = pci_find_parent_resource(dev, res);
216 	if (!root) {
217 		if (res->flags & IORESOURCE_IO)
218 			root = &ioport_resource;
219 		else
220 			root = &iomem_resource;
221 	}
222 
223 	dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
224 		 resno, res);
225 	conflict = request_resource_conflict(root, res);
226 	if (conflict) {
227 		dev_info(&dev->dev, "BAR %d: %pR conflicts with %s %pR\n",
228 			 resno, res, conflict->name, conflict);
229 		res->start = start;
230 		res->end = end;
231 		res->flags |= IORESOURCE_UNSET;
232 		return -EBUSY;
233 	}
234 	return 0;
235 }
236 
237 /*
238  * We don't have to worry about legacy ISA devices, so nothing to do here.
239  * This is marked as __weak because multiple architectures define it; it should
240  * eventually go away.
241  */
242 resource_size_t __weak pcibios_align_resource(void *data,
243 					      const struct resource *res,
244 					      resource_size_t size,
245 					      resource_size_t align)
246 {
247        return res->start;
248 }
249 
250 static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
251 		int resno, resource_size_t size, resource_size_t align)
252 {
253 	struct resource *res = dev->resource + resno;
254 	resource_size_t min;
255 	int ret;
256 
257 	min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
258 
259 	/*
260 	 * First, try exact prefetching match.  Even if a 64-bit
261 	 * prefetchable bridge window is below 4GB, we can't put a 32-bit
262 	 * prefetchable resource in it because pbus_size_mem() assumes a
263 	 * 64-bit window will contain no 32-bit resources.  If we assign
264 	 * things differently than they were sized, not everything will fit.
265 	 */
266 	ret = pci_bus_alloc_resource(bus, res, size, align, min,
267 				     IORESOURCE_PREFETCH | IORESOURCE_MEM_64,
268 				     pcibios_align_resource, dev);
269 	if (ret == 0)
270 		return 0;
271 
272 	/*
273 	 * If the prefetchable window is only 32 bits wide, we can put
274 	 * 64-bit prefetchable resources in it.
275 	 */
276 	if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) ==
277 	     (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) {
278 		ret = pci_bus_alloc_resource(bus, res, size, align, min,
279 					     IORESOURCE_PREFETCH,
280 					     pcibios_align_resource, dev);
281 		if (ret == 0)
282 			return 0;
283 	}
284 
285 	/*
286 	 * If we didn't find a better match, we can put any memory resource
287 	 * in a non-prefetchable window.  If this resource is 32 bits and
288 	 * non-prefetchable, the first call already tried the only possibility
289 	 * so we don't need to try again.
290 	 */
291 	if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64))
292 		ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
293 					     pcibios_align_resource, dev);
294 
295 	return ret;
296 }
297 
298 static int _pci_assign_resource(struct pci_dev *dev, int resno,
299 				resource_size_t size, resource_size_t min_align)
300 {
301 	struct pci_bus *bus;
302 	int ret;
303 
304 	bus = dev->bus;
305 	while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
306 		if (!bus->parent || !bus->self->transparent)
307 			break;
308 		bus = bus->parent;
309 	}
310 
311 	return ret;
312 }
313 
314 int pci_assign_resource(struct pci_dev *dev, int resno)
315 {
316 	struct resource *res = dev->resource + resno;
317 	resource_size_t align, size;
318 	int ret;
319 
320 	if (res->flags & IORESOURCE_PCI_FIXED)
321 		return 0;
322 
323 	res->flags |= IORESOURCE_UNSET;
324 	align = pci_resource_alignment(dev, res);
325 	if (!align) {
326 		dev_info(&dev->dev, "BAR %d: can't assign %pR (bogus alignment)\n",
327 			 resno, res);
328 		return -EINVAL;
329 	}
330 
331 	size = resource_size(res);
332 	ret = _pci_assign_resource(dev, resno, size, align);
333 
334 	/*
335 	 * If we failed to assign anything, let's try the address
336 	 * where firmware left it.  That at least has a chance of
337 	 * working, which is better than just leaving it disabled.
338 	 */
339 	if (ret < 0) {
340 		dev_info(&dev->dev, "BAR %d: no space for %pR\n", resno, res);
341 		ret = pci_revert_fw_address(res, dev, resno, size);
342 	}
343 
344 	if (ret < 0) {
345 		dev_info(&dev->dev, "BAR %d: failed to assign %pR\n", resno,
346 			 res);
347 		return ret;
348 	}
349 
350 	res->flags &= ~IORESOURCE_UNSET;
351 	res->flags &= ~IORESOURCE_STARTALIGN;
352 	dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
353 	if (resno < PCI_BRIDGE_RESOURCES)
354 		pci_update_resource(dev, resno);
355 
356 	return 0;
357 }
358 EXPORT_SYMBOL(pci_assign_resource);
359 
360 int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
361 			resource_size_t min_align)
362 {
363 	struct resource *res = dev->resource + resno;
364 	unsigned long flags;
365 	resource_size_t new_size;
366 	int ret;
367 
368 	if (res->flags & IORESOURCE_PCI_FIXED)
369 		return 0;
370 
371 	flags = res->flags;
372 	res->flags |= IORESOURCE_UNSET;
373 	if (!res->parent) {
374 		dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR\n",
375 			 resno, res);
376 		return -EINVAL;
377 	}
378 
379 	/* already aligned with min_align */
380 	new_size = resource_size(res) + addsize;
381 	ret = _pci_assign_resource(dev, resno, new_size, min_align);
382 	if (ret) {
383 		res->flags = flags;
384 		dev_info(&dev->dev, "BAR %d: %pR (failed to expand by %#llx)\n",
385 			 resno, res, (unsigned long long) addsize);
386 		return ret;
387 	}
388 
389 	res->flags &= ~IORESOURCE_UNSET;
390 	res->flags &= ~IORESOURCE_STARTALIGN;
391 	dev_info(&dev->dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
392 		 resno, res, (unsigned long long) addsize);
393 	if (resno < PCI_BRIDGE_RESOURCES)
394 		pci_update_resource(dev, resno);
395 
396 	return 0;
397 }
398 
399 int pci_enable_resources(struct pci_dev *dev, int mask)
400 {
401 	u16 cmd, old_cmd;
402 	int i;
403 	struct resource *r;
404 
405 	pci_read_config_word(dev, PCI_COMMAND, &cmd);
406 	old_cmd = cmd;
407 
408 	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
409 		if (!(mask & (1 << i)))
410 			continue;
411 
412 		r = &dev->resource[i];
413 
414 		if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
415 			continue;
416 		if ((i == PCI_ROM_RESOURCE) &&
417 				(!(r->flags & IORESOURCE_ROM_ENABLE)))
418 			continue;
419 
420 		if (r->flags & IORESOURCE_UNSET) {
421 			dev_err(&dev->dev, "can't enable device: BAR %d %pR not assigned\n",
422 				i, r);
423 			return -EINVAL;
424 		}
425 
426 		if (!r->parent) {
427 			dev_err(&dev->dev, "can't enable device: BAR %d %pR not claimed\n",
428 				i, r);
429 			return -EINVAL;
430 		}
431 
432 		if (r->flags & IORESOURCE_IO)
433 			cmd |= PCI_COMMAND_IO;
434 		if (r->flags & IORESOURCE_MEM)
435 			cmd |= PCI_COMMAND_MEMORY;
436 	}
437 
438 	if (cmd != old_cmd) {
439 		dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
440 			 old_cmd, cmd);
441 		pci_write_config_word(dev, PCI_COMMAND, cmd);
442 	}
443 	return 0;
444 }
445