1 /* 2 * drivers/pci/setup-res.c 3 * 4 * Extruded from code written by 5 * Dave Rusling (david.rusling@reo.mts.dec.com) 6 * David Mosberger (davidm@cs.arizona.edu) 7 * David Miller (davem@redhat.com) 8 * 9 * Support routines for initializing a PCI subsystem. 10 */ 11 12 /* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */ 13 14 /* 15 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> 16 * Resource sorting 17 */ 18 19 #include <linux/init.h> 20 #include <linux/kernel.h> 21 #include <linux/export.h> 22 #include <linux/pci.h> 23 #include <linux/errno.h> 24 #include <linux/ioport.h> 25 #include <linux/cache.h> 26 #include <linux/slab.h> 27 #include "pci.h" 28 29 30 void pci_update_resource(struct pci_dev *dev, int resno) 31 { 32 struct pci_bus_region region; 33 u32 new, check, mask; 34 int reg; 35 enum pci_bar_type type; 36 struct resource *res = dev->resource + resno; 37 38 /* 39 * Ignore resources for unimplemented BARs and unused resource slots 40 * for 64 bit BARs. 41 */ 42 if (!res->flags) 43 return; 44 45 /* 46 * Ignore non-moveable resources. This might be legacy resources for 47 * which no functional BAR register exists or another important 48 * system resource we shouldn't move around. 49 */ 50 if (res->flags & IORESOURCE_PCI_FIXED) 51 return; 52 53 pcibios_resource_to_bus(dev, ®ion, res); 54 55 new = region.start | (res->flags & PCI_REGION_FLAG_MASK); 56 if (res->flags & IORESOURCE_IO) 57 mask = (u32)PCI_BASE_ADDRESS_IO_MASK; 58 else 59 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; 60 61 reg = pci_resource_bar(dev, resno, &type); 62 if (!reg) 63 return; 64 if (type != pci_bar_unknown) { 65 if (!(res->flags & IORESOURCE_ROM_ENABLE)) 66 return; 67 new |= PCI_ROM_ADDRESS_ENABLE; 68 } 69 70 pci_write_config_dword(dev, reg, new); 71 pci_read_config_dword(dev, reg, &check); 72 73 if ((new ^ check) & mask) { 74 dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n", 75 resno, new, check); 76 } 77 78 if (res->flags & IORESOURCE_MEM_64) { 79 new = region.start >> 16 >> 16; 80 pci_write_config_dword(dev, reg + 4, new); 81 pci_read_config_dword(dev, reg + 4, &check); 82 if (check != new) { 83 dev_err(&dev->dev, "BAR %d: error updating " 84 "(high %#08x != %#08x)\n", resno, new, check); 85 } 86 } 87 res->flags &= ~IORESOURCE_UNSET; 88 dev_dbg(&dev->dev, "BAR %d: set to %pR (PCI address [%#llx-%#llx])\n", 89 resno, res, (unsigned long long)region.start, 90 (unsigned long long)region.end); 91 } 92 93 int pci_claim_resource(struct pci_dev *dev, int resource) 94 { 95 struct resource *res = &dev->resource[resource]; 96 struct resource *root, *conflict; 97 98 root = pci_find_parent_resource(dev, res); 99 if (!root) { 100 dev_info(&dev->dev, "no compatible bridge window for %pR\n", 101 res); 102 return -EINVAL; 103 } 104 105 conflict = request_resource_conflict(root, res); 106 if (conflict) { 107 dev_info(&dev->dev, 108 "address space collision: %pR conflicts with %s %pR\n", 109 res, conflict->name, conflict); 110 return -EBUSY; 111 } 112 113 return 0; 114 } 115 EXPORT_SYMBOL(pci_claim_resource); 116 117 void pci_disable_bridge_window(struct pci_dev *dev) 118 { 119 dev_info(&dev->dev, "disabling bridge mem windows\n"); 120 121 /* MMIO Base/Limit */ 122 pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0); 123 124 /* Prefetchable MMIO Base/Limit */ 125 pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0); 126 pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0); 127 pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff); 128 } 129 130 static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev, 131 int resno, resource_size_t size, resource_size_t align) 132 { 133 struct resource *res = dev->resource + resno; 134 resource_size_t min; 135 int ret; 136 137 min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM; 138 139 /* First, try exact prefetching match.. */ 140 ret = pci_bus_alloc_resource(bus, res, size, align, min, 141 IORESOURCE_PREFETCH, 142 pcibios_align_resource, dev); 143 144 if (ret < 0 && (res->flags & IORESOURCE_PREFETCH)) { 145 /* 146 * That failed. 147 * 148 * But a prefetching area can handle a non-prefetching 149 * window (it will just not perform as well). 150 */ 151 ret = pci_bus_alloc_resource(bus, res, size, align, min, 0, 152 pcibios_align_resource, dev); 153 } 154 return ret; 155 } 156 157 /* 158 * Generic function that returns a value indicating that the device's 159 * original BIOS BAR address was not saved and so is not available for 160 * reinstatement. 161 * 162 * Can be over-ridden by architecture specific code that implements 163 * reinstatement functionality rather than leaving it disabled when 164 * normal allocation attempts fail. 165 */ 166 resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx) 167 { 168 return 0; 169 } 170 171 static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev, 172 int resno, resource_size_t size) 173 { 174 struct resource *root, *conflict; 175 resource_size_t fw_addr, start, end; 176 int ret = 0; 177 178 fw_addr = pcibios_retrieve_fw_addr(dev, resno); 179 if (!fw_addr) 180 return 1; 181 182 start = res->start; 183 end = res->end; 184 res->start = fw_addr; 185 res->end = res->start + size - 1; 186 187 root = pci_find_parent_resource(dev, res); 188 if (!root) { 189 if (res->flags & IORESOURCE_IO) 190 root = &ioport_resource; 191 else 192 root = &iomem_resource; 193 } 194 195 dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n", 196 resno, res); 197 conflict = request_resource_conflict(root, res); 198 if (conflict) { 199 dev_info(&dev->dev, 200 "BAR %d: %pR conflicts with %s %pR\n", resno, 201 res, conflict->name, conflict); 202 res->start = start; 203 res->end = end; 204 ret = 1; 205 } 206 return ret; 207 } 208 209 static int _pci_assign_resource(struct pci_dev *dev, int resno, int size, resource_size_t min_align) 210 { 211 struct resource *res = dev->resource + resno; 212 struct pci_bus *bus; 213 int ret; 214 char *type; 215 216 bus = dev->bus; 217 while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) { 218 if (!bus->parent || !bus->self->transparent) 219 break; 220 bus = bus->parent; 221 } 222 223 if (ret) { 224 if (res->flags & IORESOURCE_MEM) 225 if (res->flags & IORESOURCE_PREFETCH) 226 type = "mem pref"; 227 else 228 type = "mem"; 229 else if (res->flags & IORESOURCE_IO) 230 type = "io"; 231 else 232 type = "unknown"; 233 dev_info(&dev->dev, 234 "BAR %d: can't assign %s (size %#llx)\n", 235 resno, type, (unsigned long long) resource_size(res)); 236 } 237 238 return ret; 239 } 240 241 int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize, 242 resource_size_t min_align) 243 { 244 struct resource *res = dev->resource + resno; 245 resource_size_t new_size; 246 int ret; 247 248 if (!res->parent) { 249 dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR " 250 "\n", resno, res); 251 return -EINVAL; 252 } 253 254 /* already aligned with min_align */ 255 new_size = resource_size(res) + addsize; 256 ret = _pci_assign_resource(dev, resno, new_size, min_align); 257 if (!ret) { 258 res->flags &= ~IORESOURCE_STARTALIGN; 259 dev_info(&dev->dev, "BAR %d: reassigned %pR\n", resno, res); 260 if (resno < PCI_BRIDGE_RESOURCES) 261 pci_update_resource(dev, resno); 262 } 263 return ret; 264 } 265 266 int pci_assign_resource(struct pci_dev *dev, int resno) 267 { 268 struct resource *res = dev->resource + resno; 269 resource_size_t align, size; 270 struct pci_bus *bus; 271 int ret; 272 273 align = pci_resource_alignment(dev, res); 274 if (!align) { 275 dev_info(&dev->dev, "BAR %d: can't assign %pR " 276 "(bogus alignment)\n", resno, res); 277 return -EINVAL; 278 } 279 280 bus = dev->bus; 281 size = resource_size(res); 282 ret = _pci_assign_resource(dev, resno, size, align); 283 284 /* 285 * If we failed to assign anything, let's try the address 286 * where firmware left it. That at least has a chance of 287 * working, which is better than just leaving it disabled. 288 */ 289 if (ret < 0) 290 ret = pci_revert_fw_address(res, dev, resno, size); 291 292 if (!ret) { 293 res->flags &= ~IORESOURCE_STARTALIGN; 294 dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res); 295 if (resno < PCI_BRIDGE_RESOURCES) 296 pci_update_resource(dev, resno); 297 } 298 return ret; 299 } 300 301 int pci_enable_resources(struct pci_dev *dev, int mask) 302 { 303 u16 cmd, old_cmd; 304 int i; 305 struct resource *r; 306 307 pci_read_config_word(dev, PCI_COMMAND, &cmd); 308 old_cmd = cmd; 309 310 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 311 if (!(mask & (1 << i))) 312 continue; 313 314 r = &dev->resource[i]; 315 316 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) 317 continue; 318 if ((i == PCI_ROM_RESOURCE) && 319 (!(r->flags & IORESOURCE_ROM_ENABLE))) 320 continue; 321 322 if (!r->parent) { 323 dev_err(&dev->dev, "device not available " 324 "(can't reserve %pR)\n", r); 325 return -EINVAL; 326 } 327 328 if (r->flags & IORESOURCE_IO) 329 cmd |= PCI_COMMAND_IO; 330 if (r->flags & IORESOURCE_MEM) 331 cmd |= PCI_COMMAND_MEMORY; 332 } 333 334 if (cmd != old_cmd) { 335 dev_info(&dev->dev, "enabling device (%04x -> %04x)\n", 336 old_cmd, cmd); 337 pci_write_config_word(dev, PCI_COMMAND, cmd); 338 } 339 return 0; 340 } 341