1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Support routines for initializing a PCI subsystem 4 * 5 * Extruded from code written by 6 * Dave Rusling (david.rusling@reo.mts.dec.com) 7 * David Mosberger (davidm@cs.arizona.edu) 8 * David Miller (davem@redhat.com) 9 * 10 * Fixed for multiple PCI buses, 1999 Andrea Arcangeli <andrea@suse.de> 11 * 12 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> 13 * Resource sorting 14 */ 15 16 #include <linux/kernel.h> 17 #include <linux/export.h> 18 #include <linux/pci.h> 19 #include <linux/errno.h> 20 #include <linux/ioport.h> 21 #include <linux/cache.h> 22 #include <linux/slab.h> 23 #include "pci.h" 24 25 static void pci_std_update_resource(struct pci_dev *dev, int resno) 26 { 27 struct pci_bus_region region; 28 bool disable; 29 u16 cmd; 30 u32 new, check, mask; 31 int reg; 32 struct resource *res = dev->resource + resno; 33 34 /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */ 35 if (dev->is_virtfn) 36 return; 37 38 /* 39 * Ignore resources for unimplemented BARs and unused resource slots 40 * for 64 bit BARs. 41 */ 42 if (!res->flags) 43 return; 44 45 if (res->flags & IORESOURCE_UNSET) 46 return; 47 48 /* 49 * Ignore non-moveable resources. This might be legacy resources for 50 * which no functional BAR register exists or another important 51 * system resource we shouldn't move around. 52 */ 53 if (res->flags & IORESOURCE_PCI_FIXED) 54 return; 55 56 pcibios_resource_to_bus(dev->bus, ®ion, res); 57 new = region.start; 58 59 if (res->flags & IORESOURCE_IO) { 60 mask = (u32)PCI_BASE_ADDRESS_IO_MASK; 61 new |= res->flags & ~PCI_BASE_ADDRESS_IO_MASK; 62 } else if (resno == PCI_ROM_RESOURCE) { 63 mask = PCI_ROM_ADDRESS_MASK; 64 } else { 65 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; 66 new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK; 67 } 68 69 if (resno < PCI_ROM_RESOURCE) { 70 reg = PCI_BASE_ADDRESS_0 + 4 * resno; 71 } else if (resno == PCI_ROM_RESOURCE) { 72 73 /* 74 * Apparently some Matrox devices have ROM BARs that read 75 * as zero when disabled, so don't update ROM BARs unless 76 * they're enabled. See https://lkml.org/lkml/2005/8/30/138. 77 */ 78 if (!(res->flags & IORESOURCE_ROM_ENABLE)) 79 return; 80 81 reg = dev->rom_base_reg; 82 new |= PCI_ROM_ADDRESS_ENABLE; 83 } else 84 return; 85 86 /* 87 * We can't update a 64-bit BAR atomically, so when possible, 88 * disable decoding so that a half-updated BAR won't conflict 89 * with another device. 90 */ 91 disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on; 92 if (disable) { 93 pci_read_config_word(dev, PCI_COMMAND, &cmd); 94 pci_write_config_word(dev, PCI_COMMAND, 95 cmd & ~PCI_COMMAND_MEMORY); 96 } 97 98 pci_write_config_dword(dev, reg, new); 99 pci_read_config_dword(dev, reg, &check); 100 101 if ((new ^ check) & mask) { 102 pci_err(dev, "BAR %d: error updating (%#08x != %#08x)\n", 103 resno, new, check); 104 } 105 106 if (res->flags & IORESOURCE_MEM_64) { 107 new = region.start >> 16 >> 16; 108 pci_write_config_dword(dev, reg + 4, new); 109 pci_read_config_dword(dev, reg + 4, &check); 110 if (check != new) { 111 pci_err(dev, "BAR %d: error updating (high %#08x != %#08x)\n", 112 resno, new, check); 113 } 114 } 115 116 if (disable) 117 pci_write_config_word(dev, PCI_COMMAND, cmd); 118 } 119 120 void pci_update_resource(struct pci_dev *dev, int resno) 121 { 122 if (resno <= PCI_ROM_RESOURCE) 123 pci_std_update_resource(dev, resno); 124 #ifdef CONFIG_PCI_IOV 125 else if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) 126 pci_iov_update_resource(dev, resno); 127 #endif 128 } 129 130 int pci_claim_resource(struct pci_dev *dev, int resource) 131 { 132 struct resource *res = &dev->resource[resource]; 133 struct resource *root, *conflict; 134 135 if (res->flags & IORESOURCE_UNSET) { 136 pci_info(dev, "can't claim BAR %d %pR: no address assigned\n", 137 resource, res); 138 return -EINVAL; 139 } 140 141 /* 142 * If we have a shadow copy in RAM, the PCI device doesn't respond 143 * to the shadow range, so we don't need to claim it, and upstream 144 * bridges don't need to route the range to the device. 145 */ 146 if (res->flags & IORESOURCE_ROM_SHADOW) 147 return 0; 148 149 root = pci_find_parent_resource(dev, res); 150 if (!root) { 151 pci_info(dev, "can't claim BAR %d %pR: no compatible bridge window\n", 152 resource, res); 153 res->flags |= IORESOURCE_UNSET; 154 return -EINVAL; 155 } 156 157 conflict = request_resource_conflict(root, res); 158 if (conflict) { 159 pci_info(dev, "can't claim BAR %d %pR: address conflict with %s %pR\n", 160 resource, res, conflict->name, conflict); 161 res->flags |= IORESOURCE_UNSET; 162 return -EBUSY; 163 } 164 165 return 0; 166 } 167 EXPORT_SYMBOL(pci_claim_resource); 168 169 void pci_disable_bridge_window(struct pci_dev *dev) 170 { 171 pci_info(dev, "disabling bridge mem windows\n"); 172 173 /* MMIO Base/Limit */ 174 pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0); 175 176 /* Prefetchable MMIO Base/Limit */ 177 pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0); 178 pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0); 179 pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff); 180 } 181 182 /* 183 * Generic function that returns a value indicating that the device's 184 * original BIOS BAR address was not saved and so is not available for 185 * reinstatement. 186 * 187 * Can be over-ridden by architecture specific code that implements 188 * reinstatement functionality rather than leaving it disabled when 189 * normal allocation attempts fail. 190 */ 191 resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx) 192 { 193 return 0; 194 } 195 196 static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev, 197 int resno, resource_size_t size) 198 { 199 struct resource *root, *conflict; 200 resource_size_t fw_addr, start, end; 201 202 fw_addr = pcibios_retrieve_fw_addr(dev, resno); 203 if (!fw_addr) 204 return -ENOMEM; 205 206 start = res->start; 207 end = res->end; 208 res->start = fw_addr; 209 res->end = res->start + size - 1; 210 res->flags &= ~IORESOURCE_UNSET; 211 212 root = pci_find_parent_resource(dev, res); 213 if (!root) { 214 if (res->flags & IORESOURCE_IO) 215 root = &ioport_resource; 216 else 217 root = &iomem_resource; 218 } 219 220 pci_info(dev, "BAR %d: trying firmware assignment %pR\n", 221 resno, res); 222 conflict = request_resource_conflict(root, res); 223 if (conflict) { 224 pci_info(dev, "BAR %d: %pR conflicts with %s %pR\n", 225 resno, res, conflict->name, conflict); 226 res->start = start; 227 res->end = end; 228 res->flags |= IORESOURCE_UNSET; 229 return -EBUSY; 230 } 231 return 0; 232 } 233 234 /* 235 * We don't have to worry about legacy ISA devices, so nothing to do here. 236 * This is marked as __weak because multiple architectures define it; it should 237 * eventually go away. 238 */ 239 resource_size_t __weak pcibios_align_resource(void *data, 240 const struct resource *res, 241 resource_size_t size, 242 resource_size_t align) 243 { 244 return res->start; 245 } 246 247 static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev, 248 int resno, resource_size_t size, resource_size_t align) 249 { 250 struct resource *res = dev->resource + resno; 251 resource_size_t min; 252 int ret; 253 254 min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM; 255 256 /* 257 * First, try exact prefetching match. Even if a 64-bit 258 * prefetchable bridge window is below 4GB, we can't put a 32-bit 259 * prefetchable resource in it because pbus_size_mem() assumes a 260 * 64-bit window will contain no 32-bit resources. If we assign 261 * things differently than they were sized, not everything will fit. 262 */ 263 ret = pci_bus_alloc_resource(bus, res, size, align, min, 264 IORESOURCE_PREFETCH | IORESOURCE_MEM_64, 265 pcibios_align_resource, dev); 266 if (ret == 0) 267 return 0; 268 269 /* 270 * If the prefetchable window is only 32 bits wide, we can put 271 * 64-bit prefetchable resources in it. 272 */ 273 if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) == 274 (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) { 275 ret = pci_bus_alloc_resource(bus, res, size, align, min, 276 IORESOURCE_PREFETCH, 277 pcibios_align_resource, dev); 278 if (ret == 0) 279 return 0; 280 } 281 282 /* 283 * If we didn't find a better match, we can put any memory resource 284 * in a non-prefetchable window. If this resource is 32 bits and 285 * non-prefetchable, the first call already tried the only possibility 286 * so we don't need to try again. 287 */ 288 if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) 289 ret = pci_bus_alloc_resource(bus, res, size, align, min, 0, 290 pcibios_align_resource, dev); 291 292 return ret; 293 } 294 295 static int _pci_assign_resource(struct pci_dev *dev, int resno, 296 resource_size_t size, resource_size_t min_align) 297 { 298 struct pci_bus *bus; 299 int ret; 300 301 bus = dev->bus; 302 while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) { 303 if (!bus->parent || !bus->self->transparent) 304 break; 305 bus = bus->parent; 306 } 307 308 return ret; 309 } 310 311 int pci_assign_resource(struct pci_dev *dev, int resno) 312 { 313 struct resource *res = dev->resource + resno; 314 resource_size_t align, size; 315 int ret; 316 317 if (res->flags & IORESOURCE_PCI_FIXED) 318 return 0; 319 320 res->flags |= IORESOURCE_UNSET; 321 align = pci_resource_alignment(dev, res); 322 if (!align) { 323 pci_info(dev, "BAR %d: can't assign %pR (bogus alignment)\n", 324 resno, res); 325 return -EINVAL; 326 } 327 328 size = resource_size(res); 329 ret = _pci_assign_resource(dev, resno, size, align); 330 331 /* 332 * If we failed to assign anything, let's try the address 333 * where firmware left it. That at least has a chance of 334 * working, which is better than just leaving it disabled. 335 */ 336 if (ret < 0) { 337 pci_info(dev, "BAR %d: no space for %pR\n", resno, res); 338 ret = pci_revert_fw_address(res, dev, resno, size); 339 } 340 341 if (ret < 0) { 342 pci_info(dev, "BAR %d: failed to assign %pR\n", resno, res); 343 return ret; 344 } 345 346 res->flags &= ~IORESOURCE_UNSET; 347 res->flags &= ~IORESOURCE_STARTALIGN; 348 pci_info(dev, "BAR %d: assigned %pR\n", resno, res); 349 if (resno < PCI_BRIDGE_RESOURCES) 350 pci_update_resource(dev, resno); 351 352 return 0; 353 } 354 EXPORT_SYMBOL(pci_assign_resource); 355 356 int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize, 357 resource_size_t min_align) 358 { 359 struct resource *res = dev->resource + resno; 360 unsigned long flags; 361 resource_size_t new_size; 362 int ret; 363 364 if (res->flags & IORESOURCE_PCI_FIXED) 365 return 0; 366 367 flags = res->flags; 368 res->flags |= IORESOURCE_UNSET; 369 if (!res->parent) { 370 pci_info(dev, "BAR %d: can't reassign an unassigned resource %pR\n", 371 resno, res); 372 return -EINVAL; 373 } 374 375 /* already aligned with min_align */ 376 new_size = resource_size(res) + addsize; 377 ret = _pci_assign_resource(dev, resno, new_size, min_align); 378 if (ret) { 379 res->flags = flags; 380 pci_info(dev, "BAR %d: %pR (failed to expand by %#llx)\n", 381 resno, res, (unsigned long long) addsize); 382 return ret; 383 } 384 385 res->flags &= ~IORESOURCE_UNSET; 386 res->flags &= ~IORESOURCE_STARTALIGN; 387 pci_info(dev, "BAR %d: reassigned %pR (expanded by %#llx)\n", 388 resno, res, (unsigned long long) addsize); 389 if (resno < PCI_BRIDGE_RESOURCES) 390 pci_update_resource(dev, resno); 391 392 return 0; 393 } 394 395 void pci_release_resource(struct pci_dev *dev, int resno) 396 { 397 struct resource *res = dev->resource + resno; 398 399 pci_info(dev, "BAR %d: releasing %pR\n", resno, res); 400 401 if (!res->parent) 402 return; 403 404 release_resource(res); 405 res->end = resource_size(res) - 1; 406 res->start = 0; 407 res->flags |= IORESOURCE_UNSET; 408 } 409 EXPORT_SYMBOL(pci_release_resource); 410 411 int pci_resize_resource(struct pci_dev *dev, int resno, int size) 412 { 413 struct resource *res = dev->resource + resno; 414 int old, ret; 415 u32 sizes; 416 u16 cmd; 417 418 /* Make sure the resource isn't assigned before resizing it. */ 419 if (!(res->flags & IORESOURCE_UNSET)) 420 return -EBUSY; 421 422 pci_read_config_word(dev, PCI_COMMAND, &cmd); 423 if (cmd & PCI_COMMAND_MEMORY) 424 return -EBUSY; 425 426 sizes = pci_rebar_get_possible_sizes(dev, resno); 427 if (!sizes) 428 return -ENOTSUPP; 429 430 if (!(sizes & BIT(size))) 431 return -EINVAL; 432 433 old = pci_rebar_get_current_size(dev, resno); 434 if (old < 0) 435 return old; 436 437 ret = pci_rebar_set_size(dev, resno, size); 438 if (ret) 439 return ret; 440 441 res->end = res->start + pci_rebar_size_to_bytes(size) - 1; 442 443 /* Check if the new config works by trying to assign everything. */ 444 ret = pci_reassign_bridge_resources(dev->bus->self, res->flags); 445 if (ret) 446 goto error_resize; 447 448 return 0; 449 450 error_resize: 451 pci_rebar_set_size(dev, resno, old); 452 res->end = res->start + pci_rebar_size_to_bytes(old) - 1; 453 return ret; 454 } 455 EXPORT_SYMBOL(pci_resize_resource); 456 457 int pci_enable_resources(struct pci_dev *dev, int mask) 458 { 459 u16 cmd, old_cmd; 460 int i; 461 struct resource *r; 462 463 pci_read_config_word(dev, PCI_COMMAND, &cmd); 464 old_cmd = cmd; 465 466 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 467 if (!(mask & (1 << i))) 468 continue; 469 470 r = &dev->resource[i]; 471 472 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) 473 continue; 474 if ((i == PCI_ROM_RESOURCE) && 475 (!(r->flags & IORESOURCE_ROM_ENABLE))) 476 continue; 477 478 if (r->flags & IORESOURCE_UNSET) { 479 pci_err(dev, "can't enable device: BAR %d %pR not assigned\n", 480 i, r); 481 return -EINVAL; 482 } 483 484 if (!r->parent) { 485 pci_err(dev, "can't enable device: BAR %d %pR not claimed\n", 486 i, r); 487 return -EINVAL; 488 } 489 490 if (r->flags & IORESOURCE_IO) 491 cmd |= PCI_COMMAND_IO; 492 if (r->flags & IORESOURCE_MEM) 493 cmd |= PCI_COMMAND_MEMORY; 494 } 495 496 if (cmd != old_cmd) { 497 pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd); 498 pci_write_config_word(dev, PCI_COMMAND, cmd); 499 } 500 return 0; 501 } 502