1# SPDX-License-Identifier: GPL-2.0 2# 3# PCI Express Port Bus Configuration 4# 5config PCIEPORTBUS 6 bool "PCI Express Port Bus support" 7 depends on PCI 8 help 9 This automatically enables PCI Express Port Bus support. Users can 10 choose Native Hot-Plug support, Advanced Error Reporting support, 11 Power Management Event support and Virtual Channel support to run 12 on PCI Express Ports (Root or Switch). 13 14# 15# Include service Kconfig here 16# 17config HOTPLUG_PCI_PCIE 18 bool "PCI Express Hotplug driver" 19 depends on HOTPLUG_PCI && PCIEPORTBUS 20 help 21 Say Y here if you have a motherboard that supports PCI Express Native 22 Hotplug 23 24 When in doubt, say N. 25 26config PCIEAER 27 bool "PCI Express Advanced Error Reporting support" 28 depends on PCIEPORTBUS 29 select RAS 30 default y 31 help 32 This enables PCI Express Root Port Advanced Error Reporting 33 (AER) driver support. Error reporting messages sent to Root 34 Port will be handled by PCI Express AER driver. 35 36config PCIEAER_INJECT 37 tristate "PCI Express error injection support" 38 depends on PCIEAER 39 default n 40 help 41 This enables PCI Express Root Port Advanced Error Reporting 42 (AER) software error injector. 43 44 Debugging AER code is quite difficult because it is hard 45 to trigger various real hardware errors. Software-based 46 error injection can fake almost all kinds of errors with the 47 help of a user space helper tool aer-inject, which can be 48 gotten from: 49 http://www.kernel.org/pub/linux/utils/pci/aer-inject/ 50 51# 52# PCI Express ECRC 53# 54config PCIE_ECRC 55 bool "PCI Express ECRC settings control" 56 depends on PCIEAER 57 help 58 Used to override firmware/bios settings for PCI Express ECRC 59 (transaction layer end-to-end CRC checking). 60 61 When in doubt, say N. 62 63# 64# PCI Express ASPM 65# 66config PCIEASPM 67 bool "PCI Express ASPM control" if EXPERT 68 depends on PCI && PCIEPORTBUS 69 default y 70 help 71 This enables OS control over PCI Express ASPM (Active State 72 Power Management) and Clock Power Management. ASPM supports 73 state L0/L0s/L1. 74 75 ASPM is initially set up by the firmware. With this option enabled, 76 Linux can modify this state in order to disable ASPM on known-bad 77 hardware or configurations and enable it when known-safe. 78 79 ASPM can be disabled or enabled at runtime via 80 /sys/module/pcie_aspm/parameters/policy 81 82 When in doubt, say Y. 83 84config PCIEASPM_DEBUG 85 bool "Debug PCI Express ASPM" 86 depends on PCIEASPM 87 default n 88 help 89 This enables PCI Express ASPM debug support. It will add per-device 90 interface to control ASPM. 91 92choice 93 prompt "Default ASPM policy" 94 default PCIEASPM_DEFAULT 95 depends on PCIEASPM 96 97config PCIEASPM_DEFAULT 98 bool "BIOS default" 99 depends on PCIEASPM 100 help 101 Use the BIOS defaults for PCI Express ASPM. 102 103config PCIEASPM_POWERSAVE 104 bool "Powersave" 105 depends on PCIEASPM 106 help 107 Enable PCI Express ASPM L0s and L1 where possible, even if the 108 BIOS did not. 109 110config PCIEASPM_POWER_SUPERSAVE 111 bool "Power Supersave" 112 depends on PCIEASPM 113 help 114 Same as PCIEASPM_POWERSAVE, except it also enables L1 substates where 115 possible. This would result in higher power savings while staying in L1 116 where the components support it. 117 118config PCIEASPM_PERFORMANCE 119 bool "Performance" 120 depends on PCIEASPM 121 help 122 Disable PCI Express ASPM L0s and L1, even if the BIOS enabled them. 123endchoice 124 125config PCIE_PME 126 def_bool y 127 depends on PCIEPORTBUS && PM 128 129config PCIE_DPC 130 bool "PCI Express Downstream Port Containment support" 131 depends on PCIEPORTBUS && PCIEAER 132 default n 133 help 134 This enables PCI Express Downstream Port Containment (DPC) 135 driver support. DPC events from Root and Downstream ports 136 will be handled by the DPC driver. If your system doesn't 137 have this capability or you do not want to use this feature, 138 it is safe to answer N. 139 140config PCIE_PTM 141 bool "PCI Express Precision Time Measurement support" 142 default n 143 depends on PCIEPORTBUS 144 help 145 This enables PCI Express Precision Time Measurement (PTM) 146 support. 147 148 This is only useful if you have devices that support PTM, but it 149 is safe to enable even if you don't. 150