1 /* 2 * Copyright (c) 2011-2014, Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 */ 13 14 #ifndef _NVME_H 15 #define _NVME_H 16 17 #include <linux/nvme.h> 18 #include <linux/cdev.h> 19 #include <linux/pci.h> 20 #include <linux/kref.h> 21 #include <linux/blk-mq.h> 22 #include <linux/lightnvm.h> 23 #include <linux/sed-opal.h> 24 25 extern unsigned int nvme_io_timeout; 26 #define NVME_IO_TIMEOUT (nvme_io_timeout * HZ) 27 28 extern unsigned int admin_timeout; 29 #define ADMIN_TIMEOUT (admin_timeout * HZ) 30 31 #define NVME_DEFAULT_KATO 5 32 #define NVME_KATO_GRACE 10 33 34 extern struct workqueue_struct *nvme_wq; 35 36 enum { 37 NVME_NS_LBA = 0, 38 NVME_NS_LIGHTNVM = 1, 39 }; 40 41 /* 42 * List of workarounds for devices that required behavior not specified in 43 * the standard. 44 */ 45 enum nvme_quirks { 46 /* 47 * Prefers I/O aligned to a stripe size specified in a vendor 48 * specific Identify field. 49 */ 50 NVME_QUIRK_STRIPE_SIZE = (1 << 0), 51 52 /* 53 * The controller doesn't handle Identify value others than 0 or 1 54 * correctly. 55 */ 56 NVME_QUIRK_IDENTIFY_CNS = (1 << 1), 57 58 /* 59 * The controller deterministically returns O's on reads to 60 * logical blocks that deallocate was called on. 61 */ 62 NVME_QUIRK_DEALLOCATE_ZEROES = (1 << 2), 63 64 /* 65 * The controller needs a delay before starts checking the device 66 * readiness, which is done by reading the NVME_CSTS_RDY bit. 67 */ 68 NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3), 69 70 /* 71 * APST should not be used. 72 */ 73 NVME_QUIRK_NO_APST = (1 << 4), 74 75 /* 76 * The deepest sleep state should not be used. 77 */ 78 NVME_QUIRK_NO_DEEPEST_PS = (1 << 5), 79 80 /* 81 * Supports the LighNVM command set if indicated in vs[1]. 82 */ 83 NVME_QUIRK_LIGHTNVM = (1 << 6), 84 }; 85 86 /* 87 * Common request structure for NVMe passthrough. All drivers must have 88 * this structure as the first member of their request-private data. 89 */ 90 struct nvme_request { 91 struct nvme_command *cmd; 92 union nvme_result result; 93 u8 retries; 94 u8 flags; 95 u16 status; 96 }; 97 98 enum { 99 NVME_REQ_CANCELLED = (1 << 0), 100 }; 101 102 static inline struct nvme_request *nvme_req(struct request *req) 103 { 104 return blk_mq_rq_to_pdu(req); 105 } 106 107 /* The below value is the specific amount of delay needed before checking 108 * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the 109 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was 110 * found empirically. 111 */ 112 #define NVME_QUIRK_DELAY_AMOUNT 2000 113 114 enum nvme_ctrl_state { 115 NVME_CTRL_NEW, 116 NVME_CTRL_LIVE, 117 NVME_CTRL_RESETTING, 118 NVME_CTRL_RECONNECTING, 119 NVME_CTRL_DELETING, 120 NVME_CTRL_DEAD, 121 }; 122 123 struct nvme_ctrl { 124 enum nvme_ctrl_state state; 125 bool identified; 126 spinlock_t lock; 127 const struct nvme_ctrl_ops *ops; 128 struct request_queue *admin_q; 129 struct request_queue *connect_q; 130 struct device *dev; 131 int instance; 132 struct blk_mq_tag_set *tagset; 133 struct blk_mq_tag_set *admin_tagset; 134 struct list_head namespaces; 135 struct mutex namespaces_mutex; 136 struct device ctrl_device; 137 struct device *device; /* char device */ 138 struct cdev cdev; 139 struct ida ns_ida; 140 struct work_struct reset_work; 141 struct work_struct delete_work; 142 143 struct nvme_subsystem *subsys; 144 struct list_head subsys_entry; 145 146 struct opal_dev *opal_dev; 147 148 char name[12]; 149 u16 cntlid; 150 151 u32 ctrl_config; 152 u16 mtfa; 153 u32 queue_count; 154 155 u64 cap; 156 u32 page_size; 157 u32 max_hw_sectors; 158 u16 oncs; 159 u16 oacs; 160 u16 nssa; 161 u16 nr_streams; 162 atomic_t abort_limit; 163 u8 vwc; 164 u32 vs; 165 u32 sgls; 166 u16 kas; 167 u8 npss; 168 u8 apsta; 169 u32 aen_result; 170 unsigned int shutdown_timeout; 171 unsigned int kato; 172 bool subsystem; 173 unsigned long quirks; 174 struct nvme_id_power_state psd[32]; 175 struct nvme_effects_log *effects; 176 struct work_struct scan_work; 177 struct work_struct async_event_work; 178 struct delayed_work ka_work; 179 struct work_struct fw_act_work; 180 181 /* Power saving configuration */ 182 u64 ps_max_latency_us; 183 bool apst_enabled; 184 185 /* PCIe only: */ 186 u32 hmpre; 187 u32 hmmin; 188 u32 hmminds; 189 u16 hmmaxd; 190 191 /* Fabrics only */ 192 u16 sqsize; 193 u32 ioccsz; 194 u32 iorcsz; 195 u16 icdoff; 196 u16 maxcmd; 197 int nr_reconnects; 198 struct nvmf_ctrl_options *opts; 199 }; 200 201 struct nvme_subsystem { 202 int instance; 203 struct device dev; 204 /* 205 * Because we unregister the device on the last put we need 206 * a separate refcount. 207 */ 208 struct kref ref; 209 struct list_head entry; 210 struct mutex lock; 211 struct list_head ctrls; 212 char subnqn[NVMF_NQN_SIZE]; 213 char serial[20]; 214 char model[40]; 215 char firmware_rev[8]; 216 u8 cmic; 217 u16 vendor_id; 218 }; 219 220 struct nvme_ns { 221 struct list_head list; 222 223 struct nvme_ctrl *ctrl; 224 struct request_queue *queue; 225 struct gendisk *disk; 226 struct nvm_dev *ndev; 227 struct kref kref; 228 int instance; 229 230 u8 eui[8]; 231 u8 nguid[16]; 232 uuid_t uuid; 233 234 unsigned ns_id; 235 int lba_shift; 236 u16 ms; 237 u16 sgs; 238 u32 sws; 239 bool ext; 240 u8 pi_type; 241 unsigned long flags; 242 #define NVME_NS_REMOVING 0 243 #define NVME_NS_DEAD 1 244 u16 noiob; 245 }; 246 247 struct nvme_ctrl_ops { 248 const char *name; 249 struct module *module; 250 unsigned int flags; 251 #define NVME_F_FABRICS (1 << 0) 252 #define NVME_F_METADATA_SUPPORTED (1 << 1) 253 int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val); 254 int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val); 255 int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val); 256 void (*free_ctrl)(struct nvme_ctrl *ctrl); 257 void (*submit_async_event)(struct nvme_ctrl *ctrl); 258 void (*delete_ctrl)(struct nvme_ctrl *ctrl); 259 int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size); 260 int (*reinit_request)(void *data, struct request *rq); 261 }; 262 263 static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl) 264 { 265 u32 val = 0; 266 267 if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val)) 268 return false; 269 return val & NVME_CSTS_RDY; 270 } 271 272 static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl) 273 { 274 if (!ctrl->subsystem) 275 return -ENOTTY; 276 return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65); 277 } 278 279 static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector) 280 { 281 return (sector >> (ns->lba_shift - 9)); 282 } 283 284 static inline void nvme_cleanup_cmd(struct request *req) 285 { 286 if (req->rq_flags & RQF_SPECIAL_PAYLOAD) { 287 kfree(page_address(req->special_vec.bv_page) + 288 req->special_vec.bv_offset); 289 } 290 } 291 292 static inline void nvme_end_request(struct request *req, __le16 status, 293 union nvme_result result) 294 { 295 struct nvme_request *rq = nvme_req(req); 296 297 rq->status = le16_to_cpu(status) >> 1; 298 rq->result = result; 299 blk_mq_complete_request(req); 300 } 301 302 static inline void nvme_get_ctrl(struct nvme_ctrl *ctrl) 303 { 304 get_device(ctrl->device); 305 } 306 307 static inline void nvme_put_ctrl(struct nvme_ctrl *ctrl) 308 { 309 put_device(ctrl->device); 310 } 311 312 void nvme_complete_rq(struct request *req); 313 void nvme_cancel_request(struct request *req, void *data, bool reserved); 314 bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl, 315 enum nvme_ctrl_state new_state); 316 int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap); 317 int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap); 318 int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl); 319 int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev, 320 const struct nvme_ctrl_ops *ops, unsigned long quirks); 321 void nvme_uninit_ctrl(struct nvme_ctrl *ctrl); 322 void nvme_start_ctrl(struct nvme_ctrl *ctrl); 323 void nvme_stop_ctrl(struct nvme_ctrl *ctrl); 324 void nvme_put_ctrl(struct nvme_ctrl *ctrl); 325 int nvme_init_identify(struct nvme_ctrl *ctrl); 326 327 void nvme_queue_scan(struct nvme_ctrl *ctrl); 328 void nvme_remove_namespaces(struct nvme_ctrl *ctrl); 329 330 int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len, 331 bool send); 332 333 void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status, 334 union nvme_result *res); 335 336 void nvme_stop_queues(struct nvme_ctrl *ctrl); 337 void nvme_start_queues(struct nvme_ctrl *ctrl); 338 void nvme_kill_queues(struct nvme_ctrl *ctrl); 339 void nvme_unfreeze(struct nvme_ctrl *ctrl); 340 void nvme_wait_freeze(struct nvme_ctrl *ctrl); 341 void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout); 342 void nvme_start_freeze(struct nvme_ctrl *ctrl); 343 int nvme_reinit_tagset(struct nvme_ctrl *ctrl, struct blk_mq_tag_set *set); 344 345 #define NVME_QID_ANY -1 346 struct request *nvme_alloc_request(struct request_queue *q, 347 struct nvme_command *cmd, blk_mq_req_flags_t flags, int qid); 348 blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req, 349 struct nvme_command *cmd); 350 int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, 351 void *buf, unsigned bufflen); 352 int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, 353 union nvme_result *result, void *buffer, unsigned bufflen, 354 unsigned timeout, int qid, int at_head, 355 blk_mq_req_flags_t flags); 356 int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count); 357 void nvme_start_keep_alive(struct nvme_ctrl *ctrl); 358 void nvme_stop_keep_alive(struct nvme_ctrl *ctrl); 359 int nvme_reset_ctrl(struct nvme_ctrl *ctrl); 360 int nvme_delete_ctrl(struct nvme_ctrl *ctrl); 361 int nvme_delete_ctrl_sync(struct nvme_ctrl *ctrl); 362 363 #ifdef CONFIG_NVM 364 int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, int node); 365 void nvme_nvm_unregister(struct nvme_ns *ns); 366 int nvme_nvm_register_sysfs(struct nvme_ns *ns); 367 void nvme_nvm_unregister_sysfs(struct nvme_ns *ns); 368 int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, unsigned long arg); 369 #else 370 static inline int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, 371 int node) 372 { 373 return 0; 374 } 375 376 static inline void nvme_nvm_unregister(struct nvme_ns *ns) {}; 377 static inline int nvme_nvm_register_sysfs(struct nvme_ns *ns) 378 { 379 return 0; 380 } 381 static inline void nvme_nvm_unregister_sysfs(struct nvme_ns *ns) {}; 382 static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, 383 unsigned long arg) 384 { 385 return -ENOTTY; 386 } 387 #endif /* CONFIG_NVM */ 388 389 static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev) 390 { 391 return dev_to_disk(dev)->private_data; 392 } 393 394 int __init nvme_core_init(void); 395 void nvme_core_exit(void); 396 397 #endif /* _NVME_H */ 398