1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2011-2014, Intel Corporation. 4 */ 5 6 #ifndef _NVME_H 7 #define _NVME_H 8 9 #include <linux/nvme.h> 10 #include <linux/cdev.h> 11 #include <linux/pci.h> 12 #include <linux/kref.h> 13 #include <linux/blk-mq.h> 14 #include <linux/sed-opal.h> 15 #include <linux/fault-inject.h> 16 #include <linux/rcupdate.h> 17 #include <linux/wait.h> 18 #include <linux/t10-pi.h> 19 20 #include <trace/events/block.h> 21 22 extern const struct pr_ops nvme_pr_ops; 23 24 extern unsigned int nvme_io_timeout; 25 #define NVME_IO_TIMEOUT (nvme_io_timeout * HZ) 26 27 extern unsigned int admin_timeout; 28 #define NVME_ADMIN_TIMEOUT (admin_timeout * HZ) 29 30 #define NVME_DEFAULT_KATO 5 31 32 #ifdef CONFIG_ARCH_NO_SG_CHAIN 33 #define NVME_INLINE_SG_CNT 0 34 #define NVME_INLINE_METADATA_SG_CNT 0 35 #else 36 #define NVME_INLINE_SG_CNT 2 37 #define NVME_INLINE_METADATA_SG_CNT 1 38 #endif 39 40 /* 41 * Default to a 4K page size, with the intention to update this 42 * path in the future to accommodate architectures with differing 43 * kernel and IO page sizes. 44 */ 45 #define NVME_CTRL_PAGE_SHIFT 12 46 #define NVME_CTRL_PAGE_SIZE (1 << NVME_CTRL_PAGE_SHIFT) 47 48 extern struct workqueue_struct *nvme_wq; 49 extern struct workqueue_struct *nvme_reset_wq; 50 extern struct workqueue_struct *nvme_delete_wq; 51 52 /* 53 * List of workarounds for devices that required behavior not specified in 54 * the standard. 55 */ 56 enum nvme_quirks { 57 /* 58 * Prefers I/O aligned to a stripe size specified in a vendor 59 * specific Identify field. 60 */ 61 NVME_QUIRK_STRIPE_SIZE = (1 << 0), 62 63 /* 64 * The controller doesn't handle Identify value others than 0 or 1 65 * correctly. 66 */ 67 NVME_QUIRK_IDENTIFY_CNS = (1 << 1), 68 69 /* 70 * The controller deterministically returns O's on reads to 71 * logical blocks that deallocate was called on. 72 */ 73 NVME_QUIRK_DEALLOCATE_ZEROES = (1 << 2), 74 75 /* 76 * The controller needs a delay before starts checking the device 77 * readiness, which is done by reading the NVME_CSTS_RDY bit. 78 */ 79 NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3), 80 81 /* 82 * APST should not be used. 83 */ 84 NVME_QUIRK_NO_APST = (1 << 4), 85 86 /* 87 * The deepest sleep state should not be used. 88 */ 89 NVME_QUIRK_NO_DEEPEST_PS = (1 << 5), 90 91 /* 92 * Set MEDIUM priority on SQ creation 93 */ 94 NVME_QUIRK_MEDIUM_PRIO_SQ = (1 << 7), 95 96 /* 97 * Ignore device provided subnqn. 98 */ 99 NVME_QUIRK_IGNORE_DEV_SUBNQN = (1 << 8), 100 101 /* 102 * Broken Write Zeroes. 103 */ 104 NVME_QUIRK_DISABLE_WRITE_ZEROES = (1 << 9), 105 106 /* 107 * Force simple suspend/resume path. 108 */ 109 NVME_QUIRK_SIMPLE_SUSPEND = (1 << 10), 110 111 /* 112 * Use only one interrupt vector for all queues 113 */ 114 NVME_QUIRK_SINGLE_VECTOR = (1 << 11), 115 116 /* 117 * Use non-standard 128 bytes SQEs. 118 */ 119 NVME_QUIRK_128_BYTES_SQES = (1 << 12), 120 121 /* 122 * Prevent tag overlap between queues 123 */ 124 NVME_QUIRK_SHARED_TAGS = (1 << 13), 125 126 /* 127 * Don't change the value of the temperature threshold feature 128 */ 129 NVME_QUIRK_NO_TEMP_THRESH_CHANGE = (1 << 14), 130 131 /* 132 * The controller doesn't handle the Identify Namespace 133 * Identification Descriptor list subcommand despite claiming 134 * NVMe 1.3 compliance. 135 */ 136 NVME_QUIRK_NO_NS_DESC_LIST = (1 << 15), 137 138 /* 139 * The controller does not properly handle DMA addresses over 140 * 48 bits. 141 */ 142 NVME_QUIRK_DMA_ADDRESS_BITS_48 = (1 << 16), 143 144 /* 145 * The controller requires the command_id value be limited, so skip 146 * encoding the generation sequence number. 147 */ 148 NVME_QUIRK_SKIP_CID_GEN = (1 << 17), 149 150 /* 151 * Reports garbage in the namespace identifiers (eui64, nguid, uuid). 152 */ 153 NVME_QUIRK_BOGUS_NID = (1 << 18), 154 155 /* 156 * No temperature thresholds for channels other than 0 (Composite). 157 */ 158 NVME_QUIRK_NO_SECONDARY_TEMP_THRESH = (1 << 19), 159 160 /* 161 * Disables simple suspend/resume path. 162 */ 163 NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND = (1 << 20), 164 165 /* 166 * MSI (but not MSI-X) interrupts are broken and never fire. 167 */ 168 NVME_QUIRK_BROKEN_MSI = (1 << 21), 169 }; 170 171 /* 172 * Common request structure for NVMe passthrough. All drivers must have 173 * this structure as the first member of their request-private data. 174 */ 175 struct nvme_request { 176 struct nvme_command *cmd; 177 union nvme_result result; 178 u8 genctr; 179 u8 retries; 180 u8 flags; 181 u16 status; 182 #ifdef CONFIG_NVME_MULTIPATH 183 unsigned long start_time; 184 #endif 185 struct nvme_ctrl *ctrl; 186 }; 187 188 /* 189 * Mark a bio as coming in through the mpath node. 190 */ 191 #define REQ_NVME_MPATH REQ_DRV 192 193 enum { 194 NVME_REQ_CANCELLED = (1 << 0), 195 NVME_REQ_USERCMD = (1 << 1), 196 NVME_MPATH_IO_STATS = (1 << 2), 197 }; 198 199 static inline struct nvme_request *nvme_req(struct request *req) 200 { 201 return blk_mq_rq_to_pdu(req); 202 } 203 204 static inline u16 nvme_req_qid(struct request *req) 205 { 206 if (!req->q->queuedata) 207 return 0; 208 209 return req->mq_hctx->queue_num + 1; 210 } 211 212 /* The below value is the specific amount of delay needed before checking 213 * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the 214 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was 215 * found empirically. 216 */ 217 #define NVME_QUIRK_DELAY_AMOUNT 2300 218 219 /* 220 * enum nvme_ctrl_state: Controller state 221 * 222 * @NVME_CTRL_NEW: New controller just allocated, initial state 223 * @NVME_CTRL_LIVE: Controller is connected and I/O capable 224 * @NVME_CTRL_RESETTING: Controller is resetting (or scheduled reset) 225 * @NVME_CTRL_CONNECTING: Controller is disconnected, now connecting the 226 * transport 227 * @NVME_CTRL_DELETING: Controller is deleting (or scheduled deletion) 228 * @NVME_CTRL_DELETING_NOIO: Controller is deleting and I/O is not 229 * disabled/failed immediately. This state comes 230 * after all async event processing took place and 231 * before ns removal and the controller deletion 232 * progress 233 * @NVME_CTRL_DEAD: Controller is non-present/unresponsive during 234 * shutdown or removal. In this case we forcibly 235 * kill all inflight I/O as they have no chance to 236 * complete 237 */ 238 enum nvme_ctrl_state { 239 NVME_CTRL_NEW, 240 NVME_CTRL_LIVE, 241 NVME_CTRL_RESETTING, 242 NVME_CTRL_CONNECTING, 243 NVME_CTRL_DELETING, 244 NVME_CTRL_DELETING_NOIO, 245 NVME_CTRL_DEAD, 246 }; 247 248 struct nvme_fault_inject { 249 #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS 250 struct fault_attr attr; 251 struct dentry *parent; 252 bool dont_retry; /* DNR, do not retry */ 253 u16 status; /* status code */ 254 #endif 255 }; 256 257 enum nvme_ctrl_flags { 258 NVME_CTRL_FAILFAST_EXPIRED = 0, 259 NVME_CTRL_ADMIN_Q_STOPPED = 1, 260 NVME_CTRL_STARTED_ONCE = 2, 261 NVME_CTRL_STOPPED = 3, 262 NVME_CTRL_SKIP_ID_CNS_CS = 4, 263 NVME_CTRL_DIRTY_CAPABILITY = 5, 264 NVME_CTRL_FROZEN = 6, 265 }; 266 267 struct nvme_ctrl { 268 bool comp_seen; 269 bool identified; 270 enum nvme_ctrl_state state; 271 spinlock_t lock; 272 struct mutex scan_lock; 273 const struct nvme_ctrl_ops *ops; 274 struct request_queue *admin_q; 275 struct request_queue *connect_q; 276 struct request_queue *fabrics_q; 277 struct device *dev; 278 int instance; 279 int numa_node; 280 struct blk_mq_tag_set *tagset; 281 struct blk_mq_tag_set *admin_tagset; 282 struct list_head namespaces; 283 struct rw_semaphore namespaces_rwsem; 284 struct device ctrl_device; 285 struct device *device; /* char device */ 286 #ifdef CONFIG_NVME_HWMON 287 struct device *hwmon_device; 288 #endif 289 struct cdev cdev; 290 struct work_struct reset_work; 291 struct work_struct delete_work; 292 wait_queue_head_t state_wq; 293 294 struct nvme_subsystem *subsys; 295 struct list_head subsys_entry; 296 297 struct opal_dev *opal_dev; 298 299 char name[12]; 300 u16 cntlid; 301 302 u16 mtfa; 303 u32 ctrl_config; 304 u32 queue_count; 305 306 u64 cap; 307 u32 max_hw_sectors; 308 u32 max_segments; 309 u32 max_integrity_segments; 310 u32 max_discard_sectors; 311 u32 max_discard_segments; 312 u32 max_zeroes_sectors; 313 #ifdef CONFIG_BLK_DEV_ZONED 314 u32 max_zone_append; 315 #endif 316 u16 crdt[3]; 317 u16 oncs; 318 u32 dmrsl; 319 u16 oacs; 320 u16 sqsize; 321 u32 max_namespaces; 322 atomic_t abort_limit; 323 u8 vwc; 324 u32 vs; 325 u32 sgls; 326 u16 kas; 327 u8 npss; 328 u8 apsta; 329 u16 wctemp; 330 u16 cctemp; 331 u32 oaes; 332 u32 aen_result; 333 u32 ctratt; 334 unsigned int shutdown_timeout; 335 unsigned int kato; 336 bool subsystem; 337 unsigned long quirks; 338 struct nvme_id_power_state psd[32]; 339 struct nvme_effects_log *effects; 340 struct xarray cels; 341 struct work_struct scan_work; 342 struct work_struct async_event_work; 343 struct delayed_work ka_work; 344 struct delayed_work failfast_work; 345 struct nvme_command ka_cmd; 346 unsigned long ka_last_check_time; 347 struct work_struct fw_act_work; 348 unsigned long events; 349 350 #ifdef CONFIG_NVME_MULTIPATH 351 /* asymmetric namespace access: */ 352 u8 anacap; 353 u8 anatt; 354 u32 anagrpmax; 355 u32 nanagrpid; 356 struct mutex ana_lock; 357 struct nvme_ana_rsp_hdr *ana_log_buf; 358 size_t ana_log_size; 359 struct timer_list anatt_timer; 360 struct work_struct ana_work; 361 #endif 362 363 #ifdef CONFIG_NVME_AUTH 364 struct work_struct dhchap_auth_work; 365 struct mutex dhchap_auth_mutex; 366 struct nvme_dhchap_queue_context *dhchap_ctxs; 367 struct nvme_dhchap_key *host_key; 368 struct nvme_dhchap_key *ctrl_key; 369 u16 transaction; 370 #endif 371 372 /* Power saving configuration */ 373 u64 ps_max_latency_us; 374 bool apst_enabled; 375 376 /* PCIe only: */ 377 u16 hmmaxd; 378 u32 hmpre; 379 u32 hmmin; 380 u32 hmminds; 381 382 /* Fabrics only */ 383 u32 ioccsz; 384 u32 iorcsz; 385 u16 icdoff; 386 u16 maxcmd; 387 int nr_reconnects; 388 unsigned long flags; 389 struct nvmf_ctrl_options *opts; 390 391 struct page *discard_page; 392 unsigned long discard_page_busy; 393 394 struct nvme_fault_inject fault_inject; 395 396 enum nvme_ctrl_type cntrltype; 397 enum nvme_dctype dctype; 398 }; 399 400 static inline enum nvme_ctrl_state nvme_ctrl_state(struct nvme_ctrl *ctrl) 401 { 402 return READ_ONCE(ctrl->state); 403 } 404 405 enum nvme_iopolicy { 406 NVME_IOPOLICY_NUMA, 407 NVME_IOPOLICY_RR, 408 }; 409 410 struct nvme_subsystem { 411 int instance; 412 struct device dev; 413 /* 414 * Because we unregister the device on the last put we need 415 * a separate refcount. 416 */ 417 struct kref ref; 418 struct list_head entry; 419 struct mutex lock; 420 struct list_head ctrls; 421 struct list_head nsheads; 422 char subnqn[NVMF_NQN_SIZE]; 423 char serial[20]; 424 char model[40]; 425 char firmware_rev[8]; 426 u8 cmic; 427 enum nvme_subsys_type subtype; 428 u16 vendor_id; 429 u16 awupf; /* 0's based awupf value. */ 430 struct ida ns_ida; 431 #ifdef CONFIG_NVME_MULTIPATH 432 enum nvme_iopolicy iopolicy; 433 #endif 434 }; 435 436 /* 437 * Container structure for uniqueue namespace identifiers. 438 */ 439 struct nvme_ns_ids { 440 u8 eui64[8]; 441 u8 nguid[16]; 442 uuid_t uuid; 443 u8 csi; 444 }; 445 446 /* 447 * Anchor structure for namespaces. There is one for each namespace in a 448 * NVMe subsystem that any of our controllers can see, and the namespace 449 * structure for each controller is chained of it. For private namespaces 450 * there is a 1:1 relation to our namespace structures, that is ->list 451 * only ever has a single entry for private namespaces. 452 */ 453 struct nvme_ns_head { 454 struct list_head list; 455 struct srcu_struct srcu; 456 struct nvme_subsystem *subsys; 457 unsigned ns_id; 458 struct nvme_ns_ids ids; 459 struct list_head entry; 460 struct kref ref; 461 bool shared; 462 int instance; 463 struct nvme_effects_log *effects; 464 465 struct cdev cdev; 466 struct device cdev_device; 467 468 struct gendisk *disk; 469 #ifdef CONFIG_NVME_MULTIPATH 470 struct bio_list requeue_list; 471 spinlock_t requeue_lock; 472 struct work_struct requeue_work; 473 struct mutex lock; 474 unsigned long flags; 475 #define NVME_NSHEAD_DISK_LIVE 0 476 struct nvme_ns __rcu *current_path[]; 477 #endif 478 }; 479 480 static inline bool nvme_ns_head_multipath(struct nvme_ns_head *head) 481 { 482 return IS_ENABLED(CONFIG_NVME_MULTIPATH) && head->disk; 483 } 484 485 enum nvme_ns_features { 486 NVME_NS_EXT_LBAS = 1 << 0, /* support extended LBA format */ 487 NVME_NS_METADATA_SUPPORTED = 1 << 1, /* support getting generated md */ 488 NVME_NS_DEAC, /* DEAC bit in Write Zeores supported */ 489 }; 490 491 struct nvme_ns { 492 struct list_head list; 493 494 struct nvme_ctrl *ctrl; 495 struct request_queue *queue; 496 struct gendisk *disk; 497 #ifdef CONFIG_NVME_MULTIPATH 498 enum nvme_ana_state ana_state; 499 u32 ana_grpid; 500 #endif 501 struct list_head siblings; 502 struct kref kref; 503 struct nvme_ns_head *head; 504 505 int lba_shift; 506 u16 ms; 507 u16 pi_size; 508 u16 sgs; 509 u32 sws; 510 u8 pi_type; 511 u8 guard_type; 512 #ifdef CONFIG_BLK_DEV_ZONED 513 u64 zsze; 514 #endif 515 unsigned long features; 516 unsigned long flags; 517 #define NVME_NS_REMOVING 0 518 #define NVME_NS_ANA_PENDING 2 519 #define NVME_NS_FORCE_RO 3 520 #define NVME_NS_READY 4 521 522 struct cdev cdev; 523 struct device cdev_device; 524 525 struct nvme_fault_inject fault_inject; 526 527 }; 528 529 /* NVMe ns supports metadata actions by the controller (generate/strip) */ 530 static inline bool nvme_ns_has_pi(struct nvme_ns *ns) 531 { 532 return ns->pi_type && ns->ms == ns->pi_size; 533 } 534 535 struct nvme_ctrl_ops { 536 const char *name; 537 struct module *module; 538 unsigned int flags; 539 #define NVME_F_FABRICS (1 << 0) 540 #define NVME_F_METADATA_SUPPORTED (1 << 1) 541 #define NVME_F_BLOCKING (1 << 2) 542 543 const struct attribute_group **dev_attr_groups; 544 int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val); 545 int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val); 546 int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val); 547 void (*free_ctrl)(struct nvme_ctrl *ctrl); 548 void (*submit_async_event)(struct nvme_ctrl *ctrl); 549 void (*delete_ctrl)(struct nvme_ctrl *ctrl); 550 void (*stop_ctrl)(struct nvme_ctrl *ctrl); 551 int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size); 552 void (*print_device_info)(struct nvme_ctrl *ctrl); 553 bool (*supports_pci_p2pdma)(struct nvme_ctrl *ctrl); 554 }; 555 556 /* 557 * nvme command_id is constructed as such: 558 * | xxxx | xxxxxxxxxxxx | 559 * gen request tag 560 */ 561 #define nvme_genctr_mask(gen) (gen & 0xf) 562 #define nvme_cid_install_genctr(gen) (nvme_genctr_mask(gen) << 12) 563 #define nvme_genctr_from_cid(cid) ((cid & 0xf000) >> 12) 564 #define nvme_tag_from_cid(cid) (cid & 0xfff) 565 566 static inline u16 nvme_cid(struct request *rq) 567 { 568 return nvme_cid_install_genctr(nvme_req(rq)->genctr) | rq->tag; 569 } 570 571 static inline struct request *nvme_find_rq(struct blk_mq_tags *tags, 572 u16 command_id) 573 { 574 u8 genctr = nvme_genctr_from_cid(command_id); 575 u16 tag = nvme_tag_from_cid(command_id); 576 struct request *rq; 577 578 rq = blk_mq_tag_to_rq(tags, tag); 579 if (unlikely(!rq)) { 580 pr_err("could not locate request for tag %#x\n", 581 tag); 582 return NULL; 583 } 584 if (unlikely(nvme_genctr_mask(nvme_req(rq)->genctr) != genctr)) { 585 dev_err(nvme_req(rq)->ctrl->device, 586 "request %#x genctr mismatch (got %#x expected %#x)\n", 587 tag, genctr, nvme_genctr_mask(nvme_req(rq)->genctr)); 588 return NULL; 589 } 590 return rq; 591 } 592 593 static inline struct request *nvme_cid_to_rq(struct blk_mq_tags *tags, 594 u16 command_id) 595 { 596 return blk_mq_tag_to_rq(tags, nvme_tag_from_cid(command_id)); 597 } 598 599 /* 600 * Return the length of the string without the space padding 601 */ 602 static inline int nvme_strlen(char *s, int len) 603 { 604 while (s[len - 1] == ' ') 605 len--; 606 return len; 607 } 608 609 static inline void nvme_print_device_info(struct nvme_ctrl *ctrl) 610 { 611 struct nvme_subsystem *subsys = ctrl->subsys; 612 613 if (ctrl->ops->print_device_info) { 614 ctrl->ops->print_device_info(ctrl); 615 return; 616 } 617 618 dev_err(ctrl->device, 619 "VID:%04x model:%.*s firmware:%.*s\n", subsys->vendor_id, 620 nvme_strlen(subsys->model, sizeof(subsys->model)), 621 subsys->model, nvme_strlen(subsys->firmware_rev, 622 sizeof(subsys->firmware_rev)), 623 subsys->firmware_rev); 624 } 625 626 #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS 627 void nvme_fault_inject_init(struct nvme_fault_inject *fault_inj, 628 const char *dev_name); 629 void nvme_fault_inject_fini(struct nvme_fault_inject *fault_inject); 630 void nvme_should_fail(struct request *req); 631 #else 632 static inline void nvme_fault_inject_init(struct nvme_fault_inject *fault_inj, 633 const char *dev_name) 634 { 635 } 636 static inline void nvme_fault_inject_fini(struct nvme_fault_inject *fault_inj) 637 { 638 } 639 static inline void nvme_should_fail(struct request *req) {} 640 #endif 641 642 bool nvme_wait_reset(struct nvme_ctrl *ctrl); 643 int nvme_try_sched_reset(struct nvme_ctrl *ctrl); 644 645 static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl) 646 { 647 int ret; 648 649 if (!ctrl->subsystem) 650 return -ENOTTY; 651 if (!nvme_wait_reset(ctrl)) 652 return -EBUSY; 653 654 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65); 655 if (ret) 656 return ret; 657 658 return nvme_try_sched_reset(ctrl); 659 } 660 661 /* 662 * Convert a 512B sector number to a device logical block number. 663 */ 664 static inline u64 nvme_sect_to_lba(struct nvme_ns *ns, sector_t sector) 665 { 666 return sector >> (ns->lba_shift - SECTOR_SHIFT); 667 } 668 669 /* 670 * Convert a device logical block number to a 512B sector number. 671 */ 672 static inline sector_t nvme_lba_to_sect(struct nvme_ns *ns, u64 lba) 673 { 674 return lba << (ns->lba_shift - SECTOR_SHIFT); 675 } 676 677 /* 678 * Convert byte length to nvme's 0-based num dwords 679 */ 680 static inline u32 nvme_bytes_to_numd(size_t len) 681 { 682 return (len >> 2) - 1; 683 } 684 685 static inline bool nvme_is_ana_error(u16 status) 686 { 687 switch (status & 0x7ff) { 688 case NVME_SC_ANA_TRANSITION: 689 case NVME_SC_ANA_INACCESSIBLE: 690 case NVME_SC_ANA_PERSISTENT_LOSS: 691 return true; 692 default: 693 return false; 694 } 695 } 696 697 static inline bool nvme_is_path_error(u16 status) 698 { 699 /* check for a status code type of 'path related status' */ 700 return (status & 0x700) == 0x300; 701 } 702 703 /* 704 * Fill in the status and result information from the CQE, and then figure out 705 * if blk-mq will need to use IPI magic to complete the request, and if yes do 706 * so. If not let the caller complete the request without an indirect function 707 * call. 708 */ 709 static inline bool nvme_try_complete_req(struct request *req, __le16 status, 710 union nvme_result result) 711 { 712 struct nvme_request *rq = nvme_req(req); 713 struct nvme_ctrl *ctrl = rq->ctrl; 714 715 if (!(ctrl->quirks & NVME_QUIRK_SKIP_CID_GEN)) 716 rq->genctr++; 717 718 rq->status = le16_to_cpu(status) >> 1; 719 rq->result = result; 720 /* inject error when permitted by fault injection framework */ 721 nvme_should_fail(req); 722 if (unlikely(blk_should_fake_timeout(req->q))) 723 return true; 724 return blk_mq_complete_request_remote(req); 725 } 726 727 static inline void nvme_get_ctrl(struct nvme_ctrl *ctrl) 728 { 729 get_device(ctrl->device); 730 } 731 732 static inline void nvme_put_ctrl(struct nvme_ctrl *ctrl) 733 { 734 put_device(ctrl->device); 735 } 736 737 static inline bool nvme_is_aen_req(u16 qid, __u16 command_id) 738 { 739 return !qid && 740 nvme_tag_from_cid(command_id) >= NVME_AQ_BLK_MQ_DEPTH; 741 } 742 743 /* 744 * Returns true for sink states that can't ever transition back to live. 745 */ 746 static inline bool nvme_state_terminal(struct nvme_ctrl *ctrl) 747 { 748 switch (nvme_ctrl_state(ctrl)) { 749 case NVME_CTRL_NEW: 750 case NVME_CTRL_LIVE: 751 case NVME_CTRL_RESETTING: 752 case NVME_CTRL_CONNECTING: 753 return false; 754 case NVME_CTRL_DELETING: 755 case NVME_CTRL_DELETING_NOIO: 756 case NVME_CTRL_DEAD: 757 return true; 758 default: 759 WARN_ONCE(1, "Unhandled ctrl state:%d", ctrl->state); 760 return true; 761 } 762 } 763 764 void nvme_complete_rq(struct request *req); 765 void nvme_complete_batch_req(struct request *req); 766 767 static __always_inline void nvme_complete_batch(struct io_comp_batch *iob, 768 void (*fn)(struct request *rq)) 769 { 770 struct request *req; 771 772 rq_list_for_each(&iob->req_list, req) { 773 fn(req); 774 nvme_complete_batch_req(req); 775 } 776 blk_mq_end_request_batch(iob); 777 } 778 779 blk_status_t nvme_host_path_error(struct request *req); 780 bool nvme_cancel_request(struct request *req, void *data); 781 void nvme_cancel_tagset(struct nvme_ctrl *ctrl); 782 void nvme_cancel_admin_tagset(struct nvme_ctrl *ctrl); 783 bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl, 784 enum nvme_ctrl_state new_state); 785 int nvme_disable_ctrl(struct nvme_ctrl *ctrl, bool shutdown); 786 int nvme_enable_ctrl(struct nvme_ctrl *ctrl); 787 int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev, 788 const struct nvme_ctrl_ops *ops, unsigned long quirks); 789 void nvme_uninit_ctrl(struct nvme_ctrl *ctrl); 790 void nvme_start_ctrl(struct nvme_ctrl *ctrl); 791 void nvme_stop_ctrl(struct nvme_ctrl *ctrl); 792 int nvme_init_ctrl_finish(struct nvme_ctrl *ctrl, bool was_suspended); 793 int nvme_alloc_admin_tag_set(struct nvme_ctrl *ctrl, struct blk_mq_tag_set *set, 794 const struct blk_mq_ops *ops, unsigned int cmd_size); 795 void nvme_remove_admin_tag_set(struct nvme_ctrl *ctrl); 796 int nvme_alloc_io_tag_set(struct nvme_ctrl *ctrl, struct blk_mq_tag_set *set, 797 const struct blk_mq_ops *ops, unsigned int nr_maps, 798 unsigned int cmd_size); 799 void nvme_remove_io_tag_set(struct nvme_ctrl *ctrl); 800 801 void nvme_remove_namespaces(struct nvme_ctrl *ctrl); 802 803 void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status, 804 volatile union nvme_result *res); 805 806 void nvme_quiesce_io_queues(struct nvme_ctrl *ctrl); 807 void nvme_unquiesce_io_queues(struct nvme_ctrl *ctrl); 808 void nvme_quiesce_admin_queue(struct nvme_ctrl *ctrl); 809 void nvme_unquiesce_admin_queue(struct nvme_ctrl *ctrl); 810 void nvme_mark_namespaces_dead(struct nvme_ctrl *ctrl); 811 void nvme_sync_queues(struct nvme_ctrl *ctrl); 812 void nvme_sync_io_queues(struct nvme_ctrl *ctrl); 813 void nvme_unfreeze(struct nvme_ctrl *ctrl); 814 void nvme_wait_freeze(struct nvme_ctrl *ctrl); 815 int nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout); 816 void nvme_start_freeze(struct nvme_ctrl *ctrl); 817 818 static inline enum req_op nvme_req_op(struct nvme_command *cmd) 819 { 820 return nvme_is_write(cmd) ? REQ_OP_DRV_OUT : REQ_OP_DRV_IN; 821 } 822 823 #define NVME_QID_ANY -1 824 void nvme_init_request(struct request *req, struct nvme_command *cmd); 825 void nvme_cleanup_cmd(struct request *req); 826 blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req); 827 blk_status_t nvme_fail_nonready_command(struct nvme_ctrl *ctrl, 828 struct request *req); 829 bool __nvme_check_ready(struct nvme_ctrl *ctrl, struct request *rq, 830 bool queue_live); 831 832 static inline bool nvme_check_ready(struct nvme_ctrl *ctrl, struct request *rq, 833 bool queue_live) 834 { 835 if (likely(ctrl->state == NVME_CTRL_LIVE)) 836 return true; 837 if (ctrl->ops->flags & NVME_F_FABRICS && 838 ctrl->state == NVME_CTRL_DELETING) 839 return queue_live; 840 return __nvme_check_ready(ctrl, rq, queue_live); 841 } 842 843 /* 844 * NSID shall be unique for all shared namespaces, or if at least one of the 845 * following conditions is met: 846 * 1. Namespace Management is supported by the controller 847 * 2. ANA is supported by the controller 848 * 3. NVM Set are supported by the controller 849 * 850 * In other case, private namespace are not required to report a unique NSID. 851 */ 852 static inline bool nvme_is_unique_nsid(struct nvme_ctrl *ctrl, 853 struct nvme_ns_head *head) 854 { 855 return head->shared || 856 (ctrl->oacs & NVME_CTRL_OACS_NS_MNGT_SUPP) || 857 (ctrl->subsys->cmic & NVME_CTRL_CMIC_ANA) || 858 (ctrl->ctratt & NVME_CTRL_CTRATT_NVM_SETS); 859 } 860 861 int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, 862 void *buf, unsigned bufflen); 863 int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, 864 union nvme_result *result, void *buffer, unsigned bufflen, 865 int qid, int at_head, 866 blk_mq_req_flags_t flags); 867 int nvme_set_features(struct nvme_ctrl *dev, unsigned int fid, 868 unsigned int dword11, void *buffer, size_t buflen, 869 u32 *result); 870 int nvme_get_features(struct nvme_ctrl *dev, unsigned int fid, 871 unsigned int dword11, void *buffer, size_t buflen, 872 u32 *result); 873 int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count); 874 void nvme_stop_keep_alive(struct nvme_ctrl *ctrl); 875 int nvme_reset_ctrl(struct nvme_ctrl *ctrl); 876 int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl); 877 int nvme_delete_ctrl(struct nvme_ctrl *ctrl); 878 void nvme_queue_scan(struct nvme_ctrl *ctrl); 879 int nvme_get_log(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, u8 lsp, u8 csi, 880 void *log, size_t size, u64 offset); 881 bool nvme_tryget_ns_head(struct nvme_ns_head *head); 882 void nvme_put_ns_head(struct nvme_ns_head *head); 883 int nvme_cdev_add(struct cdev *cdev, struct device *cdev_device, 884 const struct file_operations *fops, struct module *owner); 885 void nvme_cdev_del(struct cdev *cdev, struct device *cdev_device); 886 int nvme_ioctl(struct block_device *bdev, blk_mode_t mode, 887 unsigned int cmd, unsigned long arg); 888 long nvme_ns_chr_ioctl(struct file *file, unsigned int cmd, unsigned long arg); 889 int nvme_ns_head_ioctl(struct block_device *bdev, blk_mode_t mode, 890 unsigned int cmd, unsigned long arg); 891 long nvme_ns_head_chr_ioctl(struct file *file, unsigned int cmd, 892 unsigned long arg); 893 long nvme_dev_ioctl(struct file *file, unsigned int cmd, 894 unsigned long arg); 895 int nvme_ns_chr_uring_cmd_iopoll(struct io_uring_cmd *ioucmd, 896 struct io_comp_batch *iob, unsigned int poll_flags); 897 int nvme_ns_chr_uring_cmd(struct io_uring_cmd *ioucmd, 898 unsigned int issue_flags); 899 int nvme_ns_head_chr_uring_cmd(struct io_uring_cmd *ioucmd, 900 unsigned int issue_flags); 901 int nvme_getgeo(struct block_device *bdev, struct hd_geometry *geo); 902 int nvme_dev_uring_cmd(struct io_uring_cmd *ioucmd, unsigned int issue_flags); 903 904 extern const struct attribute_group *nvme_ns_id_attr_groups[]; 905 extern const struct pr_ops nvme_pr_ops; 906 extern const struct block_device_operations nvme_ns_head_ops; 907 extern const struct attribute_group nvme_dev_attrs_group; 908 extern const struct attribute_group *nvme_subsys_attrs_groups[]; 909 extern const struct attribute_group *nvme_dev_attr_groups[]; 910 extern const struct block_device_operations nvme_bdev_ops; 911 912 void nvme_delete_ctrl_sync(struct nvme_ctrl *ctrl); 913 struct nvme_ns *nvme_find_path(struct nvme_ns_head *head); 914 #ifdef CONFIG_NVME_MULTIPATH 915 static inline bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl) 916 { 917 return ctrl->ana_log_buf != NULL; 918 } 919 920 void nvme_mpath_unfreeze(struct nvme_subsystem *subsys); 921 void nvme_mpath_wait_freeze(struct nvme_subsystem *subsys); 922 void nvme_mpath_start_freeze(struct nvme_subsystem *subsys); 923 void nvme_mpath_default_iopolicy(struct nvme_subsystem *subsys); 924 void nvme_failover_req(struct request *req); 925 void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl); 926 int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl,struct nvme_ns_head *head); 927 void nvme_mpath_add_disk(struct nvme_ns *ns, __le32 anagrpid); 928 void nvme_mpath_remove_disk(struct nvme_ns_head *head); 929 int nvme_mpath_init_identify(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id); 930 void nvme_mpath_init_ctrl(struct nvme_ctrl *ctrl); 931 void nvme_mpath_update(struct nvme_ctrl *ctrl); 932 void nvme_mpath_uninit(struct nvme_ctrl *ctrl); 933 void nvme_mpath_stop(struct nvme_ctrl *ctrl); 934 bool nvme_mpath_clear_current_path(struct nvme_ns *ns); 935 void nvme_mpath_revalidate_paths(struct nvme_ns *ns); 936 void nvme_mpath_clear_ctrl_paths(struct nvme_ctrl *ctrl); 937 void nvme_mpath_shutdown_disk(struct nvme_ns_head *head); 938 void nvme_mpath_start_request(struct request *rq); 939 void nvme_mpath_end_request(struct request *rq); 940 941 static inline void nvme_trace_bio_complete(struct request *req) 942 { 943 struct nvme_ns *ns = req->q->queuedata; 944 945 if ((req->cmd_flags & REQ_NVME_MPATH) && req->bio) 946 trace_block_bio_complete(ns->head->disk->queue, req->bio); 947 } 948 949 extern bool multipath; 950 extern struct device_attribute dev_attr_ana_grpid; 951 extern struct device_attribute dev_attr_ana_state; 952 extern struct device_attribute subsys_attr_iopolicy; 953 954 #else 955 #define multipath false 956 static inline bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl) 957 { 958 return false; 959 } 960 static inline void nvme_failover_req(struct request *req) 961 { 962 } 963 static inline void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl) 964 { 965 } 966 static inline int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl, 967 struct nvme_ns_head *head) 968 { 969 return 0; 970 } 971 static inline void nvme_mpath_add_disk(struct nvme_ns *ns, __le32 anagrpid) 972 { 973 } 974 static inline void nvme_mpath_remove_disk(struct nvme_ns_head *head) 975 { 976 } 977 static inline bool nvme_mpath_clear_current_path(struct nvme_ns *ns) 978 { 979 return false; 980 } 981 static inline void nvme_mpath_revalidate_paths(struct nvme_ns *ns) 982 { 983 } 984 static inline void nvme_mpath_clear_ctrl_paths(struct nvme_ctrl *ctrl) 985 { 986 } 987 static inline void nvme_mpath_shutdown_disk(struct nvme_ns_head *head) 988 { 989 } 990 static inline void nvme_trace_bio_complete(struct request *req) 991 { 992 } 993 static inline void nvme_mpath_init_ctrl(struct nvme_ctrl *ctrl) 994 { 995 } 996 static inline int nvme_mpath_init_identify(struct nvme_ctrl *ctrl, 997 struct nvme_id_ctrl *id) 998 { 999 if (ctrl->subsys->cmic & NVME_CTRL_CMIC_ANA) 1000 dev_warn(ctrl->device, 1001 "Please enable CONFIG_NVME_MULTIPATH for full support of multi-port devices.\n"); 1002 return 0; 1003 } 1004 static inline void nvme_mpath_update(struct nvme_ctrl *ctrl) 1005 { 1006 } 1007 static inline void nvme_mpath_uninit(struct nvme_ctrl *ctrl) 1008 { 1009 } 1010 static inline void nvme_mpath_stop(struct nvme_ctrl *ctrl) 1011 { 1012 } 1013 static inline void nvme_mpath_unfreeze(struct nvme_subsystem *subsys) 1014 { 1015 } 1016 static inline void nvme_mpath_wait_freeze(struct nvme_subsystem *subsys) 1017 { 1018 } 1019 static inline void nvme_mpath_start_freeze(struct nvme_subsystem *subsys) 1020 { 1021 } 1022 static inline void nvme_mpath_default_iopolicy(struct nvme_subsystem *subsys) 1023 { 1024 } 1025 static inline void nvme_mpath_start_request(struct request *rq) 1026 { 1027 } 1028 static inline void nvme_mpath_end_request(struct request *rq) 1029 { 1030 } 1031 #endif /* CONFIG_NVME_MULTIPATH */ 1032 1033 int nvme_revalidate_zones(struct nvme_ns *ns); 1034 int nvme_ns_report_zones(struct nvme_ns *ns, sector_t sector, 1035 unsigned int nr_zones, report_zones_cb cb, void *data); 1036 #ifdef CONFIG_BLK_DEV_ZONED 1037 int nvme_update_zone_info(struct nvme_ns *ns, unsigned lbaf); 1038 blk_status_t nvme_setup_zone_mgmt_send(struct nvme_ns *ns, struct request *req, 1039 struct nvme_command *cmnd, 1040 enum nvme_zone_mgmt_action action); 1041 #else 1042 static inline blk_status_t nvme_setup_zone_mgmt_send(struct nvme_ns *ns, 1043 struct request *req, struct nvme_command *cmnd, 1044 enum nvme_zone_mgmt_action action) 1045 { 1046 return BLK_STS_NOTSUPP; 1047 } 1048 1049 static inline int nvme_update_zone_info(struct nvme_ns *ns, unsigned lbaf) 1050 { 1051 dev_warn(ns->ctrl->device, 1052 "Please enable CONFIG_BLK_DEV_ZONED to support ZNS devices\n"); 1053 return -EPROTONOSUPPORT; 1054 } 1055 #endif 1056 1057 static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev) 1058 { 1059 return dev_to_disk(dev)->private_data; 1060 } 1061 1062 #ifdef CONFIG_NVME_HWMON 1063 int nvme_hwmon_init(struct nvme_ctrl *ctrl); 1064 void nvme_hwmon_exit(struct nvme_ctrl *ctrl); 1065 #else 1066 static inline int nvme_hwmon_init(struct nvme_ctrl *ctrl) 1067 { 1068 return 0; 1069 } 1070 1071 static inline void nvme_hwmon_exit(struct nvme_ctrl *ctrl) 1072 { 1073 } 1074 #endif 1075 1076 static inline void nvme_start_request(struct request *rq) 1077 { 1078 if (rq->cmd_flags & REQ_NVME_MPATH) 1079 nvme_mpath_start_request(rq); 1080 blk_mq_start_request(rq); 1081 } 1082 1083 static inline bool nvme_ctrl_sgl_supported(struct nvme_ctrl *ctrl) 1084 { 1085 return ctrl->sgls & ((1 << 0) | (1 << 1)); 1086 } 1087 1088 #ifdef CONFIG_NVME_AUTH 1089 int __init nvme_init_auth(void); 1090 void __exit nvme_exit_auth(void); 1091 int nvme_auth_init_ctrl(struct nvme_ctrl *ctrl); 1092 void nvme_auth_stop(struct nvme_ctrl *ctrl); 1093 int nvme_auth_negotiate(struct nvme_ctrl *ctrl, int qid); 1094 int nvme_auth_wait(struct nvme_ctrl *ctrl, int qid); 1095 void nvme_auth_free(struct nvme_ctrl *ctrl); 1096 #else 1097 static inline int nvme_auth_init_ctrl(struct nvme_ctrl *ctrl) 1098 { 1099 return 0; 1100 } 1101 static inline int __init nvme_init_auth(void) 1102 { 1103 return 0; 1104 } 1105 static inline void __exit nvme_exit_auth(void) 1106 { 1107 } 1108 static inline void nvme_auth_stop(struct nvme_ctrl *ctrl) {}; 1109 static inline int nvme_auth_negotiate(struct nvme_ctrl *ctrl, int qid) 1110 { 1111 return -EPROTONOSUPPORT; 1112 } 1113 static inline int nvme_auth_wait(struct nvme_ctrl *ctrl, int qid) 1114 { 1115 return NVME_SC_AUTH_REQUIRED; 1116 } 1117 static inline void nvme_auth_free(struct nvme_ctrl *ctrl) {}; 1118 #endif 1119 1120 u32 nvme_command_effects(struct nvme_ctrl *ctrl, struct nvme_ns *ns, 1121 u8 opcode); 1122 u32 nvme_passthru_start(struct nvme_ctrl *ctrl, struct nvme_ns *ns, u8 opcode); 1123 int nvme_execute_rq(struct request *rq, bool at_head); 1124 void nvme_passthru_end(struct nvme_ctrl *ctrl, struct nvme_ns *ns, u32 effects, 1125 struct nvme_command *cmd, int status); 1126 struct nvme_ctrl *nvme_ctrl_from_file(struct file *file); 1127 struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid); 1128 void nvme_put_ns(struct nvme_ns *ns); 1129 1130 static inline bool nvme_multi_css(struct nvme_ctrl *ctrl) 1131 { 1132 return (ctrl->ctrl_config & NVME_CC_CSS_MASK) == NVME_CC_CSS_CSI; 1133 } 1134 1135 #ifdef CONFIG_NVME_VERBOSE_ERRORS 1136 const unsigned char *nvme_get_error_status_str(u16 status); 1137 const unsigned char *nvme_get_opcode_str(u8 opcode); 1138 const unsigned char *nvme_get_admin_opcode_str(u8 opcode); 1139 const unsigned char *nvme_get_fabrics_opcode_str(u8 opcode); 1140 #else /* CONFIG_NVME_VERBOSE_ERRORS */ 1141 static inline const unsigned char *nvme_get_error_status_str(u16 status) 1142 { 1143 return "I/O Error"; 1144 } 1145 static inline const unsigned char *nvme_get_opcode_str(u8 opcode) 1146 { 1147 return "I/O Cmd"; 1148 } 1149 static inline const unsigned char *nvme_get_admin_opcode_str(u8 opcode) 1150 { 1151 return "Admin Cmd"; 1152 } 1153 1154 static inline const unsigned char *nvme_get_fabrics_opcode_str(u8 opcode) 1155 { 1156 return "Fabrics Cmd"; 1157 } 1158 #endif /* CONFIG_NVME_VERBOSE_ERRORS */ 1159 1160 static inline const unsigned char *nvme_opcode_str(int qid, u8 opcode, u8 fctype) 1161 { 1162 if (opcode == nvme_fabrics_command) 1163 return nvme_get_fabrics_opcode_str(fctype); 1164 return qid ? nvme_get_opcode_str(opcode) : 1165 nvme_get_admin_opcode_str(opcode); 1166 } 1167 #endif /* _NVME_H */ 1168