1bc50ad75SChristoph Hellwig /* SPDX-License-Identifier: GPL-2.0 */ 257dacad5SJay Sternberg /* 357dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 457dacad5SJay Sternberg */ 557dacad5SJay Sternberg 657dacad5SJay Sternberg #ifndef _NVME_H 757dacad5SJay Sternberg #define _NVME_H 857dacad5SJay Sternberg 957dacad5SJay Sternberg #include <linux/nvme.h> 10a6a5149bSChristoph Hellwig #include <linux/cdev.h> 1157dacad5SJay Sternberg #include <linux/pci.h> 1257dacad5SJay Sternberg #include <linux/kref.h> 1357dacad5SJay Sternberg #include <linux/blk-mq.h> 14b0b4e09cSMatias Bjørling #include <linux/lightnvm.h> 15a98e58e5SScott Bauer #include <linux/sed-opal.h> 16b9e03857SThomas Tai #include <linux/fault-inject.h> 17978628ecSJohannes Thumshirn #include <linux/rcupdate.h> 18c1ac9a4bSKeith Busch #include <linux/wait.h> 194d2ce688SJames Smart #include <linux/t10-pi.h> 2057dacad5SJay Sternberg 2135fe0d12SHannes Reinecke #include <trace/events/block.h> 2235fe0d12SHannes Reinecke 238ae4e447SMarc Olson extern unsigned int nvme_io_timeout; 2457dacad5SJay Sternberg #define NVME_IO_TIMEOUT (nvme_io_timeout * HZ) 2557dacad5SJay Sternberg 268ae4e447SMarc Olson extern unsigned int admin_timeout; 27dc96f938SChaitanya Kulkarni #define NVME_ADMIN_TIMEOUT (admin_timeout * HZ) 2821d34711SChristoph Hellwig 29038bd4cbSSagi Grimberg #define NVME_DEFAULT_KATO 5 30038bd4cbSSagi Grimberg 3138e18002SIsrael Rukshin #ifdef CONFIG_ARCH_NO_SG_CHAIN 3238e18002SIsrael Rukshin #define NVME_INLINE_SG_CNT 0 33ba7ca2aeSIsrael Rukshin #define NVME_INLINE_METADATA_SG_CNT 0 3438e18002SIsrael Rukshin #else 3538e18002SIsrael Rukshin #define NVME_INLINE_SG_CNT 2 36ba7ca2aeSIsrael Rukshin #define NVME_INLINE_METADATA_SG_CNT 1 3738e18002SIsrael Rukshin #endif 3838e18002SIsrael Rukshin 396c3c05b0SChaitanya Kulkarni /* 406c3c05b0SChaitanya Kulkarni * Default to a 4K page size, with the intention to update this 416c3c05b0SChaitanya Kulkarni * path in the future to accommodate architectures with differing 426c3c05b0SChaitanya Kulkarni * kernel and IO page sizes. 436c3c05b0SChaitanya Kulkarni */ 446c3c05b0SChaitanya Kulkarni #define NVME_CTRL_PAGE_SHIFT 12 456c3c05b0SChaitanya Kulkarni #define NVME_CTRL_PAGE_SIZE (1 << NVME_CTRL_PAGE_SHIFT) 466c3c05b0SChaitanya Kulkarni 479a6327d2SSagi Grimberg extern struct workqueue_struct *nvme_wq; 48b227c59bSRoy Shterman extern struct workqueue_struct *nvme_reset_wq; 49b227c59bSRoy Shterman extern struct workqueue_struct *nvme_delete_wq; 509a6327d2SSagi Grimberg 51ca064085SMatias Bjørling enum { 52ca064085SMatias Bjørling NVME_NS_LBA = 0, 53ca064085SMatias Bjørling NVME_NS_LIGHTNVM = 1, 54ca064085SMatias Bjørling }; 55ca064085SMatias Bjørling 5657dacad5SJay Sternberg /* 57106198edSChristoph Hellwig * List of workarounds for devices that required behavior not specified in 58106198edSChristoph Hellwig * the standard. 5957dacad5SJay Sternberg */ 60106198edSChristoph Hellwig enum nvme_quirks { 61106198edSChristoph Hellwig /* 62106198edSChristoph Hellwig * Prefers I/O aligned to a stripe size specified in a vendor 63106198edSChristoph Hellwig * specific Identify field. 64106198edSChristoph Hellwig */ 65106198edSChristoph Hellwig NVME_QUIRK_STRIPE_SIZE = (1 << 0), 66540c801cSKeith Busch 67540c801cSKeith Busch /* 68540c801cSKeith Busch * The controller doesn't handle Identify value others than 0 or 1 69540c801cSKeith Busch * correctly. 70540c801cSKeith Busch */ 71540c801cSKeith Busch NVME_QUIRK_IDENTIFY_CNS = (1 << 1), 7208095e70SKeith Busch 7308095e70SKeith Busch /* 74e850fd16SChristoph Hellwig * The controller deterministically returns O's on reads to 75e850fd16SChristoph Hellwig * logical blocks that deallocate was called on. 7608095e70SKeith Busch */ 77e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES = (1 << 2), 7854adc010SGuilherme G. Piccoli 7954adc010SGuilherme G. Piccoli /* 8054adc010SGuilherme G. Piccoli * The controller needs a delay before starts checking the device 8154adc010SGuilherme G. Piccoli * readiness, which is done by reading the NVME_CSTS_RDY bit. 8254adc010SGuilherme G. Piccoli */ 8354adc010SGuilherme G. Piccoli NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3), 84c5552fdeSAndy Lutomirski 85c5552fdeSAndy Lutomirski /* 86c5552fdeSAndy Lutomirski * APST should not be used. 87c5552fdeSAndy Lutomirski */ 88c5552fdeSAndy Lutomirski NVME_QUIRK_NO_APST = (1 << 4), 89ff5350a8SAndy Lutomirski 90ff5350a8SAndy Lutomirski /* 91ff5350a8SAndy Lutomirski * The deepest sleep state should not be used. 92ff5350a8SAndy Lutomirski */ 93ff5350a8SAndy Lutomirski NVME_QUIRK_NO_DEEPEST_PS = (1 << 5), 94608cc4b1SChristoph Hellwig 95608cc4b1SChristoph Hellwig /* 96608cc4b1SChristoph Hellwig * Supports the LighNVM command set if indicated in vs[1]. 97608cc4b1SChristoph Hellwig */ 98608cc4b1SChristoph Hellwig NVME_QUIRK_LIGHTNVM = (1 << 6), 999abd68efSJens Axboe 1009abd68efSJens Axboe /* 1019abd68efSJens Axboe * Set MEDIUM priority on SQ creation 1029abd68efSJens Axboe */ 1039abd68efSJens Axboe NVME_QUIRK_MEDIUM_PRIO_SQ = (1 << 7), 1046299358dSJames Dingwall 1056299358dSJames Dingwall /* 1066299358dSJames Dingwall * Ignore device provided subnqn. 1076299358dSJames Dingwall */ 1086299358dSJames Dingwall NVME_QUIRK_IGNORE_DEV_SUBNQN = (1 << 8), 1097b210e4eSChristoph Hellwig 1107b210e4eSChristoph Hellwig /* 1117b210e4eSChristoph Hellwig * Broken Write Zeroes. 1127b210e4eSChristoph Hellwig */ 1137b210e4eSChristoph Hellwig NVME_QUIRK_DISABLE_WRITE_ZEROES = (1 << 9), 114cb32de1bSMario Limonciello 115cb32de1bSMario Limonciello /* 116cb32de1bSMario Limonciello * Force simple suspend/resume path. 117cb32de1bSMario Limonciello */ 118cb32de1bSMario Limonciello NVME_QUIRK_SIMPLE_SUSPEND = (1 << 10), 1197ad67ca5SLinus Torvalds 1207ad67ca5SLinus Torvalds /* 12166341331SBenjamin Herrenschmidt * Use only one interrupt vector for all queues 12266341331SBenjamin Herrenschmidt */ 1237ad67ca5SLinus Torvalds NVME_QUIRK_SINGLE_VECTOR = (1 << 11), 12466341331SBenjamin Herrenschmidt 12566341331SBenjamin Herrenschmidt /* 12666341331SBenjamin Herrenschmidt * Use non-standard 128 bytes SQEs. 12766341331SBenjamin Herrenschmidt */ 1287ad67ca5SLinus Torvalds NVME_QUIRK_128_BYTES_SQES = (1 << 12), 129d38e9f04SBenjamin Herrenschmidt 130d38e9f04SBenjamin Herrenschmidt /* 131d38e9f04SBenjamin Herrenschmidt * Prevent tag overlap between queues 132d38e9f04SBenjamin Herrenschmidt */ 1337ad67ca5SLinus Torvalds NVME_QUIRK_SHARED_TAGS = (1 << 13), 1346c6aa2f2SAkinobu Mita 1356c6aa2f2SAkinobu Mita /* 1366c6aa2f2SAkinobu Mita * Don't change the value of the temperature threshold feature 1376c6aa2f2SAkinobu Mita */ 1386c6aa2f2SAkinobu Mita NVME_QUIRK_NO_TEMP_THRESH_CHANGE = (1 << 14), 1395bedd3afSChristoph Hellwig 1405bedd3afSChristoph Hellwig /* 1415bedd3afSChristoph Hellwig * The controller doesn't handle the Identify Namespace 1425bedd3afSChristoph Hellwig * Identification Descriptor list subcommand despite claiming 1435bedd3afSChristoph Hellwig * NVMe 1.3 compliance. 1445bedd3afSChristoph Hellwig */ 1455bedd3afSChristoph Hellwig NVME_QUIRK_NO_NS_DESC_LIST = (1 << 15), 1464bdf2603SFilippo Sironi 1474bdf2603SFilippo Sironi /* 1484bdf2603SFilippo Sironi * The controller does not properly handle DMA addresses over 1494bdf2603SFilippo Sironi * 48 bits. 1504bdf2603SFilippo Sironi */ 1514bdf2603SFilippo Sironi NVME_QUIRK_DMA_ADDRESS_BITS_48 = (1 << 16), 152106198edSChristoph Hellwig }; 153106198edSChristoph Hellwig 154d49187e9SChristoph Hellwig /* 155d49187e9SChristoph Hellwig * Common request structure for NVMe passthrough. All drivers must have 156d49187e9SChristoph Hellwig * this structure as the first member of their request-private data. 157d49187e9SChristoph Hellwig */ 158d49187e9SChristoph Hellwig struct nvme_request { 159d49187e9SChristoph Hellwig struct nvme_command *cmd; 160d49187e9SChristoph Hellwig union nvme_result result; 16144e44b29SChristoph Hellwig u8 retries; 16227fa9bc5SChristoph Hellwig u8 flags; 16327fa9bc5SChristoph Hellwig u16 status; 16459e29ce6SSagi Grimberg struct nvme_ctrl *ctrl; 16527fa9bc5SChristoph Hellwig }; 16627fa9bc5SChristoph Hellwig 16732acab31SChristoph Hellwig /* 16832acab31SChristoph Hellwig * Mark a bio as coming in through the mpath node. 16932acab31SChristoph Hellwig */ 17032acab31SChristoph Hellwig #define REQ_NVME_MPATH REQ_DRV 17132acab31SChristoph Hellwig 17227fa9bc5SChristoph Hellwig enum { 17327fa9bc5SChristoph Hellwig NVME_REQ_CANCELLED = (1 << 0), 174bb06ec31SJames Smart NVME_REQ_USERCMD = (1 << 1), 175d49187e9SChristoph Hellwig }; 176d49187e9SChristoph Hellwig 177d49187e9SChristoph Hellwig static inline struct nvme_request *nvme_req(struct request *req) 178d49187e9SChristoph Hellwig { 179d49187e9SChristoph Hellwig return blk_mq_rq_to_pdu(req); 180d49187e9SChristoph Hellwig } 181d49187e9SChristoph Hellwig 1825d87eb94SKeith Busch static inline u16 nvme_req_qid(struct request *req) 1835d87eb94SKeith Busch { 184643c476dSKeith Busch if (!req->q->queuedata) 1855d87eb94SKeith Busch return 0; 18684115d6dSBaolin Wang 18784115d6dSBaolin Wang return req->mq_hctx->queue_num + 1; 1885d87eb94SKeith Busch } 1895d87eb94SKeith Busch 19054adc010SGuilherme G. Piccoli /* The below value is the specific amount of delay needed before checking 19154adc010SGuilherme G. Piccoli * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the 19254adc010SGuilherme G. Piccoli * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was 19354adc010SGuilherme G. Piccoli * found empirically. 19454adc010SGuilherme G. Piccoli */ 1958c97eeccSJeff Lien #define NVME_QUIRK_DELAY_AMOUNT 2300 19654adc010SGuilherme G. Piccoli 1974212f4e9SSagi Grimberg /* 1984212f4e9SSagi Grimberg * enum nvme_ctrl_state: Controller state 1994212f4e9SSagi Grimberg * 2004212f4e9SSagi Grimberg * @NVME_CTRL_NEW: New controller just allocated, initial state 2014212f4e9SSagi Grimberg * @NVME_CTRL_LIVE: Controller is connected and I/O capable 2024212f4e9SSagi Grimberg * @NVME_CTRL_RESETTING: Controller is resetting (or scheduled reset) 2034212f4e9SSagi Grimberg * @NVME_CTRL_CONNECTING: Controller is disconnected, now connecting the 2044212f4e9SSagi Grimberg * transport 2054212f4e9SSagi Grimberg * @NVME_CTRL_DELETING: Controller is deleting (or scheduled deletion) 206ecca390eSSagi Grimberg * @NVME_CTRL_DELETING_NOIO: Controller is deleting and I/O is not 207ecca390eSSagi Grimberg * disabled/failed immediately. This state comes 208ecca390eSSagi Grimberg * after all async event processing took place and 209ecca390eSSagi Grimberg * before ns removal and the controller deletion 210ecca390eSSagi Grimberg * progress 2114212f4e9SSagi Grimberg * @NVME_CTRL_DEAD: Controller is non-present/unresponsive during 2124212f4e9SSagi Grimberg * shutdown or removal. In this case we forcibly 2134212f4e9SSagi Grimberg * kill all inflight I/O as they have no chance to 2144212f4e9SSagi Grimberg * complete 2154212f4e9SSagi Grimberg */ 216bb8d261eSChristoph Hellwig enum nvme_ctrl_state { 217bb8d261eSChristoph Hellwig NVME_CTRL_NEW, 218bb8d261eSChristoph Hellwig NVME_CTRL_LIVE, 219bb8d261eSChristoph Hellwig NVME_CTRL_RESETTING, 220ad6a0a52SMax Gurtovoy NVME_CTRL_CONNECTING, 221bb8d261eSChristoph Hellwig NVME_CTRL_DELETING, 222ecca390eSSagi Grimberg NVME_CTRL_DELETING_NOIO, 2230ff9d4e1SKeith Busch NVME_CTRL_DEAD, 224bb8d261eSChristoph Hellwig }; 225bb8d261eSChristoph Hellwig 226a3646451SAkinobu Mita struct nvme_fault_inject { 227a3646451SAkinobu Mita #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS 228a3646451SAkinobu Mita struct fault_attr attr; 229a3646451SAkinobu Mita struct dentry *parent; 230a3646451SAkinobu Mita bool dont_retry; /* DNR, do not retry */ 231a3646451SAkinobu Mita u16 status; /* status code */ 232a3646451SAkinobu Mita #endif 233a3646451SAkinobu Mita }; 234a3646451SAkinobu Mita 2351c63dc66SChristoph Hellwig struct nvme_ctrl { 2366e3ca03eSSagi Grimberg bool comp_seen; 237bb8d261eSChristoph Hellwig enum nvme_ctrl_state state; 238bd4da3abSAndy Lutomirski bool identified; 239bb8d261eSChristoph Hellwig spinlock_t lock; 240e7ad43c3SKeith Busch struct mutex scan_lock; 2411c63dc66SChristoph Hellwig const struct nvme_ctrl_ops *ops; 24257dacad5SJay Sternberg struct request_queue *admin_q; 24307bfcd09SChristoph Hellwig struct request_queue *connect_q; 244e7832cb4SSagi Grimberg struct request_queue *fabrics_q; 24557dacad5SJay Sternberg struct device *dev; 24657dacad5SJay Sternberg int instance; 247103e515eSHannes Reinecke int numa_node; 2485bae7f73SChristoph Hellwig struct blk_mq_tag_set *tagset; 24934b6c231SSagi Grimberg struct blk_mq_tag_set *admin_tagset; 2505bae7f73SChristoph Hellwig struct list_head namespaces; 251765cc031SJianchao Wang struct rw_semaphore namespaces_rwsem; 252d22524a4SChristoph Hellwig struct device ctrl_device; 2535bae7f73SChristoph Hellwig struct device *device; /* char device */ 254ed7770f6SHannes Reinecke #ifdef CONFIG_NVME_HWMON 255ed7770f6SHannes Reinecke struct device *hwmon_device; 256ed7770f6SHannes Reinecke #endif 257a6a5149bSChristoph Hellwig struct cdev cdev; 258d86c4d8eSChristoph Hellwig struct work_struct reset_work; 259c5017e85SChristoph Hellwig struct work_struct delete_work; 260c1ac9a4bSKeith Busch wait_queue_head_t state_wq; 2611c63dc66SChristoph Hellwig 262ab9e00ccSChristoph Hellwig struct nvme_subsystem *subsys; 263ab9e00ccSChristoph Hellwig struct list_head subsys_entry; 264ab9e00ccSChristoph Hellwig 2654f1244c8SChristoph Hellwig struct opal_dev *opal_dev; 266a98e58e5SScott Bauer 26757dacad5SJay Sternberg char name[12]; 26876e3914aSChristoph Hellwig u16 cntlid; 2695fd4ce1bSChristoph Hellwig 2705fd4ce1bSChristoph Hellwig u32 ctrl_config; 271b6dccf7fSArnav Dawn u16 mtfa; 272d858e5f0SSagi Grimberg u32 queue_count; 2735fd4ce1bSChristoph Hellwig 27420d0dfe6SSagi Grimberg u64 cap; 27557dacad5SJay Sternberg u32 max_hw_sectors; 276943e942eSJens Axboe u32 max_segments; 27795093350SMax Gurtovoy u32 max_integrity_segments; 2785befc7c2SKeith Busch u32 max_discard_sectors; 2795befc7c2SKeith Busch u32 max_discard_segments; 2805befc7c2SKeith Busch u32 max_zeroes_sectors; 281240e6ee2SKeith Busch #ifdef CONFIG_BLK_DEV_ZONED 282240e6ee2SKeith Busch u32 max_zone_append; 283240e6ee2SKeith Busch #endif 28449cd84b6SKeith Busch u16 crdt[3]; 28557dacad5SJay Sternberg u16 oncs; 2868a9ae523SScott Bauer u16 oacs; 287f5d11840SJens Axboe u16 nssa; 288f5d11840SJens Axboe u16 nr_streams; 289f968688fSKeith Busch u16 sqsize; 2900d0b660fSChristoph Hellwig u32 max_namespaces; 2916bf25d16SChristoph Hellwig atomic_t abort_limit; 29257dacad5SJay Sternberg u8 vwc; 293f3ca80fcSChristoph Hellwig u32 vs; 29407bfcd09SChristoph Hellwig u32 sgls; 295038bd4cbSSagi Grimberg u16 kas; 296c5552fdeSAndy Lutomirski u8 npss; 297c5552fdeSAndy Lutomirski u8 apsta; 298400b6a7bSGuenter Roeck u16 wctemp; 299400b6a7bSGuenter Roeck u16 cctemp; 300c0561f82SHannes Reinecke u32 oaes; 301e3d7874dSKeith Busch u32 aen_result; 3023e53ba38SSagi Grimberg u32 ctratt; 30307fbd32aSMartin K. Petersen unsigned int shutdown_timeout; 304038bd4cbSSagi Grimberg unsigned int kato; 305f3ca80fcSChristoph Hellwig bool subsystem; 306106198edSChristoph Hellwig unsigned long quirks; 307c5552fdeSAndy Lutomirski struct nvme_id_power_state psd[32]; 30884fef62dSKeith Busch struct nvme_effects_log *effects; 3091cf7a12eSChaitanya Kulkarni struct xarray cels; 3105955be21SChristoph Hellwig struct work_struct scan_work; 311f866fc42SChristoph Hellwig struct work_struct async_event_work; 312038bd4cbSSagi Grimberg struct delayed_work ka_work; 3138c4dfea9SVictor Gladkov struct delayed_work failfast_work; 3140a34e466SRoland Dreier struct nvme_command ka_cmd; 315b6dccf7fSArnav Dawn struct work_struct fw_act_work; 31630d90964SChristoph Hellwig unsigned long events; 31707bfcd09SChristoph Hellwig 3180d0b660fSChristoph Hellwig #ifdef CONFIG_NVME_MULTIPATH 3190d0b660fSChristoph Hellwig /* asymmetric namespace access: */ 3200d0b660fSChristoph Hellwig u8 anacap; 3210d0b660fSChristoph Hellwig u8 anatt; 3220d0b660fSChristoph Hellwig u32 anagrpmax; 3230d0b660fSChristoph Hellwig u32 nanagrpid; 3240d0b660fSChristoph Hellwig struct mutex ana_lock; 3250d0b660fSChristoph Hellwig struct nvme_ana_rsp_hdr *ana_log_buf; 3260d0b660fSChristoph Hellwig size_t ana_log_size; 3270d0b660fSChristoph Hellwig struct timer_list anatt_timer; 3280d0b660fSChristoph Hellwig struct work_struct ana_work; 3290d0b660fSChristoph Hellwig #endif 3300d0b660fSChristoph Hellwig 331c5552fdeSAndy Lutomirski /* Power saving configuration */ 332c5552fdeSAndy Lutomirski u64 ps_max_latency_us; 33376a5af84SKai-Heng Feng bool apst_enabled; 334c5552fdeSAndy Lutomirski 335044a9df1SChristoph Hellwig /* PCIe only: */ 336fe6d53c9SChristoph Hellwig u32 hmpre; 337fe6d53c9SChristoph Hellwig u32 hmmin; 338044a9df1SChristoph Hellwig u32 hmminds; 339044a9df1SChristoph Hellwig u16 hmmaxd; 340fe6d53c9SChristoph Hellwig 34107bfcd09SChristoph Hellwig /* Fabrics only */ 34207bfcd09SChristoph Hellwig u32 ioccsz; 34307bfcd09SChristoph Hellwig u32 iorcsz; 34407bfcd09SChristoph Hellwig u16 icdoff; 34507bfcd09SChristoph Hellwig u16 maxcmd; 346fdf9dfa8SSagi Grimberg int nr_reconnects; 3478c4dfea9SVictor Gladkov unsigned long flags; 3488c4dfea9SVictor Gladkov #define NVME_CTRL_FAILFAST_EXPIRED 0 34907bfcd09SChristoph Hellwig struct nvmf_ctrl_options *opts; 350cb5b7262SJens Axboe 351cb5b7262SJens Axboe struct page *discard_page; 352cb5b7262SJens Axboe unsigned long discard_page_busy; 353f79d5fdaSAkinobu Mita 354f79d5fdaSAkinobu Mita struct nvme_fault_inject fault_inject; 35557dacad5SJay Sternberg }; 35657dacad5SJay Sternberg 35775c10e73SHannes Reinecke enum nvme_iopolicy { 35875c10e73SHannes Reinecke NVME_IOPOLICY_NUMA, 35975c10e73SHannes Reinecke NVME_IOPOLICY_RR, 36075c10e73SHannes Reinecke }; 36175c10e73SHannes Reinecke 362ab9e00ccSChristoph Hellwig struct nvme_subsystem { 363ab9e00ccSChristoph Hellwig int instance; 364ab9e00ccSChristoph Hellwig struct device dev; 365ab9e00ccSChristoph Hellwig /* 366ab9e00ccSChristoph Hellwig * Because we unregister the device on the last put we need 367ab9e00ccSChristoph Hellwig * a separate refcount. 368ab9e00ccSChristoph Hellwig */ 369ab9e00ccSChristoph Hellwig struct kref ref; 370ab9e00ccSChristoph Hellwig struct list_head entry; 371ab9e00ccSChristoph Hellwig struct mutex lock; 372ab9e00ccSChristoph Hellwig struct list_head ctrls; 373ed754e5dSChristoph Hellwig struct list_head nsheads; 374ab9e00ccSChristoph Hellwig char subnqn[NVMF_NQN_SIZE]; 375ab9e00ccSChristoph Hellwig char serial[20]; 376ab9e00ccSChristoph Hellwig char model[40]; 377ab9e00ccSChristoph Hellwig char firmware_rev[8]; 378ab9e00ccSChristoph Hellwig u8 cmic; 379ab9e00ccSChristoph Hellwig u16 vendor_id; 38081adb863SBart Van Assche u16 awupf; /* 0's based awupf value. */ 381ed754e5dSChristoph Hellwig struct ida ns_ida; 38275c10e73SHannes Reinecke #ifdef CONFIG_NVME_MULTIPATH 38375c10e73SHannes Reinecke enum nvme_iopolicy iopolicy; 38475c10e73SHannes Reinecke #endif 385ab9e00ccSChristoph Hellwig }; 386ab9e00ccSChristoph Hellwig 387002fab04SChristoph Hellwig /* 388002fab04SChristoph Hellwig * Container structure for uniqueue namespace identifiers. 389002fab04SChristoph Hellwig */ 390002fab04SChristoph Hellwig struct nvme_ns_ids { 391002fab04SChristoph Hellwig u8 eui64[8]; 392002fab04SChristoph Hellwig u8 nguid[16]; 393002fab04SChristoph Hellwig uuid_t uuid; 39471010c30SNiklas Cassel u8 csi; 395002fab04SChristoph Hellwig }; 396002fab04SChristoph Hellwig 397ed754e5dSChristoph Hellwig /* 398ed754e5dSChristoph Hellwig * Anchor structure for namespaces. There is one for each namespace in a 399ed754e5dSChristoph Hellwig * NVMe subsystem that any of our controllers can see, and the namespace 400ed754e5dSChristoph Hellwig * structure for each controller is chained of it. For private namespaces 401ed754e5dSChristoph Hellwig * there is a 1:1 relation to our namespace structures, that is ->list 402ed754e5dSChristoph Hellwig * only ever has a single entry for private namespaces. 403ed754e5dSChristoph Hellwig */ 404ed754e5dSChristoph Hellwig struct nvme_ns_head { 405ed754e5dSChristoph Hellwig struct list_head list; 406ed754e5dSChristoph Hellwig struct srcu_struct srcu; 407ed754e5dSChristoph Hellwig struct nvme_subsystem *subsys; 408ed754e5dSChristoph Hellwig unsigned ns_id; 409ed754e5dSChristoph Hellwig struct nvme_ns_ids ids; 410ed754e5dSChristoph Hellwig struct list_head entry; 411ed754e5dSChristoph Hellwig struct kref ref; 4120c284db7SKeith Busch bool shared; 413ed754e5dSChristoph Hellwig int instance; 414be93e87eSKeith Busch struct nvme_effects_log *effects; 4152637baedSMinwoo Im 4162637baedSMinwoo Im struct cdev cdev; 4172637baedSMinwoo Im struct device cdev_device; 4182637baedSMinwoo Im 419f3334447SChristoph Hellwig struct gendisk *disk; 42030897388SMinwoo Im #ifdef CONFIG_NVME_MULTIPATH 421f3334447SChristoph Hellwig struct bio_list requeue_list; 422f3334447SChristoph Hellwig spinlock_t requeue_lock; 423f3334447SChristoph Hellwig struct work_struct requeue_work; 424f3334447SChristoph Hellwig struct mutex lock; 425d8a22f85SAnton Eidelman unsigned long flags; 426d8a22f85SAnton Eidelman #define NVME_NSHEAD_DISK_LIVE 0 427f3334447SChristoph Hellwig struct nvme_ns __rcu *current_path[]; 428f3334447SChristoph Hellwig #endif 429ed754e5dSChristoph Hellwig }; 430ed754e5dSChristoph Hellwig 43130897388SMinwoo Im static inline bool nvme_ns_head_multipath(struct nvme_ns_head *head) 43230897388SMinwoo Im { 43330897388SMinwoo Im return IS_ENABLED(CONFIG_NVME_MULTIPATH) && head->disk; 43430897388SMinwoo Im } 43530897388SMinwoo Im 436ffc89b1dSMax Gurtovoy enum nvme_ns_features { 437ffc89b1dSMax Gurtovoy NVME_NS_EXT_LBAS = 1 << 0, /* support extended LBA format */ 438b29f8485SMax Gurtovoy NVME_NS_METADATA_SUPPORTED = 1 << 1, /* support getting generated md */ 439ffc89b1dSMax Gurtovoy }; 440ffc89b1dSMax Gurtovoy 44157dacad5SJay Sternberg struct nvme_ns { 44257dacad5SJay Sternberg struct list_head list; 44357dacad5SJay Sternberg 4441c63dc66SChristoph Hellwig struct nvme_ctrl *ctrl; 44557dacad5SJay Sternberg struct request_queue *queue; 44657dacad5SJay Sternberg struct gendisk *disk; 4470d0b660fSChristoph Hellwig #ifdef CONFIG_NVME_MULTIPATH 4480d0b660fSChristoph Hellwig enum nvme_ana_state ana_state; 4490d0b660fSChristoph Hellwig u32 ana_grpid; 4500d0b660fSChristoph Hellwig #endif 451ed754e5dSChristoph Hellwig struct list_head siblings; 452b0b4e09cSMatias Bjørling struct nvm_dev *ndev; 45357dacad5SJay Sternberg struct kref kref; 454ed754e5dSChristoph Hellwig struct nvme_ns_head *head; 45557dacad5SJay Sternberg 45657dacad5SJay Sternberg int lba_shift; 45757dacad5SJay Sternberg u16 ms; 458f5d11840SJens Axboe u16 sgs; 459f5d11840SJens Axboe u32 sws; 46057dacad5SJay Sternberg u8 pi_type; 461240e6ee2SKeith Busch #ifdef CONFIG_BLK_DEV_ZONED 462240e6ee2SKeith Busch u64 zsze; 463240e6ee2SKeith Busch #endif 464ffc89b1dSMax Gurtovoy unsigned long features; 465646017a6SKeith Busch unsigned long flags; 466646017a6SKeith Busch #define NVME_NS_REMOVING 0 46769d9a99cSKeith Busch #define NVME_NS_DEAD 1 4680d0b660fSChristoph Hellwig #define NVME_NS_ANA_PENDING 2 4692f4c9ba2SJavier González #define NVME_NS_FORCE_RO 3 470b9e03857SThomas Tai 4712637baedSMinwoo Im struct cdev cdev; 4722637baedSMinwoo Im struct device cdev_device; 4732637baedSMinwoo Im 474b9e03857SThomas Tai struct nvme_fault_inject fault_inject; 475b9e03857SThomas Tai 47657dacad5SJay Sternberg }; 47757dacad5SJay Sternberg 4784d2ce688SJames Smart /* NVMe ns supports metadata actions by the controller (generate/strip) */ 4794d2ce688SJames Smart static inline bool nvme_ns_has_pi(struct nvme_ns *ns) 4804d2ce688SJames Smart { 4814d2ce688SJames Smart return ns->pi_type && ns->ms == sizeof(struct t10_pi_tuple); 4824d2ce688SJames Smart } 4834d2ce688SJames Smart 4841c63dc66SChristoph Hellwig struct nvme_ctrl_ops { 4851a353d85SMing Lin const char *name; 486e439bb12SSagi Grimberg struct module *module; 487d3d5b87dSChristoph Hellwig unsigned int flags; 488d3d5b87dSChristoph Hellwig #define NVME_F_FABRICS (1 << 0) 489c81bfba9SChristoph Hellwig #define NVME_F_METADATA_SUPPORTED (1 << 1) 490e0596ab2SLogan Gunthorpe #define NVME_F_PCI_P2PDMA (1 << 2) 4911c63dc66SChristoph Hellwig int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val); 4925fd4ce1bSChristoph Hellwig int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val); 4937fd8930fSChristoph Hellwig int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val); 4941673f1f0SChristoph Hellwig void (*free_ctrl)(struct nvme_ctrl *ctrl); 495ad22c355SKeith Busch void (*submit_async_event)(struct nvme_ctrl *ctrl); 496c5017e85SChristoph Hellwig void (*delete_ctrl)(struct nvme_ctrl *ctrl); 4971a353d85SMing Lin int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size); 49857dacad5SJay Sternberg }; 49957dacad5SJay Sternberg 500b9e03857SThomas Tai #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS 501a3646451SAkinobu Mita void nvme_fault_inject_init(struct nvme_fault_inject *fault_inj, 502a3646451SAkinobu Mita const char *dev_name); 503a3646451SAkinobu Mita void nvme_fault_inject_fini(struct nvme_fault_inject *fault_inject); 504b9e03857SThomas Tai void nvme_should_fail(struct request *req); 505b9e03857SThomas Tai #else 506a3646451SAkinobu Mita static inline void nvme_fault_inject_init(struct nvme_fault_inject *fault_inj, 507a3646451SAkinobu Mita const char *dev_name) 508a3646451SAkinobu Mita { 509a3646451SAkinobu Mita } 510a3646451SAkinobu Mita static inline void nvme_fault_inject_fini(struct nvme_fault_inject *fault_inj) 511a3646451SAkinobu Mita { 512a3646451SAkinobu Mita } 513b9e03857SThomas Tai static inline void nvme_should_fail(struct request *req) {} 514b9e03857SThomas Tai #endif 515b9e03857SThomas Tai 516f3ca80fcSChristoph Hellwig static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl) 517f3ca80fcSChristoph Hellwig { 518f3ca80fcSChristoph Hellwig if (!ctrl->subsystem) 519f3ca80fcSChristoph Hellwig return -ENOTTY; 520f3ca80fcSChristoph Hellwig return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65); 521f3ca80fcSChristoph Hellwig } 522f3ca80fcSChristoph Hellwig 523314d48ddSDamien Le Moal /* 524314d48ddSDamien Le Moal * Convert a 512B sector number to a device logical block number. 525314d48ddSDamien Le Moal */ 526314d48ddSDamien Le Moal static inline u64 nvme_sect_to_lba(struct nvme_ns *ns, sector_t sector) 52757dacad5SJay Sternberg { 528314d48ddSDamien Le Moal return sector >> (ns->lba_shift - SECTOR_SHIFT); 52957dacad5SJay Sternberg } 53057dacad5SJay Sternberg 531e08f2ae8SDamien Le Moal /* 532e08f2ae8SDamien Le Moal * Convert a device logical block number to a 512B sector number. 533e08f2ae8SDamien Le Moal */ 534e08f2ae8SDamien Le Moal static inline sector_t nvme_lba_to_sect(struct nvme_ns *ns, u64 lba) 535e08f2ae8SDamien Le Moal { 536e08f2ae8SDamien Le Moal return lba << (ns->lba_shift - SECTOR_SHIFT); 53757dacad5SJay Sternberg } 53857dacad5SJay Sternberg 53971fb90ebSKeith Busch /* 54071fb90ebSKeith Busch * Convert byte length to nvme's 0-based num dwords 54171fb90ebSKeith Busch */ 54271fb90ebSKeith Busch static inline u32 nvme_bytes_to_numd(size_t len) 54371fb90ebSKeith Busch { 54471fb90ebSKeith Busch return (len >> 2) - 1; 54571fb90ebSKeith Busch } 54671fb90ebSKeith Busch 5475ddaabe8SChristoph Hellwig static inline bool nvme_is_ana_error(u16 status) 5485ddaabe8SChristoph Hellwig { 5495ddaabe8SChristoph Hellwig switch (status & 0x7ff) { 5505ddaabe8SChristoph Hellwig case NVME_SC_ANA_TRANSITION: 5515ddaabe8SChristoph Hellwig case NVME_SC_ANA_INACCESSIBLE: 5525ddaabe8SChristoph Hellwig case NVME_SC_ANA_PERSISTENT_LOSS: 5535ddaabe8SChristoph Hellwig return true; 5545ddaabe8SChristoph Hellwig default: 5555ddaabe8SChristoph Hellwig return false; 5565ddaabe8SChristoph Hellwig } 5575ddaabe8SChristoph Hellwig } 5585ddaabe8SChristoph Hellwig 5595ddaabe8SChristoph Hellwig static inline bool nvme_is_path_error(u16 status) 5605ddaabe8SChristoph Hellwig { 5611e41f3bdSChristoph Hellwig /* check for a status code type of 'path related status' */ 5621e41f3bdSChristoph Hellwig return (status & 0x700) == 0x300; 5635ddaabe8SChristoph Hellwig } 5645ddaabe8SChristoph Hellwig 5652eb81a33SChristoph Hellwig /* 5662eb81a33SChristoph Hellwig * Fill in the status and result information from the CQE, and then figure out 5672eb81a33SChristoph Hellwig * if blk-mq will need to use IPI magic to complete the request, and if yes do 5682eb81a33SChristoph Hellwig * so. If not let the caller complete the request without an indirect function 5692eb81a33SChristoph Hellwig * call. 5702eb81a33SChristoph Hellwig */ 5712eb81a33SChristoph Hellwig static inline bool nvme_try_complete_req(struct request *req, __le16 status, 57227fa9bc5SChristoph Hellwig union nvme_result result) 57315a190f7SChristoph Hellwig { 57427fa9bc5SChristoph Hellwig struct nvme_request *rq = nvme_req(req); 57527fa9bc5SChristoph Hellwig 57627fa9bc5SChristoph Hellwig rq->status = le16_to_cpu(status) >> 1; 57727fa9bc5SChristoph Hellwig rq->result = result; 578b9e03857SThomas Tai /* inject error when permitted by fault injection framework */ 579b9e03857SThomas Tai nvme_should_fail(req); 580ff029451SChristoph Hellwig if (unlikely(blk_should_fake_timeout(req->q))) 581ff029451SChristoph Hellwig return true; 582ff029451SChristoph Hellwig return blk_mq_complete_request_remote(req); 58315a190f7SChristoph Hellwig } 58415a190f7SChristoph Hellwig 585d22524a4SChristoph Hellwig static inline void nvme_get_ctrl(struct nvme_ctrl *ctrl) 586d22524a4SChristoph Hellwig { 587d22524a4SChristoph Hellwig get_device(ctrl->device); 588d22524a4SChristoph Hellwig } 589d22524a4SChristoph Hellwig 590d22524a4SChristoph Hellwig static inline void nvme_put_ctrl(struct nvme_ctrl *ctrl) 591d22524a4SChristoph Hellwig { 592d22524a4SChristoph Hellwig put_device(ctrl->device); 593d22524a4SChristoph Hellwig } 594d22524a4SChristoph Hellwig 59558a8df67SIsrael Rukshin static inline bool nvme_is_aen_req(u16 qid, __u16 command_id) 59658a8df67SIsrael Rukshin { 59758a8df67SIsrael Rukshin return !qid && command_id >= NVME_AQ_BLK_MQ_DEPTH; 59858a8df67SIsrael Rukshin } 59958a8df67SIsrael Rukshin 60077f02a7aSChristoph Hellwig void nvme_complete_rq(struct request *req); 601dda3248eSChao Leng blk_status_t nvme_host_path_error(struct request *req); 6027baa8572SJens Axboe bool nvme_cancel_request(struct request *req, void *data, bool reserved); 60325479069SChao Leng void nvme_cancel_tagset(struct nvme_ctrl *ctrl); 60425479069SChao Leng void nvme_cancel_admin_tagset(struct nvme_ctrl *ctrl); 605bb8d261eSChristoph Hellwig bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl, 606bb8d261eSChristoph Hellwig enum nvme_ctrl_state new_state); 607c1ac9a4bSKeith Busch bool nvme_wait_reset(struct nvme_ctrl *ctrl); 608b5b05048SSagi Grimberg int nvme_disable_ctrl(struct nvme_ctrl *ctrl); 609c0f2f45bSSagi Grimberg int nvme_enable_ctrl(struct nvme_ctrl *ctrl); 6105fd4ce1bSChristoph Hellwig int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl); 611f3ca80fcSChristoph Hellwig int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev, 612f3ca80fcSChristoph Hellwig const struct nvme_ctrl_ops *ops, unsigned long quirks); 61353029b04SKeith Busch void nvme_uninit_ctrl(struct nvme_ctrl *ctrl); 614d09f2b45SSagi Grimberg void nvme_start_ctrl(struct nvme_ctrl *ctrl); 615d09f2b45SSagi Grimberg void nvme_stop_ctrl(struct nvme_ctrl *ctrl); 616f21c4769SChaitanya Kulkarni int nvme_init_ctrl_finish(struct nvme_ctrl *ctrl); 6175bae7f73SChristoph Hellwig 6185bae7f73SChristoph Hellwig void nvme_remove_namespaces(struct nvme_ctrl *ctrl); 6191673f1f0SChristoph Hellwig 6204f1244c8SChristoph Hellwig int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len, 6214f1244c8SChristoph Hellwig bool send); 622a98e58e5SScott Bauer 6237bf58533SChristoph Hellwig void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status, 624287a63ebSChristoph Hellwig volatile union nvme_result *res); 625f866fc42SChristoph Hellwig 62625646264SKeith Busch void nvme_stop_queues(struct nvme_ctrl *ctrl); 62725646264SKeith Busch void nvme_start_queues(struct nvme_ctrl *ctrl); 62869d9a99cSKeith Busch void nvme_kill_queues(struct nvme_ctrl *ctrl); 629d6135c3aSKeith Busch void nvme_sync_queues(struct nvme_ctrl *ctrl); 63004800fbfSChao Leng void nvme_sync_io_queues(struct nvme_ctrl *ctrl); 631302ad8ccSKeith Busch void nvme_unfreeze(struct nvme_ctrl *ctrl); 632302ad8ccSKeith Busch void nvme_wait_freeze(struct nvme_ctrl *ctrl); 6337cf0d7c0SSagi Grimberg int nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout); 634302ad8ccSKeith Busch void nvme_start_freeze(struct nvme_ctrl *ctrl); 635363c9aacSSagi Grimberg 636eb71f435SChristoph Hellwig #define NVME_QID_ANY -1 6374160982eSChristoph Hellwig struct request *nvme_alloc_request(struct request_queue *q, 63839dfe844SChaitanya Kulkarni struct nvme_command *cmd, blk_mq_req_flags_t flags); 639f7f1fc36SMax Gurtovoy void nvme_cleanup_cmd(struct request *req); 640f4b9e6c9SKeith Busch blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req); 641*a9715744STao Chiu blk_status_t nvme_fail_nonready_command(struct nvme_ctrl *ctrl, 642*a9715744STao Chiu struct request *req); 643*a9715744STao Chiu bool __nvme_check_ready(struct nvme_ctrl *ctrl, struct request *rq, 644*a9715744STao Chiu bool queue_live); 645*a9715744STao Chiu 646*a9715744STao Chiu static inline bool nvme_check_ready(struct nvme_ctrl *ctrl, struct request *rq, 647*a9715744STao Chiu bool queue_live) 648*a9715744STao Chiu { 649*a9715744STao Chiu if (likely(ctrl->state == NVME_CTRL_LIVE)) 650*a9715744STao Chiu return true; 651*a9715744STao Chiu if (ctrl->ops->flags & NVME_F_FABRICS && 652*a9715744STao Chiu ctrl->state == NVME_CTRL_DELETING) 653*a9715744STao Chiu return true; 654*a9715744STao Chiu return __nvme_check_ready(ctrl, rq, queue_live); 655*a9715744STao Chiu } 65657dacad5SJay Sternberg int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, 65757dacad5SJay Sternberg void *buf, unsigned bufflen); 65857dacad5SJay Sternberg int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, 659d49187e9SChristoph Hellwig union nvme_result *result, void *buffer, unsigned bufflen, 6609a95e4efSBart Van Assche unsigned timeout, int qid, int at_head, 6616287b51cSSagi Grimberg blk_mq_req_flags_t flags, bool poll); 6621a87ee65SKeith Busch int nvme_set_features(struct nvme_ctrl *dev, unsigned int fid, 6631a87ee65SKeith Busch unsigned int dword11, void *buffer, size_t buflen, 6641a87ee65SKeith Busch u32 *result); 6651a87ee65SKeith Busch int nvme_get_features(struct nvme_ctrl *dev, unsigned int fid, 6661a87ee65SKeith Busch unsigned int dword11, void *buffer, size_t buflen, 6671a87ee65SKeith Busch u32 *result); 6689a0be7abSChristoph Hellwig int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count); 669038bd4cbSSagi Grimberg void nvme_stop_keep_alive(struct nvme_ctrl *ctrl); 670d86c4d8eSChristoph Hellwig int nvme_reset_ctrl(struct nvme_ctrl *ctrl); 6712405252aSChristoph Hellwig int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl); 672c1ac9a4bSKeith Busch int nvme_try_sched_reset(struct nvme_ctrl *ctrl); 673c5017e85SChristoph Hellwig int nvme_delete_ctrl(struct nvme_ctrl *ctrl); 6742405252aSChristoph Hellwig void nvme_queue_scan(struct nvme_ctrl *ctrl); 675be93e87eSKeith Busch int nvme_get_log(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, u8 lsp, u8 csi, 6760e98719bSChristoph Hellwig void *log, size_t size, u64 offset); 677240e6ee2SKeith Busch struct nvme_ns *nvme_get_ns_from_disk(struct gendisk *disk, 678240e6ee2SKeith Busch struct nvme_ns_head **head, int *srcu_idx); 679240e6ee2SKeith Busch void nvme_put_ns_from_disk(struct nvme_ns_head *head, int idx); 6801496bd49SChristoph Hellwig bool nvme_tryget_ns_head(struct nvme_ns_head *head); 6811496bd49SChristoph Hellwig void nvme_put_ns_head(struct nvme_ns_head *head); 6822637baedSMinwoo Im int nvme_cdev_add(struct cdev *cdev, struct device *cdev_device, 6832637baedSMinwoo Im const struct file_operations *fops, struct module *owner); 6842637baedSMinwoo Im void nvme_cdev_del(struct cdev *cdev, struct device *cdev_device); 6852405252aSChristoph Hellwig int nvme_ioctl(struct block_device *bdev, fmode_t mode, 6862405252aSChristoph Hellwig unsigned int cmd, unsigned long arg); 6872637baedSMinwoo Im long nvme_ns_chr_ioctl(struct file *file, unsigned int cmd, unsigned long arg); 6882405252aSChristoph Hellwig int nvme_ns_head_ioctl(struct block_device *bdev, fmode_t mode, 6892405252aSChristoph Hellwig unsigned int cmd, unsigned long arg); 6902637baedSMinwoo Im long nvme_ns_head_chr_ioctl(struct file *file, unsigned int cmd, 6912637baedSMinwoo Im unsigned long arg); 6922405252aSChristoph Hellwig long nvme_dev_ioctl(struct file *file, unsigned int cmd, 6932405252aSChristoph Hellwig unsigned long arg); 6941496bd49SChristoph Hellwig int nvme_getgeo(struct block_device *bdev, struct hd_geometry *geo); 695d558fb51SMatias Bjørling 69633b14f67SHannes Reinecke extern const struct attribute_group *nvme_ns_id_attr_groups[]; 6971496bd49SChristoph Hellwig extern const struct pr_ops nvme_pr_ops; 69832acab31SChristoph Hellwig extern const struct block_device_operations nvme_ns_head_ops; 69932acab31SChristoph Hellwig 70032acab31SChristoph Hellwig #ifdef CONFIG_NVME_MULTIPATH 70166b20ac0SMarta Rybczynska static inline bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl) 70266b20ac0SMarta Rybczynska { 70366b20ac0SMarta Rybczynska return ctrl->ana_log_buf != NULL; 70466b20ac0SMarta Rybczynska } 70566b20ac0SMarta Rybczynska 706b9156daeSSagi Grimberg void nvme_mpath_unfreeze(struct nvme_subsystem *subsys); 707b9156daeSSagi Grimberg void nvme_mpath_wait_freeze(struct nvme_subsystem *subsys); 708b9156daeSSagi Grimberg void nvme_mpath_start_freeze(struct nvme_subsystem *subsys); 7099953ab0cSChristoph Hellwig bool nvme_mpath_set_disk_name(struct nvme_ns *ns, char *disk_name, int *flags); 7105ddaabe8SChristoph Hellwig void nvme_failover_req(struct request *req); 71132acab31SChristoph Hellwig void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl); 71232acab31SChristoph Hellwig int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl,struct nvme_ns_head *head); 7130d0b660fSChristoph Hellwig void nvme_mpath_add_disk(struct nvme_ns *ns, struct nvme_id_ns *id); 71432acab31SChristoph Hellwig void nvme_mpath_remove_disk(struct nvme_ns_head *head); 7150d0b660fSChristoph Hellwig int nvme_mpath_init(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id); 7160d0b660fSChristoph Hellwig void nvme_mpath_uninit(struct nvme_ctrl *ctrl); 7170d0b660fSChristoph Hellwig void nvme_mpath_stop(struct nvme_ctrl *ctrl); 7180157ec8dSSagi Grimberg bool nvme_mpath_clear_current_path(struct nvme_ns *ns); 7190157ec8dSSagi Grimberg void nvme_mpath_clear_ctrl_paths(struct nvme_ctrl *ctrl); 72032acab31SChristoph Hellwig struct nvme_ns *nvme_find_path(struct nvme_ns_head *head); 721479a322fSSagi Grimberg 722479a322fSSagi Grimberg static inline void nvme_mpath_check_last_path(struct nvme_ns *ns) 723479a322fSSagi Grimberg { 724479a322fSSagi Grimberg struct nvme_ns_head *head = ns->head; 725479a322fSSagi Grimberg 726479a322fSSagi Grimberg if (head->disk && list_empty(&head->list)) 727479a322fSSagi Grimberg kblockd_schedule_work(&head->requeue_work); 728479a322fSSagi Grimberg } 729479a322fSSagi Grimberg 7302b59787aSMax Gurtovoy static inline void nvme_trace_bio_complete(struct request *req) 73135fe0d12SHannes Reinecke { 73235fe0d12SHannes Reinecke struct nvme_ns *ns = req->q->queuedata; 73335fe0d12SHannes Reinecke 73435fe0d12SHannes Reinecke if (req->cmd_flags & REQ_NVME_MPATH) 735d24de76aSChristoph Hellwig trace_block_bio_complete(ns->head->disk->queue, req->bio); 73635fe0d12SHannes Reinecke } 73735fe0d12SHannes Reinecke 7380d0b660fSChristoph Hellwig extern struct device_attribute dev_attr_ana_grpid; 7390d0b660fSChristoph Hellwig extern struct device_attribute dev_attr_ana_state; 74075c10e73SHannes Reinecke extern struct device_attribute subsys_attr_iopolicy; 7410d0b660fSChristoph Hellwig 74232acab31SChristoph Hellwig #else 7430d0b660fSChristoph Hellwig static inline bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl) 7440d0b660fSChristoph Hellwig { 7450d0b660fSChristoph Hellwig return false; 7460d0b660fSChristoph Hellwig } 7479953ab0cSChristoph Hellwig static inline bool nvme_mpath_set_disk_name(struct nvme_ns *ns, char *disk_name, 7489953ab0cSChristoph Hellwig int *flags) 749a785dbccSKeith Busch { 7509953ab0cSChristoph Hellwig return false; 751a785dbccSKeith Busch } 7525ddaabe8SChristoph Hellwig static inline void nvme_failover_req(struct request *req) 75332acab31SChristoph Hellwig { 75432acab31SChristoph Hellwig } 75532acab31SChristoph Hellwig static inline void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl) 75632acab31SChristoph Hellwig { 75732acab31SChristoph Hellwig } 75832acab31SChristoph Hellwig static inline int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl, 75932acab31SChristoph Hellwig struct nvme_ns_head *head) 76032acab31SChristoph Hellwig { 76132acab31SChristoph Hellwig return 0; 76232acab31SChristoph Hellwig } 7630d0b660fSChristoph Hellwig static inline void nvme_mpath_add_disk(struct nvme_ns *ns, 7640d0b660fSChristoph Hellwig struct nvme_id_ns *id) 76532acab31SChristoph Hellwig { 76632acab31SChristoph Hellwig } 76732acab31SChristoph Hellwig static inline void nvme_mpath_remove_disk(struct nvme_ns_head *head) 76832acab31SChristoph Hellwig { 76932acab31SChristoph Hellwig } 7700157ec8dSSagi Grimberg static inline bool nvme_mpath_clear_current_path(struct nvme_ns *ns) 7710157ec8dSSagi Grimberg { 7720157ec8dSSagi Grimberg return false; 7730157ec8dSSagi Grimberg } 7740157ec8dSSagi Grimberg static inline void nvme_mpath_clear_ctrl_paths(struct nvme_ctrl *ctrl) 77532acab31SChristoph Hellwig { 77632acab31SChristoph Hellwig } 777479a322fSSagi Grimberg static inline void nvme_mpath_check_last_path(struct nvme_ns *ns) 778479a322fSSagi Grimberg { 779479a322fSSagi Grimberg } 7802b59787aSMax Gurtovoy static inline void nvme_trace_bio_complete(struct request *req) 78135fe0d12SHannes Reinecke { 78235fe0d12SHannes Reinecke } 7830d0b660fSChristoph Hellwig static inline int nvme_mpath_init(struct nvme_ctrl *ctrl, 7840d0b660fSChristoph Hellwig struct nvme_id_ctrl *id) 7850d0b660fSChristoph Hellwig { 7862bd64307SKanchan Joshi if (ctrl->subsys->cmic & NVME_CTRL_CMIC_ANA) 78714a1336eSChristoph Hellwig dev_warn(ctrl->device, 78814a1336eSChristoph Hellwig "Please enable CONFIG_NVME_MULTIPATH for full support of multi-port devices.\n"); 7890d0b660fSChristoph Hellwig return 0; 7900d0b660fSChristoph Hellwig } 7910d0b660fSChristoph Hellwig static inline void nvme_mpath_uninit(struct nvme_ctrl *ctrl) 7920d0b660fSChristoph Hellwig { 7930d0b660fSChristoph Hellwig } 7940d0b660fSChristoph Hellwig static inline void nvme_mpath_stop(struct nvme_ctrl *ctrl) 7950d0b660fSChristoph Hellwig { 7960d0b660fSChristoph Hellwig } 797b9156daeSSagi Grimberg static inline void nvme_mpath_unfreeze(struct nvme_subsystem *subsys) 798b9156daeSSagi Grimberg { 799b9156daeSSagi Grimberg } 800b9156daeSSagi Grimberg static inline void nvme_mpath_wait_freeze(struct nvme_subsystem *subsys) 801b9156daeSSagi Grimberg { 802b9156daeSSagi Grimberg } 803b9156daeSSagi Grimberg static inline void nvme_mpath_start_freeze(struct nvme_subsystem *subsys) 804b9156daeSSagi Grimberg { 805b9156daeSSagi Grimberg } 80632acab31SChristoph Hellwig #endif /* CONFIG_NVME_MULTIPATH */ 80732acab31SChristoph Hellwig 8087fad20ddSChristoph Hellwig int nvme_revalidate_zones(struct nvme_ns *ns); 809240e6ee2SKeith Busch #ifdef CONFIG_BLK_DEV_ZONED 810d525c3c0SChristoph Hellwig int nvme_update_zone_info(struct nvme_ns *ns, unsigned lbaf); 811240e6ee2SKeith Busch int nvme_report_zones(struct gendisk *disk, sector_t sector, 812240e6ee2SKeith Busch unsigned int nr_zones, report_zones_cb cb, void *data); 813240e6ee2SKeith Busch 814240e6ee2SKeith Busch blk_status_t nvme_setup_zone_mgmt_send(struct nvme_ns *ns, struct request *req, 815240e6ee2SKeith Busch struct nvme_command *cmnd, 816240e6ee2SKeith Busch enum nvme_zone_mgmt_action action); 817240e6ee2SKeith Busch #else 818240e6ee2SKeith Busch #define nvme_report_zones NULL 819240e6ee2SKeith Busch 820240e6ee2SKeith Busch static inline blk_status_t nvme_setup_zone_mgmt_send(struct nvme_ns *ns, 821240e6ee2SKeith Busch struct request *req, struct nvme_command *cmnd, 822240e6ee2SKeith Busch enum nvme_zone_mgmt_action action) 823240e6ee2SKeith Busch { 824240e6ee2SKeith Busch return BLK_STS_NOTSUPP; 825240e6ee2SKeith Busch } 826240e6ee2SKeith Busch 827d525c3c0SChristoph Hellwig static inline int nvme_update_zone_info(struct nvme_ns *ns, unsigned lbaf) 828240e6ee2SKeith Busch { 829240e6ee2SKeith Busch dev_warn(ns->ctrl->device, 830240e6ee2SKeith Busch "Please enable CONFIG_BLK_DEV_ZONED to support ZNS devices\n"); 831240e6ee2SKeith Busch return -EPROTONOSUPPORT; 832240e6ee2SKeith Busch } 833240e6ee2SKeith Busch #endif 834240e6ee2SKeith Busch 835c4699e70SKeith Busch #ifdef CONFIG_NVM 8363dc87dd0SMatias Bjørling int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, int node); 837b0b4e09cSMatias Bjørling void nvme_nvm_unregister(struct nvme_ns *ns); 83833b14f67SHannes Reinecke extern const struct attribute_group nvme_nvm_attr_group; 839d7790d37SChristoph Hellwig int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, void __user *argp); 840c4699e70SKeith Busch #else 841b0b4e09cSMatias Bjørling static inline int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, 8423dc87dd0SMatias Bjørling int node) 843c4699e70SKeith Busch { 844c4699e70SKeith Busch return 0; 845c4699e70SKeith Busch } 846c4699e70SKeith Busch 847b0b4e09cSMatias Bjørling static inline void nvme_nvm_unregister(struct nvme_ns *ns) {}; 84884d4add7SMatias Bjørling static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, 849d7790d37SChristoph Hellwig void __user *argp) 85084d4add7SMatias Bjørling { 85184d4add7SMatias Bjørling return -ENOTTY; 85284d4add7SMatias Bjørling } 8533dc87dd0SMatias Bjørling #endif /* CONFIG_NVM */ 8543dc87dd0SMatias Bjørling 85540267efdSSimon A. F. Lund static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev) 85640267efdSSimon A. F. Lund { 85740267efdSSimon A. F. Lund return dev_to_disk(dev)->private_data; 85840267efdSSimon A. F. Lund } 859ca064085SMatias Bjørling 860400b6a7bSGuenter Roeck #ifdef CONFIG_NVME_HWMON 86159e330f8SKeith Busch int nvme_hwmon_init(struct nvme_ctrl *ctrl); 862ed7770f6SHannes Reinecke void nvme_hwmon_exit(struct nvme_ctrl *ctrl); 863400b6a7bSGuenter Roeck #else 86459e330f8SKeith Busch static inline int nvme_hwmon_init(struct nvme_ctrl *ctrl) 86559e330f8SKeith Busch { 86659e330f8SKeith Busch return 0; 86759e330f8SKeith Busch } 868ed7770f6SHannes Reinecke 869ed7770f6SHannes Reinecke static inline void nvme_hwmon_exit(struct nvme_ctrl *ctrl) 870ed7770f6SHannes Reinecke { 871ed7770f6SHannes Reinecke } 872400b6a7bSGuenter Roeck #endif 873400b6a7bSGuenter Roeck 874df21b6b1SLogan Gunthorpe u32 nvme_command_effects(struct nvme_ctrl *ctrl, struct nvme_ns *ns, 875df21b6b1SLogan Gunthorpe u8 opcode); 87617365ae6SLogan Gunthorpe void nvme_execute_passthru_rq(struct request *rq); 877b2702aaaSChaitanya Kulkarni struct nvme_ctrl *nvme_ctrl_from_file(struct file *file); 87824493b8bSLogan Gunthorpe struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid); 87924493b8bSLogan Gunthorpe void nvme_put_ns(struct nvme_ns *ns); 880df21b6b1SLogan Gunthorpe 88157dacad5SJay Sternberg #endif /* _NVME_H */ 882