1bc50ad75SChristoph Hellwig /* SPDX-License-Identifier: GPL-2.0 */ 257dacad5SJay Sternberg /* 357dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 457dacad5SJay Sternberg */ 557dacad5SJay Sternberg 657dacad5SJay Sternberg #ifndef _NVME_H 757dacad5SJay Sternberg #define _NVME_H 857dacad5SJay Sternberg 957dacad5SJay Sternberg #include <linux/nvme.h> 10a6a5149bSChristoph Hellwig #include <linux/cdev.h> 1157dacad5SJay Sternberg #include <linux/pci.h> 1257dacad5SJay Sternberg #include <linux/kref.h> 1357dacad5SJay Sternberg #include <linux/blk-mq.h> 14a98e58e5SScott Bauer #include <linux/sed-opal.h> 15b9e03857SThomas Tai #include <linux/fault-inject.h> 16978628ecSJohannes Thumshirn #include <linux/rcupdate.h> 17c1ac9a4bSKeith Busch #include <linux/wait.h> 184d2ce688SJames Smart #include <linux/t10-pi.h> 1957dacad5SJay Sternberg 2035fe0d12SHannes Reinecke #include <trace/events/block.h> 2135fe0d12SHannes Reinecke 228ae4e447SMarc Olson extern unsigned int nvme_io_timeout; 2357dacad5SJay Sternberg #define NVME_IO_TIMEOUT (nvme_io_timeout * HZ) 2457dacad5SJay Sternberg 258ae4e447SMarc Olson extern unsigned int admin_timeout; 26dc96f938SChaitanya Kulkarni #define NVME_ADMIN_TIMEOUT (admin_timeout * HZ) 2721d34711SChristoph Hellwig 28038bd4cbSSagi Grimberg #define NVME_DEFAULT_KATO 5 29038bd4cbSSagi Grimberg 3038e18002SIsrael Rukshin #ifdef CONFIG_ARCH_NO_SG_CHAIN 3138e18002SIsrael Rukshin #define NVME_INLINE_SG_CNT 0 32ba7ca2aeSIsrael Rukshin #define NVME_INLINE_METADATA_SG_CNT 0 3338e18002SIsrael Rukshin #else 3438e18002SIsrael Rukshin #define NVME_INLINE_SG_CNT 2 35ba7ca2aeSIsrael Rukshin #define NVME_INLINE_METADATA_SG_CNT 1 3638e18002SIsrael Rukshin #endif 3738e18002SIsrael Rukshin 386c3c05b0SChaitanya Kulkarni /* 396c3c05b0SChaitanya Kulkarni * Default to a 4K page size, with the intention to update this 406c3c05b0SChaitanya Kulkarni * path in the future to accommodate architectures with differing 416c3c05b0SChaitanya Kulkarni * kernel and IO page sizes. 426c3c05b0SChaitanya Kulkarni */ 436c3c05b0SChaitanya Kulkarni #define NVME_CTRL_PAGE_SHIFT 12 446c3c05b0SChaitanya Kulkarni #define NVME_CTRL_PAGE_SIZE (1 << NVME_CTRL_PAGE_SHIFT) 456c3c05b0SChaitanya Kulkarni 469a6327d2SSagi Grimberg extern struct workqueue_struct *nvme_wq; 47b227c59bSRoy Shterman extern struct workqueue_struct *nvme_reset_wq; 48b227c59bSRoy Shterman extern struct workqueue_struct *nvme_delete_wq; 499a6327d2SSagi Grimberg 5057dacad5SJay Sternberg /* 51106198edSChristoph Hellwig * List of workarounds for devices that required behavior not specified in 52106198edSChristoph Hellwig * the standard. 5357dacad5SJay Sternberg */ 54106198edSChristoph Hellwig enum nvme_quirks { 55106198edSChristoph Hellwig /* 56106198edSChristoph Hellwig * Prefers I/O aligned to a stripe size specified in a vendor 57106198edSChristoph Hellwig * specific Identify field. 58106198edSChristoph Hellwig */ 59106198edSChristoph Hellwig NVME_QUIRK_STRIPE_SIZE = (1 << 0), 60540c801cSKeith Busch 61540c801cSKeith Busch /* 62540c801cSKeith Busch * The controller doesn't handle Identify value others than 0 or 1 63540c801cSKeith Busch * correctly. 64540c801cSKeith Busch */ 65540c801cSKeith Busch NVME_QUIRK_IDENTIFY_CNS = (1 << 1), 6608095e70SKeith Busch 6708095e70SKeith Busch /* 68e850fd16SChristoph Hellwig * The controller deterministically returns O's on reads to 69e850fd16SChristoph Hellwig * logical blocks that deallocate was called on. 7008095e70SKeith Busch */ 71e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES = (1 << 2), 7254adc010SGuilherme G. Piccoli 7354adc010SGuilherme G. Piccoli /* 7454adc010SGuilherme G. Piccoli * The controller needs a delay before starts checking the device 7554adc010SGuilherme G. Piccoli * readiness, which is done by reading the NVME_CSTS_RDY bit. 7654adc010SGuilherme G. Piccoli */ 7754adc010SGuilherme G. Piccoli NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3), 78c5552fdeSAndy Lutomirski 79c5552fdeSAndy Lutomirski /* 80c5552fdeSAndy Lutomirski * APST should not be used. 81c5552fdeSAndy Lutomirski */ 82c5552fdeSAndy Lutomirski NVME_QUIRK_NO_APST = (1 << 4), 83ff5350a8SAndy Lutomirski 84ff5350a8SAndy Lutomirski /* 85ff5350a8SAndy Lutomirski * The deepest sleep state should not be used. 86ff5350a8SAndy Lutomirski */ 87ff5350a8SAndy Lutomirski NVME_QUIRK_NO_DEEPEST_PS = (1 << 5), 88608cc4b1SChristoph Hellwig 89608cc4b1SChristoph Hellwig /* 909abd68efSJens Axboe * Set MEDIUM priority on SQ creation 919abd68efSJens Axboe */ 929abd68efSJens Axboe NVME_QUIRK_MEDIUM_PRIO_SQ = (1 << 7), 936299358dSJames Dingwall 946299358dSJames Dingwall /* 956299358dSJames Dingwall * Ignore device provided subnqn. 966299358dSJames Dingwall */ 976299358dSJames Dingwall NVME_QUIRK_IGNORE_DEV_SUBNQN = (1 << 8), 987b210e4eSChristoph Hellwig 997b210e4eSChristoph Hellwig /* 1007b210e4eSChristoph Hellwig * Broken Write Zeroes. 1017b210e4eSChristoph Hellwig */ 1027b210e4eSChristoph Hellwig NVME_QUIRK_DISABLE_WRITE_ZEROES = (1 << 9), 103cb32de1bSMario Limonciello 104cb32de1bSMario Limonciello /* 105cb32de1bSMario Limonciello * Force simple suspend/resume path. 106cb32de1bSMario Limonciello */ 107cb32de1bSMario Limonciello NVME_QUIRK_SIMPLE_SUSPEND = (1 << 10), 1087ad67ca5SLinus Torvalds 1097ad67ca5SLinus Torvalds /* 11066341331SBenjamin Herrenschmidt * Use only one interrupt vector for all queues 11166341331SBenjamin Herrenschmidt */ 1127ad67ca5SLinus Torvalds NVME_QUIRK_SINGLE_VECTOR = (1 << 11), 11366341331SBenjamin Herrenschmidt 11466341331SBenjamin Herrenschmidt /* 11566341331SBenjamin Herrenschmidt * Use non-standard 128 bytes SQEs. 11666341331SBenjamin Herrenschmidt */ 1177ad67ca5SLinus Torvalds NVME_QUIRK_128_BYTES_SQES = (1 << 12), 118d38e9f04SBenjamin Herrenschmidt 119d38e9f04SBenjamin Herrenschmidt /* 120d38e9f04SBenjamin Herrenschmidt * Prevent tag overlap between queues 121d38e9f04SBenjamin Herrenschmidt */ 1227ad67ca5SLinus Torvalds NVME_QUIRK_SHARED_TAGS = (1 << 13), 1236c6aa2f2SAkinobu Mita 1246c6aa2f2SAkinobu Mita /* 1256c6aa2f2SAkinobu Mita * Don't change the value of the temperature threshold feature 1266c6aa2f2SAkinobu Mita */ 1276c6aa2f2SAkinobu Mita NVME_QUIRK_NO_TEMP_THRESH_CHANGE = (1 << 14), 1285bedd3afSChristoph Hellwig 1295bedd3afSChristoph Hellwig /* 1305bedd3afSChristoph Hellwig * The controller doesn't handle the Identify Namespace 1315bedd3afSChristoph Hellwig * Identification Descriptor list subcommand despite claiming 1325bedd3afSChristoph Hellwig * NVMe 1.3 compliance. 1335bedd3afSChristoph Hellwig */ 1345bedd3afSChristoph Hellwig NVME_QUIRK_NO_NS_DESC_LIST = (1 << 15), 1354bdf2603SFilippo Sironi 1364bdf2603SFilippo Sironi /* 1374bdf2603SFilippo Sironi * The controller does not properly handle DMA addresses over 1384bdf2603SFilippo Sironi * 48 bits. 1394bdf2603SFilippo Sironi */ 1404bdf2603SFilippo Sironi NVME_QUIRK_DMA_ADDRESS_BITS_48 = (1 << 16), 141a2941f6aSKeith Busch 142a2941f6aSKeith Busch /* 143b7df575fSXiang wangx * The controller requires the command_id value be limited, so skip 144a2941f6aSKeith Busch * encoding the generation sequence number. 145a2941f6aSKeith Busch */ 146a2941f6aSKeith Busch NVME_QUIRK_SKIP_CID_GEN = (1 << 17), 14700ff400eSChristoph Hellwig 14800ff400eSChristoph Hellwig /* 14900ff400eSChristoph Hellwig * Reports garbage in the namespace identifiers (eui64, nguid, uuid). 15000ff400eSChristoph Hellwig */ 15100ff400eSChristoph Hellwig NVME_QUIRK_BOGUS_NID = (1 << 18), 152106198edSChristoph Hellwig }; 153106198edSChristoph Hellwig 154d49187e9SChristoph Hellwig /* 155d49187e9SChristoph Hellwig * Common request structure for NVMe passthrough. All drivers must have 156d49187e9SChristoph Hellwig * this structure as the first member of their request-private data. 157d49187e9SChristoph Hellwig */ 158d49187e9SChristoph Hellwig struct nvme_request { 159d49187e9SChristoph Hellwig struct nvme_command *cmd; 160d49187e9SChristoph Hellwig union nvme_result result; 161e7006de6SSagi Grimberg u8 genctr; 16244e44b29SChristoph Hellwig u8 retries; 16327fa9bc5SChristoph Hellwig u8 flags; 16427fa9bc5SChristoph Hellwig u16 status; 165d4d957b5SSagi Grimberg #ifdef CONFIG_NVME_MULTIPATH 166d4d957b5SSagi Grimberg unsigned long start_time; 167d4d957b5SSagi Grimberg #endif 16859e29ce6SSagi Grimberg struct nvme_ctrl *ctrl; 16927fa9bc5SChristoph Hellwig }; 17027fa9bc5SChristoph Hellwig 17132acab31SChristoph Hellwig /* 17232acab31SChristoph Hellwig * Mark a bio as coming in through the mpath node. 17332acab31SChristoph Hellwig */ 17432acab31SChristoph Hellwig #define REQ_NVME_MPATH REQ_DRV 17532acab31SChristoph Hellwig 17627fa9bc5SChristoph Hellwig enum { 17727fa9bc5SChristoph Hellwig NVME_REQ_CANCELLED = (1 << 0), 178bb06ec31SJames Smart NVME_REQ_USERCMD = (1 << 1), 179d4d957b5SSagi Grimberg NVME_MPATH_IO_STATS = (1 << 2), 180d49187e9SChristoph Hellwig }; 181d49187e9SChristoph Hellwig 182d49187e9SChristoph Hellwig static inline struct nvme_request *nvme_req(struct request *req) 183d49187e9SChristoph Hellwig { 184d49187e9SChristoph Hellwig return blk_mq_rq_to_pdu(req); 185d49187e9SChristoph Hellwig } 186d49187e9SChristoph Hellwig 1875d87eb94SKeith Busch static inline u16 nvme_req_qid(struct request *req) 1885d87eb94SKeith Busch { 189643c476dSKeith Busch if (!req->q->queuedata) 1905d87eb94SKeith Busch return 0; 19184115d6dSBaolin Wang 19284115d6dSBaolin Wang return req->mq_hctx->queue_num + 1; 1935d87eb94SKeith Busch } 1945d87eb94SKeith Busch 19554adc010SGuilherme G. Piccoli /* The below value is the specific amount of delay needed before checking 19654adc010SGuilherme G. Piccoli * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the 19754adc010SGuilherme G. Piccoli * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was 19854adc010SGuilherme G. Piccoli * found empirically. 19954adc010SGuilherme G. Piccoli */ 2008c97eeccSJeff Lien #define NVME_QUIRK_DELAY_AMOUNT 2300 20154adc010SGuilherme G. Piccoli 2024212f4e9SSagi Grimberg /* 2034212f4e9SSagi Grimberg * enum nvme_ctrl_state: Controller state 2044212f4e9SSagi Grimberg * 2054212f4e9SSagi Grimberg * @NVME_CTRL_NEW: New controller just allocated, initial state 2064212f4e9SSagi Grimberg * @NVME_CTRL_LIVE: Controller is connected and I/O capable 2074212f4e9SSagi Grimberg * @NVME_CTRL_RESETTING: Controller is resetting (or scheduled reset) 2084212f4e9SSagi Grimberg * @NVME_CTRL_CONNECTING: Controller is disconnected, now connecting the 2094212f4e9SSagi Grimberg * transport 2104212f4e9SSagi Grimberg * @NVME_CTRL_DELETING: Controller is deleting (or scheduled deletion) 211ecca390eSSagi Grimberg * @NVME_CTRL_DELETING_NOIO: Controller is deleting and I/O is not 212ecca390eSSagi Grimberg * disabled/failed immediately. This state comes 213ecca390eSSagi Grimberg * after all async event processing took place and 214ecca390eSSagi Grimberg * before ns removal and the controller deletion 215ecca390eSSagi Grimberg * progress 2164212f4e9SSagi Grimberg * @NVME_CTRL_DEAD: Controller is non-present/unresponsive during 2174212f4e9SSagi Grimberg * shutdown or removal. In this case we forcibly 2184212f4e9SSagi Grimberg * kill all inflight I/O as they have no chance to 2194212f4e9SSagi Grimberg * complete 2204212f4e9SSagi Grimberg */ 221bb8d261eSChristoph Hellwig enum nvme_ctrl_state { 222bb8d261eSChristoph Hellwig NVME_CTRL_NEW, 223bb8d261eSChristoph Hellwig NVME_CTRL_LIVE, 224bb8d261eSChristoph Hellwig NVME_CTRL_RESETTING, 225ad6a0a52SMax Gurtovoy NVME_CTRL_CONNECTING, 226bb8d261eSChristoph Hellwig NVME_CTRL_DELETING, 227ecca390eSSagi Grimberg NVME_CTRL_DELETING_NOIO, 2280ff9d4e1SKeith Busch NVME_CTRL_DEAD, 229bb8d261eSChristoph Hellwig }; 230bb8d261eSChristoph Hellwig 231a3646451SAkinobu Mita struct nvme_fault_inject { 232a3646451SAkinobu Mita #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS 233a3646451SAkinobu Mita struct fault_attr attr; 234a3646451SAkinobu Mita struct dentry *parent; 235a3646451SAkinobu Mita bool dont_retry; /* DNR, do not retry */ 236a3646451SAkinobu Mita u16 status; /* status code */ 237a3646451SAkinobu Mita #endif 238a3646451SAkinobu Mita }; 239a3646451SAkinobu Mita 240bf093d97SSagi Grimberg enum nvme_ctrl_flags { 241bf093d97SSagi Grimberg NVME_CTRL_FAILFAST_EXPIRED = 0, 242bf093d97SSagi Grimberg NVME_CTRL_ADMIN_Q_STOPPED = 1, 243f46ef9e8SSagi Grimberg NVME_CTRL_STARTED_ONCE = 2, 24498d81f0dSChao Leng NVME_CTRL_STOPPED = 3, 245bf093d97SSagi Grimberg }; 246bf093d97SSagi Grimberg 2471c63dc66SChristoph Hellwig struct nvme_ctrl { 2486e3ca03eSSagi Grimberg bool comp_seen; 249bd4da3abSAndy Lutomirski bool identified; 250*9d217fb0SChristophe JAILLET enum nvme_ctrl_state state; 251bb8d261eSChristoph Hellwig spinlock_t lock; 252e7ad43c3SKeith Busch struct mutex scan_lock; 2531c63dc66SChristoph Hellwig const struct nvme_ctrl_ops *ops; 25457dacad5SJay Sternberg struct request_queue *admin_q; 25507bfcd09SChristoph Hellwig struct request_queue *connect_q; 256e7832cb4SSagi Grimberg struct request_queue *fabrics_q; 25757dacad5SJay Sternberg struct device *dev; 25857dacad5SJay Sternberg int instance; 259103e515eSHannes Reinecke int numa_node; 2605bae7f73SChristoph Hellwig struct blk_mq_tag_set *tagset; 26134b6c231SSagi Grimberg struct blk_mq_tag_set *admin_tagset; 2625bae7f73SChristoph Hellwig struct list_head namespaces; 263765cc031SJianchao Wang struct rw_semaphore namespaces_rwsem; 264d22524a4SChristoph Hellwig struct device ctrl_device; 2655bae7f73SChristoph Hellwig struct device *device; /* char device */ 266ed7770f6SHannes Reinecke #ifdef CONFIG_NVME_HWMON 267ed7770f6SHannes Reinecke struct device *hwmon_device; 268ed7770f6SHannes Reinecke #endif 269a6a5149bSChristoph Hellwig struct cdev cdev; 270d86c4d8eSChristoph Hellwig struct work_struct reset_work; 271c5017e85SChristoph Hellwig struct work_struct delete_work; 272c1ac9a4bSKeith Busch wait_queue_head_t state_wq; 2731c63dc66SChristoph Hellwig 274ab9e00ccSChristoph Hellwig struct nvme_subsystem *subsys; 275ab9e00ccSChristoph Hellwig struct list_head subsys_entry; 276ab9e00ccSChristoph Hellwig 2774f1244c8SChristoph Hellwig struct opal_dev *opal_dev; 278a98e58e5SScott Bauer 27957dacad5SJay Sternberg char name[12]; 28076e3914aSChristoph Hellwig u16 cntlid; 2815fd4ce1bSChristoph Hellwig 282b6dccf7fSArnav Dawn u16 mtfa; 283*9d217fb0SChristophe JAILLET u32 ctrl_config; 284d858e5f0SSagi Grimberg u32 queue_count; 2855fd4ce1bSChristoph Hellwig 28620d0dfe6SSagi Grimberg u64 cap; 28757dacad5SJay Sternberg u32 max_hw_sectors; 288943e942eSJens Axboe u32 max_segments; 28995093350SMax Gurtovoy u32 max_integrity_segments; 2905befc7c2SKeith Busch u32 max_discard_sectors; 2915befc7c2SKeith Busch u32 max_discard_segments; 2925befc7c2SKeith Busch u32 max_zeroes_sectors; 293240e6ee2SKeith Busch #ifdef CONFIG_BLK_DEV_ZONED 294240e6ee2SKeith Busch u32 max_zone_append; 295240e6ee2SKeith Busch #endif 29649cd84b6SKeith Busch u16 crdt[3]; 29757dacad5SJay Sternberg u16 oncs; 2981a86924eSTom Yan u32 dmrsl; 2998a9ae523SScott Bauer u16 oacs; 300f968688fSKeith Busch u16 sqsize; 3010d0b660fSChristoph Hellwig u32 max_namespaces; 3026bf25d16SChristoph Hellwig atomic_t abort_limit; 30357dacad5SJay Sternberg u8 vwc; 304f3ca80fcSChristoph Hellwig u32 vs; 30507bfcd09SChristoph Hellwig u32 sgls; 306038bd4cbSSagi Grimberg u16 kas; 307c5552fdeSAndy Lutomirski u8 npss; 308c5552fdeSAndy Lutomirski u8 apsta; 309400b6a7bSGuenter Roeck u16 wctemp; 310400b6a7bSGuenter Roeck u16 cctemp; 311c0561f82SHannes Reinecke u32 oaes; 312e3d7874dSKeith Busch u32 aen_result; 3133e53ba38SSagi Grimberg u32 ctratt; 31407fbd32aSMartin K. Petersen unsigned int shutdown_timeout; 315038bd4cbSSagi Grimberg unsigned int kato; 316f3ca80fcSChristoph Hellwig bool subsystem; 317106198edSChristoph Hellwig unsigned long quirks; 318c5552fdeSAndy Lutomirski struct nvme_id_power_state psd[32]; 31984fef62dSKeith Busch struct nvme_effects_log *effects; 3201cf7a12eSChaitanya Kulkarni struct xarray cels; 3215955be21SChristoph Hellwig struct work_struct scan_work; 322f866fc42SChristoph Hellwig struct work_struct async_event_work; 323038bd4cbSSagi Grimberg struct delayed_work ka_work; 3248c4dfea9SVictor Gladkov struct delayed_work failfast_work; 3250a34e466SRoland Dreier struct nvme_command ka_cmd; 326b6dccf7fSArnav Dawn struct work_struct fw_act_work; 32730d90964SChristoph Hellwig unsigned long events; 32807bfcd09SChristoph Hellwig 3290d0b660fSChristoph Hellwig #ifdef CONFIG_NVME_MULTIPATH 3300d0b660fSChristoph Hellwig /* asymmetric namespace access: */ 3310d0b660fSChristoph Hellwig u8 anacap; 3320d0b660fSChristoph Hellwig u8 anatt; 3330d0b660fSChristoph Hellwig u32 anagrpmax; 3340d0b660fSChristoph Hellwig u32 nanagrpid; 3350d0b660fSChristoph Hellwig struct mutex ana_lock; 3360d0b660fSChristoph Hellwig struct nvme_ana_rsp_hdr *ana_log_buf; 3370d0b660fSChristoph Hellwig size_t ana_log_size; 3380d0b660fSChristoph Hellwig struct timer_list anatt_timer; 3390d0b660fSChristoph Hellwig struct work_struct ana_work; 3400d0b660fSChristoph Hellwig #endif 3410d0b660fSChristoph Hellwig 342f50fff73SHannes Reinecke #ifdef CONFIG_NVME_AUTH 343f50fff73SHannes Reinecke struct work_struct dhchap_auth_work; 344f50fff73SHannes Reinecke struct mutex dhchap_auth_mutex; 345aa36d711SSagi Grimberg struct nvme_dhchap_queue_context *dhchap_ctxs; 346f50fff73SHannes Reinecke struct nvme_dhchap_key *host_key; 347f50fff73SHannes Reinecke struct nvme_dhchap_key *ctrl_key; 348f50fff73SHannes Reinecke u16 transaction; 349f50fff73SHannes Reinecke #endif 350f50fff73SHannes Reinecke 351c5552fdeSAndy Lutomirski /* Power saving configuration */ 352c5552fdeSAndy Lutomirski u64 ps_max_latency_us; 35376a5af84SKai-Heng Feng bool apst_enabled; 354c5552fdeSAndy Lutomirski 355044a9df1SChristoph Hellwig /* PCIe only: */ 356*9d217fb0SChristophe JAILLET u16 hmmaxd; 357fe6d53c9SChristoph Hellwig u32 hmpre; 358fe6d53c9SChristoph Hellwig u32 hmmin; 359044a9df1SChristoph Hellwig u32 hmminds; 360fe6d53c9SChristoph Hellwig 36107bfcd09SChristoph Hellwig /* Fabrics only */ 36207bfcd09SChristoph Hellwig u32 ioccsz; 36307bfcd09SChristoph Hellwig u32 iorcsz; 36407bfcd09SChristoph Hellwig u16 icdoff; 36507bfcd09SChristoph Hellwig u16 maxcmd; 366fdf9dfa8SSagi Grimberg int nr_reconnects; 3678c4dfea9SVictor Gladkov unsigned long flags; 36807bfcd09SChristoph Hellwig struct nvmf_ctrl_options *opts; 369cb5b7262SJens Axboe 370cb5b7262SJens Axboe struct page *discard_page; 371cb5b7262SJens Axboe unsigned long discard_page_busy; 372f79d5fdaSAkinobu Mita 373f79d5fdaSAkinobu Mita struct nvme_fault_inject fault_inject; 37486c2457aSMartin Belanger 37586c2457aSMartin Belanger enum nvme_ctrl_type cntrltype; 37686c2457aSMartin Belanger enum nvme_dctype dctype; 37757dacad5SJay Sternberg }; 37857dacad5SJay Sternberg 37975c10e73SHannes Reinecke enum nvme_iopolicy { 38075c10e73SHannes Reinecke NVME_IOPOLICY_NUMA, 38175c10e73SHannes Reinecke NVME_IOPOLICY_RR, 38275c10e73SHannes Reinecke }; 38375c10e73SHannes Reinecke 384ab9e00ccSChristoph Hellwig struct nvme_subsystem { 385ab9e00ccSChristoph Hellwig int instance; 386ab9e00ccSChristoph Hellwig struct device dev; 387ab9e00ccSChristoph Hellwig /* 388ab9e00ccSChristoph Hellwig * Because we unregister the device on the last put we need 389ab9e00ccSChristoph Hellwig * a separate refcount. 390ab9e00ccSChristoph Hellwig */ 391ab9e00ccSChristoph Hellwig struct kref ref; 392ab9e00ccSChristoph Hellwig struct list_head entry; 393ab9e00ccSChristoph Hellwig struct mutex lock; 394ab9e00ccSChristoph Hellwig struct list_head ctrls; 395ed754e5dSChristoph Hellwig struct list_head nsheads; 396ab9e00ccSChristoph Hellwig char subnqn[NVMF_NQN_SIZE]; 397ab9e00ccSChristoph Hellwig char serial[20]; 398ab9e00ccSChristoph Hellwig char model[40]; 399ab9e00ccSChristoph Hellwig char firmware_rev[8]; 400ab9e00ccSChristoph Hellwig u8 cmic; 401954ae166SHannes Reinecke enum nvme_subsys_type subtype; 402ab9e00ccSChristoph Hellwig u16 vendor_id; 40381adb863SBart Van Assche u16 awupf; /* 0's based awupf value. */ 404ed754e5dSChristoph Hellwig struct ida ns_ida; 40575c10e73SHannes Reinecke #ifdef CONFIG_NVME_MULTIPATH 40675c10e73SHannes Reinecke enum nvme_iopolicy iopolicy; 40775c10e73SHannes Reinecke #endif 408ab9e00ccSChristoph Hellwig }; 409ab9e00ccSChristoph Hellwig 410002fab04SChristoph Hellwig /* 411002fab04SChristoph Hellwig * Container structure for uniqueue namespace identifiers. 412002fab04SChristoph Hellwig */ 413002fab04SChristoph Hellwig struct nvme_ns_ids { 414002fab04SChristoph Hellwig u8 eui64[8]; 415002fab04SChristoph Hellwig u8 nguid[16]; 416002fab04SChristoph Hellwig uuid_t uuid; 41771010c30SNiklas Cassel u8 csi; 418002fab04SChristoph Hellwig }; 419002fab04SChristoph Hellwig 420ed754e5dSChristoph Hellwig /* 421ed754e5dSChristoph Hellwig * Anchor structure for namespaces. There is one for each namespace in a 422ed754e5dSChristoph Hellwig * NVMe subsystem that any of our controllers can see, and the namespace 423ed754e5dSChristoph Hellwig * structure for each controller is chained of it. For private namespaces 424ed754e5dSChristoph Hellwig * there is a 1:1 relation to our namespace structures, that is ->list 425ed754e5dSChristoph Hellwig * only ever has a single entry for private namespaces. 426ed754e5dSChristoph Hellwig */ 427ed754e5dSChristoph Hellwig struct nvme_ns_head { 428ed754e5dSChristoph Hellwig struct list_head list; 429ed754e5dSChristoph Hellwig struct srcu_struct srcu; 430ed754e5dSChristoph Hellwig struct nvme_subsystem *subsys; 431ed754e5dSChristoph Hellwig unsigned ns_id; 432ed754e5dSChristoph Hellwig struct nvme_ns_ids ids; 433ed754e5dSChristoph Hellwig struct list_head entry; 434ed754e5dSChristoph Hellwig struct kref ref; 4350c284db7SKeith Busch bool shared; 436ed754e5dSChristoph Hellwig int instance; 437be93e87eSKeith Busch struct nvme_effects_log *effects; 4382637baedSMinwoo Im 4392637baedSMinwoo Im struct cdev cdev; 4402637baedSMinwoo Im struct device cdev_device; 4412637baedSMinwoo Im 442f3334447SChristoph Hellwig struct gendisk *disk; 44330897388SMinwoo Im #ifdef CONFIG_NVME_MULTIPATH 444f3334447SChristoph Hellwig struct bio_list requeue_list; 445f3334447SChristoph Hellwig spinlock_t requeue_lock; 446f3334447SChristoph Hellwig struct work_struct requeue_work; 447f3334447SChristoph Hellwig struct mutex lock; 448d8a22f85SAnton Eidelman unsigned long flags; 449d8a22f85SAnton Eidelman #define NVME_NSHEAD_DISK_LIVE 0 450f3334447SChristoph Hellwig struct nvme_ns __rcu *current_path[]; 451f3334447SChristoph Hellwig #endif 452ed754e5dSChristoph Hellwig }; 453ed754e5dSChristoph Hellwig 45430897388SMinwoo Im static inline bool nvme_ns_head_multipath(struct nvme_ns_head *head) 45530897388SMinwoo Im { 45630897388SMinwoo Im return IS_ENABLED(CONFIG_NVME_MULTIPATH) && head->disk; 45730897388SMinwoo Im } 45830897388SMinwoo Im 459ffc89b1dSMax Gurtovoy enum nvme_ns_features { 460ffc89b1dSMax Gurtovoy NVME_NS_EXT_LBAS = 1 << 0, /* support extended LBA format */ 461b29f8485SMax Gurtovoy NVME_NS_METADATA_SUPPORTED = 1 << 1, /* support getting generated md */ 4621b96f862SChristoph Hellwig NVME_NS_DEAC, /* DEAC bit in Write Zeores supported */ 463ffc89b1dSMax Gurtovoy }; 464ffc89b1dSMax Gurtovoy 46557dacad5SJay Sternberg struct nvme_ns { 46657dacad5SJay Sternberg struct list_head list; 46757dacad5SJay Sternberg 4681c63dc66SChristoph Hellwig struct nvme_ctrl *ctrl; 46957dacad5SJay Sternberg struct request_queue *queue; 47057dacad5SJay Sternberg struct gendisk *disk; 4710d0b660fSChristoph Hellwig #ifdef CONFIG_NVME_MULTIPATH 4720d0b660fSChristoph Hellwig enum nvme_ana_state ana_state; 4730d0b660fSChristoph Hellwig u32 ana_grpid; 4740d0b660fSChristoph Hellwig #endif 475ed754e5dSChristoph Hellwig struct list_head siblings; 47657dacad5SJay Sternberg struct kref kref; 477ed754e5dSChristoph Hellwig struct nvme_ns_head *head; 47857dacad5SJay Sternberg 47957dacad5SJay Sternberg int lba_shift; 48057dacad5SJay Sternberg u16 ms; 4814020aad8SKeith Busch u16 pi_size; 482f5d11840SJens Axboe u16 sgs; 483f5d11840SJens Axboe u32 sws; 48457dacad5SJay Sternberg u8 pi_type; 4854020aad8SKeith Busch u8 guard_type; 486240e6ee2SKeith Busch #ifdef CONFIG_BLK_DEV_ZONED 487240e6ee2SKeith Busch u64 zsze; 488240e6ee2SKeith Busch #endif 489ffc89b1dSMax Gurtovoy unsigned long features; 490646017a6SKeith Busch unsigned long flags; 491646017a6SKeith Busch #define NVME_NS_REMOVING 0 4920d0b660fSChristoph Hellwig #define NVME_NS_ANA_PENDING 2 4932f4c9ba2SJavier González #define NVME_NS_FORCE_RO 3 494e7d65803SHannes Reinecke #define NVME_NS_READY 4 495b9e03857SThomas Tai 4962637baedSMinwoo Im struct cdev cdev; 4972637baedSMinwoo Im struct device cdev_device; 4982637baedSMinwoo Im 499b9e03857SThomas Tai struct nvme_fault_inject fault_inject; 500b9e03857SThomas Tai 50157dacad5SJay Sternberg }; 50257dacad5SJay Sternberg 5034d2ce688SJames Smart /* NVMe ns supports metadata actions by the controller (generate/strip) */ 5044d2ce688SJames Smart static inline bool nvme_ns_has_pi(struct nvme_ns *ns) 5054d2ce688SJames Smart { 5064020aad8SKeith Busch return ns->pi_type && ns->ms == ns->pi_size; 5074d2ce688SJames Smart } 5084d2ce688SJames Smart 5091c63dc66SChristoph Hellwig struct nvme_ctrl_ops { 5101a353d85SMing Lin const char *name; 511e439bb12SSagi Grimberg struct module *module; 512d3d5b87dSChristoph Hellwig unsigned int flags; 513d3d5b87dSChristoph Hellwig #define NVME_F_FABRICS (1 << 0) 514c81bfba9SChristoph Hellwig #define NVME_F_METADATA_SUPPORTED (1 << 1) 515db45e1a5SChristoph Hellwig #define NVME_F_BLOCKING (1 << 2) 516db45e1a5SChristoph Hellwig 51786adbf0cSChristoph Hellwig const struct attribute_group **dev_attr_groups; 5181c63dc66SChristoph Hellwig int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val); 5195fd4ce1bSChristoph Hellwig int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val); 5207fd8930fSChristoph Hellwig int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val); 5211673f1f0SChristoph Hellwig void (*free_ctrl)(struct nvme_ctrl *ctrl); 522ad22c355SKeith Busch void (*submit_async_event)(struct nvme_ctrl *ctrl); 523c5017e85SChristoph Hellwig void (*delete_ctrl)(struct nvme_ctrl *ctrl); 524f7f70f4aSRuozhu Li void (*stop_ctrl)(struct nvme_ctrl *ctrl); 5251a353d85SMing Lin int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size); 5262f0dad17SKeith Busch void (*print_device_info)(struct nvme_ctrl *ctrl); 5272f859441SLogan Gunthorpe bool (*supports_pci_p2pdma)(struct nvme_ctrl *ctrl); 52857dacad5SJay Sternberg }; 52957dacad5SJay Sternberg 530e7006de6SSagi Grimberg /* 531e7006de6SSagi Grimberg * nvme command_id is constructed as such: 532e7006de6SSagi Grimberg * | xxxx | xxxxxxxxxxxx | 533e7006de6SSagi Grimberg * gen request tag 534e7006de6SSagi Grimberg */ 535e7006de6SSagi Grimberg #define nvme_genctr_mask(gen) (gen & 0xf) 536e7006de6SSagi Grimberg #define nvme_cid_install_genctr(gen) (nvme_genctr_mask(gen) << 12) 537e7006de6SSagi Grimberg #define nvme_genctr_from_cid(cid) ((cid & 0xf000) >> 12) 538e7006de6SSagi Grimberg #define nvme_tag_from_cid(cid) (cid & 0xfff) 539e7006de6SSagi Grimberg 540e7006de6SSagi Grimberg static inline u16 nvme_cid(struct request *rq) 541e7006de6SSagi Grimberg { 542e7006de6SSagi Grimberg return nvme_cid_install_genctr(nvme_req(rq)->genctr) | rq->tag; 543e7006de6SSagi Grimberg } 544e7006de6SSagi Grimberg 545e7006de6SSagi Grimberg static inline struct request *nvme_find_rq(struct blk_mq_tags *tags, 546e7006de6SSagi Grimberg u16 command_id) 547e7006de6SSagi Grimberg { 548e7006de6SSagi Grimberg u8 genctr = nvme_genctr_from_cid(command_id); 549e7006de6SSagi Grimberg u16 tag = nvme_tag_from_cid(command_id); 550e7006de6SSagi Grimberg struct request *rq; 551e7006de6SSagi Grimberg 552e7006de6SSagi Grimberg rq = blk_mq_tag_to_rq(tags, tag); 553e7006de6SSagi Grimberg if (unlikely(!rq)) { 554e7006de6SSagi Grimberg pr_err("could not locate request for tag %#x\n", 555e7006de6SSagi Grimberg tag); 556e7006de6SSagi Grimberg return NULL; 557e7006de6SSagi Grimberg } 558e7006de6SSagi Grimberg if (unlikely(nvme_genctr_mask(nvme_req(rq)->genctr) != genctr)) { 559e7006de6SSagi Grimberg dev_err(nvme_req(rq)->ctrl->device, 560e7006de6SSagi Grimberg "request %#x genctr mismatch (got %#x expected %#x)\n", 561e7006de6SSagi Grimberg tag, genctr, nvme_genctr_mask(nvme_req(rq)->genctr)); 562e7006de6SSagi Grimberg return NULL; 563e7006de6SSagi Grimberg } 564e7006de6SSagi Grimberg return rq; 565e7006de6SSagi Grimberg } 566e7006de6SSagi Grimberg 567e7006de6SSagi Grimberg static inline struct request *nvme_cid_to_rq(struct blk_mq_tags *tags, 568e7006de6SSagi Grimberg u16 command_id) 569e7006de6SSagi Grimberg { 570e7006de6SSagi Grimberg return blk_mq_tag_to_rq(tags, nvme_tag_from_cid(command_id)); 571e7006de6SSagi Grimberg } 572e7006de6SSagi Grimberg 5732f0dad17SKeith Busch /* 5742f0dad17SKeith Busch * Return the length of the string without the space padding 5752f0dad17SKeith Busch */ 5762f0dad17SKeith Busch static inline int nvme_strlen(char *s, int len) 5772f0dad17SKeith Busch { 5782f0dad17SKeith Busch while (s[len - 1] == ' ') 5792f0dad17SKeith Busch len--; 5802f0dad17SKeith Busch return len; 5812f0dad17SKeith Busch } 5822f0dad17SKeith Busch 5832f0dad17SKeith Busch static inline void nvme_print_device_info(struct nvme_ctrl *ctrl) 5842f0dad17SKeith Busch { 5852f0dad17SKeith Busch struct nvme_subsystem *subsys = ctrl->subsys; 5862f0dad17SKeith Busch 5872f0dad17SKeith Busch if (ctrl->ops->print_device_info) { 5882f0dad17SKeith Busch ctrl->ops->print_device_info(ctrl); 5892f0dad17SKeith Busch return; 5902f0dad17SKeith Busch } 5912f0dad17SKeith Busch 5922f0dad17SKeith Busch dev_err(ctrl->device, 5932f0dad17SKeith Busch "VID:%04x model:%.*s firmware:%.*s\n", subsys->vendor_id, 5942f0dad17SKeith Busch nvme_strlen(subsys->model, sizeof(subsys->model)), 5952f0dad17SKeith Busch subsys->model, nvme_strlen(subsys->firmware_rev, 5962f0dad17SKeith Busch sizeof(subsys->firmware_rev)), 5972f0dad17SKeith Busch subsys->firmware_rev); 5982f0dad17SKeith Busch } 5992f0dad17SKeith Busch 600b9e03857SThomas Tai #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS 601a3646451SAkinobu Mita void nvme_fault_inject_init(struct nvme_fault_inject *fault_inj, 602a3646451SAkinobu Mita const char *dev_name); 603a3646451SAkinobu Mita void nvme_fault_inject_fini(struct nvme_fault_inject *fault_inject); 604b9e03857SThomas Tai void nvme_should_fail(struct request *req); 605b9e03857SThomas Tai #else 606a3646451SAkinobu Mita static inline void nvme_fault_inject_init(struct nvme_fault_inject *fault_inj, 607a3646451SAkinobu Mita const char *dev_name) 608a3646451SAkinobu Mita { 609a3646451SAkinobu Mita } 610a3646451SAkinobu Mita static inline void nvme_fault_inject_fini(struct nvme_fault_inject *fault_inj) 611a3646451SAkinobu Mita { 612a3646451SAkinobu Mita } 613b9e03857SThomas Tai static inline void nvme_should_fail(struct request *req) {} 614b9e03857SThomas Tai #endif 615b9e03857SThomas Tai 6161e866afdSKeith Busch bool nvme_wait_reset(struct nvme_ctrl *ctrl); 6171e866afdSKeith Busch int nvme_try_sched_reset(struct nvme_ctrl *ctrl); 6181e866afdSKeith Busch 619f3ca80fcSChristoph Hellwig static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl) 620f3ca80fcSChristoph Hellwig { 6211e866afdSKeith Busch int ret; 6221e866afdSKeith Busch 623f3ca80fcSChristoph Hellwig if (!ctrl->subsystem) 624f3ca80fcSChristoph Hellwig return -ENOTTY; 6251e866afdSKeith Busch if (!nvme_wait_reset(ctrl)) 6261e866afdSKeith Busch return -EBUSY; 6271e866afdSKeith Busch 6281e866afdSKeith Busch ret = ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65); 6291e866afdSKeith Busch if (ret) 6301e866afdSKeith Busch return ret; 6311e866afdSKeith Busch 6321e866afdSKeith Busch return nvme_try_sched_reset(ctrl); 633f3ca80fcSChristoph Hellwig } 634f3ca80fcSChristoph Hellwig 635314d48ddSDamien Le Moal /* 636314d48ddSDamien Le Moal * Convert a 512B sector number to a device logical block number. 637314d48ddSDamien Le Moal */ 638314d48ddSDamien Le Moal static inline u64 nvme_sect_to_lba(struct nvme_ns *ns, sector_t sector) 63957dacad5SJay Sternberg { 640314d48ddSDamien Le Moal return sector >> (ns->lba_shift - SECTOR_SHIFT); 64157dacad5SJay Sternberg } 64257dacad5SJay Sternberg 643e08f2ae8SDamien Le Moal /* 644e08f2ae8SDamien Le Moal * Convert a device logical block number to a 512B sector number. 645e08f2ae8SDamien Le Moal */ 646e08f2ae8SDamien Le Moal static inline sector_t nvme_lba_to_sect(struct nvme_ns *ns, u64 lba) 647e08f2ae8SDamien Le Moal { 648e08f2ae8SDamien Le Moal return lba << (ns->lba_shift - SECTOR_SHIFT); 64957dacad5SJay Sternberg } 65057dacad5SJay Sternberg 65171fb90ebSKeith Busch /* 65271fb90ebSKeith Busch * Convert byte length to nvme's 0-based num dwords 65371fb90ebSKeith Busch */ 65471fb90ebSKeith Busch static inline u32 nvme_bytes_to_numd(size_t len) 65571fb90ebSKeith Busch { 65671fb90ebSKeith Busch return (len >> 2) - 1; 65771fb90ebSKeith Busch } 65871fb90ebSKeith Busch 6595ddaabe8SChristoph Hellwig static inline bool nvme_is_ana_error(u16 status) 6605ddaabe8SChristoph Hellwig { 6615ddaabe8SChristoph Hellwig switch (status & 0x7ff) { 6625ddaabe8SChristoph Hellwig case NVME_SC_ANA_TRANSITION: 6635ddaabe8SChristoph Hellwig case NVME_SC_ANA_INACCESSIBLE: 6645ddaabe8SChristoph Hellwig case NVME_SC_ANA_PERSISTENT_LOSS: 6655ddaabe8SChristoph Hellwig return true; 6665ddaabe8SChristoph Hellwig default: 6675ddaabe8SChristoph Hellwig return false; 6685ddaabe8SChristoph Hellwig } 6695ddaabe8SChristoph Hellwig } 6705ddaabe8SChristoph Hellwig 6715ddaabe8SChristoph Hellwig static inline bool nvme_is_path_error(u16 status) 6725ddaabe8SChristoph Hellwig { 6731e41f3bdSChristoph Hellwig /* check for a status code type of 'path related status' */ 6741e41f3bdSChristoph Hellwig return (status & 0x700) == 0x300; 6755ddaabe8SChristoph Hellwig } 6765ddaabe8SChristoph Hellwig 6772eb81a33SChristoph Hellwig /* 6782eb81a33SChristoph Hellwig * Fill in the status and result information from the CQE, and then figure out 6792eb81a33SChristoph Hellwig * if blk-mq will need to use IPI magic to complete the request, and if yes do 6802eb81a33SChristoph Hellwig * so. If not let the caller complete the request without an indirect function 6812eb81a33SChristoph Hellwig * call. 6822eb81a33SChristoph Hellwig */ 6832eb81a33SChristoph Hellwig static inline bool nvme_try_complete_req(struct request *req, __le16 status, 68427fa9bc5SChristoph Hellwig union nvme_result result) 68515a190f7SChristoph Hellwig { 68627fa9bc5SChristoph Hellwig struct nvme_request *rq = nvme_req(req); 687e4fdb2b1SKeith Busch struct nvme_ctrl *ctrl = rq->ctrl; 688e4fdb2b1SKeith Busch 689e4fdb2b1SKeith Busch if (!(ctrl->quirks & NVME_QUIRK_SKIP_CID_GEN)) 690e4fdb2b1SKeith Busch rq->genctr++; 69127fa9bc5SChristoph Hellwig 69227fa9bc5SChristoph Hellwig rq->status = le16_to_cpu(status) >> 1; 69327fa9bc5SChristoph Hellwig rq->result = result; 694b9e03857SThomas Tai /* inject error when permitted by fault injection framework */ 695b9e03857SThomas Tai nvme_should_fail(req); 696ff029451SChristoph Hellwig if (unlikely(blk_should_fake_timeout(req->q))) 697ff029451SChristoph Hellwig return true; 698ff029451SChristoph Hellwig return blk_mq_complete_request_remote(req); 69915a190f7SChristoph Hellwig } 70015a190f7SChristoph Hellwig 701d22524a4SChristoph Hellwig static inline void nvme_get_ctrl(struct nvme_ctrl *ctrl) 702d22524a4SChristoph Hellwig { 703d22524a4SChristoph Hellwig get_device(ctrl->device); 704d22524a4SChristoph Hellwig } 705d22524a4SChristoph Hellwig 706d22524a4SChristoph Hellwig static inline void nvme_put_ctrl(struct nvme_ctrl *ctrl) 707d22524a4SChristoph Hellwig { 708d22524a4SChristoph Hellwig put_device(ctrl->device); 709d22524a4SChristoph Hellwig } 710d22524a4SChristoph Hellwig 71158a8df67SIsrael Rukshin static inline bool nvme_is_aen_req(u16 qid, __u16 command_id) 71258a8df67SIsrael Rukshin { 713e7006de6SSagi Grimberg return !qid && 714e7006de6SSagi Grimberg nvme_tag_from_cid(command_id) >= NVME_AQ_BLK_MQ_DEPTH; 71558a8df67SIsrael Rukshin } 71658a8df67SIsrael Rukshin 71777f02a7aSChristoph Hellwig void nvme_complete_rq(struct request *req); 718c234a653SJens Axboe void nvme_complete_batch_req(struct request *req); 719c234a653SJens Axboe 720c234a653SJens Axboe static __always_inline void nvme_complete_batch(struct io_comp_batch *iob, 721c234a653SJens Axboe void (*fn)(struct request *rq)) 722c234a653SJens Axboe { 723c234a653SJens Axboe struct request *req; 724c234a653SJens Axboe 725c234a653SJens Axboe rq_list_for_each(&iob->req_list, req) { 726c234a653SJens Axboe fn(req); 727c234a653SJens Axboe nvme_complete_batch_req(req); 728c234a653SJens Axboe } 729c234a653SJens Axboe blk_mq_end_request_batch(iob); 730c234a653SJens Axboe } 731c234a653SJens Axboe 732dda3248eSChao Leng blk_status_t nvme_host_path_error(struct request *req); 7332dd6532eSJohn Garry bool nvme_cancel_request(struct request *req, void *data); 73425479069SChao Leng void nvme_cancel_tagset(struct nvme_ctrl *ctrl); 73525479069SChao Leng void nvme_cancel_admin_tagset(struct nvme_ctrl *ctrl); 736bb8d261eSChristoph Hellwig bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl, 737bb8d261eSChristoph Hellwig enum nvme_ctrl_state new_state); 738285b6e9bSChristoph Hellwig int nvme_disable_ctrl(struct nvme_ctrl *ctrl, bool shutdown); 739c0f2f45bSSagi Grimberg int nvme_enable_ctrl(struct nvme_ctrl *ctrl); 740f3ca80fcSChristoph Hellwig int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev, 741f3ca80fcSChristoph Hellwig const struct nvme_ctrl_ops *ops, unsigned long quirks); 74253029b04SKeith Busch void nvme_uninit_ctrl(struct nvme_ctrl *ctrl); 743d09f2b45SSagi Grimberg void nvme_start_ctrl(struct nvme_ctrl *ctrl); 744d09f2b45SSagi Grimberg void nvme_stop_ctrl(struct nvme_ctrl *ctrl); 74594cc781fSChristoph Hellwig int nvme_init_ctrl_finish(struct nvme_ctrl *ctrl, bool was_suspended); 746fe60e8c5SChristoph Hellwig int nvme_alloc_admin_tag_set(struct nvme_ctrl *ctrl, struct blk_mq_tag_set *set, 747db45e1a5SChristoph Hellwig const struct blk_mq_ops *ops, unsigned int cmd_size); 748fe60e8c5SChristoph Hellwig void nvme_remove_admin_tag_set(struct nvme_ctrl *ctrl); 749fe60e8c5SChristoph Hellwig int nvme_alloc_io_tag_set(struct nvme_ctrl *ctrl, struct blk_mq_tag_set *set, 750db45e1a5SChristoph Hellwig const struct blk_mq_ops *ops, unsigned int nr_maps, 751db45e1a5SChristoph Hellwig unsigned int cmd_size); 752fe60e8c5SChristoph Hellwig void nvme_remove_io_tag_set(struct nvme_ctrl *ctrl); 7535bae7f73SChristoph Hellwig 7545bae7f73SChristoph Hellwig void nvme_remove_namespaces(struct nvme_ctrl *ctrl); 7551673f1f0SChristoph Hellwig 7567bf58533SChristoph Hellwig void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status, 757287a63ebSChristoph Hellwig volatile union nvme_result *res); 758f866fc42SChristoph Hellwig 7599f27bd70SChristoph Hellwig void nvme_quiesce_io_queues(struct nvme_ctrl *ctrl); 7609f27bd70SChristoph Hellwig void nvme_unquiesce_io_queues(struct nvme_ctrl *ctrl); 7619f27bd70SChristoph Hellwig void nvme_quiesce_admin_queue(struct nvme_ctrl *ctrl); 7629f27bd70SChristoph Hellwig void nvme_unquiesce_admin_queue(struct nvme_ctrl *ctrl); 763cd50f9b2SChristoph Hellwig void nvme_mark_namespaces_dead(struct nvme_ctrl *ctrl); 764d6135c3aSKeith Busch void nvme_sync_queues(struct nvme_ctrl *ctrl); 76504800fbfSChao Leng void nvme_sync_io_queues(struct nvme_ctrl *ctrl); 766302ad8ccSKeith Busch void nvme_unfreeze(struct nvme_ctrl *ctrl); 767302ad8ccSKeith Busch void nvme_wait_freeze(struct nvme_ctrl *ctrl); 7687cf0d7c0SSagi Grimberg int nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout); 769302ad8ccSKeith Busch void nvme_start_freeze(struct nvme_ctrl *ctrl); 770363c9aacSSagi Grimberg 771f9ed86dcSBart Van Assche static inline enum req_op nvme_req_op(struct nvme_command *cmd) 772e559398fSChristoph Hellwig { 773e559398fSChristoph Hellwig return nvme_is_write(cmd) ? REQ_OP_DRV_OUT : REQ_OP_DRV_IN; 774e559398fSChristoph Hellwig } 775e559398fSChristoph Hellwig 776eb71f435SChristoph Hellwig #define NVME_QID_ANY -1 777e559398fSChristoph Hellwig void nvme_init_request(struct request *req, struct nvme_command *cmd); 778f7f1fc36SMax Gurtovoy void nvme_cleanup_cmd(struct request *req); 779f4b9e6c9SKeith Busch blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req); 780a9715744STao Chiu blk_status_t nvme_fail_nonready_command(struct nvme_ctrl *ctrl, 781a9715744STao Chiu struct request *req); 782a9715744STao Chiu bool __nvme_check_ready(struct nvme_ctrl *ctrl, struct request *rq, 783a9715744STao Chiu bool queue_live); 784a9715744STao Chiu 785a9715744STao Chiu static inline bool nvme_check_ready(struct nvme_ctrl *ctrl, struct request *rq, 786a9715744STao Chiu bool queue_live) 787a9715744STao Chiu { 788a9715744STao Chiu if (likely(ctrl->state == NVME_CTRL_LIVE)) 789a9715744STao Chiu return true; 790a9715744STao Chiu if (ctrl->ops->flags & NVME_F_FABRICS && 791a9715744STao Chiu ctrl->state == NVME_CTRL_DELETING) 7928b77fa6fSRuozhu Li return queue_live; 793a9715744STao Chiu return __nvme_check_ready(ctrl, rq, queue_live); 794a9715744STao Chiu } 7955974ea7cSSungup Moon 7965974ea7cSSungup Moon /* 7975974ea7cSSungup Moon * NSID shall be unique for all shared namespaces, or if at least one of the 7985974ea7cSSungup Moon * following conditions is met: 7995974ea7cSSungup Moon * 1. Namespace Management is supported by the controller 8005974ea7cSSungup Moon * 2. ANA is supported by the controller 8015974ea7cSSungup Moon * 3. NVM Set are supported by the controller 8025974ea7cSSungup Moon * 8035974ea7cSSungup Moon * In other case, private namespace are not required to report a unique NSID. 8045974ea7cSSungup Moon */ 8055974ea7cSSungup Moon static inline bool nvme_is_unique_nsid(struct nvme_ctrl *ctrl, 8065974ea7cSSungup Moon struct nvme_ns_head *head) 8075974ea7cSSungup Moon { 8085974ea7cSSungup Moon return head->shared || 8095974ea7cSSungup Moon (ctrl->oacs & NVME_CTRL_OACS_NS_MNGT_SUPP) || 8105974ea7cSSungup Moon (ctrl->subsys->cmic & NVME_CTRL_CMIC_ANA) || 8115974ea7cSSungup Moon (ctrl->ctratt & NVME_CTRL_CTRATT_NVM_SETS); 8125974ea7cSSungup Moon } 8135974ea7cSSungup Moon 81457dacad5SJay Sternberg int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, 81557dacad5SJay Sternberg void *buf, unsigned bufflen); 81657dacad5SJay Sternberg int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, 817d49187e9SChristoph Hellwig union nvme_result *result, void *buffer, unsigned bufflen, 8186b46fa02SChaitanya Kulkarni int qid, int at_head, 819be42a33bSKeith Busch blk_mq_req_flags_t flags); 8201a87ee65SKeith Busch int nvme_set_features(struct nvme_ctrl *dev, unsigned int fid, 8211a87ee65SKeith Busch unsigned int dword11, void *buffer, size_t buflen, 8221a87ee65SKeith Busch u32 *result); 8231a87ee65SKeith Busch int nvme_get_features(struct nvme_ctrl *dev, unsigned int fid, 8241a87ee65SKeith Busch unsigned int dword11, void *buffer, size_t buflen, 8251a87ee65SKeith Busch u32 *result); 8269a0be7abSChristoph Hellwig int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count); 827038bd4cbSSagi Grimberg void nvme_stop_keep_alive(struct nvme_ctrl *ctrl); 828d86c4d8eSChristoph Hellwig int nvme_reset_ctrl(struct nvme_ctrl *ctrl); 8292405252aSChristoph Hellwig int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl); 830c5017e85SChristoph Hellwig int nvme_delete_ctrl(struct nvme_ctrl *ctrl); 8312405252aSChristoph Hellwig void nvme_queue_scan(struct nvme_ctrl *ctrl); 832be93e87eSKeith Busch int nvme_get_log(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, u8 lsp, u8 csi, 8330e98719bSChristoph Hellwig void *log, size_t size, u64 offset); 8341496bd49SChristoph Hellwig bool nvme_tryget_ns_head(struct nvme_ns_head *head); 8351496bd49SChristoph Hellwig void nvme_put_ns_head(struct nvme_ns_head *head); 8362637baedSMinwoo Im int nvme_cdev_add(struct cdev *cdev, struct device *cdev_device, 8372637baedSMinwoo Im const struct file_operations *fops, struct module *owner); 8382637baedSMinwoo Im void nvme_cdev_del(struct cdev *cdev, struct device *cdev_device); 83905bdb996SChristoph Hellwig int nvme_ioctl(struct block_device *bdev, blk_mode_t mode, 8402405252aSChristoph Hellwig unsigned int cmd, unsigned long arg); 8412637baedSMinwoo Im long nvme_ns_chr_ioctl(struct file *file, unsigned int cmd, unsigned long arg); 84205bdb996SChristoph Hellwig int nvme_ns_head_ioctl(struct block_device *bdev, blk_mode_t mode, 8432405252aSChristoph Hellwig unsigned int cmd, unsigned long arg); 8442637baedSMinwoo Im long nvme_ns_head_chr_ioctl(struct file *file, unsigned int cmd, 8452637baedSMinwoo Im unsigned long arg); 8462405252aSChristoph Hellwig long nvme_dev_ioctl(struct file *file, unsigned int cmd, 8472405252aSChristoph Hellwig unsigned long arg); 848de97fcb3SJens Axboe int nvme_ns_chr_uring_cmd_iopoll(struct io_uring_cmd *ioucmd, 849de97fcb3SJens Axboe struct io_comp_batch *iob, unsigned int poll_flags); 850de97fcb3SJens Axboe int nvme_ns_head_chr_uring_cmd_iopoll(struct io_uring_cmd *ioucmd, 851de97fcb3SJens Axboe struct io_comp_batch *iob, unsigned int poll_flags); 852456cba38SKanchan Joshi int nvme_ns_chr_uring_cmd(struct io_uring_cmd *ioucmd, 853456cba38SKanchan Joshi unsigned int issue_flags); 854456cba38SKanchan Joshi int nvme_ns_head_chr_uring_cmd(struct io_uring_cmd *ioucmd, 855456cba38SKanchan Joshi unsigned int issue_flags); 8561496bd49SChristoph Hellwig int nvme_getgeo(struct block_device *bdev, struct hd_geometry *geo); 85758e5bdebSKanchan Joshi int nvme_dev_uring_cmd(struct io_uring_cmd *ioucmd, unsigned int issue_flags); 858d558fb51SMatias Bjørling 85933b14f67SHannes Reinecke extern const struct attribute_group *nvme_ns_id_attr_groups[]; 8601496bd49SChristoph Hellwig extern const struct pr_ops nvme_pr_ops; 86132acab31SChristoph Hellwig extern const struct block_device_operations nvme_ns_head_ops; 86286adbf0cSChristoph Hellwig extern const struct attribute_group nvme_dev_attrs_group; 86332acab31SChristoph Hellwig 864f1cf35e1SChristoph Hellwig struct nvme_ns *nvme_find_path(struct nvme_ns_head *head); 86532acab31SChristoph Hellwig #ifdef CONFIG_NVME_MULTIPATH 86666b20ac0SMarta Rybczynska static inline bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl) 86766b20ac0SMarta Rybczynska { 86866b20ac0SMarta Rybczynska return ctrl->ana_log_buf != NULL; 86966b20ac0SMarta Rybczynska } 87066b20ac0SMarta Rybczynska 871b9156daeSSagi Grimberg void nvme_mpath_unfreeze(struct nvme_subsystem *subsys); 872b9156daeSSagi Grimberg void nvme_mpath_wait_freeze(struct nvme_subsystem *subsys); 873b9156daeSSagi Grimberg void nvme_mpath_start_freeze(struct nvme_subsystem *subsys); 874e3d34794SHannes Reinecke void nvme_mpath_default_iopolicy(struct nvme_subsystem *subsys); 8755ddaabe8SChristoph Hellwig void nvme_failover_req(struct request *req); 87632acab31SChristoph Hellwig void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl); 87732acab31SChristoph Hellwig int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl,struct nvme_ns_head *head); 878c13cf14fSJoel Granados void nvme_mpath_add_disk(struct nvme_ns *ns, __le32 anagrpid); 87932acab31SChristoph Hellwig void nvme_mpath_remove_disk(struct nvme_ns_head *head); 8805e1f6899SChristoph Hellwig int nvme_mpath_init_identify(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id); 8815e1f6899SChristoph Hellwig void nvme_mpath_init_ctrl(struct nvme_ctrl *ctrl); 882a4a6f3c8SAnton Eidelman void nvme_mpath_update(struct nvme_ctrl *ctrl); 8830d0b660fSChristoph Hellwig void nvme_mpath_uninit(struct nvme_ctrl *ctrl); 8840d0b660fSChristoph Hellwig void nvme_mpath_stop(struct nvme_ctrl *ctrl); 8850157ec8dSSagi Grimberg bool nvme_mpath_clear_current_path(struct nvme_ns *ns); 886e7d65803SHannes Reinecke void nvme_mpath_revalidate_paths(struct nvme_ns *ns); 8870157ec8dSSagi Grimberg void nvme_mpath_clear_ctrl_paths(struct nvme_ctrl *ctrl); 8885396fdacSHannes Reinecke void nvme_mpath_shutdown_disk(struct nvme_ns_head *head); 889d4d957b5SSagi Grimberg void nvme_mpath_start_request(struct request *rq); 890d4d957b5SSagi Grimberg void nvme_mpath_end_request(struct request *rq); 891479a322fSSagi Grimberg 8922b59787aSMax Gurtovoy static inline void nvme_trace_bio_complete(struct request *req) 89335fe0d12SHannes Reinecke { 89435fe0d12SHannes Reinecke struct nvme_ns *ns = req->q->queuedata; 89535fe0d12SHannes Reinecke 8963659fb5aSYanjun Zhang if ((req->cmd_flags & REQ_NVME_MPATH) && req->bio) 897d24de76aSChristoph Hellwig trace_block_bio_complete(ns->head->disk->queue, req->bio); 89835fe0d12SHannes Reinecke } 89935fe0d12SHannes Reinecke 900b739e137SChristoph Hellwig extern bool multipath; 9010d0b660fSChristoph Hellwig extern struct device_attribute dev_attr_ana_grpid; 9020d0b660fSChristoph Hellwig extern struct device_attribute dev_attr_ana_state; 90375c10e73SHannes Reinecke extern struct device_attribute subsys_attr_iopolicy; 9040d0b660fSChristoph Hellwig 90532acab31SChristoph Hellwig #else 906b739e137SChristoph Hellwig #define multipath false 9070d0b660fSChristoph Hellwig static inline bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl) 9080d0b660fSChristoph Hellwig { 9090d0b660fSChristoph Hellwig return false; 9100d0b660fSChristoph Hellwig } 9115ddaabe8SChristoph Hellwig static inline void nvme_failover_req(struct request *req) 91232acab31SChristoph Hellwig { 91332acab31SChristoph Hellwig } 91432acab31SChristoph Hellwig static inline void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl) 91532acab31SChristoph Hellwig { 91632acab31SChristoph Hellwig } 91732acab31SChristoph Hellwig static inline int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl, 91832acab31SChristoph Hellwig struct nvme_ns_head *head) 91932acab31SChristoph Hellwig { 92032acab31SChristoph Hellwig return 0; 92132acab31SChristoph Hellwig } 922c13cf14fSJoel Granados static inline void nvme_mpath_add_disk(struct nvme_ns *ns, __le32 anagrpid) 92332acab31SChristoph Hellwig { 92432acab31SChristoph Hellwig } 92532acab31SChristoph Hellwig static inline void nvme_mpath_remove_disk(struct nvme_ns_head *head) 92632acab31SChristoph Hellwig { 92732acab31SChristoph Hellwig } 9280157ec8dSSagi Grimberg static inline bool nvme_mpath_clear_current_path(struct nvme_ns *ns) 9290157ec8dSSagi Grimberg { 9300157ec8dSSagi Grimberg return false; 9310157ec8dSSagi Grimberg } 932e7d65803SHannes Reinecke static inline void nvme_mpath_revalidate_paths(struct nvme_ns *ns) 933e7d65803SHannes Reinecke { 934e7d65803SHannes Reinecke } 9350157ec8dSSagi Grimberg static inline void nvme_mpath_clear_ctrl_paths(struct nvme_ctrl *ctrl) 93632acab31SChristoph Hellwig { 93732acab31SChristoph Hellwig } 9385396fdacSHannes Reinecke static inline void nvme_mpath_shutdown_disk(struct nvme_ns_head *head) 939479a322fSSagi Grimberg { 940479a322fSSagi Grimberg } 9412b59787aSMax Gurtovoy static inline void nvme_trace_bio_complete(struct request *req) 94235fe0d12SHannes Reinecke { 94335fe0d12SHannes Reinecke } 9445e1f6899SChristoph Hellwig static inline void nvme_mpath_init_ctrl(struct nvme_ctrl *ctrl) 9455e1f6899SChristoph Hellwig { 9465e1f6899SChristoph Hellwig } 9475e1f6899SChristoph Hellwig static inline int nvme_mpath_init_identify(struct nvme_ctrl *ctrl, 9480d0b660fSChristoph Hellwig struct nvme_id_ctrl *id) 9490d0b660fSChristoph Hellwig { 9502bd64307SKanchan Joshi if (ctrl->subsys->cmic & NVME_CTRL_CMIC_ANA) 95114a1336eSChristoph Hellwig dev_warn(ctrl->device, 95214a1336eSChristoph Hellwig "Please enable CONFIG_NVME_MULTIPATH for full support of multi-port devices.\n"); 9530d0b660fSChristoph Hellwig return 0; 9540d0b660fSChristoph Hellwig } 955a4a6f3c8SAnton Eidelman static inline void nvme_mpath_update(struct nvme_ctrl *ctrl) 956a4a6f3c8SAnton Eidelman { 957a4a6f3c8SAnton Eidelman } 9580d0b660fSChristoph Hellwig static inline void nvme_mpath_uninit(struct nvme_ctrl *ctrl) 9590d0b660fSChristoph Hellwig { 9600d0b660fSChristoph Hellwig } 9610d0b660fSChristoph Hellwig static inline void nvme_mpath_stop(struct nvme_ctrl *ctrl) 9620d0b660fSChristoph Hellwig { 9630d0b660fSChristoph Hellwig } 964b9156daeSSagi Grimberg static inline void nvme_mpath_unfreeze(struct nvme_subsystem *subsys) 965b9156daeSSagi Grimberg { 966b9156daeSSagi Grimberg } 967b9156daeSSagi Grimberg static inline void nvme_mpath_wait_freeze(struct nvme_subsystem *subsys) 968b9156daeSSagi Grimberg { 969b9156daeSSagi Grimberg } 970b9156daeSSagi Grimberg static inline void nvme_mpath_start_freeze(struct nvme_subsystem *subsys) 971b9156daeSSagi Grimberg { 972b9156daeSSagi Grimberg } 973e3d34794SHannes Reinecke static inline void nvme_mpath_default_iopolicy(struct nvme_subsystem *subsys) 974e3d34794SHannes Reinecke { 975e3d34794SHannes Reinecke } 976d4d957b5SSagi Grimberg static inline void nvme_mpath_start_request(struct request *rq) 977d4d957b5SSagi Grimberg { 978d4d957b5SSagi Grimberg } 979d4d957b5SSagi Grimberg static inline void nvme_mpath_end_request(struct request *rq) 980d4d957b5SSagi Grimberg { 981d4d957b5SSagi Grimberg } 98232acab31SChristoph Hellwig #endif /* CONFIG_NVME_MULTIPATH */ 98332acab31SChristoph Hellwig 9847fad20ddSChristoph Hellwig int nvme_revalidate_zones(struct nvme_ns *ns); 9858b4fb0f9SChristoph Hellwig int nvme_ns_report_zones(struct nvme_ns *ns, sector_t sector, 9868b4fb0f9SChristoph Hellwig unsigned int nr_zones, report_zones_cb cb, void *data); 987240e6ee2SKeith Busch #ifdef CONFIG_BLK_DEV_ZONED 988d525c3c0SChristoph Hellwig int nvme_update_zone_info(struct nvme_ns *ns, unsigned lbaf); 989240e6ee2SKeith Busch blk_status_t nvme_setup_zone_mgmt_send(struct nvme_ns *ns, struct request *req, 990240e6ee2SKeith Busch struct nvme_command *cmnd, 991240e6ee2SKeith Busch enum nvme_zone_mgmt_action action); 992240e6ee2SKeith Busch #else 993240e6ee2SKeith Busch static inline blk_status_t nvme_setup_zone_mgmt_send(struct nvme_ns *ns, 994240e6ee2SKeith Busch struct request *req, struct nvme_command *cmnd, 995240e6ee2SKeith Busch enum nvme_zone_mgmt_action action) 996240e6ee2SKeith Busch { 997240e6ee2SKeith Busch return BLK_STS_NOTSUPP; 998240e6ee2SKeith Busch } 999240e6ee2SKeith Busch 1000d525c3c0SChristoph Hellwig static inline int nvme_update_zone_info(struct nvme_ns *ns, unsigned lbaf) 1001240e6ee2SKeith Busch { 1002240e6ee2SKeith Busch dev_warn(ns->ctrl->device, 1003240e6ee2SKeith Busch "Please enable CONFIG_BLK_DEV_ZONED to support ZNS devices\n"); 1004240e6ee2SKeith Busch return -EPROTONOSUPPORT; 1005240e6ee2SKeith Busch } 1006240e6ee2SKeith Busch #endif 1007240e6ee2SKeith Busch 100840267efdSSimon A. F. Lund static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev) 100940267efdSSimon A. F. Lund { 101040267efdSSimon A. F. Lund return dev_to_disk(dev)->private_data; 101140267efdSSimon A. F. Lund } 1012ca064085SMatias Bjørling 1013400b6a7bSGuenter Roeck #ifdef CONFIG_NVME_HWMON 101459e330f8SKeith Busch int nvme_hwmon_init(struct nvme_ctrl *ctrl); 1015ed7770f6SHannes Reinecke void nvme_hwmon_exit(struct nvme_ctrl *ctrl); 1016400b6a7bSGuenter Roeck #else 101759e330f8SKeith Busch static inline int nvme_hwmon_init(struct nvme_ctrl *ctrl) 101859e330f8SKeith Busch { 101959e330f8SKeith Busch return 0; 102059e330f8SKeith Busch } 1021ed7770f6SHannes Reinecke 1022ed7770f6SHannes Reinecke static inline void nvme_hwmon_exit(struct nvme_ctrl *ctrl) 1023ed7770f6SHannes Reinecke { 1024ed7770f6SHannes Reinecke } 1025400b6a7bSGuenter Roeck #endif 1026400b6a7bSGuenter Roeck 10276887fc64SSagi Grimberg static inline void nvme_start_request(struct request *rq) 10286887fc64SSagi Grimberg { 1029d4d957b5SSagi Grimberg if (rq->cmd_flags & REQ_NVME_MPATH) 1030d4d957b5SSagi Grimberg nvme_mpath_start_request(rq); 10316887fc64SSagi Grimberg blk_mq_start_request(rq); 10326887fc64SSagi Grimberg } 10336887fc64SSagi Grimberg 103473eefc27SChaitanya Kulkarni static inline bool nvme_ctrl_sgl_supported(struct nvme_ctrl *ctrl) 103573eefc27SChaitanya Kulkarni { 103673eefc27SChaitanya Kulkarni return ctrl->sgls & ((1 << 0) | (1 << 1)); 103773eefc27SChaitanya Kulkarni } 103873eefc27SChaitanya Kulkarni 1039f50fff73SHannes Reinecke #ifdef CONFIG_NVME_AUTH 1040e481fc0aSSagi Grimberg int __init nvme_init_auth(void); 1041e481fc0aSSagi Grimberg void __exit nvme_exit_auth(void); 1042193a8c7eSSagi Grimberg int nvme_auth_init_ctrl(struct nvme_ctrl *ctrl); 1043f50fff73SHannes Reinecke void nvme_auth_stop(struct nvme_ctrl *ctrl); 1044f50fff73SHannes Reinecke int nvme_auth_negotiate(struct nvme_ctrl *ctrl, int qid); 1045f50fff73SHannes Reinecke int nvme_auth_wait(struct nvme_ctrl *ctrl, int qid); 1046f50fff73SHannes Reinecke void nvme_auth_free(struct nvme_ctrl *ctrl); 1047f50fff73SHannes Reinecke #else 1048193a8c7eSSagi Grimberg static inline int nvme_auth_init_ctrl(struct nvme_ctrl *ctrl) 1049193a8c7eSSagi Grimberg { 1050193a8c7eSSagi Grimberg return 0; 1051193a8c7eSSagi Grimberg } 1052e481fc0aSSagi Grimberg static inline int __init nvme_init_auth(void) 1053e481fc0aSSagi Grimberg { 1054e481fc0aSSagi Grimberg return 0; 1055e481fc0aSSagi Grimberg } 1056e481fc0aSSagi Grimberg static inline void __exit nvme_exit_auth(void) 1057e481fc0aSSagi Grimberg { 1058e481fc0aSSagi Grimberg } 1059f50fff73SHannes Reinecke static inline void nvme_auth_stop(struct nvme_ctrl *ctrl) {}; 1060f50fff73SHannes Reinecke static inline int nvme_auth_negotiate(struct nvme_ctrl *ctrl, int qid) 1061f50fff73SHannes Reinecke { 1062f50fff73SHannes Reinecke return -EPROTONOSUPPORT; 1063f50fff73SHannes Reinecke } 1064f50fff73SHannes Reinecke static inline int nvme_auth_wait(struct nvme_ctrl *ctrl, int qid) 1065f50fff73SHannes Reinecke { 1066f50fff73SHannes Reinecke return NVME_SC_AUTH_REQUIRED; 1067f50fff73SHannes Reinecke } 1068f50fff73SHannes Reinecke static inline void nvme_auth_free(struct nvme_ctrl *ctrl) {}; 1069f50fff73SHannes Reinecke #endif 1070f50fff73SHannes Reinecke 1071df21b6b1SLogan Gunthorpe u32 nvme_command_effects(struct nvme_ctrl *ctrl, struct nvme_ns *ns, 1072df21b6b1SLogan Gunthorpe u8 opcode); 107362281b9eSChristoph Hellwig u32 nvme_passthru_start(struct nvme_ctrl *ctrl, struct nvme_ns *ns, u8 opcode); 107462281b9eSChristoph Hellwig int nvme_execute_rq(struct request *rq, bool at_head); 1075bc8fb906SKeith Busch void nvme_passthru_end(struct nvme_ctrl *ctrl, u32 effects, 1076bc8fb906SKeith Busch struct nvme_command *cmd, int status); 1077b2702aaaSChaitanya Kulkarni struct nvme_ctrl *nvme_ctrl_from_file(struct file *file); 107824493b8bSLogan Gunthorpe struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid); 107924493b8bSLogan Gunthorpe void nvme_put_ns(struct nvme_ns *ns); 1080df21b6b1SLogan Gunthorpe 108143dc9878SAdam Manzanares static inline bool nvme_multi_css(struct nvme_ctrl *ctrl) 108243dc9878SAdam Manzanares { 108343dc9878SAdam Manzanares return (ctrl->ctrl_config & NVME_CC_CSS_MASK) == NVME_CC_CSS_CSI; 108443dc9878SAdam Manzanares } 108543dc9878SAdam Manzanares 1086bd83fe6fSAlan Adamson #ifdef CONFIG_NVME_VERBOSE_ERRORS 1087bd83fe6fSAlan Adamson const unsigned char *nvme_get_error_status_str(u16 status); 1088bd83fe6fSAlan Adamson const unsigned char *nvme_get_opcode_str(u8 opcode); 1089bd83fe6fSAlan Adamson const unsigned char *nvme_get_admin_opcode_str(u8 opcode); 1090567da14dSAmit Engel const unsigned char *nvme_get_fabrics_opcode_str(u8 opcode); 1091bd83fe6fSAlan Adamson #else /* CONFIG_NVME_VERBOSE_ERRORS */ 1092bd83fe6fSAlan Adamson static inline const unsigned char *nvme_get_error_status_str(u16 status) 1093bd83fe6fSAlan Adamson { 1094bd83fe6fSAlan Adamson return "I/O Error"; 1095bd83fe6fSAlan Adamson } 1096bd83fe6fSAlan Adamson static inline const unsigned char *nvme_get_opcode_str(u8 opcode) 1097bd83fe6fSAlan Adamson { 1098bd83fe6fSAlan Adamson return "I/O Cmd"; 1099bd83fe6fSAlan Adamson } 1100bd83fe6fSAlan Adamson static inline const unsigned char *nvme_get_admin_opcode_str(u8 opcode) 1101bd83fe6fSAlan Adamson { 1102bd83fe6fSAlan Adamson return "Admin Cmd"; 1103bd83fe6fSAlan Adamson } 1104567da14dSAmit Engel 1105567da14dSAmit Engel static inline const unsigned char *nvme_get_fabrics_opcode_str(u8 opcode) 1106567da14dSAmit Engel { 1107567da14dSAmit Engel return "Fabrics Cmd"; 1108567da14dSAmit Engel } 1109bd83fe6fSAlan Adamson #endif /* CONFIG_NVME_VERBOSE_ERRORS */ 1110bd83fe6fSAlan Adamson 1111567da14dSAmit Engel static inline const unsigned char *nvme_opcode_str(int qid, u8 opcode, u8 fctype) 1112567da14dSAmit Engel { 1113567da14dSAmit Engel if (opcode == nvme_fabrics_command) 1114567da14dSAmit Engel return nvme_get_fabrics_opcode_str(fctype); 1115567da14dSAmit Engel return qid ? nvme_get_opcode_str(opcode) : 1116567da14dSAmit Engel nvme_get_admin_opcode_str(opcode); 1117567da14dSAmit Engel } 111857dacad5SJay Sternberg #endif /* _NVME_H */ 1119