1bc50ad75SChristoph Hellwig /* SPDX-License-Identifier: GPL-2.0 */ 257dacad5SJay Sternberg /* 357dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 457dacad5SJay Sternberg */ 557dacad5SJay Sternberg 657dacad5SJay Sternberg #ifndef _NVME_H 757dacad5SJay Sternberg #define _NVME_H 857dacad5SJay Sternberg 957dacad5SJay Sternberg #include <linux/nvme.h> 10a6a5149bSChristoph Hellwig #include <linux/cdev.h> 1157dacad5SJay Sternberg #include <linux/pci.h> 1257dacad5SJay Sternberg #include <linux/kref.h> 1357dacad5SJay Sternberg #include <linux/blk-mq.h> 14b0b4e09cSMatias Bjørling #include <linux/lightnvm.h> 15a98e58e5SScott Bauer #include <linux/sed-opal.h> 16b9e03857SThomas Tai #include <linux/fault-inject.h> 17978628ecSJohannes Thumshirn #include <linux/rcupdate.h> 1857dacad5SJay Sternberg 198ae4e447SMarc Olson extern unsigned int nvme_io_timeout; 2057dacad5SJay Sternberg #define NVME_IO_TIMEOUT (nvme_io_timeout * HZ) 2157dacad5SJay Sternberg 228ae4e447SMarc Olson extern unsigned int admin_timeout; 2321d34711SChristoph Hellwig #define ADMIN_TIMEOUT (admin_timeout * HZ) 2421d34711SChristoph Hellwig 25038bd4cbSSagi Grimberg #define NVME_DEFAULT_KATO 5 26038bd4cbSSagi Grimberg #define NVME_KATO_GRACE 10 27038bd4cbSSagi Grimberg 289a6327d2SSagi Grimberg extern struct workqueue_struct *nvme_wq; 29b227c59bSRoy Shterman extern struct workqueue_struct *nvme_reset_wq; 30b227c59bSRoy Shterman extern struct workqueue_struct *nvme_delete_wq; 319a6327d2SSagi Grimberg 32ca064085SMatias Bjørling enum { 33ca064085SMatias Bjørling NVME_NS_LBA = 0, 34ca064085SMatias Bjørling NVME_NS_LIGHTNVM = 1, 35ca064085SMatias Bjørling }; 36ca064085SMatias Bjørling 3757dacad5SJay Sternberg /* 38106198edSChristoph Hellwig * List of workarounds for devices that required behavior not specified in 39106198edSChristoph Hellwig * the standard. 4057dacad5SJay Sternberg */ 41106198edSChristoph Hellwig enum nvme_quirks { 42106198edSChristoph Hellwig /* 43106198edSChristoph Hellwig * Prefers I/O aligned to a stripe size specified in a vendor 44106198edSChristoph Hellwig * specific Identify field. 45106198edSChristoph Hellwig */ 46106198edSChristoph Hellwig NVME_QUIRK_STRIPE_SIZE = (1 << 0), 47540c801cSKeith Busch 48540c801cSKeith Busch /* 49540c801cSKeith Busch * The controller doesn't handle Identify value others than 0 or 1 50540c801cSKeith Busch * correctly. 51540c801cSKeith Busch */ 52540c801cSKeith Busch NVME_QUIRK_IDENTIFY_CNS = (1 << 1), 5308095e70SKeith Busch 5408095e70SKeith Busch /* 55e850fd16SChristoph Hellwig * The controller deterministically returns O's on reads to 56e850fd16SChristoph Hellwig * logical blocks that deallocate was called on. 5708095e70SKeith Busch */ 58e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES = (1 << 2), 5954adc010SGuilherme G. Piccoli 6054adc010SGuilherme G. Piccoli /* 6154adc010SGuilherme G. Piccoli * The controller needs a delay before starts checking the device 6254adc010SGuilherme G. Piccoli * readiness, which is done by reading the NVME_CSTS_RDY bit. 6354adc010SGuilherme G. Piccoli */ 6454adc010SGuilherme G. Piccoli NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3), 65c5552fdeSAndy Lutomirski 66c5552fdeSAndy Lutomirski /* 67c5552fdeSAndy Lutomirski * APST should not be used. 68c5552fdeSAndy Lutomirski */ 69c5552fdeSAndy Lutomirski NVME_QUIRK_NO_APST = (1 << 4), 70ff5350a8SAndy Lutomirski 71ff5350a8SAndy Lutomirski /* 72ff5350a8SAndy Lutomirski * The deepest sleep state should not be used. 73ff5350a8SAndy Lutomirski */ 74ff5350a8SAndy Lutomirski NVME_QUIRK_NO_DEEPEST_PS = (1 << 5), 75608cc4b1SChristoph Hellwig 76608cc4b1SChristoph Hellwig /* 77608cc4b1SChristoph Hellwig * Supports the LighNVM command set if indicated in vs[1]. 78608cc4b1SChristoph Hellwig */ 79608cc4b1SChristoph Hellwig NVME_QUIRK_LIGHTNVM = (1 << 6), 809abd68efSJens Axboe 819abd68efSJens Axboe /* 829abd68efSJens Axboe * Set MEDIUM priority on SQ creation 839abd68efSJens Axboe */ 849abd68efSJens Axboe NVME_QUIRK_MEDIUM_PRIO_SQ = (1 << 7), 856299358dSJames Dingwall 866299358dSJames Dingwall /* 876299358dSJames Dingwall * Ignore device provided subnqn. 886299358dSJames Dingwall */ 896299358dSJames Dingwall NVME_QUIRK_IGNORE_DEV_SUBNQN = (1 << 8), 90*7b210e4eSChristoph Hellwig 91*7b210e4eSChristoph Hellwig /* 92*7b210e4eSChristoph Hellwig * Broken Write Zeroes. 93*7b210e4eSChristoph Hellwig */ 94*7b210e4eSChristoph Hellwig NVME_QUIRK_DISABLE_WRITE_ZEROES = (1 << 9), 95106198edSChristoph Hellwig }; 96106198edSChristoph Hellwig 97d49187e9SChristoph Hellwig /* 98d49187e9SChristoph Hellwig * Common request structure for NVMe passthrough. All drivers must have 99d49187e9SChristoph Hellwig * this structure as the first member of their request-private data. 100d49187e9SChristoph Hellwig */ 101d49187e9SChristoph Hellwig struct nvme_request { 102d49187e9SChristoph Hellwig struct nvme_command *cmd; 103d49187e9SChristoph Hellwig union nvme_result result; 10444e44b29SChristoph Hellwig u8 retries; 10527fa9bc5SChristoph Hellwig u8 flags; 10627fa9bc5SChristoph Hellwig u16 status; 10759e29ce6SSagi Grimberg struct nvme_ctrl *ctrl; 10827fa9bc5SChristoph Hellwig }; 10927fa9bc5SChristoph Hellwig 11032acab31SChristoph Hellwig /* 11132acab31SChristoph Hellwig * Mark a bio as coming in through the mpath node. 11232acab31SChristoph Hellwig */ 11332acab31SChristoph Hellwig #define REQ_NVME_MPATH REQ_DRV 11432acab31SChristoph Hellwig 11527fa9bc5SChristoph Hellwig enum { 11627fa9bc5SChristoph Hellwig NVME_REQ_CANCELLED = (1 << 0), 117bb06ec31SJames Smart NVME_REQ_USERCMD = (1 << 1), 118d49187e9SChristoph Hellwig }; 119d49187e9SChristoph Hellwig 120d49187e9SChristoph Hellwig static inline struct nvme_request *nvme_req(struct request *req) 121d49187e9SChristoph Hellwig { 122d49187e9SChristoph Hellwig return blk_mq_rq_to_pdu(req); 123d49187e9SChristoph Hellwig } 124d49187e9SChristoph Hellwig 1255d87eb94SKeith Busch static inline u16 nvme_req_qid(struct request *req) 1265d87eb94SKeith Busch { 1275d87eb94SKeith Busch if (!req->rq_disk) 1285d87eb94SKeith Busch return 0; 1295d87eb94SKeith Busch return blk_mq_unique_tag_to_hwq(blk_mq_unique_tag(req)) + 1; 1305d87eb94SKeith Busch } 1315d87eb94SKeith Busch 13254adc010SGuilherme G. Piccoli /* The below value is the specific amount of delay needed before checking 13354adc010SGuilherme G. Piccoli * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the 13454adc010SGuilherme G. Piccoli * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was 13554adc010SGuilherme G. Piccoli * found empirically. 13654adc010SGuilherme G. Piccoli */ 1378c97eeccSJeff Lien #define NVME_QUIRK_DELAY_AMOUNT 2300 13854adc010SGuilherme G. Piccoli 139bb8d261eSChristoph Hellwig enum nvme_ctrl_state { 140bb8d261eSChristoph Hellwig NVME_CTRL_NEW, 141bb8d261eSChristoph Hellwig NVME_CTRL_LIVE, 1422b1b7e78SJianchao Wang NVME_CTRL_ADMIN_ONLY, /* Only admin queue live */ 143bb8d261eSChristoph Hellwig NVME_CTRL_RESETTING, 144ad6a0a52SMax Gurtovoy NVME_CTRL_CONNECTING, 145bb8d261eSChristoph Hellwig NVME_CTRL_DELETING, 1460ff9d4e1SKeith Busch NVME_CTRL_DEAD, 147bb8d261eSChristoph Hellwig }; 148bb8d261eSChristoph Hellwig 1491c63dc66SChristoph Hellwig struct nvme_ctrl { 1506e3ca03eSSagi Grimberg bool comp_seen; 151bb8d261eSChristoph Hellwig enum nvme_ctrl_state state; 152bd4da3abSAndy Lutomirski bool identified; 153bb8d261eSChristoph Hellwig spinlock_t lock; 154e7ad43c3SKeith Busch struct mutex scan_lock; 1551c63dc66SChristoph Hellwig const struct nvme_ctrl_ops *ops; 15657dacad5SJay Sternberg struct request_queue *admin_q; 15707bfcd09SChristoph Hellwig struct request_queue *connect_q; 15857dacad5SJay Sternberg struct device *dev; 15957dacad5SJay Sternberg int instance; 160103e515eSHannes Reinecke int numa_node; 1615bae7f73SChristoph Hellwig struct blk_mq_tag_set *tagset; 16234b6c231SSagi Grimberg struct blk_mq_tag_set *admin_tagset; 1635bae7f73SChristoph Hellwig struct list_head namespaces; 164765cc031SJianchao Wang struct rw_semaphore namespaces_rwsem; 165d22524a4SChristoph Hellwig struct device ctrl_device; 1665bae7f73SChristoph Hellwig struct device *device; /* char device */ 167a6a5149bSChristoph Hellwig struct cdev cdev; 168d86c4d8eSChristoph Hellwig struct work_struct reset_work; 169c5017e85SChristoph Hellwig struct work_struct delete_work; 1701c63dc66SChristoph Hellwig 171ab9e00ccSChristoph Hellwig struct nvme_subsystem *subsys; 172ab9e00ccSChristoph Hellwig struct list_head subsys_entry; 173ab9e00ccSChristoph Hellwig 1744f1244c8SChristoph Hellwig struct opal_dev *opal_dev; 175a98e58e5SScott Bauer 17657dacad5SJay Sternberg char name[12]; 17776e3914aSChristoph Hellwig u16 cntlid; 1785fd4ce1bSChristoph Hellwig 1795fd4ce1bSChristoph Hellwig u32 ctrl_config; 180b6dccf7fSArnav Dawn u16 mtfa; 181d858e5f0SSagi Grimberg u32 queue_count; 1825fd4ce1bSChristoph Hellwig 18320d0dfe6SSagi Grimberg u64 cap; 1845fd4ce1bSChristoph Hellwig u32 page_size; 18557dacad5SJay Sternberg u32 max_hw_sectors; 186943e942eSJens Axboe u32 max_segments; 18749cd84b6SKeith Busch u16 crdt[3]; 18857dacad5SJay Sternberg u16 oncs; 1898a9ae523SScott Bauer u16 oacs; 190f5d11840SJens Axboe u16 nssa; 191f5d11840SJens Axboe u16 nr_streams; 1920d0b660fSChristoph Hellwig u32 max_namespaces; 1936bf25d16SChristoph Hellwig atomic_t abort_limit; 19457dacad5SJay Sternberg u8 vwc; 195f3ca80fcSChristoph Hellwig u32 vs; 19607bfcd09SChristoph Hellwig u32 sgls; 197038bd4cbSSagi Grimberg u16 kas; 198c5552fdeSAndy Lutomirski u8 npss; 199c5552fdeSAndy Lutomirski u8 apsta; 200c0561f82SHannes Reinecke u32 oaes; 201e3d7874dSKeith Busch u32 aen_result; 2023e53ba38SSagi Grimberg u32 ctratt; 20307fbd32aSMartin K. Petersen unsigned int shutdown_timeout; 204038bd4cbSSagi Grimberg unsigned int kato; 205f3ca80fcSChristoph Hellwig bool subsystem; 206106198edSChristoph Hellwig unsigned long quirks; 207c5552fdeSAndy Lutomirski struct nvme_id_power_state psd[32]; 20884fef62dSKeith Busch struct nvme_effects_log *effects; 2095955be21SChristoph Hellwig struct work_struct scan_work; 210f866fc42SChristoph Hellwig struct work_struct async_event_work; 211038bd4cbSSagi Grimberg struct delayed_work ka_work; 2120a34e466SRoland Dreier struct nvme_command ka_cmd; 213b6dccf7fSArnav Dawn struct work_struct fw_act_work; 21430d90964SChristoph Hellwig unsigned long events; 21507bfcd09SChristoph Hellwig 2160d0b660fSChristoph Hellwig #ifdef CONFIG_NVME_MULTIPATH 2170d0b660fSChristoph Hellwig /* asymmetric namespace access: */ 2180d0b660fSChristoph Hellwig u8 anacap; 2190d0b660fSChristoph Hellwig u8 anatt; 2200d0b660fSChristoph Hellwig u32 anagrpmax; 2210d0b660fSChristoph Hellwig u32 nanagrpid; 2220d0b660fSChristoph Hellwig struct mutex ana_lock; 2230d0b660fSChristoph Hellwig struct nvme_ana_rsp_hdr *ana_log_buf; 2240d0b660fSChristoph Hellwig size_t ana_log_size; 2250d0b660fSChristoph Hellwig struct timer_list anatt_timer; 2260d0b660fSChristoph Hellwig struct work_struct ana_work; 2270d0b660fSChristoph Hellwig #endif 2280d0b660fSChristoph Hellwig 229c5552fdeSAndy Lutomirski /* Power saving configuration */ 230c5552fdeSAndy Lutomirski u64 ps_max_latency_us; 23176a5af84SKai-Heng Feng bool apst_enabled; 232c5552fdeSAndy Lutomirski 233044a9df1SChristoph Hellwig /* PCIe only: */ 234fe6d53c9SChristoph Hellwig u32 hmpre; 235fe6d53c9SChristoph Hellwig u32 hmmin; 236044a9df1SChristoph Hellwig u32 hmminds; 237044a9df1SChristoph Hellwig u16 hmmaxd; 238fe6d53c9SChristoph Hellwig 23907bfcd09SChristoph Hellwig /* Fabrics only */ 24007bfcd09SChristoph Hellwig u16 sqsize; 24107bfcd09SChristoph Hellwig u32 ioccsz; 24207bfcd09SChristoph Hellwig u32 iorcsz; 24307bfcd09SChristoph Hellwig u16 icdoff; 24407bfcd09SChristoph Hellwig u16 maxcmd; 245fdf9dfa8SSagi Grimberg int nr_reconnects; 24607bfcd09SChristoph Hellwig struct nvmf_ctrl_options *opts; 247cb5b7262SJens Axboe 248cb5b7262SJens Axboe struct page *discard_page; 249cb5b7262SJens Axboe unsigned long discard_page_busy; 25057dacad5SJay Sternberg }; 25157dacad5SJay Sternberg 25275c10e73SHannes Reinecke enum nvme_iopolicy { 25375c10e73SHannes Reinecke NVME_IOPOLICY_NUMA, 25475c10e73SHannes Reinecke NVME_IOPOLICY_RR, 25575c10e73SHannes Reinecke }; 25675c10e73SHannes Reinecke 257ab9e00ccSChristoph Hellwig struct nvme_subsystem { 258ab9e00ccSChristoph Hellwig int instance; 259ab9e00ccSChristoph Hellwig struct device dev; 260ab9e00ccSChristoph Hellwig /* 261ab9e00ccSChristoph Hellwig * Because we unregister the device on the last put we need 262ab9e00ccSChristoph Hellwig * a separate refcount. 263ab9e00ccSChristoph Hellwig */ 264ab9e00ccSChristoph Hellwig struct kref ref; 265ab9e00ccSChristoph Hellwig struct list_head entry; 266ab9e00ccSChristoph Hellwig struct mutex lock; 267ab9e00ccSChristoph Hellwig struct list_head ctrls; 268ed754e5dSChristoph Hellwig struct list_head nsheads; 269ab9e00ccSChristoph Hellwig char subnqn[NVMF_NQN_SIZE]; 270ab9e00ccSChristoph Hellwig char serial[20]; 271ab9e00ccSChristoph Hellwig char model[40]; 272ab9e00ccSChristoph Hellwig char firmware_rev[8]; 273ab9e00ccSChristoph Hellwig u8 cmic; 274ab9e00ccSChristoph Hellwig u16 vendor_id; 275ed754e5dSChristoph Hellwig struct ida ns_ida; 27675c10e73SHannes Reinecke #ifdef CONFIG_NVME_MULTIPATH 27775c10e73SHannes Reinecke enum nvme_iopolicy iopolicy; 27875c10e73SHannes Reinecke #endif 279ab9e00ccSChristoph Hellwig }; 280ab9e00ccSChristoph Hellwig 281002fab04SChristoph Hellwig /* 282002fab04SChristoph Hellwig * Container structure for uniqueue namespace identifiers. 283002fab04SChristoph Hellwig */ 284002fab04SChristoph Hellwig struct nvme_ns_ids { 285002fab04SChristoph Hellwig u8 eui64[8]; 286002fab04SChristoph Hellwig u8 nguid[16]; 287002fab04SChristoph Hellwig uuid_t uuid; 288002fab04SChristoph Hellwig }; 289002fab04SChristoph Hellwig 290ed754e5dSChristoph Hellwig /* 291ed754e5dSChristoph Hellwig * Anchor structure for namespaces. There is one for each namespace in a 292ed754e5dSChristoph Hellwig * NVMe subsystem that any of our controllers can see, and the namespace 293ed754e5dSChristoph Hellwig * structure for each controller is chained of it. For private namespaces 294ed754e5dSChristoph Hellwig * there is a 1:1 relation to our namespace structures, that is ->list 295ed754e5dSChristoph Hellwig * only ever has a single entry for private namespaces. 296ed754e5dSChristoph Hellwig */ 297ed754e5dSChristoph Hellwig struct nvme_ns_head { 298ed754e5dSChristoph Hellwig struct list_head list; 299ed754e5dSChristoph Hellwig struct srcu_struct srcu; 300ed754e5dSChristoph Hellwig struct nvme_subsystem *subsys; 301ed754e5dSChristoph Hellwig unsigned ns_id; 302ed754e5dSChristoph Hellwig struct nvme_ns_ids ids; 303ed754e5dSChristoph Hellwig struct list_head entry; 304ed754e5dSChristoph Hellwig struct kref ref; 305ed754e5dSChristoph Hellwig int instance; 306f3334447SChristoph Hellwig #ifdef CONFIG_NVME_MULTIPATH 307f3334447SChristoph Hellwig struct gendisk *disk; 308f3334447SChristoph Hellwig struct bio_list requeue_list; 309f3334447SChristoph Hellwig spinlock_t requeue_lock; 310f3334447SChristoph Hellwig struct work_struct requeue_work; 311f3334447SChristoph Hellwig struct mutex lock; 312f3334447SChristoph Hellwig struct nvme_ns __rcu *current_path[]; 313f3334447SChristoph Hellwig #endif 314ed754e5dSChristoph Hellwig }; 315ed754e5dSChristoph Hellwig 316b9e03857SThomas Tai #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS 317b9e03857SThomas Tai struct nvme_fault_inject { 318b9e03857SThomas Tai struct fault_attr attr; 319b9e03857SThomas Tai struct dentry *parent; 320b9e03857SThomas Tai bool dont_retry; /* DNR, do not retry */ 321b9e03857SThomas Tai u16 status; /* status code */ 322b9e03857SThomas Tai }; 323b9e03857SThomas Tai #endif 324b9e03857SThomas Tai 32557dacad5SJay Sternberg struct nvme_ns { 32657dacad5SJay Sternberg struct list_head list; 32757dacad5SJay Sternberg 3281c63dc66SChristoph Hellwig struct nvme_ctrl *ctrl; 32957dacad5SJay Sternberg struct request_queue *queue; 33057dacad5SJay Sternberg struct gendisk *disk; 3310d0b660fSChristoph Hellwig #ifdef CONFIG_NVME_MULTIPATH 3320d0b660fSChristoph Hellwig enum nvme_ana_state ana_state; 3330d0b660fSChristoph Hellwig u32 ana_grpid; 3340d0b660fSChristoph Hellwig #endif 335ed754e5dSChristoph Hellwig struct list_head siblings; 336b0b4e09cSMatias Bjørling struct nvm_dev *ndev; 33757dacad5SJay Sternberg struct kref kref; 338ed754e5dSChristoph Hellwig struct nvme_ns_head *head; 33957dacad5SJay Sternberg 34057dacad5SJay Sternberg int lba_shift; 34157dacad5SJay Sternberg u16 ms; 342f5d11840SJens Axboe u16 sgs; 343f5d11840SJens Axboe u32 sws; 34457dacad5SJay Sternberg bool ext; 34557dacad5SJay Sternberg u8 pi_type; 346646017a6SKeith Busch unsigned long flags; 347646017a6SKeith Busch #define NVME_NS_REMOVING 0 34869d9a99cSKeith Busch #define NVME_NS_DEAD 1 3490d0b660fSChristoph Hellwig #define NVME_NS_ANA_PENDING 2 35057eeaf8eSChristoph Hellwig u16 noiob; 351b9e03857SThomas Tai 352b9e03857SThomas Tai #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS 353b9e03857SThomas Tai struct nvme_fault_inject fault_inject; 354b9e03857SThomas Tai #endif 355b9e03857SThomas Tai 35657dacad5SJay Sternberg }; 35757dacad5SJay Sternberg 3581c63dc66SChristoph Hellwig struct nvme_ctrl_ops { 3591a353d85SMing Lin const char *name; 360e439bb12SSagi Grimberg struct module *module; 361d3d5b87dSChristoph Hellwig unsigned int flags; 362d3d5b87dSChristoph Hellwig #define NVME_F_FABRICS (1 << 0) 363c81bfba9SChristoph Hellwig #define NVME_F_METADATA_SUPPORTED (1 << 1) 364e0596ab2SLogan Gunthorpe #define NVME_F_PCI_P2PDMA (1 << 2) 3651c63dc66SChristoph Hellwig int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val); 3665fd4ce1bSChristoph Hellwig int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val); 3677fd8930fSChristoph Hellwig int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val); 3681673f1f0SChristoph Hellwig void (*free_ctrl)(struct nvme_ctrl *ctrl); 369ad22c355SKeith Busch void (*submit_async_event)(struct nvme_ctrl *ctrl); 370c5017e85SChristoph Hellwig void (*delete_ctrl)(struct nvme_ctrl *ctrl); 3711a353d85SMing Lin int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size); 37257dacad5SJay Sternberg }; 37357dacad5SJay Sternberg 374b9e03857SThomas Tai #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS 375b9e03857SThomas Tai void nvme_fault_inject_init(struct nvme_ns *ns); 376b9e03857SThomas Tai void nvme_fault_inject_fini(struct nvme_ns *ns); 377b9e03857SThomas Tai void nvme_should_fail(struct request *req); 378b9e03857SThomas Tai #else 379b9e03857SThomas Tai static inline void nvme_fault_inject_init(struct nvme_ns *ns) {} 380b9e03857SThomas Tai static inline void nvme_fault_inject_fini(struct nvme_ns *ns) {} 381b9e03857SThomas Tai static inline void nvme_should_fail(struct request *req) {} 382b9e03857SThomas Tai #endif 383b9e03857SThomas Tai 384f3ca80fcSChristoph Hellwig static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl) 385f3ca80fcSChristoph Hellwig { 386f3ca80fcSChristoph Hellwig if (!ctrl->subsystem) 387f3ca80fcSChristoph Hellwig return -ENOTTY; 388f3ca80fcSChristoph Hellwig return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65); 389f3ca80fcSChristoph Hellwig } 390f3ca80fcSChristoph Hellwig 39157dacad5SJay Sternberg static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector) 39257dacad5SJay Sternberg { 39357dacad5SJay Sternberg return (sector >> (ns->lba_shift - 9)); 39457dacad5SJay Sternberg } 39557dacad5SJay Sternberg 39627fa9bc5SChristoph Hellwig static inline void nvme_end_request(struct request *req, __le16 status, 39727fa9bc5SChristoph Hellwig union nvme_result result) 39815a190f7SChristoph Hellwig { 39927fa9bc5SChristoph Hellwig struct nvme_request *rq = nvme_req(req); 40027fa9bc5SChristoph Hellwig 40127fa9bc5SChristoph Hellwig rq->status = le16_to_cpu(status) >> 1; 40227fa9bc5SChristoph Hellwig rq->result = result; 403b9e03857SThomas Tai /* inject error when permitted by fault injection framework */ 404b9e03857SThomas Tai nvme_should_fail(req); 40508e0029aSChristoph Hellwig blk_mq_complete_request(req); 40615a190f7SChristoph Hellwig } 40715a190f7SChristoph Hellwig 408d22524a4SChristoph Hellwig static inline void nvme_get_ctrl(struct nvme_ctrl *ctrl) 409d22524a4SChristoph Hellwig { 410d22524a4SChristoph Hellwig get_device(ctrl->device); 411d22524a4SChristoph Hellwig } 412d22524a4SChristoph Hellwig 413d22524a4SChristoph Hellwig static inline void nvme_put_ctrl(struct nvme_ctrl *ctrl) 414d22524a4SChristoph Hellwig { 415d22524a4SChristoph Hellwig put_device(ctrl->device); 416d22524a4SChristoph Hellwig } 417d22524a4SChristoph Hellwig 41877f02a7aSChristoph Hellwig void nvme_complete_rq(struct request *req); 4197baa8572SJens Axboe bool nvme_cancel_request(struct request *req, void *data, bool reserved); 420bb8d261eSChristoph Hellwig bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl, 421bb8d261eSChristoph Hellwig enum nvme_ctrl_state new_state); 4225fd4ce1bSChristoph Hellwig int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap); 4235fd4ce1bSChristoph Hellwig int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap); 4245fd4ce1bSChristoph Hellwig int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl); 425f3ca80fcSChristoph Hellwig int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev, 426f3ca80fcSChristoph Hellwig const struct nvme_ctrl_ops *ops, unsigned long quirks); 42753029b04SKeith Busch void nvme_uninit_ctrl(struct nvme_ctrl *ctrl); 428d09f2b45SSagi Grimberg void nvme_start_ctrl(struct nvme_ctrl *ctrl); 429d09f2b45SSagi Grimberg void nvme_stop_ctrl(struct nvme_ctrl *ctrl); 4301673f1f0SChristoph Hellwig void nvme_put_ctrl(struct nvme_ctrl *ctrl); 4317fd8930fSChristoph Hellwig int nvme_init_identify(struct nvme_ctrl *ctrl); 4325bae7f73SChristoph Hellwig 4335bae7f73SChristoph Hellwig void nvme_remove_namespaces(struct nvme_ctrl *ctrl); 4341673f1f0SChristoph Hellwig 4354f1244c8SChristoph Hellwig int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len, 4364f1244c8SChristoph Hellwig bool send); 437a98e58e5SScott Bauer 4387bf58533SChristoph Hellwig void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status, 439287a63ebSChristoph Hellwig volatile union nvme_result *res); 440f866fc42SChristoph Hellwig 44125646264SKeith Busch void nvme_stop_queues(struct nvme_ctrl *ctrl); 44225646264SKeith Busch void nvme_start_queues(struct nvme_ctrl *ctrl); 44369d9a99cSKeith Busch void nvme_kill_queues(struct nvme_ctrl *ctrl); 444302ad8ccSKeith Busch void nvme_unfreeze(struct nvme_ctrl *ctrl); 445302ad8ccSKeith Busch void nvme_wait_freeze(struct nvme_ctrl *ctrl); 446302ad8ccSKeith Busch void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout); 447302ad8ccSKeith Busch void nvme_start_freeze(struct nvme_ctrl *ctrl); 448363c9aacSSagi Grimberg 449eb71f435SChristoph Hellwig #define NVME_QID_ANY -1 4504160982eSChristoph Hellwig struct request *nvme_alloc_request(struct request_queue *q, 4519a95e4efSBart Van Assche struct nvme_command *cmd, blk_mq_req_flags_t flags, int qid); 452f7f1fc36SMax Gurtovoy void nvme_cleanup_cmd(struct request *req); 453fc17b653SChristoph Hellwig blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req, 4548093f7caSMing Lin struct nvme_command *cmd); 45557dacad5SJay Sternberg int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, 45657dacad5SJay Sternberg void *buf, unsigned bufflen); 45757dacad5SJay Sternberg int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, 458d49187e9SChristoph Hellwig union nvme_result *result, void *buffer, unsigned bufflen, 4599a95e4efSBart Van Assche unsigned timeout, int qid, int at_head, 4606287b51cSSagi Grimberg blk_mq_req_flags_t flags, bool poll); 4619a0be7abSChristoph Hellwig int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count); 462038bd4cbSSagi Grimberg void nvme_stop_keep_alive(struct nvme_ctrl *ctrl); 463d86c4d8eSChristoph Hellwig int nvme_reset_ctrl(struct nvme_ctrl *ctrl); 46479c48ccfSSagi Grimberg int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl); 465c5017e85SChristoph Hellwig int nvme_delete_ctrl(struct nvme_ctrl *ctrl); 46657dacad5SJay Sternberg 4670e98719bSChristoph Hellwig int nvme_get_log(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, u8 lsp, 4680e98719bSChristoph Hellwig void *log, size_t size, u64 offset); 469d558fb51SMatias Bjørling 47033b14f67SHannes Reinecke extern const struct attribute_group *nvme_ns_id_attr_groups[]; 47132acab31SChristoph Hellwig extern const struct block_device_operations nvme_ns_head_ops; 47232acab31SChristoph Hellwig 47332acab31SChristoph Hellwig #ifdef CONFIG_NVME_MULTIPATH 4740d0b660fSChristoph Hellwig bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl); 475a785dbccSKeith Busch void nvme_set_disk_name(char *disk_name, struct nvme_ns *ns, 476a785dbccSKeith Busch struct nvme_ctrl *ctrl, int *flags); 47732acab31SChristoph Hellwig void nvme_failover_req(struct request *req); 47832acab31SChristoph Hellwig void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl); 47932acab31SChristoph Hellwig int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl,struct nvme_ns_head *head); 4800d0b660fSChristoph Hellwig void nvme_mpath_add_disk(struct nvme_ns *ns, struct nvme_id_ns *id); 48132acab31SChristoph Hellwig void nvme_mpath_remove_disk(struct nvme_ns_head *head); 4820d0b660fSChristoph Hellwig int nvme_mpath_init(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id); 4830d0b660fSChristoph Hellwig void nvme_mpath_uninit(struct nvme_ctrl *ctrl); 4840d0b660fSChristoph Hellwig void nvme_mpath_stop(struct nvme_ctrl *ctrl); 485f3334447SChristoph Hellwig void nvme_mpath_clear_current_path(struct nvme_ns *ns); 48632acab31SChristoph Hellwig struct nvme_ns *nvme_find_path(struct nvme_ns_head *head); 487479a322fSSagi Grimberg 488479a322fSSagi Grimberg static inline void nvme_mpath_check_last_path(struct nvme_ns *ns) 489479a322fSSagi Grimberg { 490479a322fSSagi Grimberg struct nvme_ns_head *head = ns->head; 491479a322fSSagi Grimberg 492479a322fSSagi Grimberg if (head->disk && list_empty(&head->list)) 493479a322fSSagi Grimberg kblockd_schedule_work(&head->requeue_work); 494479a322fSSagi Grimberg } 495479a322fSSagi Grimberg 4960d0b660fSChristoph Hellwig extern struct device_attribute dev_attr_ana_grpid; 4970d0b660fSChristoph Hellwig extern struct device_attribute dev_attr_ana_state; 49875c10e73SHannes Reinecke extern struct device_attribute subsys_attr_iopolicy; 4990d0b660fSChristoph Hellwig 50032acab31SChristoph Hellwig #else 5010d0b660fSChristoph Hellwig static inline bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl) 5020d0b660fSChristoph Hellwig { 5030d0b660fSChristoph Hellwig return false; 5040d0b660fSChristoph Hellwig } 505a785dbccSKeith Busch /* 506a785dbccSKeith Busch * Without the multipath code enabled, multiple controller per subsystems are 507a785dbccSKeith Busch * visible as devices and thus we cannot use the subsystem instance. 508a785dbccSKeith Busch */ 509a785dbccSKeith Busch static inline void nvme_set_disk_name(char *disk_name, struct nvme_ns *ns, 510a785dbccSKeith Busch struct nvme_ctrl *ctrl, int *flags) 511a785dbccSKeith Busch { 512a785dbccSKeith Busch sprintf(disk_name, "nvme%dn%d", ctrl->instance, ns->head->instance); 513a785dbccSKeith Busch } 514a785dbccSKeith Busch 51532acab31SChristoph Hellwig static inline void nvme_failover_req(struct request *req) 51632acab31SChristoph Hellwig { 51732acab31SChristoph Hellwig } 51832acab31SChristoph Hellwig static inline void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl) 51932acab31SChristoph Hellwig { 52032acab31SChristoph Hellwig } 52132acab31SChristoph Hellwig static inline int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl, 52232acab31SChristoph Hellwig struct nvme_ns_head *head) 52332acab31SChristoph Hellwig { 52432acab31SChristoph Hellwig return 0; 52532acab31SChristoph Hellwig } 5260d0b660fSChristoph Hellwig static inline void nvme_mpath_add_disk(struct nvme_ns *ns, 5270d0b660fSChristoph Hellwig struct nvme_id_ns *id) 52832acab31SChristoph Hellwig { 52932acab31SChristoph Hellwig } 53032acab31SChristoph Hellwig static inline void nvme_mpath_remove_disk(struct nvme_ns_head *head) 53132acab31SChristoph Hellwig { 53232acab31SChristoph Hellwig } 53332acab31SChristoph Hellwig static inline void nvme_mpath_clear_current_path(struct nvme_ns *ns) 53432acab31SChristoph Hellwig { 53532acab31SChristoph Hellwig } 536479a322fSSagi Grimberg static inline void nvme_mpath_check_last_path(struct nvme_ns *ns) 537479a322fSSagi Grimberg { 538479a322fSSagi Grimberg } 5390d0b660fSChristoph Hellwig static inline int nvme_mpath_init(struct nvme_ctrl *ctrl, 5400d0b660fSChristoph Hellwig struct nvme_id_ctrl *id) 5410d0b660fSChristoph Hellwig { 54214a1336eSChristoph Hellwig if (ctrl->subsys->cmic & (1 << 3)) 54314a1336eSChristoph Hellwig dev_warn(ctrl->device, 54414a1336eSChristoph Hellwig "Please enable CONFIG_NVME_MULTIPATH for full support of multi-port devices.\n"); 5450d0b660fSChristoph Hellwig return 0; 5460d0b660fSChristoph Hellwig } 5470d0b660fSChristoph Hellwig static inline void nvme_mpath_uninit(struct nvme_ctrl *ctrl) 5480d0b660fSChristoph Hellwig { 5490d0b660fSChristoph Hellwig } 5500d0b660fSChristoph Hellwig static inline void nvme_mpath_stop(struct nvme_ctrl *ctrl) 5510d0b660fSChristoph Hellwig { 5520d0b660fSChristoph Hellwig } 55332acab31SChristoph Hellwig #endif /* CONFIG_NVME_MULTIPATH */ 55432acab31SChristoph Hellwig 555c4699e70SKeith Busch #ifdef CONFIG_NVM 5563dc87dd0SMatias Bjørling int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, int node); 557b0b4e09cSMatias Bjørling void nvme_nvm_unregister(struct nvme_ns *ns); 55833b14f67SHannes Reinecke extern const struct attribute_group nvme_nvm_attr_group; 55984d4add7SMatias Bjørling int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, unsigned long arg); 560c4699e70SKeith Busch #else 561b0b4e09cSMatias Bjørling static inline int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, 5623dc87dd0SMatias Bjørling int node) 563c4699e70SKeith Busch { 564c4699e70SKeith Busch return 0; 565c4699e70SKeith Busch } 566c4699e70SKeith Busch 567b0b4e09cSMatias Bjørling static inline void nvme_nvm_unregister(struct nvme_ns *ns) {}; 56884d4add7SMatias Bjørling static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, 56984d4add7SMatias Bjørling unsigned long arg) 57084d4add7SMatias Bjørling { 57184d4add7SMatias Bjørling return -ENOTTY; 57284d4add7SMatias Bjørling } 5733dc87dd0SMatias Bjørling #endif /* CONFIG_NVM */ 5743dc87dd0SMatias Bjørling 57540267efdSSimon A. F. Lund static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev) 57640267efdSSimon A. F. Lund { 57740267efdSSimon A. F. Lund return dev_to_disk(dev)->private_data; 57840267efdSSimon A. F. Lund } 579ca064085SMatias Bjørling 5805bae7f73SChristoph Hellwig int __init nvme_core_init(void); 5818eb5d89fSChengguang Xu void __exit nvme_core_exit(void); 5825bae7f73SChristoph Hellwig 58357dacad5SJay Sternberg #endif /* _NVME_H */ 584