1bc50ad75SChristoph Hellwig /* SPDX-License-Identifier: GPL-2.0 */ 257dacad5SJay Sternberg /* 357dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 457dacad5SJay Sternberg */ 557dacad5SJay Sternberg 657dacad5SJay Sternberg #ifndef _NVME_H 757dacad5SJay Sternberg #define _NVME_H 857dacad5SJay Sternberg 957dacad5SJay Sternberg #include <linux/nvme.h> 10a6a5149bSChristoph Hellwig #include <linux/cdev.h> 1157dacad5SJay Sternberg #include <linux/pci.h> 1257dacad5SJay Sternberg #include <linux/kref.h> 1357dacad5SJay Sternberg #include <linux/blk-mq.h> 14b0b4e09cSMatias Bjørling #include <linux/lightnvm.h> 15a98e58e5SScott Bauer #include <linux/sed-opal.h> 16b9e03857SThomas Tai #include <linux/fault-inject.h> 17978628ecSJohannes Thumshirn #include <linux/rcupdate.h> 18c1ac9a4bSKeith Busch #include <linux/wait.h> 194d2ce688SJames Smart #include <linux/t10-pi.h> 2057dacad5SJay Sternberg 2135fe0d12SHannes Reinecke #include <trace/events/block.h> 2235fe0d12SHannes Reinecke 238ae4e447SMarc Olson extern unsigned int nvme_io_timeout; 2457dacad5SJay Sternberg #define NVME_IO_TIMEOUT (nvme_io_timeout * HZ) 2557dacad5SJay Sternberg 268ae4e447SMarc Olson extern unsigned int admin_timeout; 27dc96f938SChaitanya Kulkarni #define NVME_ADMIN_TIMEOUT (admin_timeout * HZ) 2821d34711SChristoph Hellwig 29038bd4cbSSagi Grimberg #define NVME_DEFAULT_KATO 5 30038bd4cbSSagi Grimberg #define NVME_KATO_GRACE 10 31038bd4cbSSagi Grimberg 3238e18002SIsrael Rukshin #ifdef CONFIG_ARCH_NO_SG_CHAIN 3338e18002SIsrael Rukshin #define NVME_INLINE_SG_CNT 0 34ba7ca2aeSIsrael Rukshin #define NVME_INLINE_METADATA_SG_CNT 0 3538e18002SIsrael Rukshin #else 3638e18002SIsrael Rukshin #define NVME_INLINE_SG_CNT 2 37ba7ca2aeSIsrael Rukshin #define NVME_INLINE_METADATA_SG_CNT 1 3838e18002SIsrael Rukshin #endif 3938e18002SIsrael Rukshin 406c3c05b0SChaitanya Kulkarni /* 416c3c05b0SChaitanya Kulkarni * Default to a 4K page size, with the intention to update this 426c3c05b0SChaitanya Kulkarni * path in the future to accommodate architectures with differing 436c3c05b0SChaitanya Kulkarni * kernel and IO page sizes. 446c3c05b0SChaitanya Kulkarni */ 456c3c05b0SChaitanya Kulkarni #define NVME_CTRL_PAGE_SHIFT 12 466c3c05b0SChaitanya Kulkarni #define NVME_CTRL_PAGE_SIZE (1 << NVME_CTRL_PAGE_SHIFT) 476c3c05b0SChaitanya Kulkarni 489a6327d2SSagi Grimberg extern struct workqueue_struct *nvme_wq; 49b227c59bSRoy Shterman extern struct workqueue_struct *nvme_reset_wq; 50b227c59bSRoy Shterman extern struct workqueue_struct *nvme_delete_wq; 519a6327d2SSagi Grimberg 52ca064085SMatias Bjørling enum { 53ca064085SMatias Bjørling NVME_NS_LBA = 0, 54ca064085SMatias Bjørling NVME_NS_LIGHTNVM = 1, 55ca064085SMatias Bjørling }; 56ca064085SMatias Bjørling 5757dacad5SJay Sternberg /* 58106198edSChristoph Hellwig * List of workarounds for devices that required behavior not specified in 59106198edSChristoph Hellwig * the standard. 6057dacad5SJay Sternberg */ 61106198edSChristoph Hellwig enum nvme_quirks { 62106198edSChristoph Hellwig /* 63106198edSChristoph Hellwig * Prefers I/O aligned to a stripe size specified in a vendor 64106198edSChristoph Hellwig * specific Identify field. 65106198edSChristoph Hellwig */ 66106198edSChristoph Hellwig NVME_QUIRK_STRIPE_SIZE = (1 << 0), 67540c801cSKeith Busch 68540c801cSKeith Busch /* 69540c801cSKeith Busch * The controller doesn't handle Identify value others than 0 or 1 70540c801cSKeith Busch * correctly. 71540c801cSKeith Busch */ 72540c801cSKeith Busch NVME_QUIRK_IDENTIFY_CNS = (1 << 1), 7308095e70SKeith Busch 7408095e70SKeith Busch /* 75e850fd16SChristoph Hellwig * The controller deterministically returns O's on reads to 76e850fd16SChristoph Hellwig * logical blocks that deallocate was called on. 7708095e70SKeith Busch */ 78e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES = (1 << 2), 7954adc010SGuilherme G. Piccoli 8054adc010SGuilherme G. Piccoli /* 8154adc010SGuilherme G. Piccoli * The controller needs a delay before starts checking the device 8254adc010SGuilherme G. Piccoli * readiness, which is done by reading the NVME_CSTS_RDY bit. 8354adc010SGuilherme G. Piccoli */ 8454adc010SGuilherme G. Piccoli NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3), 85c5552fdeSAndy Lutomirski 86c5552fdeSAndy Lutomirski /* 87c5552fdeSAndy Lutomirski * APST should not be used. 88c5552fdeSAndy Lutomirski */ 89c5552fdeSAndy Lutomirski NVME_QUIRK_NO_APST = (1 << 4), 90ff5350a8SAndy Lutomirski 91ff5350a8SAndy Lutomirski /* 92ff5350a8SAndy Lutomirski * The deepest sleep state should not be used. 93ff5350a8SAndy Lutomirski */ 94ff5350a8SAndy Lutomirski NVME_QUIRK_NO_DEEPEST_PS = (1 << 5), 95608cc4b1SChristoph Hellwig 96608cc4b1SChristoph Hellwig /* 97608cc4b1SChristoph Hellwig * Supports the LighNVM command set if indicated in vs[1]. 98608cc4b1SChristoph Hellwig */ 99608cc4b1SChristoph Hellwig NVME_QUIRK_LIGHTNVM = (1 << 6), 1009abd68efSJens Axboe 1019abd68efSJens Axboe /* 1029abd68efSJens Axboe * Set MEDIUM priority on SQ creation 1039abd68efSJens Axboe */ 1049abd68efSJens Axboe NVME_QUIRK_MEDIUM_PRIO_SQ = (1 << 7), 1056299358dSJames Dingwall 1066299358dSJames Dingwall /* 1076299358dSJames Dingwall * Ignore device provided subnqn. 1086299358dSJames Dingwall */ 1096299358dSJames Dingwall NVME_QUIRK_IGNORE_DEV_SUBNQN = (1 << 8), 1107b210e4eSChristoph Hellwig 1117b210e4eSChristoph Hellwig /* 1127b210e4eSChristoph Hellwig * Broken Write Zeroes. 1137b210e4eSChristoph Hellwig */ 1147b210e4eSChristoph Hellwig NVME_QUIRK_DISABLE_WRITE_ZEROES = (1 << 9), 115cb32de1bSMario Limonciello 116cb32de1bSMario Limonciello /* 117cb32de1bSMario Limonciello * Force simple suspend/resume path. 118cb32de1bSMario Limonciello */ 119cb32de1bSMario Limonciello NVME_QUIRK_SIMPLE_SUSPEND = (1 << 10), 1207ad67ca5SLinus Torvalds 1217ad67ca5SLinus Torvalds /* 12266341331SBenjamin Herrenschmidt * Use only one interrupt vector for all queues 12366341331SBenjamin Herrenschmidt */ 1247ad67ca5SLinus Torvalds NVME_QUIRK_SINGLE_VECTOR = (1 << 11), 12566341331SBenjamin Herrenschmidt 12666341331SBenjamin Herrenschmidt /* 12766341331SBenjamin Herrenschmidt * Use non-standard 128 bytes SQEs. 12866341331SBenjamin Herrenschmidt */ 1297ad67ca5SLinus Torvalds NVME_QUIRK_128_BYTES_SQES = (1 << 12), 130d38e9f04SBenjamin Herrenschmidt 131d38e9f04SBenjamin Herrenschmidt /* 132d38e9f04SBenjamin Herrenschmidt * Prevent tag overlap between queues 133d38e9f04SBenjamin Herrenschmidt */ 1347ad67ca5SLinus Torvalds NVME_QUIRK_SHARED_TAGS = (1 << 13), 1356c6aa2f2SAkinobu Mita 1366c6aa2f2SAkinobu Mita /* 1376c6aa2f2SAkinobu Mita * Don't change the value of the temperature threshold feature 1386c6aa2f2SAkinobu Mita */ 1396c6aa2f2SAkinobu Mita NVME_QUIRK_NO_TEMP_THRESH_CHANGE = (1 << 14), 1405bedd3afSChristoph Hellwig 1415bedd3afSChristoph Hellwig /* 1425bedd3afSChristoph Hellwig * The controller doesn't handle the Identify Namespace 1435bedd3afSChristoph Hellwig * Identification Descriptor list subcommand despite claiming 1445bedd3afSChristoph Hellwig * NVMe 1.3 compliance. 1455bedd3afSChristoph Hellwig */ 1465bedd3afSChristoph Hellwig NVME_QUIRK_NO_NS_DESC_LIST = (1 << 15), 1474bdf2603SFilippo Sironi 1484bdf2603SFilippo Sironi /* 1494bdf2603SFilippo Sironi * The controller does not properly handle DMA addresses over 1504bdf2603SFilippo Sironi * 48 bits. 1514bdf2603SFilippo Sironi */ 1524bdf2603SFilippo Sironi NVME_QUIRK_DMA_ADDRESS_BITS_48 = (1 << 16), 153106198edSChristoph Hellwig }; 154106198edSChristoph Hellwig 155d49187e9SChristoph Hellwig /* 156d49187e9SChristoph Hellwig * Common request structure for NVMe passthrough. All drivers must have 157d49187e9SChristoph Hellwig * this structure as the first member of their request-private data. 158d49187e9SChristoph Hellwig */ 159d49187e9SChristoph Hellwig struct nvme_request { 160d49187e9SChristoph Hellwig struct nvme_command *cmd; 161d49187e9SChristoph Hellwig union nvme_result result; 16244e44b29SChristoph Hellwig u8 retries; 16327fa9bc5SChristoph Hellwig u8 flags; 16427fa9bc5SChristoph Hellwig u16 status; 16559e29ce6SSagi Grimberg struct nvme_ctrl *ctrl; 16627fa9bc5SChristoph Hellwig }; 16727fa9bc5SChristoph Hellwig 16832acab31SChristoph Hellwig /* 16932acab31SChristoph Hellwig * Mark a bio as coming in through the mpath node. 17032acab31SChristoph Hellwig */ 17132acab31SChristoph Hellwig #define REQ_NVME_MPATH REQ_DRV 17232acab31SChristoph Hellwig 17327fa9bc5SChristoph Hellwig enum { 17427fa9bc5SChristoph Hellwig NVME_REQ_CANCELLED = (1 << 0), 175bb06ec31SJames Smart NVME_REQ_USERCMD = (1 << 1), 176d49187e9SChristoph Hellwig }; 177d49187e9SChristoph Hellwig 178d49187e9SChristoph Hellwig static inline struct nvme_request *nvme_req(struct request *req) 179d49187e9SChristoph Hellwig { 180d49187e9SChristoph Hellwig return blk_mq_rq_to_pdu(req); 181d49187e9SChristoph Hellwig } 182d49187e9SChristoph Hellwig 1835d87eb94SKeith Busch static inline u16 nvme_req_qid(struct request *req) 1845d87eb94SKeith Busch { 185643c476dSKeith Busch if (!req->q->queuedata) 1865d87eb94SKeith Busch return 0; 18784115d6dSBaolin Wang 18884115d6dSBaolin Wang return req->mq_hctx->queue_num + 1; 1895d87eb94SKeith Busch } 1905d87eb94SKeith Busch 19154adc010SGuilherme G. Piccoli /* The below value is the specific amount of delay needed before checking 19254adc010SGuilherme G. Piccoli * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the 19354adc010SGuilherme G. Piccoli * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was 19454adc010SGuilherme G. Piccoli * found empirically. 19554adc010SGuilherme G. Piccoli */ 1968c97eeccSJeff Lien #define NVME_QUIRK_DELAY_AMOUNT 2300 19754adc010SGuilherme G. Piccoli 1984212f4e9SSagi Grimberg /* 1994212f4e9SSagi Grimberg * enum nvme_ctrl_state: Controller state 2004212f4e9SSagi Grimberg * 2014212f4e9SSagi Grimberg * @NVME_CTRL_NEW: New controller just allocated, initial state 2024212f4e9SSagi Grimberg * @NVME_CTRL_LIVE: Controller is connected and I/O capable 2034212f4e9SSagi Grimberg * @NVME_CTRL_RESETTING: Controller is resetting (or scheduled reset) 2044212f4e9SSagi Grimberg * @NVME_CTRL_CONNECTING: Controller is disconnected, now connecting the 2054212f4e9SSagi Grimberg * transport 2064212f4e9SSagi Grimberg * @NVME_CTRL_DELETING: Controller is deleting (or scheduled deletion) 207ecca390eSSagi Grimberg * @NVME_CTRL_DELETING_NOIO: Controller is deleting and I/O is not 208ecca390eSSagi Grimberg * disabled/failed immediately. This state comes 209ecca390eSSagi Grimberg * after all async event processing took place and 210ecca390eSSagi Grimberg * before ns removal and the controller deletion 211ecca390eSSagi Grimberg * progress 2124212f4e9SSagi Grimberg * @NVME_CTRL_DEAD: Controller is non-present/unresponsive during 2134212f4e9SSagi Grimberg * shutdown or removal. In this case we forcibly 2144212f4e9SSagi Grimberg * kill all inflight I/O as they have no chance to 2154212f4e9SSagi Grimberg * complete 2164212f4e9SSagi Grimberg */ 217bb8d261eSChristoph Hellwig enum nvme_ctrl_state { 218bb8d261eSChristoph Hellwig NVME_CTRL_NEW, 219bb8d261eSChristoph Hellwig NVME_CTRL_LIVE, 220bb8d261eSChristoph Hellwig NVME_CTRL_RESETTING, 221ad6a0a52SMax Gurtovoy NVME_CTRL_CONNECTING, 222bb8d261eSChristoph Hellwig NVME_CTRL_DELETING, 223ecca390eSSagi Grimberg NVME_CTRL_DELETING_NOIO, 2240ff9d4e1SKeith Busch NVME_CTRL_DEAD, 225bb8d261eSChristoph Hellwig }; 226bb8d261eSChristoph Hellwig 227a3646451SAkinobu Mita struct nvme_fault_inject { 228a3646451SAkinobu Mita #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS 229a3646451SAkinobu Mita struct fault_attr attr; 230a3646451SAkinobu Mita struct dentry *parent; 231a3646451SAkinobu Mita bool dont_retry; /* DNR, do not retry */ 232a3646451SAkinobu Mita u16 status; /* status code */ 233a3646451SAkinobu Mita #endif 234a3646451SAkinobu Mita }; 235a3646451SAkinobu Mita 2361c63dc66SChristoph Hellwig struct nvme_ctrl { 2376e3ca03eSSagi Grimberg bool comp_seen; 238bb8d261eSChristoph Hellwig enum nvme_ctrl_state state; 239bd4da3abSAndy Lutomirski bool identified; 240bb8d261eSChristoph Hellwig spinlock_t lock; 241e7ad43c3SKeith Busch struct mutex scan_lock; 2421c63dc66SChristoph Hellwig const struct nvme_ctrl_ops *ops; 24357dacad5SJay Sternberg struct request_queue *admin_q; 24407bfcd09SChristoph Hellwig struct request_queue *connect_q; 245e7832cb4SSagi Grimberg struct request_queue *fabrics_q; 24657dacad5SJay Sternberg struct device *dev; 24757dacad5SJay Sternberg int instance; 248103e515eSHannes Reinecke int numa_node; 2495bae7f73SChristoph Hellwig struct blk_mq_tag_set *tagset; 25034b6c231SSagi Grimberg struct blk_mq_tag_set *admin_tagset; 2515bae7f73SChristoph Hellwig struct list_head namespaces; 252765cc031SJianchao Wang struct rw_semaphore namespaces_rwsem; 253d22524a4SChristoph Hellwig struct device ctrl_device; 2545bae7f73SChristoph Hellwig struct device *device; /* char device */ 255ed7770f6SHannes Reinecke #ifdef CONFIG_NVME_HWMON 256ed7770f6SHannes Reinecke struct device *hwmon_device; 257ed7770f6SHannes Reinecke #endif 258a6a5149bSChristoph Hellwig struct cdev cdev; 259d86c4d8eSChristoph Hellwig struct work_struct reset_work; 260c5017e85SChristoph Hellwig struct work_struct delete_work; 261c1ac9a4bSKeith Busch wait_queue_head_t state_wq; 2621c63dc66SChristoph Hellwig 263ab9e00ccSChristoph Hellwig struct nvme_subsystem *subsys; 264ab9e00ccSChristoph Hellwig struct list_head subsys_entry; 265ab9e00ccSChristoph Hellwig 2664f1244c8SChristoph Hellwig struct opal_dev *opal_dev; 267a98e58e5SScott Bauer 26857dacad5SJay Sternberg char name[12]; 26976e3914aSChristoph Hellwig u16 cntlid; 2705fd4ce1bSChristoph Hellwig 2715fd4ce1bSChristoph Hellwig u32 ctrl_config; 272b6dccf7fSArnav Dawn u16 mtfa; 273d858e5f0SSagi Grimberg u32 queue_count; 2745fd4ce1bSChristoph Hellwig 27520d0dfe6SSagi Grimberg u64 cap; 27657dacad5SJay Sternberg u32 max_hw_sectors; 277943e942eSJens Axboe u32 max_segments; 27895093350SMax Gurtovoy u32 max_integrity_segments; 2795befc7c2SKeith Busch u32 max_discard_sectors; 2805befc7c2SKeith Busch u32 max_discard_segments; 2815befc7c2SKeith Busch u32 max_zeroes_sectors; 282240e6ee2SKeith Busch #ifdef CONFIG_BLK_DEV_ZONED 283240e6ee2SKeith Busch u32 max_zone_append; 284240e6ee2SKeith Busch #endif 28549cd84b6SKeith Busch u16 crdt[3]; 28657dacad5SJay Sternberg u16 oncs; 2878a9ae523SScott Bauer u16 oacs; 288f5d11840SJens Axboe u16 nssa; 289f5d11840SJens Axboe u16 nr_streams; 290f968688fSKeith Busch u16 sqsize; 2910d0b660fSChristoph Hellwig u32 max_namespaces; 2926bf25d16SChristoph Hellwig atomic_t abort_limit; 29357dacad5SJay Sternberg u8 vwc; 294f3ca80fcSChristoph Hellwig u32 vs; 29507bfcd09SChristoph Hellwig u32 sgls; 296038bd4cbSSagi Grimberg u16 kas; 297c5552fdeSAndy Lutomirski u8 npss; 298c5552fdeSAndy Lutomirski u8 apsta; 299400b6a7bSGuenter Roeck u16 wctemp; 300400b6a7bSGuenter Roeck u16 cctemp; 301c0561f82SHannes Reinecke u32 oaes; 302e3d7874dSKeith Busch u32 aen_result; 3033e53ba38SSagi Grimberg u32 ctratt; 30407fbd32aSMartin K. Petersen unsigned int shutdown_timeout; 305038bd4cbSSagi Grimberg unsigned int kato; 306f3ca80fcSChristoph Hellwig bool subsystem; 307106198edSChristoph Hellwig unsigned long quirks; 308c5552fdeSAndy Lutomirski struct nvme_id_power_state psd[32]; 30984fef62dSKeith Busch struct nvme_effects_log *effects; 3101cf7a12eSChaitanya Kulkarni struct xarray cels; 3115955be21SChristoph Hellwig struct work_struct scan_work; 312f866fc42SChristoph Hellwig struct work_struct async_event_work; 313038bd4cbSSagi Grimberg struct delayed_work ka_work; 3148c4dfea9SVictor Gladkov struct delayed_work failfast_work; 3150a34e466SRoland Dreier struct nvme_command ka_cmd; 316b6dccf7fSArnav Dawn struct work_struct fw_act_work; 31730d90964SChristoph Hellwig unsigned long events; 31807bfcd09SChristoph Hellwig 3190d0b660fSChristoph Hellwig #ifdef CONFIG_NVME_MULTIPATH 3200d0b660fSChristoph Hellwig /* asymmetric namespace access: */ 3210d0b660fSChristoph Hellwig u8 anacap; 3220d0b660fSChristoph Hellwig u8 anatt; 3230d0b660fSChristoph Hellwig u32 anagrpmax; 3240d0b660fSChristoph Hellwig u32 nanagrpid; 3250d0b660fSChristoph Hellwig struct mutex ana_lock; 3260d0b660fSChristoph Hellwig struct nvme_ana_rsp_hdr *ana_log_buf; 3270d0b660fSChristoph Hellwig size_t ana_log_size; 3280d0b660fSChristoph Hellwig struct timer_list anatt_timer; 3290d0b660fSChristoph Hellwig struct work_struct ana_work; 3300d0b660fSChristoph Hellwig #endif 3310d0b660fSChristoph Hellwig 332c5552fdeSAndy Lutomirski /* Power saving configuration */ 333c5552fdeSAndy Lutomirski u64 ps_max_latency_us; 33476a5af84SKai-Heng Feng bool apst_enabled; 335c5552fdeSAndy Lutomirski 336044a9df1SChristoph Hellwig /* PCIe only: */ 337fe6d53c9SChristoph Hellwig u32 hmpre; 338fe6d53c9SChristoph Hellwig u32 hmmin; 339044a9df1SChristoph Hellwig u32 hmminds; 340044a9df1SChristoph Hellwig u16 hmmaxd; 341fe6d53c9SChristoph Hellwig 34207bfcd09SChristoph Hellwig /* Fabrics only */ 34307bfcd09SChristoph Hellwig u32 ioccsz; 34407bfcd09SChristoph Hellwig u32 iorcsz; 34507bfcd09SChristoph Hellwig u16 icdoff; 34607bfcd09SChristoph Hellwig u16 maxcmd; 347fdf9dfa8SSagi Grimberg int nr_reconnects; 3488c4dfea9SVictor Gladkov unsigned long flags; 3498c4dfea9SVictor Gladkov #define NVME_CTRL_FAILFAST_EXPIRED 0 35007bfcd09SChristoph Hellwig struct nvmf_ctrl_options *opts; 351cb5b7262SJens Axboe 352cb5b7262SJens Axboe struct page *discard_page; 353cb5b7262SJens Axboe unsigned long discard_page_busy; 354f79d5fdaSAkinobu Mita 355f79d5fdaSAkinobu Mita struct nvme_fault_inject fault_inject; 35657dacad5SJay Sternberg }; 35757dacad5SJay Sternberg 35875c10e73SHannes Reinecke enum nvme_iopolicy { 35975c10e73SHannes Reinecke NVME_IOPOLICY_NUMA, 36075c10e73SHannes Reinecke NVME_IOPOLICY_RR, 36175c10e73SHannes Reinecke }; 36275c10e73SHannes Reinecke 363ab9e00ccSChristoph Hellwig struct nvme_subsystem { 364ab9e00ccSChristoph Hellwig int instance; 365ab9e00ccSChristoph Hellwig struct device dev; 366ab9e00ccSChristoph Hellwig /* 367ab9e00ccSChristoph Hellwig * Because we unregister the device on the last put we need 368ab9e00ccSChristoph Hellwig * a separate refcount. 369ab9e00ccSChristoph Hellwig */ 370ab9e00ccSChristoph Hellwig struct kref ref; 371ab9e00ccSChristoph Hellwig struct list_head entry; 372ab9e00ccSChristoph Hellwig struct mutex lock; 373ab9e00ccSChristoph Hellwig struct list_head ctrls; 374ed754e5dSChristoph Hellwig struct list_head nsheads; 375ab9e00ccSChristoph Hellwig char subnqn[NVMF_NQN_SIZE]; 376ab9e00ccSChristoph Hellwig char serial[20]; 377ab9e00ccSChristoph Hellwig char model[40]; 378ab9e00ccSChristoph Hellwig char firmware_rev[8]; 379ab9e00ccSChristoph Hellwig u8 cmic; 380ab9e00ccSChristoph Hellwig u16 vendor_id; 38181adb863SBart Van Assche u16 awupf; /* 0's based awupf value. */ 382ed754e5dSChristoph Hellwig struct ida ns_ida; 38375c10e73SHannes Reinecke #ifdef CONFIG_NVME_MULTIPATH 38475c10e73SHannes Reinecke enum nvme_iopolicy iopolicy; 38575c10e73SHannes Reinecke #endif 386ab9e00ccSChristoph Hellwig }; 387ab9e00ccSChristoph Hellwig 388002fab04SChristoph Hellwig /* 389002fab04SChristoph Hellwig * Container structure for uniqueue namespace identifiers. 390002fab04SChristoph Hellwig */ 391002fab04SChristoph Hellwig struct nvme_ns_ids { 392002fab04SChristoph Hellwig u8 eui64[8]; 393002fab04SChristoph Hellwig u8 nguid[16]; 394002fab04SChristoph Hellwig uuid_t uuid; 39571010c30SNiklas Cassel u8 csi; 396002fab04SChristoph Hellwig }; 397002fab04SChristoph Hellwig 398ed754e5dSChristoph Hellwig /* 399ed754e5dSChristoph Hellwig * Anchor structure for namespaces. There is one for each namespace in a 400ed754e5dSChristoph Hellwig * NVMe subsystem that any of our controllers can see, and the namespace 401ed754e5dSChristoph Hellwig * structure for each controller is chained of it. For private namespaces 402ed754e5dSChristoph Hellwig * there is a 1:1 relation to our namespace structures, that is ->list 403ed754e5dSChristoph Hellwig * only ever has a single entry for private namespaces. 404ed754e5dSChristoph Hellwig */ 405ed754e5dSChristoph Hellwig struct nvme_ns_head { 406ed754e5dSChristoph Hellwig struct list_head list; 407ed754e5dSChristoph Hellwig struct srcu_struct srcu; 408ed754e5dSChristoph Hellwig struct nvme_subsystem *subsys; 409ed754e5dSChristoph Hellwig unsigned ns_id; 410ed754e5dSChristoph Hellwig struct nvme_ns_ids ids; 411ed754e5dSChristoph Hellwig struct list_head entry; 412ed754e5dSChristoph Hellwig struct kref ref; 4130c284db7SKeith Busch bool shared; 414ed754e5dSChristoph Hellwig int instance; 415be93e87eSKeith Busch struct nvme_effects_log *effects; 416f3334447SChristoph Hellwig struct gendisk *disk; 41730897388SMinwoo Im #ifdef CONFIG_NVME_MULTIPATH 418f3334447SChristoph Hellwig struct bio_list requeue_list; 419f3334447SChristoph Hellwig spinlock_t requeue_lock; 420f3334447SChristoph Hellwig struct work_struct requeue_work; 421f3334447SChristoph Hellwig struct mutex lock; 422d8a22f85SAnton Eidelman unsigned long flags; 423d8a22f85SAnton Eidelman #define NVME_NSHEAD_DISK_LIVE 0 424f3334447SChristoph Hellwig struct nvme_ns __rcu *current_path[]; 425f3334447SChristoph Hellwig #endif 426ed754e5dSChristoph Hellwig }; 427ed754e5dSChristoph Hellwig 42830897388SMinwoo Im static inline bool nvme_ns_head_multipath(struct nvme_ns_head *head) 42930897388SMinwoo Im { 43030897388SMinwoo Im return IS_ENABLED(CONFIG_NVME_MULTIPATH) && head->disk; 43130897388SMinwoo Im } 43230897388SMinwoo Im 433ffc89b1dSMax Gurtovoy enum nvme_ns_features { 434ffc89b1dSMax Gurtovoy NVME_NS_EXT_LBAS = 1 << 0, /* support extended LBA format */ 435b29f8485SMax Gurtovoy NVME_NS_METADATA_SUPPORTED = 1 << 1, /* support getting generated md */ 436ffc89b1dSMax Gurtovoy }; 437ffc89b1dSMax Gurtovoy 43857dacad5SJay Sternberg struct nvme_ns { 43957dacad5SJay Sternberg struct list_head list; 44057dacad5SJay Sternberg 4411c63dc66SChristoph Hellwig struct nvme_ctrl *ctrl; 44257dacad5SJay Sternberg struct request_queue *queue; 44357dacad5SJay Sternberg struct gendisk *disk; 4440d0b660fSChristoph Hellwig #ifdef CONFIG_NVME_MULTIPATH 4450d0b660fSChristoph Hellwig enum nvme_ana_state ana_state; 4460d0b660fSChristoph Hellwig u32 ana_grpid; 4470d0b660fSChristoph Hellwig #endif 448ed754e5dSChristoph Hellwig struct list_head siblings; 449b0b4e09cSMatias Bjørling struct nvm_dev *ndev; 45057dacad5SJay Sternberg struct kref kref; 451ed754e5dSChristoph Hellwig struct nvme_ns_head *head; 45257dacad5SJay Sternberg 45357dacad5SJay Sternberg int lba_shift; 45457dacad5SJay Sternberg u16 ms; 455f5d11840SJens Axboe u16 sgs; 456f5d11840SJens Axboe u32 sws; 45757dacad5SJay Sternberg u8 pi_type; 458240e6ee2SKeith Busch #ifdef CONFIG_BLK_DEV_ZONED 459240e6ee2SKeith Busch u64 zsze; 460240e6ee2SKeith Busch #endif 461ffc89b1dSMax Gurtovoy unsigned long features; 462646017a6SKeith Busch unsigned long flags; 463646017a6SKeith Busch #define NVME_NS_REMOVING 0 46469d9a99cSKeith Busch #define NVME_NS_DEAD 1 4650d0b660fSChristoph Hellwig #define NVME_NS_ANA_PENDING 2 4662f4c9ba2SJavier González #define NVME_NS_FORCE_RO 3 467b9e03857SThomas Tai 468b9e03857SThomas Tai struct nvme_fault_inject fault_inject; 469b9e03857SThomas Tai 47057dacad5SJay Sternberg }; 47157dacad5SJay Sternberg 4724d2ce688SJames Smart /* NVMe ns supports metadata actions by the controller (generate/strip) */ 4734d2ce688SJames Smart static inline bool nvme_ns_has_pi(struct nvme_ns *ns) 4744d2ce688SJames Smart { 4754d2ce688SJames Smart return ns->pi_type && ns->ms == sizeof(struct t10_pi_tuple); 4764d2ce688SJames Smart } 4774d2ce688SJames Smart 4781c63dc66SChristoph Hellwig struct nvme_ctrl_ops { 4791a353d85SMing Lin const char *name; 480e439bb12SSagi Grimberg struct module *module; 481d3d5b87dSChristoph Hellwig unsigned int flags; 482d3d5b87dSChristoph Hellwig #define NVME_F_FABRICS (1 << 0) 483c81bfba9SChristoph Hellwig #define NVME_F_METADATA_SUPPORTED (1 << 1) 484e0596ab2SLogan Gunthorpe #define NVME_F_PCI_P2PDMA (1 << 2) 4851c63dc66SChristoph Hellwig int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val); 4865fd4ce1bSChristoph Hellwig int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val); 4877fd8930fSChristoph Hellwig int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val); 4881673f1f0SChristoph Hellwig void (*free_ctrl)(struct nvme_ctrl *ctrl); 489ad22c355SKeith Busch void (*submit_async_event)(struct nvme_ctrl *ctrl); 490c5017e85SChristoph Hellwig void (*delete_ctrl)(struct nvme_ctrl *ctrl); 4911a353d85SMing Lin int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size); 49257dacad5SJay Sternberg }; 49357dacad5SJay Sternberg 494b9e03857SThomas Tai #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS 495a3646451SAkinobu Mita void nvme_fault_inject_init(struct nvme_fault_inject *fault_inj, 496a3646451SAkinobu Mita const char *dev_name); 497a3646451SAkinobu Mita void nvme_fault_inject_fini(struct nvme_fault_inject *fault_inject); 498b9e03857SThomas Tai void nvme_should_fail(struct request *req); 499b9e03857SThomas Tai #else 500a3646451SAkinobu Mita static inline void nvme_fault_inject_init(struct nvme_fault_inject *fault_inj, 501a3646451SAkinobu Mita const char *dev_name) 502a3646451SAkinobu Mita { 503a3646451SAkinobu Mita } 504a3646451SAkinobu Mita static inline void nvme_fault_inject_fini(struct nvme_fault_inject *fault_inj) 505a3646451SAkinobu Mita { 506a3646451SAkinobu Mita } 507b9e03857SThomas Tai static inline void nvme_should_fail(struct request *req) {} 508b9e03857SThomas Tai #endif 509b9e03857SThomas Tai 510f3ca80fcSChristoph Hellwig static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl) 511f3ca80fcSChristoph Hellwig { 512f3ca80fcSChristoph Hellwig if (!ctrl->subsystem) 513f3ca80fcSChristoph Hellwig return -ENOTTY; 514f3ca80fcSChristoph Hellwig return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65); 515f3ca80fcSChristoph Hellwig } 516f3ca80fcSChristoph Hellwig 517314d48ddSDamien Le Moal /* 518314d48ddSDamien Le Moal * Convert a 512B sector number to a device logical block number. 519314d48ddSDamien Le Moal */ 520314d48ddSDamien Le Moal static inline u64 nvme_sect_to_lba(struct nvme_ns *ns, sector_t sector) 52157dacad5SJay Sternberg { 522314d48ddSDamien Le Moal return sector >> (ns->lba_shift - SECTOR_SHIFT); 52357dacad5SJay Sternberg } 52457dacad5SJay Sternberg 525e08f2ae8SDamien Le Moal /* 526e08f2ae8SDamien Le Moal * Convert a device logical block number to a 512B sector number. 527e08f2ae8SDamien Le Moal */ 528e08f2ae8SDamien Le Moal static inline sector_t nvme_lba_to_sect(struct nvme_ns *ns, u64 lba) 529e08f2ae8SDamien Le Moal { 530e08f2ae8SDamien Le Moal return lba << (ns->lba_shift - SECTOR_SHIFT); 53157dacad5SJay Sternberg } 53257dacad5SJay Sternberg 53371fb90ebSKeith Busch /* 53471fb90ebSKeith Busch * Convert byte length to nvme's 0-based num dwords 53571fb90ebSKeith Busch */ 53671fb90ebSKeith Busch static inline u32 nvme_bytes_to_numd(size_t len) 53771fb90ebSKeith Busch { 53871fb90ebSKeith Busch return (len >> 2) - 1; 53971fb90ebSKeith Busch } 54071fb90ebSKeith Busch 5415ddaabe8SChristoph Hellwig static inline bool nvme_is_ana_error(u16 status) 5425ddaabe8SChristoph Hellwig { 5435ddaabe8SChristoph Hellwig switch (status & 0x7ff) { 5445ddaabe8SChristoph Hellwig case NVME_SC_ANA_TRANSITION: 5455ddaabe8SChristoph Hellwig case NVME_SC_ANA_INACCESSIBLE: 5465ddaabe8SChristoph Hellwig case NVME_SC_ANA_PERSISTENT_LOSS: 5475ddaabe8SChristoph Hellwig return true; 5485ddaabe8SChristoph Hellwig default: 5495ddaabe8SChristoph Hellwig return false; 5505ddaabe8SChristoph Hellwig } 5515ddaabe8SChristoph Hellwig } 5525ddaabe8SChristoph Hellwig 5535ddaabe8SChristoph Hellwig static inline bool nvme_is_path_error(u16 status) 5545ddaabe8SChristoph Hellwig { 5551e41f3bdSChristoph Hellwig /* check for a status code type of 'path related status' */ 5561e41f3bdSChristoph Hellwig return (status & 0x700) == 0x300; 5575ddaabe8SChristoph Hellwig } 5585ddaabe8SChristoph Hellwig 5592eb81a33SChristoph Hellwig /* 5602eb81a33SChristoph Hellwig * Fill in the status and result information from the CQE, and then figure out 5612eb81a33SChristoph Hellwig * if blk-mq will need to use IPI magic to complete the request, and if yes do 5622eb81a33SChristoph Hellwig * so. If not let the caller complete the request without an indirect function 5632eb81a33SChristoph Hellwig * call. 5642eb81a33SChristoph Hellwig */ 5652eb81a33SChristoph Hellwig static inline bool nvme_try_complete_req(struct request *req, __le16 status, 56627fa9bc5SChristoph Hellwig union nvme_result result) 56715a190f7SChristoph Hellwig { 56827fa9bc5SChristoph Hellwig struct nvme_request *rq = nvme_req(req); 56927fa9bc5SChristoph Hellwig 57027fa9bc5SChristoph Hellwig rq->status = le16_to_cpu(status) >> 1; 57127fa9bc5SChristoph Hellwig rq->result = result; 572b9e03857SThomas Tai /* inject error when permitted by fault injection framework */ 573b9e03857SThomas Tai nvme_should_fail(req); 574ff029451SChristoph Hellwig if (unlikely(blk_should_fake_timeout(req->q))) 575ff029451SChristoph Hellwig return true; 576ff029451SChristoph Hellwig return blk_mq_complete_request_remote(req); 57715a190f7SChristoph Hellwig } 57815a190f7SChristoph Hellwig 579d22524a4SChristoph Hellwig static inline void nvme_get_ctrl(struct nvme_ctrl *ctrl) 580d22524a4SChristoph Hellwig { 581d22524a4SChristoph Hellwig get_device(ctrl->device); 582d22524a4SChristoph Hellwig } 583d22524a4SChristoph Hellwig 584d22524a4SChristoph Hellwig static inline void nvme_put_ctrl(struct nvme_ctrl *ctrl) 585d22524a4SChristoph Hellwig { 586d22524a4SChristoph Hellwig put_device(ctrl->device); 587d22524a4SChristoph Hellwig } 588d22524a4SChristoph Hellwig 58958a8df67SIsrael Rukshin static inline bool nvme_is_aen_req(u16 qid, __u16 command_id) 59058a8df67SIsrael Rukshin { 59158a8df67SIsrael Rukshin return !qid && command_id >= NVME_AQ_BLK_MQ_DEPTH; 59258a8df67SIsrael Rukshin } 59358a8df67SIsrael Rukshin 59477f02a7aSChristoph Hellwig void nvme_complete_rq(struct request *req); 595dda3248eSChao Leng blk_status_t nvme_host_path_error(struct request *req); 5967baa8572SJens Axboe bool nvme_cancel_request(struct request *req, void *data, bool reserved); 59725479069SChao Leng void nvme_cancel_tagset(struct nvme_ctrl *ctrl); 59825479069SChao Leng void nvme_cancel_admin_tagset(struct nvme_ctrl *ctrl); 599bb8d261eSChristoph Hellwig bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl, 600bb8d261eSChristoph Hellwig enum nvme_ctrl_state new_state); 601c1ac9a4bSKeith Busch bool nvme_wait_reset(struct nvme_ctrl *ctrl); 602b5b05048SSagi Grimberg int nvme_disable_ctrl(struct nvme_ctrl *ctrl); 603c0f2f45bSSagi Grimberg int nvme_enable_ctrl(struct nvme_ctrl *ctrl); 6045fd4ce1bSChristoph Hellwig int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl); 605f3ca80fcSChristoph Hellwig int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev, 606f3ca80fcSChristoph Hellwig const struct nvme_ctrl_ops *ops, unsigned long quirks); 60753029b04SKeith Busch void nvme_uninit_ctrl(struct nvme_ctrl *ctrl); 608d09f2b45SSagi Grimberg void nvme_start_ctrl(struct nvme_ctrl *ctrl); 609d09f2b45SSagi Grimberg void nvme_stop_ctrl(struct nvme_ctrl *ctrl); 610f21c4769SChaitanya Kulkarni int nvme_init_ctrl_finish(struct nvme_ctrl *ctrl); 6115bae7f73SChristoph Hellwig 6125bae7f73SChristoph Hellwig void nvme_remove_namespaces(struct nvme_ctrl *ctrl); 6131673f1f0SChristoph Hellwig 6144f1244c8SChristoph Hellwig int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len, 6154f1244c8SChristoph Hellwig bool send); 616a98e58e5SScott Bauer 6177bf58533SChristoph Hellwig void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status, 618287a63ebSChristoph Hellwig volatile union nvme_result *res); 619f866fc42SChristoph Hellwig 62025646264SKeith Busch void nvme_stop_queues(struct nvme_ctrl *ctrl); 62125646264SKeith Busch void nvme_start_queues(struct nvme_ctrl *ctrl); 62269d9a99cSKeith Busch void nvme_kill_queues(struct nvme_ctrl *ctrl); 623d6135c3aSKeith Busch void nvme_sync_queues(struct nvme_ctrl *ctrl); 62404800fbfSChao Leng void nvme_sync_io_queues(struct nvme_ctrl *ctrl); 625302ad8ccSKeith Busch void nvme_unfreeze(struct nvme_ctrl *ctrl); 626302ad8ccSKeith Busch void nvme_wait_freeze(struct nvme_ctrl *ctrl); 6277cf0d7c0SSagi Grimberg int nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout); 628302ad8ccSKeith Busch void nvme_start_freeze(struct nvme_ctrl *ctrl); 629363c9aacSSagi Grimberg 630eb71f435SChristoph Hellwig #define NVME_QID_ANY -1 6314160982eSChristoph Hellwig struct request *nvme_alloc_request(struct request_queue *q, 63239dfe844SChaitanya Kulkarni struct nvme_command *cmd, blk_mq_req_flags_t flags); 633f7f1fc36SMax Gurtovoy void nvme_cleanup_cmd(struct request *req); 634f4b9e6c9SKeith Busch blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req); 63557dacad5SJay Sternberg int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, 63657dacad5SJay Sternberg void *buf, unsigned bufflen); 63757dacad5SJay Sternberg int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, 638d49187e9SChristoph Hellwig union nvme_result *result, void *buffer, unsigned bufflen, 6399a95e4efSBart Van Assche unsigned timeout, int qid, int at_head, 6406287b51cSSagi Grimberg blk_mq_req_flags_t flags, bool poll); 6411a87ee65SKeith Busch int nvme_set_features(struct nvme_ctrl *dev, unsigned int fid, 6421a87ee65SKeith Busch unsigned int dword11, void *buffer, size_t buflen, 6431a87ee65SKeith Busch u32 *result); 6441a87ee65SKeith Busch int nvme_get_features(struct nvme_ctrl *dev, unsigned int fid, 6451a87ee65SKeith Busch unsigned int dword11, void *buffer, size_t buflen, 6461a87ee65SKeith Busch u32 *result); 6479a0be7abSChristoph Hellwig int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count); 648038bd4cbSSagi Grimberg void nvme_stop_keep_alive(struct nvme_ctrl *ctrl); 649d86c4d8eSChristoph Hellwig int nvme_reset_ctrl(struct nvme_ctrl *ctrl); 650*2405252aSChristoph Hellwig int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl); 651c1ac9a4bSKeith Busch int nvme_try_sched_reset(struct nvme_ctrl *ctrl); 652c5017e85SChristoph Hellwig int nvme_delete_ctrl(struct nvme_ctrl *ctrl); 653*2405252aSChristoph Hellwig void nvme_queue_scan(struct nvme_ctrl *ctrl); 654be93e87eSKeith Busch int nvme_get_log(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, u8 lsp, u8 csi, 6550e98719bSChristoph Hellwig void *log, size_t size, u64 offset); 656240e6ee2SKeith Busch struct nvme_ns *nvme_get_ns_from_disk(struct gendisk *disk, 657240e6ee2SKeith Busch struct nvme_ns_head **head, int *srcu_idx); 658240e6ee2SKeith Busch void nvme_put_ns_from_disk(struct nvme_ns_head *head, int idx); 659*2405252aSChristoph Hellwig struct nvme_ctrl *nvme_find_get_live_ctrl(struct nvme_subsystem *subsys); 660*2405252aSChristoph Hellwig int nvme_ioctl(struct block_device *bdev, fmode_t mode, 661*2405252aSChristoph Hellwig unsigned int cmd, unsigned long arg); 662*2405252aSChristoph Hellwig int nvme_ns_head_ioctl(struct block_device *bdev, fmode_t mode, 663*2405252aSChristoph Hellwig unsigned int cmd, unsigned long arg); 664*2405252aSChristoph Hellwig long nvme_dev_ioctl(struct file *file, unsigned int cmd, 665*2405252aSChristoph Hellwig unsigned long arg); 666d558fb51SMatias Bjørling 66733b14f67SHannes Reinecke extern const struct attribute_group *nvme_ns_id_attr_groups[]; 66832acab31SChristoph Hellwig extern const struct block_device_operations nvme_ns_head_ops; 66932acab31SChristoph Hellwig 67032acab31SChristoph Hellwig #ifdef CONFIG_NVME_MULTIPATH 67166b20ac0SMarta Rybczynska static inline bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl) 67266b20ac0SMarta Rybczynska { 67366b20ac0SMarta Rybczynska return ctrl->ana_log_buf != NULL; 67466b20ac0SMarta Rybczynska } 67566b20ac0SMarta Rybczynska 676b9156daeSSagi Grimberg void nvme_mpath_unfreeze(struct nvme_subsystem *subsys); 677b9156daeSSagi Grimberg void nvme_mpath_wait_freeze(struct nvme_subsystem *subsys); 678b9156daeSSagi Grimberg void nvme_mpath_start_freeze(struct nvme_subsystem *subsys); 6799953ab0cSChristoph Hellwig bool nvme_mpath_set_disk_name(struct nvme_ns *ns, char *disk_name, int *flags); 6805ddaabe8SChristoph Hellwig void nvme_failover_req(struct request *req); 68132acab31SChristoph Hellwig void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl); 68232acab31SChristoph Hellwig int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl,struct nvme_ns_head *head); 6830d0b660fSChristoph Hellwig void nvme_mpath_add_disk(struct nvme_ns *ns, struct nvme_id_ns *id); 68432acab31SChristoph Hellwig void nvme_mpath_remove_disk(struct nvme_ns_head *head); 6850d0b660fSChristoph Hellwig int nvme_mpath_init(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id); 6860d0b660fSChristoph Hellwig void nvme_mpath_uninit(struct nvme_ctrl *ctrl); 6870d0b660fSChristoph Hellwig void nvme_mpath_stop(struct nvme_ctrl *ctrl); 6880157ec8dSSagi Grimberg bool nvme_mpath_clear_current_path(struct nvme_ns *ns); 6890157ec8dSSagi Grimberg void nvme_mpath_clear_ctrl_paths(struct nvme_ctrl *ctrl); 69032acab31SChristoph Hellwig struct nvme_ns *nvme_find_path(struct nvme_ns_head *head); 691c62b37d9SChristoph Hellwig blk_qc_t nvme_ns_head_submit_bio(struct bio *bio); 692479a322fSSagi Grimberg 693479a322fSSagi Grimberg static inline void nvme_mpath_check_last_path(struct nvme_ns *ns) 694479a322fSSagi Grimberg { 695479a322fSSagi Grimberg struct nvme_ns_head *head = ns->head; 696479a322fSSagi Grimberg 697479a322fSSagi Grimberg if (head->disk && list_empty(&head->list)) 698479a322fSSagi Grimberg kblockd_schedule_work(&head->requeue_work); 699479a322fSSagi Grimberg } 700479a322fSSagi Grimberg 7012b59787aSMax Gurtovoy static inline void nvme_trace_bio_complete(struct request *req) 70235fe0d12SHannes Reinecke { 70335fe0d12SHannes Reinecke struct nvme_ns *ns = req->q->queuedata; 70435fe0d12SHannes Reinecke 70535fe0d12SHannes Reinecke if (req->cmd_flags & REQ_NVME_MPATH) 706d24de76aSChristoph Hellwig trace_block_bio_complete(ns->head->disk->queue, req->bio); 70735fe0d12SHannes Reinecke } 70835fe0d12SHannes Reinecke 7090d0b660fSChristoph Hellwig extern struct device_attribute dev_attr_ana_grpid; 7100d0b660fSChristoph Hellwig extern struct device_attribute dev_attr_ana_state; 71175c10e73SHannes Reinecke extern struct device_attribute subsys_attr_iopolicy; 7120d0b660fSChristoph Hellwig 71332acab31SChristoph Hellwig #else 7140d0b660fSChristoph Hellwig static inline bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl) 7150d0b660fSChristoph Hellwig { 7160d0b660fSChristoph Hellwig return false; 7170d0b660fSChristoph Hellwig } 7189953ab0cSChristoph Hellwig static inline bool nvme_mpath_set_disk_name(struct nvme_ns *ns, char *disk_name, 7199953ab0cSChristoph Hellwig int *flags) 720a785dbccSKeith Busch { 7219953ab0cSChristoph Hellwig return false; 722a785dbccSKeith Busch } 7235ddaabe8SChristoph Hellwig static inline void nvme_failover_req(struct request *req) 72432acab31SChristoph Hellwig { 72532acab31SChristoph Hellwig } 72632acab31SChristoph Hellwig static inline void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl) 72732acab31SChristoph Hellwig { 72832acab31SChristoph Hellwig } 72932acab31SChristoph Hellwig static inline int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl, 73032acab31SChristoph Hellwig struct nvme_ns_head *head) 73132acab31SChristoph Hellwig { 73232acab31SChristoph Hellwig return 0; 73332acab31SChristoph Hellwig } 7340d0b660fSChristoph Hellwig static inline void nvme_mpath_add_disk(struct nvme_ns *ns, 7350d0b660fSChristoph Hellwig struct nvme_id_ns *id) 73632acab31SChristoph Hellwig { 73732acab31SChristoph Hellwig } 73832acab31SChristoph Hellwig static inline void nvme_mpath_remove_disk(struct nvme_ns_head *head) 73932acab31SChristoph Hellwig { 74032acab31SChristoph Hellwig } 7410157ec8dSSagi Grimberg static inline bool nvme_mpath_clear_current_path(struct nvme_ns *ns) 7420157ec8dSSagi Grimberg { 7430157ec8dSSagi Grimberg return false; 7440157ec8dSSagi Grimberg } 7450157ec8dSSagi Grimberg static inline void nvme_mpath_clear_ctrl_paths(struct nvme_ctrl *ctrl) 74632acab31SChristoph Hellwig { 74732acab31SChristoph Hellwig } 748479a322fSSagi Grimberg static inline void nvme_mpath_check_last_path(struct nvme_ns *ns) 749479a322fSSagi Grimberg { 750479a322fSSagi Grimberg } 7512b59787aSMax Gurtovoy static inline void nvme_trace_bio_complete(struct request *req) 75235fe0d12SHannes Reinecke { 75335fe0d12SHannes Reinecke } 7540d0b660fSChristoph Hellwig static inline int nvme_mpath_init(struct nvme_ctrl *ctrl, 7550d0b660fSChristoph Hellwig struct nvme_id_ctrl *id) 7560d0b660fSChristoph Hellwig { 7572bd64307SKanchan Joshi if (ctrl->subsys->cmic & NVME_CTRL_CMIC_ANA) 75814a1336eSChristoph Hellwig dev_warn(ctrl->device, 75914a1336eSChristoph Hellwig "Please enable CONFIG_NVME_MULTIPATH for full support of multi-port devices.\n"); 7600d0b660fSChristoph Hellwig return 0; 7610d0b660fSChristoph Hellwig } 7620d0b660fSChristoph Hellwig static inline void nvme_mpath_uninit(struct nvme_ctrl *ctrl) 7630d0b660fSChristoph Hellwig { 7640d0b660fSChristoph Hellwig } 7650d0b660fSChristoph Hellwig static inline void nvme_mpath_stop(struct nvme_ctrl *ctrl) 7660d0b660fSChristoph Hellwig { 7670d0b660fSChristoph Hellwig } 768b9156daeSSagi Grimberg static inline void nvme_mpath_unfreeze(struct nvme_subsystem *subsys) 769b9156daeSSagi Grimberg { 770b9156daeSSagi Grimberg } 771b9156daeSSagi Grimberg static inline void nvme_mpath_wait_freeze(struct nvme_subsystem *subsys) 772b9156daeSSagi Grimberg { 773b9156daeSSagi Grimberg } 774b9156daeSSagi Grimberg static inline void nvme_mpath_start_freeze(struct nvme_subsystem *subsys) 775b9156daeSSagi Grimberg { 776b9156daeSSagi Grimberg } 77732acab31SChristoph Hellwig #endif /* CONFIG_NVME_MULTIPATH */ 77832acab31SChristoph Hellwig 7797fad20ddSChristoph Hellwig int nvme_revalidate_zones(struct nvme_ns *ns); 780240e6ee2SKeith Busch #ifdef CONFIG_BLK_DEV_ZONED 781d525c3c0SChristoph Hellwig int nvme_update_zone_info(struct nvme_ns *ns, unsigned lbaf); 782240e6ee2SKeith Busch int nvme_report_zones(struct gendisk *disk, sector_t sector, 783240e6ee2SKeith Busch unsigned int nr_zones, report_zones_cb cb, void *data); 784240e6ee2SKeith Busch 785240e6ee2SKeith Busch blk_status_t nvme_setup_zone_mgmt_send(struct nvme_ns *ns, struct request *req, 786240e6ee2SKeith Busch struct nvme_command *cmnd, 787240e6ee2SKeith Busch enum nvme_zone_mgmt_action action); 788240e6ee2SKeith Busch #else 789240e6ee2SKeith Busch #define nvme_report_zones NULL 790240e6ee2SKeith Busch 791240e6ee2SKeith Busch static inline blk_status_t nvme_setup_zone_mgmt_send(struct nvme_ns *ns, 792240e6ee2SKeith Busch struct request *req, struct nvme_command *cmnd, 793240e6ee2SKeith Busch enum nvme_zone_mgmt_action action) 794240e6ee2SKeith Busch { 795240e6ee2SKeith Busch return BLK_STS_NOTSUPP; 796240e6ee2SKeith Busch } 797240e6ee2SKeith Busch 798d525c3c0SChristoph Hellwig static inline int nvme_update_zone_info(struct nvme_ns *ns, unsigned lbaf) 799240e6ee2SKeith Busch { 800240e6ee2SKeith Busch dev_warn(ns->ctrl->device, 801240e6ee2SKeith Busch "Please enable CONFIG_BLK_DEV_ZONED to support ZNS devices\n"); 802240e6ee2SKeith Busch return -EPROTONOSUPPORT; 803240e6ee2SKeith Busch } 804240e6ee2SKeith Busch #endif 805240e6ee2SKeith Busch 806c4699e70SKeith Busch #ifdef CONFIG_NVM 8073dc87dd0SMatias Bjørling int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, int node); 808b0b4e09cSMatias Bjørling void nvme_nvm_unregister(struct nvme_ns *ns); 80933b14f67SHannes Reinecke extern const struct attribute_group nvme_nvm_attr_group; 810d7790d37SChristoph Hellwig int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, void __user *argp); 811c4699e70SKeith Busch #else 812b0b4e09cSMatias Bjørling static inline int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, 8133dc87dd0SMatias Bjørling int node) 814c4699e70SKeith Busch { 815c4699e70SKeith Busch return 0; 816c4699e70SKeith Busch } 817c4699e70SKeith Busch 818b0b4e09cSMatias Bjørling static inline void nvme_nvm_unregister(struct nvme_ns *ns) {}; 81984d4add7SMatias Bjørling static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, 820d7790d37SChristoph Hellwig void __user *argp) 82184d4add7SMatias Bjørling { 82284d4add7SMatias Bjørling return -ENOTTY; 82384d4add7SMatias Bjørling } 8243dc87dd0SMatias Bjørling #endif /* CONFIG_NVM */ 8253dc87dd0SMatias Bjørling 82640267efdSSimon A. F. Lund static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev) 82740267efdSSimon A. F. Lund { 82840267efdSSimon A. F. Lund return dev_to_disk(dev)->private_data; 82940267efdSSimon A. F. Lund } 830ca064085SMatias Bjørling 831400b6a7bSGuenter Roeck #ifdef CONFIG_NVME_HWMON 83259e330f8SKeith Busch int nvme_hwmon_init(struct nvme_ctrl *ctrl); 833ed7770f6SHannes Reinecke void nvme_hwmon_exit(struct nvme_ctrl *ctrl); 834400b6a7bSGuenter Roeck #else 83559e330f8SKeith Busch static inline int nvme_hwmon_init(struct nvme_ctrl *ctrl) 83659e330f8SKeith Busch { 83759e330f8SKeith Busch return 0; 83859e330f8SKeith Busch } 839ed7770f6SHannes Reinecke 840ed7770f6SHannes Reinecke static inline void nvme_hwmon_exit(struct nvme_ctrl *ctrl) 841ed7770f6SHannes Reinecke { 842ed7770f6SHannes Reinecke } 843400b6a7bSGuenter Roeck #endif 844400b6a7bSGuenter Roeck 845df21b6b1SLogan Gunthorpe u32 nvme_command_effects(struct nvme_ctrl *ctrl, struct nvme_ns *ns, 846df21b6b1SLogan Gunthorpe u8 opcode); 84717365ae6SLogan Gunthorpe void nvme_execute_passthru_rq(struct request *rq); 848b2702aaaSChaitanya Kulkarni struct nvme_ctrl *nvme_ctrl_from_file(struct file *file); 84924493b8bSLogan Gunthorpe struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid); 85024493b8bSLogan Gunthorpe void nvme_put_ns(struct nvme_ns *ns); 851df21b6b1SLogan Gunthorpe 85257dacad5SJay Sternberg #endif /* _NVME_H */ 853