1bc50ad75SChristoph Hellwig /* SPDX-License-Identifier: GPL-2.0 */ 257dacad5SJay Sternberg /* 357dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 457dacad5SJay Sternberg */ 557dacad5SJay Sternberg 657dacad5SJay Sternberg #ifndef _NVME_H 757dacad5SJay Sternberg #define _NVME_H 857dacad5SJay Sternberg 957dacad5SJay Sternberg #include <linux/nvme.h> 10a6a5149bSChristoph Hellwig #include <linux/cdev.h> 1157dacad5SJay Sternberg #include <linux/pci.h> 1257dacad5SJay Sternberg #include <linux/kref.h> 1357dacad5SJay Sternberg #include <linux/blk-mq.h> 14a98e58e5SScott Bauer #include <linux/sed-opal.h> 15b9e03857SThomas Tai #include <linux/fault-inject.h> 16978628ecSJohannes Thumshirn #include <linux/rcupdate.h> 17c1ac9a4bSKeith Busch #include <linux/wait.h> 184d2ce688SJames Smart #include <linux/t10-pi.h> 1957dacad5SJay Sternberg 2035fe0d12SHannes Reinecke #include <trace/events/block.h> 2135fe0d12SHannes Reinecke 228ae4e447SMarc Olson extern unsigned int nvme_io_timeout; 2357dacad5SJay Sternberg #define NVME_IO_TIMEOUT (nvme_io_timeout * HZ) 2457dacad5SJay Sternberg 258ae4e447SMarc Olson extern unsigned int admin_timeout; 26dc96f938SChaitanya Kulkarni #define NVME_ADMIN_TIMEOUT (admin_timeout * HZ) 2721d34711SChristoph Hellwig 28038bd4cbSSagi Grimberg #define NVME_DEFAULT_KATO 5 29038bd4cbSSagi Grimberg 3038e18002SIsrael Rukshin #ifdef CONFIG_ARCH_NO_SG_CHAIN 3138e18002SIsrael Rukshin #define NVME_INLINE_SG_CNT 0 32ba7ca2aeSIsrael Rukshin #define NVME_INLINE_METADATA_SG_CNT 0 3338e18002SIsrael Rukshin #else 3438e18002SIsrael Rukshin #define NVME_INLINE_SG_CNT 2 35ba7ca2aeSIsrael Rukshin #define NVME_INLINE_METADATA_SG_CNT 1 3638e18002SIsrael Rukshin #endif 3738e18002SIsrael Rukshin 386c3c05b0SChaitanya Kulkarni /* 396c3c05b0SChaitanya Kulkarni * Default to a 4K page size, with the intention to update this 406c3c05b0SChaitanya Kulkarni * path in the future to accommodate architectures with differing 416c3c05b0SChaitanya Kulkarni * kernel and IO page sizes. 426c3c05b0SChaitanya Kulkarni */ 436c3c05b0SChaitanya Kulkarni #define NVME_CTRL_PAGE_SHIFT 12 446c3c05b0SChaitanya Kulkarni #define NVME_CTRL_PAGE_SIZE (1 << NVME_CTRL_PAGE_SHIFT) 456c3c05b0SChaitanya Kulkarni 469a6327d2SSagi Grimberg extern struct workqueue_struct *nvme_wq; 47b227c59bSRoy Shterman extern struct workqueue_struct *nvme_reset_wq; 48b227c59bSRoy Shterman extern struct workqueue_struct *nvme_delete_wq; 499a6327d2SSagi Grimberg 5057dacad5SJay Sternberg /* 51106198edSChristoph Hellwig * List of workarounds for devices that required behavior not specified in 52106198edSChristoph Hellwig * the standard. 5357dacad5SJay Sternberg */ 54106198edSChristoph Hellwig enum nvme_quirks { 55106198edSChristoph Hellwig /* 56106198edSChristoph Hellwig * Prefers I/O aligned to a stripe size specified in a vendor 57106198edSChristoph Hellwig * specific Identify field. 58106198edSChristoph Hellwig */ 59106198edSChristoph Hellwig NVME_QUIRK_STRIPE_SIZE = (1 << 0), 60540c801cSKeith Busch 61540c801cSKeith Busch /* 62540c801cSKeith Busch * The controller doesn't handle Identify value others than 0 or 1 63540c801cSKeith Busch * correctly. 64540c801cSKeith Busch */ 65540c801cSKeith Busch NVME_QUIRK_IDENTIFY_CNS = (1 << 1), 6608095e70SKeith Busch 6708095e70SKeith Busch /* 68e850fd16SChristoph Hellwig * The controller deterministically returns O's on reads to 69e850fd16SChristoph Hellwig * logical blocks that deallocate was called on. 7008095e70SKeith Busch */ 71e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES = (1 << 2), 7254adc010SGuilherme G. Piccoli 7354adc010SGuilherme G. Piccoli /* 7454adc010SGuilherme G. Piccoli * The controller needs a delay before starts checking the device 7554adc010SGuilherme G. Piccoli * readiness, which is done by reading the NVME_CSTS_RDY bit. 7654adc010SGuilherme G. Piccoli */ 7754adc010SGuilherme G. Piccoli NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3), 78c5552fdeSAndy Lutomirski 79c5552fdeSAndy Lutomirski /* 80c5552fdeSAndy Lutomirski * APST should not be used. 81c5552fdeSAndy Lutomirski */ 82c5552fdeSAndy Lutomirski NVME_QUIRK_NO_APST = (1 << 4), 83ff5350a8SAndy Lutomirski 84ff5350a8SAndy Lutomirski /* 85ff5350a8SAndy Lutomirski * The deepest sleep state should not be used. 86ff5350a8SAndy Lutomirski */ 87ff5350a8SAndy Lutomirski NVME_QUIRK_NO_DEEPEST_PS = (1 << 5), 88608cc4b1SChristoph Hellwig 89608cc4b1SChristoph Hellwig /* 909abd68efSJens Axboe * Set MEDIUM priority on SQ creation 919abd68efSJens Axboe */ 929abd68efSJens Axboe NVME_QUIRK_MEDIUM_PRIO_SQ = (1 << 7), 936299358dSJames Dingwall 946299358dSJames Dingwall /* 956299358dSJames Dingwall * Ignore device provided subnqn. 966299358dSJames Dingwall */ 976299358dSJames Dingwall NVME_QUIRK_IGNORE_DEV_SUBNQN = (1 << 8), 987b210e4eSChristoph Hellwig 997b210e4eSChristoph Hellwig /* 1007b210e4eSChristoph Hellwig * Broken Write Zeroes. 1017b210e4eSChristoph Hellwig */ 1027b210e4eSChristoph Hellwig NVME_QUIRK_DISABLE_WRITE_ZEROES = (1 << 9), 103cb32de1bSMario Limonciello 104cb32de1bSMario Limonciello /* 105cb32de1bSMario Limonciello * Force simple suspend/resume path. 106cb32de1bSMario Limonciello */ 107cb32de1bSMario Limonciello NVME_QUIRK_SIMPLE_SUSPEND = (1 << 10), 1087ad67ca5SLinus Torvalds 1097ad67ca5SLinus Torvalds /* 11066341331SBenjamin Herrenschmidt * Use only one interrupt vector for all queues 11166341331SBenjamin Herrenschmidt */ 1127ad67ca5SLinus Torvalds NVME_QUIRK_SINGLE_VECTOR = (1 << 11), 11366341331SBenjamin Herrenschmidt 11466341331SBenjamin Herrenschmidt /* 11566341331SBenjamin Herrenschmidt * Use non-standard 128 bytes SQEs. 11666341331SBenjamin Herrenschmidt */ 1177ad67ca5SLinus Torvalds NVME_QUIRK_128_BYTES_SQES = (1 << 12), 118d38e9f04SBenjamin Herrenschmidt 119d38e9f04SBenjamin Herrenschmidt /* 120d38e9f04SBenjamin Herrenschmidt * Prevent tag overlap between queues 121d38e9f04SBenjamin Herrenschmidt */ 1227ad67ca5SLinus Torvalds NVME_QUIRK_SHARED_TAGS = (1 << 13), 1236c6aa2f2SAkinobu Mita 1246c6aa2f2SAkinobu Mita /* 1256c6aa2f2SAkinobu Mita * Don't change the value of the temperature threshold feature 1266c6aa2f2SAkinobu Mita */ 1276c6aa2f2SAkinobu Mita NVME_QUIRK_NO_TEMP_THRESH_CHANGE = (1 << 14), 1285bedd3afSChristoph Hellwig 1295bedd3afSChristoph Hellwig /* 1305bedd3afSChristoph Hellwig * The controller doesn't handle the Identify Namespace 1315bedd3afSChristoph Hellwig * Identification Descriptor list subcommand despite claiming 1325bedd3afSChristoph Hellwig * NVMe 1.3 compliance. 1335bedd3afSChristoph Hellwig */ 1345bedd3afSChristoph Hellwig NVME_QUIRK_NO_NS_DESC_LIST = (1 << 15), 1354bdf2603SFilippo Sironi 1364bdf2603SFilippo Sironi /* 1374bdf2603SFilippo Sironi * The controller does not properly handle DMA addresses over 1384bdf2603SFilippo Sironi * 48 bits. 1394bdf2603SFilippo Sironi */ 1404bdf2603SFilippo Sironi NVME_QUIRK_DMA_ADDRESS_BITS_48 = (1 << 16), 141a2941f6aSKeith Busch 142a2941f6aSKeith Busch /* 143a2941f6aSKeith Busch * The controller requires the command_id value be be limited, so skip 144a2941f6aSKeith Busch * encoding the generation sequence number. 145a2941f6aSKeith Busch */ 146a2941f6aSKeith Busch NVME_QUIRK_SKIP_CID_GEN = (1 << 17), 14700ff400eSChristoph Hellwig 14800ff400eSChristoph Hellwig /* 14900ff400eSChristoph Hellwig * Reports garbage in the namespace identifiers (eui64, nguid, uuid). 15000ff400eSChristoph Hellwig */ 15100ff400eSChristoph Hellwig NVME_QUIRK_BOGUS_NID = (1 << 18), 152106198edSChristoph Hellwig }; 153106198edSChristoph Hellwig 154d49187e9SChristoph Hellwig /* 155d49187e9SChristoph Hellwig * Common request structure for NVMe passthrough. All drivers must have 156d49187e9SChristoph Hellwig * this structure as the first member of their request-private data. 157d49187e9SChristoph Hellwig */ 158d49187e9SChristoph Hellwig struct nvme_request { 159d49187e9SChristoph Hellwig struct nvme_command *cmd; 160d49187e9SChristoph Hellwig union nvme_result result; 161e7006de6SSagi Grimberg u8 genctr; 16244e44b29SChristoph Hellwig u8 retries; 16327fa9bc5SChristoph Hellwig u8 flags; 16427fa9bc5SChristoph Hellwig u16 status; 16559e29ce6SSagi Grimberg struct nvme_ctrl *ctrl; 16627fa9bc5SChristoph Hellwig }; 16727fa9bc5SChristoph Hellwig 16832acab31SChristoph Hellwig /* 16932acab31SChristoph Hellwig * Mark a bio as coming in through the mpath node. 17032acab31SChristoph Hellwig */ 17132acab31SChristoph Hellwig #define REQ_NVME_MPATH REQ_DRV 17232acab31SChristoph Hellwig 17327fa9bc5SChristoph Hellwig enum { 17427fa9bc5SChristoph Hellwig NVME_REQ_CANCELLED = (1 << 0), 175bb06ec31SJames Smart NVME_REQ_USERCMD = (1 << 1), 176d49187e9SChristoph Hellwig }; 177d49187e9SChristoph Hellwig 178d49187e9SChristoph Hellwig static inline struct nvme_request *nvme_req(struct request *req) 179d49187e9SChristoph Hellwig { 180d49187e9SChristoph Hellwig return blk_mq_rq_to_pdu(req); 181d49187e9SChristoph Hellwig } 182d49187e9SChristoph Hellwig 1835d87eb94SKeith Busch static inline u16 nvme_req_qid(struct request *req) 1845d87eb94SKeith Busch { 185643c476dSKeith Busch if (!req->q->queuedata) 1865d87eb94SKeith Busch return 0; 18784115d6dSBaolin Wang 18884115d6dSBaolin Wang return req->mq_hctx->queue_num + 1; 1895d87eb94SKeith Busch } 1905d87eb94SKeith Busch 19154adc010SGuilherme G. Piccoli /* The below value is the specific amount of delay needed before checking 19254adc010SGuilherme G. Piccoli * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the 19354adc010SGuilherme G. Piccoli * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was 19454adc010SGuilherme G. Piccoli * found empirically. 19554adc010SGuilherme G. Piccoli */ 1968c97eeccSJeff Lien #define NVME_QUIRK_DELAY_AMOUNT 2300 19754adc010SGuilherme G. Piccoli 1984212f4e9SSagi Grimberg /* 1994212f4e9SSagi Grimberg * enum nvme_ctrl_state: Controller state 2004212f4e9SSagi Grimberg * 2014212f4e9SSagi Grimberg * @NVME_CTRL_NEW: New controller just allocated, initial state 2024212f4e9SSagi Grimberg * @NVME_CTRL_LIVE: Controller is connected and I/O capable 2034212f4e9SSagi Grimberg * @NVME_CTRL_RESETTING: Controller is resetting (or scheduled reset) 2044212f4e9SSagi Grimberg * @NVME_CTRL_CONNECTING: Controller is disconnected, now connecting the 2054212f4e9SSagi Grimberg * transport 2064212f4e9SSagi Grimberg * @NVME_CTRL_DELETING: Controller is deleting (or scheduled deletion) 207ecca390eSSagi Grimberg * @NVME_CTRL_DELETING_NOIO: Controller is deleting and I/O is not 208ecca390eSSagi Grimberg * disabled/failed immediately. This state comes 209ecca390eSSagi Grimberg * after all async event processing took place and 210ecca390eSSagi Grimberg * before ns removal and the controller deletion 211ecca390eSSagi Grimberg * progress 2124212f4e9SSagi Grimberg * @NVME_CTRL_DEAD: Controller is non-present/unresponsive during 2134212f4e9SSagi Grimberg * shutdown or removal. In this case we forcibly 2144212f4e9SSagi Grimberg * kill all inflight I/O as they have no chance to 2154212f4e9SSagi Grimberg * complete 2164212f4e9SSagi Grimberg */ 217bb8d261eSChristoph Hellwig enum nvme_ctrl_state { 218bb8d261eSChristoph Hellwig NVME_CTRL_NEW, 219bb8d261eSChristoph Hellwig NVME_CTRL_LIVE, 220bb8d261eSChristoph Hellwig NVME_CTRL_RESETTING, 221ad6a0a52SMax Gurtovoy NVME_CTRL_CONNECTING, 222bb8d261eSChristoph Hellwig NVME_CTRL_DELETING, 223ecca390eSSagi Grimberg NVME_CTRL_DELETING_NOIO, 2240ff9d4e1SKeith Busch NVME_CTRL_DEAD, 225bb8d261eSChristoph Hellwig }; 226bb8d261eSChristoph Hellwig 227a3646451SAkinobu Mita struct nvme_fault_inject { 228a3646451SAkinobu Mita #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS 229a3646451SAkinobu Mita struct fault_attr attr; 230a3646451SAkinobu Mita struct dentry *parent; 231a3646451SAkinobu Mita bool dont_retry; /* DNR, do not retry */ 232a3646451SAkinobu Mita u16 status; /* status code */ 233a3646451SAkinobu Mita #endif 234a3646451SAkinobu Mita }; 235a3646451SAkinobu Mita 2361c63dc66SChristoph Hellwig struct nvme_ctrl { 2376e3ca03eSSagi Grimberg bool comp_seen; 238bb8d261eSChristoph Hellwig enum nvme_ctrl_state state; 239bd4da3abSAndy Lutomirski bool identified; 240bb8d261eSChristoph Hellwig spinlock_t lock; 241e7ad43c3SKeith Busch struct mutex scan_lock; 2421c63dc66SChristoph Hellwig const struct nvme_ctrl_ops *ops; 24357dacad5SJay Sternberg struct request_queue *admin_q; 24407bfcd09SChristoph Hellwig struct request_queue *connect_q; 245e7832cb4SSagi Grimberg struct request_queue *fabrics_q; 24657dacad5SJay Sternberg struct device *dev; 24757dacad5SJay Sternberg int instance; 248103e515eSHannes Reinecke int numa_node; 2495bae7f73SChristoph Hellwig struct blk_mq_tag_set *tagset; 25034b6c231SSagi Grimberg struct blk_mq_tag_set *admin_tagset; 2515bae7f73SChristoph Hellwig struct list_head namespaces; 252765cc031SJianchao Wang struct rw_semaphore namespaces_rwsem; 253d22524a4SChristoph Hellwig struct device ctrl_device; 2545bae7f73SChristoph Hellwig struct device *device; /* char device */ 255ed7770f6SHannes Reinecke #ifdef CONFIG_NVME_HWMON 256ed7770f6SHannes Reinecke struct device *hwmon_device; 257ed7770f6SHannes Reinecke #endif 258a6a5149bSChristoph Hellwig struct cdev cdev; 259d86c4d8eSChristoph Hellwig struct work_struct reset_work; 260c5017e85SChristoph Hellwig struct work_struct delete_work; 261c1ac9a4bSKeith Busch wait_queue_head_t state_wq; 2621c63dc66SChristoph Hellwig 263ab9e00ccSChristoph Hellwig struct nvme_subsystem *subsys; 264ab9e00ccSChristoph Hellwig struct list_head subsys_entry; 265ab9e00ccSChristoph Hellwig 2664f1244c8SChristoph Hellwig struct opal_dev *opal_dev; 267a98e58e5SScott Bauer 26857dacad5SJay Sternberg char name[12]; 26976e3914aSChristoph Hellwig u16 cntlid; 2705fd4ce1bSChristoph Hellwig 2715fd4ce1bSChristoph Hellwig u32 ctrl_config; 272b6dccf7fSArnav Dawn u16 mtfa; 273d858e5f0SSagi Grimberg u32 queue_count; 2745fd4ce1bSChristoph Hellwig 27520d0dfe6SSagi Grimberg u64 cap; 27657dacad5SJay Sternberg u32 max_hw_sectors; 277943e942eSJens Axboe u32 max_segments; 27895093350SMax Gurtovoy u32 max_integrity_segments; 2795befc7c2SKeith Busch u32 max_discard_sectors; 2805befc7c2SKeith Busch u32 max_discard_segments; 2815befc7c2SKeith Busch u32 max_zeroes_sectors; 282240e6ee2SKeith Busch #ifdef CONFIG_BLK_DEV_ZONED 283240e6ee2SKeith Busch u32 max_zone_append; 284240e6ee2SKeith Busch #endif 28549cd84b6SKeith Busch u16 crdt[3]; 28657dacad5SJay Sternberg u16 oncs; 287*1a86924eSTom Yan u32 dmrsl; 2888a9ae523SScott Bauer u16 oacs; 289f968688fSKeith Busch u16 sqsize; 2900d0b660fSChristoph Hellwig u32 max_namespaces; 2916bf25d16SChristoph Hellwig atomic_t abort_limit; 29257dacad5SJay Sternberg u8 vwc; 293f3ca80fcSChristoph Hellwig u32 vs; 29407bfcd09SChristoph Hellwig u32 sgls; 295038bd4cbSSagi Grimberg u16 kas; 296c5552fdeSAndy Lutomirski u8 npss; 297c5552fdeSAndy Lutomirski u8 apsta; 298400b6a7bSGuenter Roeck u16 wctemp; 299400b6a7bSGuenter Roeck u16 cctemp; 300c0561f82SHannes Reinecke u32 oaes; 301e3d7874dSKeith Busch u32 aen_result; 3023e53ba38SSagi Grimberg u32 ctratt; 30307fbd32aSMartin K. Petersen unsigned int shutdown_timeout; 304038bd4cbSSagi Grimberg unsigned int kato; 305f3ca80fcSChristoph Hellwig bool subsystem; 306106198edSChristoph Hellwig unsigned long quirks; 307c5552fdeSAndy Lutomirski struct nvme_id_power_state psd[32]; 30884fef62dSKeith Busch struct nvme_effects_log *effects; 3091cf7a12eSChaitanya Kulkarni struct xarray cels; 3105955be21SChristoph Hellwig struct work_struct scan_work; 311f866fc42SChristoph Hellwig struct work_struct async_event_work; 312038bd4cbSSagi Grimberg struct delayed_work ka_work; 3138c4dfea9SVictor Gladkov struct delayed_work failfast_work; 3140a34e466SRoland Dreier struct nvme_command ka_cmd; 315b6dccf7fSArnav Dawn struct work_struct fw_act_work; 31630d90964SChristoph Hellwig unsigned long events; 31707bfcd09SChristoph Hellwig 3180d0b660fSChristoph Hellwig #ifdef CONFIG_NVME_MULTIPATH 3190d0b660fSChristoph Hellwig /* asymmetric namespace access: */ 3200d0b660fSChristoph Hellwig u8 anacap; 3210d0b660fSChristoph Hellwig u8 anatt; 3220d0b660fSChristoph Hellwig u32 anagrpmax; 3230d0b660fSChristoph Hellwig u32 nanagrpid; 3240d0b660fSChristoph Hellwig struct mutex ana_lock; 3250d0b660fSChristoph Hellwig struct nvme_ana_rsp_hdr *ana_log_buf; 3260d0b660fSChristoph Hellwig size_t ana_log_size; 3270d0b660fSChristoph Hellwig struct timer_list anatt_timer; 3280d0b660fSChristoph Hellwig struct work_struct ana_work; 3290d0b660fSChristoph Hellwig #endif 3300d0b660fSChristoph Hellwig 331c5552fdeSAndy Lutomirski /* Power saving configuration */ 332c5552fdeSAndy Lutomirski u64 ps_max_latency_us; 33376a5af84SKai-Heng Feng bool apst_enabled; 334c5552fdeSAndy Lutomirski 335044a9df1SChristoph Hellwig /* PCIe only: */ 336fe6d53c9SChristoph Hellwig u32 hmpre; 337fe6d53c9SChristoph Hellwig u32 hmmin; 338044a9df1SChristoph Hellwig u32 hmminds; 339044a9df1SChristoph Hellwig u16 hmmaxd; 340fe6d53c9SChristoph Hellwig 34107bfcd09SChristoph Hellwig /* Fabrics only */ 34207bfcd09SChristoph Hellwig u32 ioccsz; 34307bfcd09SChristoph Hellwig u32 iorcsz; 34407bfcd09SChristoph Hellwig u16 icdoff; 34507bfcd09SChristoph Hellwig u16 maxcmd; 346fdf9dfa8SSagi Grimberg int nr_reconnects; 3478c4dfea9SVictor Gladkov unsigned long flags; 3488c4dfea9SVictor Gladkov #define NVME_CTRL_FAILFAST_EXPIRED 0 3499e6a6b12SMing Lei #define NVME_CTRL_ADMIN_Q_STOPPED 1 35007bfcd09SChristoph Hellwig struct nvmf_ctrl_options *opts; 351cb5b7262SJens Axboe 352cb5b7262SJens Axboe struct page *discard_page; 353cb5b7262SJens Axboe unsigned long discard_page_busy; 354f79d5fdaSAkinobu Mita 355f79d5fdaSAkinobu Mita struct nvme_fault_inject fault_inject; 35686c2457aSMartin Belanger 35786c2457aSMartin Belanger enum nvme_ctrl_type cntrltype; 35886c2457aSMartin Belanger enum nvme_dctype dctype; 35957dacad5SJay Sternberg }; 36057dacad5SJay Sternberg 36175c10e73SHannes Reinecke enum nvme_iopolicy { 36275c10e73SHannes Reinecke NVME_IOPOLICY_NUMA, 36375c10e73SHannes Reinecke NVME_IOPOLICY_RR, 36475c10e73SHannes Reinecke }; 36575c10e73SHannes Reinecke 366ab9e00ccSChristoph Hellwig struct nvme_subsystem { 367ab9e00ccSChristoph Hellwig int instance; 368ab9e00ccSChristoph Hellwig struct device dev; 369ab9e00ccSChristoph Hellwig /* 370ab9e00ccSChristoph Hellwig * Because we unregister the device on the last put we need 371ab9e00ccSChristoph Hellwig * a separate refcount. 372ab9e00ccSChristoph Hellwig */ 373ab9e00ccSChristoph Hellwig struct kref ref; 374ab9e00ccSChristoph Hellwig struct list_head entry; 375ab9e00ccSChristoph Hellwig struct mutex lock; 376ab9e00ccSChristoph Hellwig struct list_head ctrls; 377ed754e5dSChristoph Hellwig struct list_head nsheads; 378ab9e00ccSChristoph Hellwig char subnqn[NVMF_NQN_SIZE]; 379ab9e00ccSChristoph Hellwig char serial[20]; 380ab9e00ccSChristoph Hellwig char model[40]; 381ab9e00ccSChristoph Hellwig char firmware_rev[8]; 382ab9e00ccSChristoph Hellwig u8 cmic; 383954ae166SHannes Reinecke enum nvme_subsys_type subtype; 384ab9e00ccSChristoph Hellwig u16 vendor_id; 38581adb863SBart Van Assche u16 awupf; /* 0's based awupf value. */ 386ed754e5dSChristoph Hellwig struct ida ns_ida; 38775c10e73SHannes Reinecke #ifdef CONFIG_NVME_MULTIPATH 38875c10e73SHannes Reinecke enum nvme_iopolicy iopolicy; 38975c10e73SHannes Reinecke #endif 390ab9e00ccSChristoph Hellwig }; 391ab9e00ccSChristoph Hellwig 392002fab04SChristoph Hellwig /* 393002fab04SChristoph Hellwig * Container structure for uniqueue namespace identifiers. 394002fab04SChristoph Hellwig */ 395002fab04SChristoph Hellwig struct nvme_ns_ids { 396002fab04SChristoph Hellwig u8 eui64[8]; 397002fab04SChristoph Hellwig u8 nguid[16]; 398002fab04SChristoph Hellwig uuid_t uuid; 39971010c30SNiklas Cassel u8 csi; 400002fab04SChristoph Hellwig }; 401002fab04SChristoph Hellwig 402ed754e5dSChristoph Hellwig /* 403ed754e5dSChristoph Hellwig * Anchor structure for namespaces. There is one for each namespace in a 404ed754e5dSChristoph Hellwig * NVMe subsystem that any of our controllers can see, and the namespace 405ed754e5dSChristoph Hellwig * structure for each controller is chained of it. For private namespaces 406ed754e5dSChristoph Hellwig * there is a 1:1 relation to our namespace structures, that is ->list 407ed754e5dSChristoph Hellwig * only ever has a single entry for private namespaces. 408ed754e5dSChristoph Hellwig */ 409ed754e5dSChristoph Hellwig struct nvme_ns_head { 410ed754e5dSChristoph Hellwig struct list_head list; 411ed754e5dSChristoph Hellwig struct srcu_struct srcu; 412ed754e5dSChristoph Hellwig struct nvme_subsystem *subsys; 413ed754e5dSChristoph Hellwig unsigned ns_id; 414ed754e5dSChristoph Hellwig struct nvme_ns_ids ids; 415ed754e5dSChristoph Hellwig struct list_head entry; 416ed754e5dSChristoph Hellwig struct kref ref; 4170c284db7SKeith Busch bool shared; 418ed754e5dSChristoph Hellwig int instance; 419be93e87eSKeith Busch struct nvme_effects_log *effects; 4202637baedSMinwoo Im 4212637baedSMinwoo Im struct cdev cdev; 4222637baedSMinwoo Im struct device cdev_device; 4232637baedSMinwoo Im 424f3334447SChristoph Hellwig struct gendisk *disk; 42530897388SMinwoo Im #ifdef CONFIG_NVME_MULTIPATH 426f3334447SChristoph Hellwig struct bio_list requeue_list; 427f3334447SChristoph Hellwig spinlock_t requeue_lock; 428f3334447SChristoph Hellwig struct work_struct requeue_work; 429f3334447SChristoph Hellwig struct mutex lock; 430d8a22f85SAnton Eidelman unsigned long flags; 431d8a22f85SAnton Eidelman #define NVME_NSHEAD_DISK_LIVE 0 432f3334447SChristoph Hellwig struct nvme_ns __rcu *current_path[]; 433f3334447SChristoph Hellwig #endif 434ed754e5dSChristoph Hellwig }; 435ed754e5dSChristoph Hellwig 43630897388SMinwoo Im static inline bool nvme_ns_head_multipath(struct nvme_ns_head *head) 43730897388SMinwoo Im { 43830897388SMinwoo Im return IS_ENABLED(CONFIG_NVME_MULTIPATH) && head->disk; 43930897388SMinwoo Im } 44030897388SMinwoo Im 441ffc89b1dSMax Gurtovoy enum nvme_ns_features { 442ffc89b1dSMax Gurtovoy NVME_NS_EXT_LBAS = 1 << 0, /* support extended LBA format */ 443b29f8485SMax Gurtovoy NVME_NS_METADATA_SUPPORTED = 1 << 1, /* support getting generated md */ 444ffc89b1dSMax Gurtovoy }; 445ffc89b1dSMax Gurtovoy 44657dacad5SJay Sternberg struct nvme_ns { 44757dacad5SJay Sternberg struct list_head list; 44857dacad5SJay Sternberg 4491c63dc66SChristoph Hellwig struct nvme_ctrl *ctrl; 45057dacad5SJay Sternberg struct request_queue *queue; 45157dacad5SJay Sternberg struct gendisk *disk; 4520d0b660fSChristoph Hellwig #ifdef CONFIG_NVME_MULTIPATH 4530d0b660fSChristoph Hellwig enum nvme_ana_state ana_state; 4540d0b660fSChristoph Hellwig u32 ana_grpid; 4550d0b660fSChristoph Hellwig #endif 456ed754e5dSChristoph Hellwig struct list_head siblings; 45757dacad5SJay Sternberg struct kref kref; 458ed754e5dSChristoph Hellwig struct nvme_ns_head *head; 45957dacad5SJay Sternberg 46057dacad5SJay Sternberg int lba_shift; 46157dacad5SJay Sternberg u16 ms; 4624020aad8SKeith Busch u16 pi_size; 463f5d11840SJens Axboe u16 sgs; 464f5d11840SJens Axboe u32 sws; 46557dacad5SJay Sternberg u8 pi_type; 4664020aad8SKeith Busch u8 guard_type; 467240e6ee2SKeith Busch #ifdef CONFIG_BLK_DEV_ZONED 468240e6ee2SKeith Busch u64 zsze; 469240e6ee2SKeith Busch #endif 470ffc89b1dSMax Gurtovoy unsigned long features; 471646017a6SKeith Busch unsigned long flags; 472646017a6SKeith Busch #define NVME_NS_REMOVING 0 47369d9a99cSKeith Busch #define NVME_NS_DEAD 1 4740d0b660fSChristoph Hellwig #define NVME_NS_ANA_PENDING 2 4752f4c9ba2SJavier González #define NVME_NS_FORCE_RO 3 476e7d65803SHannes Reinecke #define NVME_NS_READY 4 4779e6a6b12SMing Lei #define NVME_NS_STOPPED 5 478b9e03857SThomas Tai 4792637baedSMinwoo Im struct cdev cdev; 4802637baedSMinwoo Im struct device cdev_device; 4812637baedSMinwoo Im 482b9e03857SThomas Tai struct nvme_fault_inject fault_inject; 483b9e03857SThomas Tai 48457dacad5SJay Sternberg }; 48557dacad5SJay Sternberg 4864d2ce688SJames Smart /* NVMe ns supports metadata actions by the controller (generate/strip) */ 4874d2ce688SJames Smart static inline bool nvme_ns_has_pi(struct nvme_ns *ns) 4884d2ce688SJames Smart { 4894020aad8SKeith Busch return ns->pi_type && ns->ms == ns->pi_size; 4904d2ce688SJames Smart } 4914d2ce688SJames Smart 4921c63dc66SChristoph Hellwig struct nvme_ctrl_ops { 4931a353d85SMing Lin const char *name; 494e439bb12SSagi Grimberg struct module *module; 495d3d5b87dSChristoph Hellwig unsigned int flags; 496d3d5b87dSChristoph Hellwig #define NVME_F_FABRICS (1 << 0) 497c81bfba9SChristoph Hellwig #define NVME_F_METADATA_SUPPORTED (1 << 1) 498e0596ab2SLogan Gunthorpe #define NVME_F_PCI_P2PDMA (1 << 2) 4991c63dc66SChristoph Hellwig int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val); 5005fd4ce1bSChristoph Hellwig int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val); 5017fd8930fSChristoph Hellwig int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val); 5021673f1f0SChristoph Hellwig void (*free_ctrl)(struct nvme_ctrl *ctrl); 503ad22c355SKeith Busch void (*submit_async_event)(struct nvme_ctrl *ctrl); 504c5017e85SChristoph Hellwig void (*delete_ctrl)(struct nvme_ctrl *ctrl); 5051a353d85SMing Lin int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size); 50657dacad5SJay Sternberg }; 50757dacad5SJay Sternberg 508e7006de6SSagi Grimberg /* 509e7006de6SSagi Grimberg * nvme command_id is constructed as such: 510e7006de6SSagi Grimberg * | xxxx | xxxxxxxxxxxx | 511e7006de6SSagi Grimberg * gen request tag 512e7006de6SSagi Grimberg */ 513e7006de6SSagi Grimberg #define nvme_genctr_mask(gen) (gen & 0xf) 514e7006de6SSagi Grimberg #define nvme_cid_install_genctr(gen) (nvme_genctr_mask(gen) << 12) 515e7006de6SSagi Grimberg #define nvme_genctr_from_cid(cid) ((cid & 0xf000) >> 12) 516e7006de6SSagi Grimberg #define nvme_tag_from_cid(cid) (cid & 0xfff) 517e7006de6SSagi Grimberg 518e7006de6SSagi Grimberg static inline u16 nvme_cid(struct request *rq) 519e7006de6SSagi Grimberg { 520e7006de6SSagi Grimberg return nvme_cid_install_genctr(nvme_req(rq)->genctr) | rq->tag; 521e7006de6SSagi Grimberg } 522e7006de6SSagi Grimberg 523e7006de6SSagi Grimberg static inline struct request *nvme_find_rq(struct blk_mq_tags *tags, 524e7006de6SSagi Grimberg u16 command_id) 525e7006de6SSagi Grimberg { 526e7006de6SSagi Grimberg u8 genctr = nvme_genctr_from_cid(command_id); 527e7006de6SSagi Grimberg u16 tag = nvme_tag_from_cid(command_id); 528e7006de6SSagi Grimberg struct request *rq; 529e7006de6SSagi Grimberg 530e7006de6SSagi Grimberg rq = blk_mq_tag_to_rq(tags, tag); 531e7006de6SSagi Grimberg if (unlikely(!rq)) { 532e7006de6SSagi Grimberg pr_err("could not locate request for tag %#x\n", 533e7006de6SSagi Grimberg tag); 534e7006de6SSagi Grimberg return NULL; 535e7006de6SSagi Grimberg } 536e7006de6SSagi Grimberg if (unlikely(nvme_genctr_mask(nvme_req(rq)->genctr) != genctr)) { 537e7006de6SSagi Grimberg dev_err(nvme_req(rq)->ctrl->device, 538e7006de6SSagi Grimberg "request %#x genctr mismatch (got %#x expected %#x)\n", 539e7006de6SSagi Grimberg tag, genctr, nvme_genctr_mask(nvme_req(rq)->genctr)); 540e7006de6SSagi Grimberg return NULL; 541e7006de6SSagi Grimberg } 542e7006de6SSagi Grimberg return rq; 543e7006de6SSagi Grimberg } 544e7006de6SSagi Grimberg 545e7006de6SSagi Grimberg static inline struct request *nvme_cid_to_rq(struct blk_mq_tags *tags, 546e7006de6SSagi Grimberg u16 command_id) 547e7006de6SSagi Grimberg { 548e7006de6SSagi Grimberg return blk_mq_tag_to_rq(tags, nvme_tag_from_cid(command_id)); 549e7006de6SSagi Grimberg } 550e7006de6SSagi Grimberg 551b9e03857SThomas Tai #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS 552a3646451SAkinobu Mita void nvme_fault_inject_init(struct nvme_fault_inject *fault_inj, 553a3646451SAkinobu Mita const char *dev_name); 554a3646451SAkinobu Mita void nvme_fault_inject_fini(struct nvme_fault_inject *fault_inject); 555b9e03857SThomas Tai void nvme_should_fail(struct request *req); 556b9e03857SThomas Tai #else 557a3646451SAkinobu Mita static inline void nvme_fault_inject_init(struct nvme_fault_inject *fault_inj, 558a3646451SAkinobu Mita const char *dev_name) 559a3646451SAkinobu Mita { 560a3646451SAkinobu Mita } 561a3646451SAkinobu Mita static inline void nvme_fault_inject_fini(struct nvme_fault_inject *fault_inj) 562a3646451SAkinobu Mita { 563a3646451SAkinobu Mita } 564b9e03857SThomas Tai static inline void nvme_should_fail(struct request *req) {} 565b9e03857SThomas Tai #endif 566b9e03857SThomas Tai 567f3ca80fcSChristoph Hellwig static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl) 568f3ca80fcSChristoph Hellwig { 569f3ca80fcSChristoph Hellwig if (!ctrl->subsystem) 570f3ca80fcSChristoph Hellwig return -ENOTTY; 571f3ca80fcSChristoph Hellwig return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65); 572f3ca80fcSChristoph Hellwig } 573f3ca80fcSChristoph Hellwig 574314d48ddSDamien Le Moal /* 575314d48ddSDamien Le Moal * Convert a 512B sector number to a device logical block number. 576314d48ddSDamien Le Moal */ 577314d48ddSDamien Le Moal static inline u64 nvme_sect_to_lba(struct nvme_ns *ns, sector_t sector) 57857dacad5SJay Sternberg { 579314d48ddSDamien Le Moal return sector >> (ns->lba_shift - SECTOR_SHIFT); 58057dacad5SJay Sternberg } 58157dacad5SJay Sternberg 582e08f2ae8SDamien Le Moal /* 583e08f2ae8SDamien Le Moal * Convert a device logical block number to a 512B sector number. 584e08f2ae8SDamien Le Moal */ 585e08f2ae8SDamien Le Moal static inline sector_t nvme_lba_to_sect(struct nvme_ns *ns, u64 lba) 586e08f2ae8SDamien Le Moal { 587e08f2ae8SDamien Le Moal return lba << (ns->lba_shift - SECTOR_SHIFT); 58857dacad5SJay Sternberg } 58957dacad5SJay Sternberg 59071fb90ebSKeith Busch /* 59171fb90ebSKeith Busch * Convert byte length to nvme's 0-based num dwords 59271fb90ebSKeith Busch */ 59371fb90ebSKeith Busch static inline u32 nvme_bytes_to_numd(size_t len) 59471fb90ebSKeith Busch { 59571fb90ebSKeith Busch return (len >> 2) - 1; 59671fb90ebSKeith Busch } 59771fb90ebSKeith Busch 5985ddaabe8SChristoph Hellwig static inline bool nvme_is_ana_error(u16 status) 5995ddaabe8SChristoph Hellwig { 6005ddaabe8SChristoph Hellwig switch (status & 0x7ff) { 6015ddaabe8SChristoph Hellwig case NVME_SC_ANA_TRANSITION: 6025ddaabe8SChristoph Hellwig case NVME_SC_ANA_INACCESSIBLE: 6035ddaabe8SChristoph Hellwig case NVME_SC_ANA_PERSISTENT_LOSS: 6045ddaabe8SChristoph Hellwig return true; 6055ddaabe8SChristoph Hellwig default: 6065ddaabe8SChristoph Hellwig return false; 6075ddaabe8SChristoph Hellwig } 6085ddaabe8SChristoph Hellwig } 6095ddaabe8SChristoph Hellwig 6105ddaabe8SChristoph Hellwig static inline bool nvme_is_path_error(u16 status) 6115ddaabe8SChristoph Hellwig { 6121e41f3bdSChristoph Hellwig /* check for a status code type of 'path related status' */ 6131e41f3bdSChristoph Hellwig return (status & 0x700) == 0x300; 6145ddaabe8SChristoph Hellwig } 6155ddaabe8SChristoph Hellwig 6162eb81a33SChristoph Hellwig /* 6172eb81a33SChristoph Hellwig * Fill in the status and result information from the CQE, and then figure out 6182eb81a33SChristoph Hellwig * if blk-mq will need to use IPI magic to complete the request, and if yes do 6192eb81a33SChristoph Hellwig * so. If not let the caller complete the request without an indirect function 6202eb81a33SChristoph Hellwig * call. 6212eb81a33SChristoph Hellwig */ 6222eb81a33SChristoph Hellwig static inline bool nvme_try_complete_req(struct request *req, __le16 status, 62327fa9bc5SChristoph Hellwig union nvme_result result) 62415a190f7SChristoph Hellwig { 62527fa9bc5SChristoph Hellwig struct nvme_request *rq = nvme_req(req); 626e4fdb2b1SKeith Busch struct nvme_ctrl *ctrl = rq->ctrl; 627e4fdb2b1SKeith Busch 628e4fdb2b1SKeith Busch if (!(ctrl->quirks & NVME_QUIRK_SKIP_CID_GEN)) 629e4fdb2b1SKeith Busch rq->genctr++; 63027fa9bc5SChristoph Hellwig 63127fa9bc5SChristoph Hellwig rq->status = le16_to_cpu(status) >> 1; 63227fa9bc5SChristoph Hellwig rq->result = result; 633b9e03857SThomas Tai /* inject error when permitted by fault injection framework */ 634b9e03857SThomas Tai nvme_should_fail(req); 635ff029451SChristoph Hellwig if (unlikely(blk_should_fake_timeout(req->q))) 636ff029451SChristoph Hellwig return true; 637ff029451SChristoph Hellwig return blk_mq_complete_request_remote(req); 63815a190f7SChristoph Hellwig } 63915a190f7SChristoph Hellwig 640d22524a4SChristoph Hellwig static inline void nvme_get_ctrl(struct nvme_ctrl *ctrl) 641d22524a4SChristoph Hellwig { 642d22524a4SChristoph Hellwig get_device(ctrl->device); 643d22524a4SChristoph Hellwig } 644d22524a4SChristoph Hellwig 645d22524a4SChristoph Hellwig static inline void nvme_put_ctrl(struct nvme_ctrl *ctrl) 646d22524a4SChristoph Hellwig { 647d22524a4SChristoph Hellwig put_device(ctrl->device); 648d22524a4SChristoph Hellwig } 649d22524a4SChristoph Hellwig 65058a8df67SIsrael Rukshin static inline bool nvme_is_aen_req(u16 qid, __u16 command_id) 65158a8df67SIsrael Rukshin { 652e7006de6SSagi Grimberg return !qid && 653e7006de6SSagi Grimberg nvme_tag_from_cid(command_id) >= NVME_AQ_BLK_MQ_DEPTH; 65458a8df67SIsrael Rukshin } 65558a8df67SIsrael Rukshin 65677f02a7aSChristoph Hellwig void nvme_complete_rq(struct request *req); 657c234a653SJens Axboe void nvme_complete_batch_req(struct request *req); 658c234a653SJens Axboe 659c234a653SJens Axboe static __always_inline void nvme_complete_batch(struct io_comp_batch *iob, 660c234a653SJens Axboe void (*fn)(struct request *rq)) 661c234a653SJens Axboe { 662c234a653SJens Axboe struct request *req; 663c234a653SJens Axboe 664c234a653SJens Axboe rq_list_for_each(&iob->req_list, req) { 665c234a653SJens Axboe fn(req); 666c234a653SJens Axboe nvme_complete_batch_req(req); 667c234a653SJens Axboe } 668c234a653SJens Axboe blk_mq_end_request_batch(iob); 669c234a653SJens Axboe } 670c234a653SJens Axboe 671dda3248eSChao Leng blk_status_t nvme_host_path_error(struct request *req); 6727baa8572SJens Axboe bool nvme_cancel_request(struct request *req, void *data, bool reserved); 67325479069SChao Leng void nvme_cancel_tagset(struct nvme_ctrl *ctrl); 67425479069SChao Leng void nvme_cancel_admin_tagset(struct nvme_ctrl *ctrl); 675bb8d261eSChristoph Hellwig bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl, 676bb8d261eSChristoph Hellwig enum nvme_ctrl_state new_state); 677c1ac9a4bSKeith Busch bool nvme_wait_reset(struct nvme_ctrl *ctrl); 678b5b05048SSagi Grimberg int nvme_disable_ctrl(struct nvme_ctrl *ctrl); 679c0f2f45bSSagi Grimberg int nvme_enable_ctrl(struct nvme_ctrl *ctrl); 6805fd4ce1bSChristoph Hellwig int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl); 681f3ca80fcSChristoph Hellwig int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev, 682f3ca80fcSChristoph Hellwig const struct nvme_ctrl_ops *ops, unsigned long quirks); 68353029b04SKeith Busch void nvme_uninit_ctrl(struct nvme_ctrl *ctrl); 684d09f2b45SSagi Grimberg void nvme_start_ctrl(struct nvme_ctrl *ctrl); 685d09f2b45SSagi Grimberg void nvme_stop_ctrl(struct nvme_ctrl *ctrl); 686f21c4769SChaitanya Kulkarni int nvme_init_ctrl_finish(struct nvme_ctrl *ctrl); 6875bae7f73SChristoph Hellwig 6885bae7f73SChristoph Hellwig void nvme_remove_namespaces(struct nvme_ctrl *ctrl); 6891673f1f0SChristoph Hellwig 6904f1244c8SChristoph Hellwig int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len, 6914f1244c8SChristoph Hellwig bool send); 692a98e58e5SScott Bauer 6937bf58533SChristoph Hellwig void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status, 694287a63ebSChristoph Hellwig volatile union nvme_result *res); 695f866fc42SChristoph Hellwig 69625646264SKeith Busch void nvme_stop_queues(struct nvme_ctrl *ctrl); 69725646264SKeith Busch void nvme_start_queues(struct nvme_ctrl *ctrl); 698a277654bSMing Lei void nvme_stop_admin_queue(struct nvme_ctrl *ctrl); 699a277654bSMing Lei void nvme_start_admin_queue(struct nvme_ctrl *ctrl); 70069d9a99cSKeith Busch void nvme_kill_queues(struct nvme_ctrl *ctrl); 701d6135c3aSKeith Busch void nvme_sync_queues(struct nvme_ctrl *ctrl); 70204800fbfSChao Leng void nvme_sync_io_queues(struct nvme_ctrl *ctrl); 703302ad8ccSKeith Busch void nvme_unfreeze(struct nvme_ctrl *ctrl); 704302ad8ccSKeith Busch void nvme_wait_freeze(struct nvme_ctrl *ctrl); 7057cf0d7c0SSagi Grimberg int nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout); 706302ad8ccSKeith Busch void nvme_start_freeze(struct nvme_ctrl *ctrl); 707363c9aacSSagi Grimberg 708e559398fSChristoph Hellwig static inline unsigned int nvme_req_op(struct nvme_command *cmd) 709e559398fSChristoph Hellwig { 710e559398fSChristoph Hellwig return nvme_is_write(cmd) ? REQ_OP_DRV_OUT : REQ_OP_DRV_IN; 711e559398fSChristoph Hellwig } 712e559398fSChristoph Hellwig 713eb71f435SChristoph Hellwig #define NVME_QID_ANY -1 714e559398fSChristoph Hellwig void nvme_init_request(struct request *req, struct nvme_command *cmd); 715f7f1fc36SMax Gurtovoy void nvme_cleanup_cmd(struct request *req); 716f4b9e6c9SKeith Busch blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req); 717a9715744STao Chiu blk_status_t nvme_fail_nonready_command(struct nvme_ctrl *ctrl, 718a9715744STao Chiu struct request *req); 719a9715744STao Chiu bool __nvme_check_ready(struct nvme_ctrl *ctrl, struct request *rq, 720a9715744STao Chiu bool queue_live); 721a9715744STao Chiu 722a9715744STao Chiu static inline bool nvme_check_ready(struct nvme_ctrl *ctrl, struct request *rq, 723a9715744STao Chiu bool queue_live) 724a9715744STao Chiu { 725a9715744STao Chiu if (likely(ctrl->state == NVME_CTRL_LIVE)) 726a9715744STao Chiu return true; 727a9715744STao Chiu if (ctrl->ops->flags & NVME_F_FABRICS && 728a9715744STao Chiu ctrl->state == NVME_CTRL_DELETING) 7298b77fa6fSRuozhu Li return queue_live; 730a9715744STao Chiu return __nvme_check_ready(ctrl, rq, queue_live); 731a9715744STao Chiu } 7325974ea7cSSungup Moon 7335974ea7cSSungup Moon /* 7345974ea7cSSungup Moon * NSID shall be unique for all shared namespaces, or if at least one of the 7355974ea7cSSungup Moon * following conditions is met: 7365974ea7cSSungup Moon * 1. Namespace Management is supported by the controller 7375974ea7cSSungup Moon * 2. ANA is supported by the controller 7385974ea7cSSungup Moon * 3. NVM Set are supported by the controller 7395974ea7cSSungup Moon * 7405974ea7cSSungup Moon * In other case, private namespace are not required to report a unique NSID. 7415974ea7cSSungup Moon */ 7425974ea7cSSungup Moon static inline bool nvme_is_unique_nsid(struct nvme_ctrl *ctrl, 7435974ea7cSSungup Moon struct nvme_ns_head *head) 7445974ea7cSSungup Moon { 7455974ea7cSSungup Moon return head->shared || 7465974ea7cSSungup Moon (ctrl->oacs & NVME_CTRL_OACS_NS_MNGT_SUPP) || 7475974ea7cSSungup Moon (ctrl->subsys->cmic & NVME_CTRL_CMIC_ANA) || 7485974ea7cSSungup Moon (ctrl->ctratt & NVME_CTRL_CTRATT_NVM_SETS); 7495974ea7cSSungup Moon } 7505974ea7cSSungup Moon 75157dacad5SJay Sternberg int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, 75257dacad5SJay Sternberg void *buf, unsigned bufflen); 75357dacad5SJay Sternberg int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, 754d49187e9SChristoph Hellwig union nvme_result *result, void *buffer, unsigned bufflen, 7559a95e4efSBart Van Assche unsigned timeout, int qid, int at_head, 756be42a33bSKeith Busch blk_mq_req_flags_t flags); 7571a87ee65SKeith Busch int nvme_set_features(struct nvme_ctrl *dev, unsigned int fid, 7581a87ee65SKeith Busch unsigned int dword11, void *buffer, size_t buflen, 7591a87ee65SKeith Busch u32 *result); 7601a87ee65SKeith Busch int nvme_get_features(struct nvme_ctrl *dev, unsigned int fid, 7611a87ee65SKeith Busch unsigned int dword11, void *buffer, size_t buflen, 7621a87ee65SKeith Busch u32 *result); 7639a0be7abSChristoph Hellwig int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count); 764038bd4cbSSagi Grimberg void nvme_stop_keep_alive(struct nvme_ctrl *ctrl); 765d86c4d8eSChristoph Hellwig int nvme_reset_ctrl(struct nvme_ctrl *ctrl); 7662405252aSChristoph Hellwig int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl); 767c1ac9a4bSKeith Busch int nvme_try_sched_reset(struct nvme_ctrl *ctrl); 768c5017e85SChristoph Hellwig int nvme_delete_ctrl(struct nvme_ctrl *ctrl); 7692405252aSChristoph Hellwig void nvme_queue_scan(struct nvme_ctrl *ctrl); 770be93e87eSKeith Busch int nvme_get_log(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, u8 lsp, u8 csi, 7710e98719bSChristoph Hellwig void *log, size_t size, u64 offset); 7721496bd49SChristoph Hellwig bool nvme_tryget_ns_head(struct nvme_ns_head *head); 7731496bd49SChristoph Hellwig void nvme_put_ns_head(struct nvme_ns_head *head); 7742637baedSMinwoo Im int nvme_cdev_add(struct cdev *cdev, struct device *cdev_device, 7752637baedSMinwoo Im const struct file_operations *fops, struct module *owner); 7762637baedSMinwoo Im void nvme_cdev_del(struct cdev *cdev, struct device *cdev_device); 7772405252aSChristoph Hellwig int nvme_ioctl(struct block_device *bdev, fmode_t mode, 7782405252aSChristoph Hellwig unsigned int cmd, unsigned long arg); 7792637baedSMinwoo Im long nvme_ns_chr_ioctl(struct file *file, unsigned int cmd, unsigned long arg); 7802405252aSChristoph Hellwig int nvme_ns_head_ioctl(struct block_device *bdev, fmode_t mode, 7812405252aSChristoph Hellwig unsigned int cmd, unsigned long arg); 7822637baedSMinwoo Im long nvme_ns_head_chr_ioctl(struct file *file, unsigned int cmd, 7832637baedSMinwoo Im unsigned long arg); 7842405252aSChristoph Hellwig long nvme_dev_ioctl(struct file *file, unsigned int cmd, 7852405252aSChristoph Hellwig unsigned long arg); 7861496bd49SChristoph Hellwig int nvme_getgeo(struct block_device *bdev, struct hd_geometry *geo); 787d558fb51SMatias Bjørling 78833b14f67SHannes Reinecke extern const struct attribute_group *nvme_ns_id_attr_groups[]; 7891496bd49SChristoph Hellwig extern const struct pr_ops nvme_pr_ops; 79032acab31SChristoph Hellwig extern const struct block_device_operations nvme_ns_head_ops; 79132acab31SChristoph Hellwig 792f1cf35e1SChristoph Hellwig struct nvme_ns *nvme_find_path(struct nvme_ns_head *head); 79332acab31SChristoph Hellwig #ifdef CONFIG_NVME_MULTIPATH 79466b20ac0SMarta Rybczynska static inline bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl) 79566b20ac0SMarta Rybczynska { 79666b20ac0SMarta Rybczynska return ctrl->ana_log_buf != NULL; 79766b20ac0SMarta Rybczynska } 79866b20ac0SMarta Rybczynska 799b9156daeSSagi Grimberg void nvme_mpath_unfreeze(struct nvme_subsystem *subsys); 800b9156daeSSagi Grimberg void nvme_mpath_wait_freeze(struct nvme_subsystem *subsys); 801b9156daeSSagi Grimberg void nvme_mpath_start_freeze(struct nvme_subsystem *subsys); 802e3d34794SHannes Reinecke void nvme_mpath_default_iopolicy(struct nvme_subsystem *subsys); 8035ddaabe8SChristoph Hellwig void nvme_failover_req(struct request *req); 80432acab31SChristoph Hellwig void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl); 80532acab31SChristoph Hellwig int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl,struct nvme_ns_head *head); 8060d0b660fSChristoph Hellwig void nvme_mpath_add_disk(struct nvme_ns *ns, struct nvme_id_ns *id); 80732acab31SChristoph Hellwig void nvme_mpath_remove_disk(struct nvme_ns_head *head); 8085e1f6899SChristoph Hellwig int nvme_mpath_init_identify(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id); 8095e1f6899SChristoph Hellwig void nvme_mpath_init_ctrl(struct nvme_ctrl *ctrl); 810a4a6f3c8SAnton Eidelman void nvme_mpath_update(struct nvme_ctrl *ctrl); 8110d0b660fSChristoph Hellwig void nvme_mpath_uninit(struct nvme_ctrl *ctrl); 8120d0b660fSChristoph Hellwig void nvme_mpath_stop(struct nvme_ctrl *ctrl); 8130157ec8dSSagi Grimberg bool nvme_mpath_clear_current_path(struct nvme_ns *ns); 814e7d65803SHannes Reinecke void nvme_mpath_revalidate_paths(struct nvme_ns *ns); 8150157ec8dSSagi Grimberg void nvme_mpath_clear_ctrl_paths(struct nvme_ctrl *ctrl); 8165396fdacSHannes Reinecke void nvme_mpath_shutdown_disk(struct nvme_ns_head *head); 817479a322fSSagi Grimberg 8182b59787aSMax Gurtovoy static inline void nvme_trace_bio_complete(struct request *req) 81935fe0d12SHannes Reinecke { 82035fe0d12SHannes Reinecke struct nvme_ns *ns = req->q->queuedata; 82135fe0d12SHannes Reinecke 82235fe0d12SHannes Reinecke if (req->cmd_flags & REQ_NVME_MPATH) 823d24de76aSChristoph Hellwig trace_block_bio_complete(ns->head->disk->queue, req->bio); 82435fe0d12SHannes Reinecke } 82535fe0d12SHannes Reinecke 826b739e137SChristoph Hellwig extern bool multipath; 8270d0b660fSChristoph Hellwig extern struct device_attribute dev_attr_ana_grpid; 8280d0b660fSChristoph Hellwig extern struct device_attribute dev_attr_ana_state; 82975c10e73SHannes Reinecke extern struct device_attribute subsys_attr_iopolicy; 8300d0b660fSChristoph Hellwig 83132acab31SChristoph Hellwig #else 832b739e137SChristoph Hellwig #define multipath false 8330d0b660fSChristoph Hellwig static inline bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl) 8340d0b660fSChristoph Hellwig { 8350d0b660fSChristoph Hellwig return false; 8360d0b660fSChristoph Hellwig } 8375ddaabe8SChristoph Hellwig static inline void nvme_failover_req(struct request *req) 83832acab31SChristoph Hellwig { 83932acab31SChristoph Hellwig } 84032acab31SChristoph Hellwig static inline void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl) 84132acab31SChristoph Hellwig { 84232acab31SChristoph Hellwig } 84332acab31SChristoph Hellwig static inline int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl, 84432acab31SChristoph Hellwig struct nvme_ns_head *head) 84532acab31SChristoph Hellwig { 84632acab31SChristoph Hellwig return 0; 84732acab31SChristoph Hellwig } 8480d0b660fSChristoph Hellwig static inline void nvme_mpath_add_disk(struct nvme_ns *ns, 8490d0b660fSChristoph Hellwig struct nvme_id_ns *id) 85032acab31SChristoph Hellwig { 85132acab31SChristoph Hellwig } 85232acab31SChristoph Hellwig static inline void nvme_mpath_remove_disk(struct nvme_ns_head *head) 85332acab31SChristoph Hellwig { 85432acab31SChristoph Hellwig } 8550157ec8dSSagi Grimberg static inline bool nvme_mpath_clear_current_path(struct nvme_ns *ns) 8560157ec8dSSagi Grimberg { 8570157ec8dSSagi Grimberg return false; 8580157ec8dSSagi Grimberg } 859e7d65803SHannes Reinecke static inline void nvme_mpath_revalidate_paths(struct nvme_ns *ns) 860e7d65803SHannes Reinecke { 861e7d65803SHannes Reinecke } 8620157ec8dSSagi Grimberg static inline void nvme_mpath_clear_ctrl_paths(struct nvme_ctrl *ctrl) 86332acab31SChristoph Hellwig { 86432acab31SChristoph Hellwig } 8655396fdacSHannes Reinecke static inline void nvme_mpath_shutdown_disk(struct nvme_ns_head *head) 866479a322fSSagi Grimberg { 867479a322fSSagi Grimberg } 8682b59787aSMax Gurtovoy static inline void nvme_trace_bio_complete(struct request *req) 86935fe0d12SHannes Reinecke { 87035fe0d12SHannes Reinecke } 8715e1f6899SChristoph Hellwig static inline void nvme_mpath_init_ctrl(struct nvme_ctrl *ctrl) 8725e1f6899SChristoph Hellwig { 8735e1f6899SChristoph Hellwig } 8745e1f6899SChristoph Hellwig static inline int nvme_mpath_init_identify(struct nvme_ctrl *ctrl, 8750d0b660fSChristoph Hellwig struct nvme_id_ctrl *id) 8760d0b660fSChristoph Hellwig { 8772bd64307SKanchan Joshi if (ctrl->subsys->cmic & NVME_CTRL_CMIC_ANA) 87814a1336eSChristoph Hellwig dev_warn(ctrl->device, 87914a1336eSChristoph Hellwig "Please enable CONFIG_NVME_MULTIPATH for full support of multi-port devices.\n"); 8800d0b660fSChristoph Hellwig return 0; 8810d0b660fSChristoph Hellwig } 882a4a6f3c8SAnton Eidelman static inline void nvme_mpath_update(struct nvme_ctrl *ctrl) 883a4a6f3c8SAnton Eidelman { 884a4a6f3c8SAnton Eidelman } 8850d0b660fSChristoph Hellwig static inline void nvme_mpath_uninit(struct nvme_ctrl *ctrl) 8860d0b660fSChristoph Hellwig { 8870d0b660fSChristoph Hellwig } 8880d0b660fSChristoph Hellwig static inline void nvme_mpath_stop(struct nvme_ctrl *ctrl) 8890d0b660fSChristoph Hellwig { 8900d0b660fSChristoph Hellwig } 891b9156daeSSagi Grimberg static inline void nvme_mpath_unfreeze(struct nvme_subsystem *subsys) 892b9156daeSSagi Grimberg { 893b9156daeSSagi Grimberg } 894b9156daeSSagi Grimberg static inline void nvme_mpath_wait_freeze(struct nvme_subsystem *subsys) 895b9156daeSSagi Grimberg { 896b9156daeSSagi Grimberg } 897b9156daeSSagi Grimberg static inline void nvme_mpath_start_freeze(struct nvme_subsystem *subsys) 898b9156daeSSagi Grimberg { 899b9156daeSSagi Grimberg } 900e3d34794SHannes Reinecke static inline void nvme_mpath_default_iopolicy(struct nvme_subsystem *subsys) 901e3d34794SHannes Reinecke { 902e3d34794SHannes Reinecke } 90332acab31SChristoph Hellwig #endif /* CONFIG_NVME_MULTIPATH */ 90432acab31SChristoph Hellwig 9057fad20ddSChristoph Hellwig int nvme_revalidate_zones(struct nvme_ns *ns); 9068b4fb0f9SChristoph Hellwig int nvme_ns_report_zones(struct nvme_ns *ns, sector_t sector, 9078b4fb0f9SChristoph Hellwig unsigned int nr_zones, report_zones_cb cb, void *data); 908240e6ee2SKeith Busch #ifdef CONFIG_BLK_DEV_ZONED 909d525c3c0SChristoph Hellwig int nvme_update_zone_info(struct nvme_ns *ns, unsigned lbaf); 910240e6ee2SKeith Busch blk_status_t nvme_setup_zone_mgmt_send(struct nvme_ns *ns, struct request *req, 911240e6ee2SKeith Busch struct nvme_command *cmnd, 912240e6ee2SKeith Busch enum nvme_zone_mgmt_action action); 913240e6ee2SKeith Busch #else 914240e6ee2SKeith Busch static inline blk_status_t nvme_setup_zone_mgmt_send(struct nvme_ns *ns, 915240e6ee2SKeith Busch struct request *req, struct nvme_command *cmnd, 916240e6ee2SKeith Busch enum nvme_zone_mgmt_action action) 917240e6ee2SKeith Busch { 918240e6ee2SKeith Busch return BLK_STS_NOTSUPP; 919240e6ee2SKeith Busch } 920240e6ee2SKeith Busch 921d525c3c0SChristoph Hellwig static inline int nvme_update_zone_info(struct nvme_ns *ns, unsigned lbaf) 922240e6ee2SKeith Busch { 923240e6ee2SKeith Busch dev_warn(ns->ctrl->device, 924240e6ee2SKeith Busch "Please enable CONFIG_BLK_DEV_ZONED to support ZNS devices\n"); 925240e6ee2SKeith Busch return -EPROTONOSUPPORT; 926240e6ee2SKeith Busch } 927240e6ee2SKeith Busch #endif 928240e6ee2SKeith Busch 92972e8b5cdSChaitanya Kulkarni static inline int nvme_ctrl_init_connect_q(struct nvme_ctrl *ctrl) 93072e8b5cdSChaitanya Kulkarni { 93172e8b5cdSChaitanya Kulkarni ctrl->connect_q = blk_mq_init_queue(ctrl->tagset); 93272e8b5cdSChaitanya Kulkarni if (IS_ERR(ctrl->connect_q)) 93372e8b5cdSChaitanya Kulkarni return PTR_ERR(ctrl->connect_q); 93472e8b5cdSChaitanya Kulkarni return 0; 93572e8b5cdSChaitanya Kulkarni } 93672e8b5cdSChaitanya Kulkarni 93740267efdSSimon A. F. Lund static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev) 93840267efdSSimon A. F. Lund { 93940267efdSSimon A. F. Lund return dev_to_disk(dev)->private_data; 94040267efdSSimon A. F. Lund } 941ca064085SMatias Bjørling 942400b6a7bSGuenter Roeck #ifdef CONFIG_NVME_HWMON 94359e330f8SKeith Busch int nvme_hwmon_init(struct nvme_ctrl *ctrl); 944ed7770f6SHannes Reinecke void nvme_hwmon_exit(struct nvme_ctrl *ctrl); 945400b6a7bSGuenter Roeck #else 94659e330f8SKeith Busch static inline int nvme_hwmon_init(struct nvme_ctrl *ctrl) 94759e330f8SKeith Busch { 94859e330f8SKeith Busch return 0; 94959e330f8SKeith Busch } 950ed7770f6SHannes Reinecke 951ed7770f6SHannes Reinecke static inline void nvme_hwmon_exit(struct nvme_ctrl *ctrl) 952ed7770f6SHannes Reinecke { 953ed7770f6SHannes Reinecke } 954400b6a7bSGuenter Roeck #endif 955400b6a7bSGuenter Roeck 95673eefc27SChaitanya Kulkarni static inline bool nvme_ctrl_sgl_supported(struct nvme_ctrl *ctrl) 95773eefc27SChaitanya Kulkarni { 95873eefc27SChaitanya Kulkarni return ctrl->sgls & ((1 << 0) | (1 << 1)); 95973eefc27SChaitanya Kulkarni } 96073eefc27SChaitanya Kulkarni 961df21b6b1SLogan Gunthorpe u32 nvme_command_effects(struct nvme_ctrl *ctrl, struct nvme_ns *ns, 962df21b6b1SLogan Gunthorpe u8 opcode); 963ae5e6886SKeith Busch int nvme_execute_passthru_rq(struct request *rq); 964b2702aaaSChaitanya Kulkarni struct nvme_ctrl *nvme_ctrl_from_file(struct file *file); 96524493b8bSLogan Gunthorpe struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid); 96624493b8bSLogan Gunthorpe void nvme_put_ns(struct nvme_ns *ns); 967df21b6b1SLogan Gunthorpe 96843dc9878SAdam Manzanares static inline bool nvme_multi_css(struct nvme_ctrl *ctrl) 96943dc9878SAdam Manzanares { 97043dc9878SAdam Manzanares return (ctrl->ctrl_config & NVME_CC_CSS_MASK) == NVME_CC_CSS_CSI; 97143dc9878SAdam Manzanares } 97243dc9878SAdam Manzanares 973bd83fe6fSAlan Adamson #ifdef CONFIG_NVME_VERBOSE_ERRORS 974bd83fe6fSAlan Adamson const unsigned char *nvme_get_error_status_str(u16 status); 975bd83fe6fSAlan Adamson const unsigned char *nvme_get_opcode_str(u8 opcode); 976bd83fe6fSAlan Adamson const unsigned char *nvme_get_admin_opcode_str(u8 opcode); 977bd83fe6fSAlan Adamson #else /* CONFIG_NVME_VERBOSE_ERRORS */ 978bd83fe6fSAlan Adamson static inline const unsigned char *nvme_get_error_status_str(u16 status) 979bd83fe6fSAlan Adamson { 980bd83fe6fSAlan Adamson return "I/O Error"; 981bd83fe6fSAlan Adamson } 982bd83fe6fSAlan Adamson static inline const unsigned char *nvme_get_opcode_str(u8 opcode) 983bd83fe6fSAlan Adamson { 984bd83fe6fSAlan Adamson return "I/O Cmd"; 985bd83fe6fSAlan Adamson } 986bd83fe6fSAlan Adamson static inline const unsigned char *nvme_get_admin_opcode_str(u8 opcode) 987bd83fe6fSAlan Adamson { 988bd83fe6fSAlan Adamson return "Admin Cmd"; 989bd83fe6fSAlan Adamson } 990bd83fe6fSAlan Adamson #endif /* CONFIG_NVME_VERBOSE_ERRORS */ 991bd83fe6fSAlan Adamson 99257dacad5SJay Sternberg #endif /* _NVME_H */ 993