1bc50ad75SChristoph Hellwig /* SPDX-License-Identifier: GPL-2.0 */ 257dacad5SJay Sternberg /* 357dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 457dacad5SJay Sternberg */ 557dacad5SJay Sternberg 657dacad5SJay Sternberg #ifndef _NVME_H 757dacad5SJay Sternberg #define _NVME_H 857dacad5SJay Sternberg 957dacad5SJay Sternberg #include <linux/nvme.h> 10a6a5149bSChristoph Hellwig #include <linux/cdev.h> 1157dacad5SJay Sternberg #include <linux/pci.h> 1257dacad5SJay Sternberg #include <linux/kref.h> 1357dacad5SJay Sternberg #include <linux/blk-mq.h> 14b0b4e09cSMatias Bjørling #include <linux/lightnvm.h> 15a98e58e5SScott Bauer #include <linux/sed-opal.h> 16b9e03857SThomas Tai #include <linux/fault-inject.h> 17978628ecSJohannes Thumshirn #include <linux/rcupdate.h> 1857dacad5SJay Sternberg 198ae4e447SMarc Olson extern unsigned int nvme_io_timeout; 2057dacad5SJay Sternberg #define NVME_IO_TIMEOUT (nvme_io_timeout * HZ) 2157dacad5SJay Sternberg 228ae4e447SMarc Olson extern unsigned int admin_timeout; 2321d34711SChristoph Hellwig #define ADMIN_TIMEOUT (admin_timeout * HZ) 2421d34711SChristoph Hellwig 25038bd4cbSSagi Grimberg #define NVME_DEFAULT_KATO 5 26038bd4cbSSagi Grimberg #define NVME_KATO_GRACE 10 27038bd4cbSSagi Grimberg 289a6327d2SSagi Grimberg extern struct workqueue_struct *nvme_wq; 29b227c59bSRoy Shterman extern struct workqueue_struct *nvme_reset_wq; 30b227c59bSRoy Shterman extern struct workqueue_struct *nvme_delete_wq; 319a6327d2SSagi Grimberg 32ca064085SMatias Bjørling enum { 33ca064085SMatias Bjørling NVME_NS_LBA = 0, 34ca064085SMatias Bjørling NVME_NS_LIGHTNVM = 1, 35ca064085SMatias Bjørling }; 36ca064085SMatias Bjørling 3757dacad5SJay Sternberg /* 38106198edSChristoph Hellwig * List of workarounds for devices that required behavior not specified in 39106198edSChristoph Hellwig * the standard. 4057dacad5SJay Sternberg */ 41106198edSChristoph Hellwig enum nvme_quirks { 42106198edSChristoph Hellwig /* 43106198edSChristoph Hellwig * Prefers I/O aligned to a stripe size specified in a vendor 44106198edSChristoph Hellwig * specific Identify field. 45106198edSChristoph Hellwig */ 46106198edSChristoph Hellwig NVME_QUIRK_STRIPE_SIZE = (1 << 0), 47540c801cSKeith Busch 48540c801cSKeith Busch /* 49540c801cSKeith Busch * The controller doesn't handle Identify value others than 0 or 1 50540c801cSKeith Busch * correctly. 51540c801cSKeith Busch */ 52540c801cSKeith Busch NVME_QUIRK_IDENTIFY_CNS = (1 << 1), 5308095e70SKeith Busch 5408095e70SKeith Busch /* 55e850fd16SChristoph Hellwig * The controller deterministically returns O's on reads to 56e850fd16SChristoph Hellwig * logical blocks that deallocate was called on. 5708095e70SKeith Busch */ 58e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES = (1 << 2), 5954adc010SGuilherme G. Piccoli 6054adc010SGuilherme G. Piccoli /* 6154adc010SGuilherme G. Piccoli * The controller needs a delay before starts checking the device 6254adc010SGuilherme G. Piccoli * readiness, which is done by reading the NVME_CSTS_RDY bit. 6354adc010SGuilherme G. Piccoli */ 6454adc010SGuilherme G. Piccoli NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3), 65c5552fdeSAndy Lutomirski 66c5552fdeSAndy Lutomirski /* 67c5552fdeSAndy Lutomirski * APST should not be used. 68c5552fdeSAndy Lutomirski */ 69c5552fdeSAndy Lutomirski NVME_QUIRK_NO_APST = (1 << 4), 70ff5350a8SAndy Lutomirski 71ff5350a8SAndy Lutomirski /* 72ff5350a8SAndy Lutomirski * The deepest sleep state should not be used. 73ff5350a8SAndy Lutomirski */ 74ff5350a8SAndy Lutomirski NVME_QUIRK_NO_DEEPEST_PS = (1 << 5), 75608cc4b1SChristoph Hellwig 76608cc4b1SChristoph Hellwig /* 77608cc4b1SChristoph Hellwig * Supports the LighNVM command set if indicated in vs[1]. 78608cc4b1SChristoph Hellwig */ 79608cc4b1SChristoph Hellwig NVME_QUIRK_LIGHTNVM = (1 << 6), 809abd68efSJens Axboe 819abd68efSJens Axboe /* 829abd68efSJens Axboe * Set MEDIUM priority on SQ creation 839abd68efSJens Axboe */ 849abd68efSJens Axboe NVME_QUIRK_MEDIUM_PRIO_SQ = (1 << 7), 856299358dSJames Dingwall 866299358dSJames Dingwall /* 876299358dSJames Dingwall * Ignore device provided subnqn. 886299358dSJames Dingwall */ 896299358dSJames Dingwall NVME_QUIRK_IGNORE_DEV_SUBNQN = (1 << 8), 907b210e4eSChristoph Hellwig 917b210e4eSChristoph Hellwig /* 927b210e4eSChristoph Hellwig * Broken Write Zeroes. 937b210e4eSChristoph Hellwig */ 947b210e4eSChristoph Hellwig NVME_QUIRK_DISABLE_WRITE_ZEROES = (1 << 9), 95106198edSChristoph Hellwig }; 96106198edSChristoph Hellwig 97d49187e9SChristoph Hellwig /* 98d49187e9SChristoph Hellwig * Common request structure for NVMe passthrough. All drivers must have 99d49187e9SChristoph Hellwig * this structure as the first member of their request-private data. 100d49187e9SChristoph Hellwig */ 101d49187e9SChristoph Hellwig struct nvme_request { 102d49187e9SChristoph Hellwig struct nvme_command *cmd; 103d49187e9SChristoph Hellwig union nvme_result result; 10444e44b29SChristoph Hellwig u8 retries; 10527fa9bc5SChristoph Hellwig u8 flags; 10627fa9bc5SChristoph Hellwig u16 status; 10759e29ce6SSagi Grimberg struct nvme_ctrl *ctrl; 10827fa9bc5SChristoph Hellwig }; 10927fa9bc5SChristoph Hellwig 11032acab31SChristoph Hellwig /* 11132acab31SChristoph Hellwig * Mark a bio as coming in through the mpath node. 11232acab31SChristoph Hellwig */ 11332acab31SChristoph Hellwig #define REQ_NVME_MPATH REQ_DRV 11432acab31SChristoph Hellwig 11527fa9bc5SChristoph Hellwig enum { 11627fa9bc5SChristoph Hellwig NVME_REQ_CANCELLED = (1 << 0), 117bb06ec31SJames Smart NVME_REQ_USERCMD = (1 << 1), 118d49187e9SChristoph Hellwig }; 119d49187e9SChristoph Hellwig 120d49187e9SChristoph Hellwig static inline struct nvme_request *nvme_req(struct request *req) 121d49187e9SChristoph Hellwig { 122d49187e9SChristoph Hellwig return blk_mq_rq_to_pdu(req); 123d49187e9SChristoph Hellwig } 124d49187e9SChristoph Hellwig 1255d87eb94SKeith Busch static inline u16 nvme_req_qid(struct request *req) 1265d87eb94SKeith Busch { 1275d87eb94SKeith Busch if (!req->rq_disk) 1285d87eb94SKeith Busch return 0; 1295d87eb94SKeith Busch return blk_mq_unique_tag_to_hwq(blk_mq_unique_tag(req)) + 1; 1305d87eb94SKeith Busch } 1315d87eb94SKeith Busch 13254adc010SGuilherme G. Piccoli /* The below value is the specific amount of delay needed before checking 13354adc010SGuilherme G. Piccoli * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the 13454adc010SGuilherme G. Piccoli * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was 13554adc010SGuilherme G. Piccoli * found empirically. 13654adc010SGuilherme G. Piccoli */ 1378c97eeccSJeff Lien #define NVME_QUIRK_DELAY_AMOUNT 2300 13854adc010SGuilherme G. Piccoli 139bb8d261eSChristoph Hellwig enum nvme_ctrl_state { 140bb8d261eSChristoph Hellwig NVME_CTRL_NEW, 141bb8d261eSChristoph Hellwig NVME_CTRL_LIVE, 1422b1b7e78SJianchao Wang NVME_CTRL_ADMIN_ONLY, /* Only admin queue live */ 143bb8d261eSChristoph Hellwig NVME_CTRL_RESETTING, 144ad6a0a52SMax Gurtovoy NVME_CTRL_CONNECTING, 145bb8d261eSChristoph Hellwig NVME_CTRL_DELETING, 1460ff9d4e1SKeith Busch NVME_CTRL_DEAD, 147bb8d261eSChristoph Hellwig }; 148bb8d261eSChristoph Hellwig 149a3646451SAkinobu Mita struct nvme_fault_inject { 150a3646451SAkinobu Mita #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS 151a3646451SAkinobu Mita struct fault_attr attr; 152a3646451SAkinobu Mita struct dentry *parent; 153a3646451SAkinobu Mita bool dont_retry; /* DNR, do not retry */ 154a3646451SAkinobu Mita u16 status; /* status code */ 155a3646451SAkinobu Mita #endif 156a3646451SAkinobu Mita }; 157a3646451SAkinobu Mita 1581c63dc66SChristoph Hellwig struct nvme_ctrl { 1596e3ca03eSSagi Grimberg bool comp_seen; 160bb8d261eSChristoph Hellwig enum nvme_ctrl_state state; 161bd4da3abSAndy Lutomirski bool identified; 162bb8d261eSChristoph Hellwig spinlock_t lock; 163e7ad43c3SKeith Busch struct mutex scan_lock; 1641c63dc66SChristoph Hellwig const struct nvme_ctrl_ops *ops; 16557dacad5SJay Sternberg struct request_queue *admin_q; 16607bfcd09SChristoph Hellwig struct request_queue *connect_q; 16757dacad5SJay Sternberg struct device *dev; 16857dacad5SJay Sternberg int instance; 169103e515eSHannes Reinecke int numa_node; 1705bae7f73SChristoph Hellwig struct blk_mq_tag_set *tagset; 17134b6c231SSagi Grimberg struct blk_mq_tag_set *admin_tagset; 1725bae7f73SChristoph Hellwig struct list_head namespaces; 173765cc031SJianchao Wang struct rw_semaphore namespaces_rwsem; 174d22524a4SChristoph Hellwig struct device ctrl_device; 1755bae7f73SChristoph Hellwig struct device *device; /* char device */ 176a6a5149bSChristoph Hellwig struct cdev cdev; 177d86c4d8eSChristoph Hellwig struct work_struct reset_work; 178c5017e85SChristoph Hellwig struct work_struct delete_work; 1791c63dc66SChristoph Hellwig 180ab9e00ccSChristoph Hellwig struct nvme_subsystem *subsys; 181ab9e00ccSChristoph Hellwig struct list_head subsys_entry; 182ab9e00ccSChristoph Hellwig 1834f1244c8SChristoph Hellwig struct opal_dev *opal_dev; 184a98e58e5SScott Bauer 18557dacad5SJay Sternberg char name[12]; 18676e3914aSChristoph Hellwig u16 cntlid; 1875fd4ce1bSChristoph Hellwig 1885fd4ce1bSChristoph Hellwig u32 ctrl_config; 189b6dccf7fSArnav Dawn u16 mtfa; 190d858e5f0SSagi Grimberg u32 queue_count; 1915fd4ce1bSChristoph Hellwig 19220d0dfe6SSagi Grimberg u64 cap; 1935fd4ce1bSChristoph Hellwig u32 page_size; 19457dacad5SJay Sternberg u32 max_hw_sectors; 195943e942eSJens Axboe u32 max_segments; 19649cd84b6SKeith Busch u16 crdt[3]; 19757dacad5SJay Sternberg u16 oncs; 1988a9ae523SScott Bauer u16 oacs; 199f5d11840SJens Axboe u16 nssa; 200f5d11840SJens Axboe u16 nr_streams; 2010d0b660fSChristoph Hellwig u32 max_namespaces; 2026bf25d16SChristoph Hellwig atomic_t abort_limit; 20357dacad5SJay Sternberg u8 vwc; 204f3ca80fcSChristoph Hellwig u32 vs; 20507bfcd09SChristoph Hellwig u32 sgls; 206038bd4cbSSagi Grimberg u16 kas; 207c5552fdeSAndy Lutomirski u8 npss; 208c5552fdeSAndy Lutomirski u8 apsta; 209c0561f82SHannes Reinecke u32 oaes; 210e3d7874dSKeith Busch u32 aen_result; 2113e53ba38SSagi Grimberg u32 ctratt; 21207fbd32aSMartin K. Petersen unsigned int shutdown_timeout; 213038bd4cbSSagi Grimberg unsigned int kato; 214f3ca80fcSChristoph Hellwig bool subsystem; 215106198edSChristoph Hellwig unsigned long quirks; 216c5552fdeSAndy Lutomirski struct nvme_id_power_state psd[32]; 21784fef62dSKeith Busch struct nvme_effects_log *effects; 2185955be21SChristoph Hellwig struct work_struct scan_work; 219f866fc42SChristoph Hellwig struct work_struct async_event_work; 220038bd4cbSSagi Grimberg struct delayed_work ka_work; 2210a34e466SRoland Dreier struct nvme_command ka_cmd; 222b6dccf7fSArnav Dawn struct work_struct fw_act_work; 22330d90964SChristoph Hellwig unsigned long events; 22407bfcd09SChristoph Hellwig 2250d0b660fSChristoph Hellwig #ifdef CONFIG_NVME_MULTIPATH 2260d0b660fSChristoph Hellwig /* asymmetric namespace access: */ 2270d0b660fSChristoph Hellwig u8 anacap; 2280d0b660fSChristoph Hellwig u8 anatt; 2290d0b660fSChristoph Hellwig u32 anagrpmax; 2300d0b660fSChristoph Hellwig u32 nanagrpid; 2310d0b660fSChristoph Hellwig struct mutex ana_lock; 2320d0b660fSChristoph Hellwig struct nvme_ana_rsp_hdr *ana_log_buf; 2330d0b660fSChristoph Hellwig size_t ana_log_size; 2340d0b660fSChristoph Hellwig struct timer_list anatt_timer; 2350d0b660fSChristoph Hellwig struct work_struct ana_work; 2360d0b660fSChristoph Hellwig #endif 2370d0b660fSChristoph Hellwig 238c5552fdeSAndy Lutomirski /* Power saving configuration */ 239c5552fdeSAndy Lutomirski u64 ps_max_latency_us; 24076a5af84SKai-Heng Feng bool apst_enabled; 241c5552fdeSAndy Lutomirski 242044a9df1SChristoph Hellwig /* PCIe only: */ 243fe6d53c9SChristoph Hellwig u32 hmpre; 244fe6d53c9SChristoph Hellwig u32 hmmin; 245044a9df1SChristoph Hellwig u32 hmminds; 246044a9df1SChristoph Hellwig u16 hmmaxd; 247fe6d53c9SChristoph Hellwig 24807bfcd09SChristoph Hellwig /* Fabrics only */ 24907bfcd09SChristoph Hellwig u16 sqsize; 25007bfcd09SChristoph Hellwig u32 ioccsz; 25107bfcd09SChristoph Hellwig u32 iorcsz; 25207bfcd09SChristoph Hellwig u16 icdoff; 25307bfcd09SChristoph Hellwig u16 maxcmd; 254fdf9dfa8SSagi Grimberg int nr_reconnects; 25507bfcd09SChristoph Hellwig struct nvmf_ctrl_options *opts; 256cb5b7262SJens Axboe 257cb5b7262SJens Axboe struct page *discard_page; 258cb5b7262SJens Axboe unsigned long discard_page_busy; 259f79d5fdaSAkinobu Mita 260f79d5fdaSAkinobu Mita struct nvme_fault_inject fault_inject; 26157dacad5SJay Sternberg }; 26257dacad5SJay Sternberg 26375c10e73SHannes Reinecke enum nvme_iopolicy { 26475c10e73SHannes Reinecke NVME_IOPOLICY_NUMA, 26575c10e73SHannes Reinecke NVME_IOPOLICY_RR, 26675c10e73SHannes Reinecke }; 26775c10e73SHannes Reinecke 268ab9e00ccSChristoph Hellwig struct nvme_subsystem { 269ab9e00ccSChristoph Hellwig int instance; 270ab9e00ccSChristoph Hellwig struct device dev; 271ab9e00ccSChristoph Hellwig /* 272ab9e00ccSChristoph Hellwig * Because we unregister the device on the last put we need 273ab9e00ccSChristoph Hellwig * a separate refcount. 274ab9e00ccSChristoph Hellwig */ 275ab9e00ccSChristoph Hellwig struct kref ref; 276ab9e00ccSChristoph Hellwig struct list_head entry; 277ab9e00ccSChristoph Hellwig struct mutex lock; 278ab9e00ccSChristoph Hellwig struct list_head ctrls; 279ed754e5dSChristoph Hellwig struct list_head nsheads; 280ab9e00ccSChristoph Hellwig char subnqn[NVMF_NQN_SIZE]; 281ab9e00ccSChristoph Hellwig char serial[20]; 282ab9e00ccSChristoph Hellwig char model[40]; 283ab9e00ccSChristoph Hellwig char firmware_rev[8]; 284ab9e00ccSChristoph Hellwig u8 cmic; 285ab9e00ccSChristoph Hellwig u16 vendor_id; 28681adb863SBart Van Assche u16 awupf; /* 0's based awupf value. */ 287ed754e5dSChristoph Hellwig struct ida ns_ida; 28875c10e73SHannes Reinecke #ifdef CONFIG_NVME_MULTIPATH 28975c10e73SHannes Reinecke enum nvme_iopolicy iopolicy; 29075c10e73SHannes Reinecke #endif 291ab9e00ccSChristoph Hellwig }; 292ab9e00ccSChristoph Hellwig 293002fab04SChristoph Hellwig /* 294002fab04SChristoph Hellwig * Container structure for uniqueue namespace identifiers. 295002fab04SChristoph Hellwig */ 296002fab04SChristoph Hellwig struct nvme_ns_ids { 297002fab04SChristoph Hellwig u8 eui64[8]; 298002fab04SChristoph Hellwig u8 nguid[16]; 299002fab04SChristoph Hellwig uuid_t uuid; 300002fab04SChristoph Hellwig }; 301002fab04SChristoph Hellwig 302ed754e5dSChristoph Hellwig /* 303ed754e5dSChristoph Hellwig * Anchor structure for namespaces. There is one for each namespace in a 304ed754e5dSChristoph Hellwig * NVMe subsystem that any of our controllers can see, and the namespace 305ed754e5dSChristoph Hellwig * structure for each controller is chained of it. For private namespaces 306ed754e5dSChristoph Hellwig * there is a 1:1 relation to our namespace structures, that is ->list 307ed754e5dSChristoph Hellwig * only ever has a single entry for private namespaces. 308ed754e5dSChristoph Hellwig */ 309ed754e5dSChristoph Hellwig struct nvme_ns_head { 310ed754e5dSChristoph Hellwig struct list_head list; 311ed754e5dSChristoph Hellwig struct srcu_struct srcu; 312ed754e5dSChristoph Hellwig struct nvme_subsystem *subsys; 313ed754e5dSChristoph Hellwig unsigned ns_id; 314ed754e5dSChristoph Hellwig struct nvme_ns_ids ids; 315ed754e5dSChristoph Hellwig struct list_head entry; 316ed754e5dSChristoph Hellwig struct kref ref; 317ed754e5dSChristoph Hellwig int instance; 318f3334447SChristoph Hellwig #ifdef CONFIG_NVME_MULTIPATH 319f3334447SChristoph Hellwig struct gendisk *disk; 320f3334447SChristoph Hellwig struct bio_list requeue_list; 321f3334447SChristoph Hellwig spinlock_t requeue_lock; 322f3334447SChristoph Hellwig struct work_struct requeue_work; 323f3334447SChristoph Hellwig struct mutex lock; 324f3334447SChristoph Hellwig struct nvme_ns __rcu *current_path[]; 325f3334447SChristoph Hellwig #endif 326ed754e5dSChristoph Hellwig }; 327ed754e5dSChristoph Hellwig 32857dacad5SJay Sternberg struct nvme_ns { 32957dacad5SJay Sternberg struct list_head list; 33057dacad5SJay Sternberg 3311c63dc66SChristoph Hellwig struct nvme_ctrl *ctrl; 33257dacad5SJay Sternberg struct request_queue *queue; 33357dacad5SJay Sternberg struct gendisk *disk; 3340d0b660fSChristoph Hellwig #ifdef CONFIG_NVME_MULTIPATH 3350d0b660fSChristoph Hellwig enum nvme_ana_state ana_state; 3360d0b660fSChristoph Hellwig u32 ana_grpid; 3370d0b660fSChristoph Hellwig #endif 338ed754e5dSChristoph Hellwig struct list_head siblings; 339b0b4e09cSMatias Bjørling struct nvm_dev *ndev; 34057dacad5SJay Sternberg struct kref kref; 341ed754e5dSChristoph Hellwig struct nvme_ns_head *head; 34257dacad5SJay Sternberg 34357dacad5SJay Sternberg int lba_shift; 34457dacad5SJay Sternberg u16 ms; 345f5d11840SJens Axboe u16 sgs; 346f5d11840SJens Axboe u32 sws; 34757dacad5SJay Sternberg bool ext; 34857dacad5SJay Sternberg u8 pi_type; 349646017a6SKeith Busch unsigned long flags; 350646017a6SKeith Busch #define NVME_NS_REMOVING 0 35169d9a99cSKeith Busch #define NVME_NS_DEAD 1 3520d0b660fSChristoph Hellwig #define NVME_NS_ANA_PENDING 2 35357eeaf8eSChristoph Hellwig u16 noiob; 354b9e03857SThomas Tai 355b9e03857SThomas Tai struct nvme_fault_inject fault_inject; 356b9e03857SThomas Tai 35757dacad5SJay Sternberg }; 35857dacad5SJay Sternberg 3591c63dc66SChristoph Hellwig struct nvme_ctrl_ops { 3601a353d85SMing Lin const char *name; 361e439bb12SSagi Grimberg struct module *module; 362d3d5b87dSChristoph Hellwig unsigned int flags; 363d3d5b87dSChristoph Hellwig #define NVME_F_FABRICS (1 << 0) 364c81bfba9SChristoph Hellwig #define NVME_F_METADATA_SUPPORTED (1 << 1) 365e0596ab2SLogan Gunthorpe #define NVME_F_PCI_P2PDMA (1 << 2) 3661c63dc66SChristoph Hellwig int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val); 3675fd4ce1bSChristoph Hellwig int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val); 3687fd8930fSChristoph Hellwig int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val); 3691673f1f0SChristoph Hellwig void (*free_ctrl)(struct nvme_ctrl *ctrl); 370ad22c355SKeith Busch void (*submit_async_event)(struct nvme_ctrl *ctrl); 371c5017e85SChristoph Hellwig void (*delete_ctrl)(struct nvme_ctrl *ctrl); 3721a353d85SMing Lin int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size); 37357dacad5SJay Sternberg }; 37457dacad5SJay Sternberg 375b9e03857SThomas Tai #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS 376a3646451SAkinobu Mita void nvme_fault_inject_init(struct nvme_fault_inject *fault_inj, 377a3646451SAkinobu Mita const char *dev_name); 378a3646451SAkinobu Mita void nvme_fault_inject_fini(struct nvme_fault_inject *fault_inject); 379b9e03857SThomas Tai void nvme_should_fail(struct request *req); 380b9e03857SThomas Tai #else 381a3646451SAkinobu Mita static inline void nvme_fault_inject_init(struct nvme_fault_inject *fault_inj, 382a3646451SAkinobu Mita const char *dev_name) 383a3646451SAkinobu Mita { 384a3646451SAkinobu Mita } 385a3646451SAkinobu Mita static inline void nvme_fault_inject_fini(struct nvme_fault_inject *fault_inj) 386a3646451SAkinobu Mita { 387a3646451SAkinobu Mita } 388b9e03857SThomas Tai static inline void nvme_should_fail(struct request *req) {} 389b9e03857SThomas Tai #endif 390b9e03857SThomas Tai 391f3ca80fcSChristoph Hellwig static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl) 392f3ca80fcSChristoph Hellwig { 393f3ca80fcSChristoph Hellwig if (!ctrl->subsystem) 394f3ca80fcSChristoph Hellwig return -ENOTTY; 395f3ca80fcSChristoph Hellwig return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65); 396f3ca80fcSChristoph Hellwig } 397f3ca80fcSChristoph Hellwig 39857dacad5SJay Sternberg static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector) 39957dacad5SJay Sternberg { 40057dacad5SJay Sternberg return (sector >> (ns->lba_shift - 9)); 40157dacad5SJay Sternberg } 40257dacad5SJay Sternberg 40327fa9bc5SChristoph Hellwig static inline void nvme_end_request(struct request *req, __le16 status, 40427fa9bc5SChristoph Hellwig union nvme_result result) 40515a190f7SChristoph Hellwig { 40627fa9bc5SChristoph Hellwig struct nvme_request *rq = nvme_req(req); 40727fa9bc5SChristoph Hellwig 40827fa9bc5SChristoph Hellwig rq->status = le16_to_cpu(status) >> 1; 40927fa9bc5SChristoph Hellwig rq->result = result; 410b9e03857SThomas Tai /* inject error when permitted by fault injection framework */ 411b9e03857SThomas Tai nvme_should_fail(req); 41208e0029aSChristoph Hellwig blk_mq_complete_request(req); 41315a190f7SChristoph Hellwig } 41415a190f7SChristoph Hellwig 415d22524a4SChristoph Hellwig static inline void nvme_get_ctrl(struct nvme_ctrl *ctrl) 416d22524a4SChristoph Hellwig { 417d22524a4SChristoph Hellwig get_device(ctrl->device); 418d22524a4SChristoph Hellwig } 419d22524a4SChristoph Hellwig 420d22524a4SChristoph Hellwig static inline void nvme_put_ctrl(struct nvme_ctrl *ctrl) 421d22524a4SChristoph Hellwig { 422d22524a4SChristoph Hellwig put_device(ctrl->device); 423d22524a4SChristoph Hellwig } 424d22524a4SChristoph Hellwig 42577f02a7aSChristoph Hellwig void nvme_complete_rq(struct request *req); 4267baa8572SJens Axboe bool nvme_cancel_request(struct request *req, void *data, bool reserved); 427bb8d261eSChristoph Hellwig bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl, 428bb8d261eSChristoph Hellwig enum nvme_ctrl_state new_state); 4295fd4ce1bSChristoph Hellwig int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap); 4305fd4ce1bSChristoph Hellwig int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap); 4315fd4ce1bSChristoph Hellwig int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl); 432f3ca80fcSChristoph Hellwig int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev, 433f3ca80fcSChristoph Hellwig const struct nvme_ctrl_ops *ops, unsigned long quirks); 43453029b04SKeith Busch void nvme_uninit_ctrl(struct nvme_ctrl *ctrl); 435d09f2b45SSagi Grimberg void nvme_start_ctrl(struct nvme_ctrl *ctrl); 436d09f2b45SSagi Grimberg void nvme_stop_ctrl(struct nvme_ctrl *ctrl); 4371673f1f0SChristoph Hellwig void nvme_put_ctrl(struct nvme_ctrl *ctrl); 4387fd8930fSChristoph Hellwig int nvme_init_identify(struct nvme_ctrl *ctrl); 4395bae7f73SChristoph Hellwig 4405bae7f73SChristoph Hellwig void nvme_remove_namespaces(struct nvme_ctrl *ctrl); 4411673f1f0SChristoph Hellwig 4424f1244c8SChristoph Hellwig int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len, 4434f1244c8SChristoph Hellwig bool send); 444a98e58e5SScott Bauer 4457bf58533SChristoph Hellwig void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status, 446287a63ebSChristoph Hellwig volatile union nvme_result *res); 447f866fc42SChristoph Hellwig 44825646264SKeith Busch void nvme_stop_queues(struct nvme_ctrl *ctrl); 44925646264SKeith Busch void nvme_start_queues(struct nvme_ctrl *ctrl); 45069d9a99cSKeith Busch void nvme_kill_queues(struct nvme_ctrl *ctrl); 451d6135c3aSKeith Busch void nvme_sync_queues(struct nvme_ctrl *ctrl); 452302ad8ccSKeith Busch void nvme_unfreeze(struct nvme_ctrl *ctrl); 453302ad8ccSKeith Busch void nvme_wait_freeze(struct nvme_ctrl *ctrl); 454302ad8ccSKeith Busch void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout); 455302ad8ccSKeith Busch void nvme_start_freeze(struct nvme_ctrl *ctrl); 456363c9aacSSagi Grimberg 457eb71f435SChristoph Hellwig #define NVME_QID_ANY -1 4584160982eSChristoph Hellwig struct request *nvme_alloc_request(struct request_queue *q, 4599a95e4efSBart Van Assche struct nvme_command *cmd, blk_mq_req_flags_t flags, int qid); 460f7f1fc36SMax Gurtovoy void nvme_cleanup_cmd(struct request *req); 461fc17b653SChristoph Hellwig blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req, 4628093f7caSMing Lin struct nvme_command *cmd); 46357dacad5SJay Sternberg int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, 46457dacad5SJay Sternberg void *buf, unsigned bufflen); 46557dacad5SJay Sternberg int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, 466d49187e9SChristoph Hellwig union nvme_result *result, void *buffer, unsigned bufflen, 4679a95e4efSBart Van Assche unsigned timeout, int qid, int at_head, 4686287b51cSSagi Grimberg blk_mq_req_flags_t flags, bool poll); 4691a87ee65SKeith Busch int nvme_set_features(struct nvme_ctrl *dev, unsigned int fid, 4701a87ee65SKeith Busch unsigned int dword11, void *buffer, size_t buflen, 4711a87ee65SKeith Busch u32 *result); 4721a87ee65SKeith Busch int nvme_get_features(struct nvme_ctrl *dev, unsigned int fid, 4731a87ee65SKeith Busch unsigned int dword11, void *buffer, size_t buflen, 4741a87ee65SKeith Busch u32 *result); 4759a0be7abSChristoph Hellwig int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count); 476038bd4cbSSagi Grimberg void nvme_stop_keep_alive(struct nvme_ctrl *ctrl); 477d86c4d8eSChristoph Hellwig int nvme_reset_ctrl(struct nvme_ctrl *ctrl); 47879c48ccfSSagi Grimberg int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl); 479c5017e85SChristoph Hellwig int nvme_delete_ctrl(struct nvme_ctrl *ctrl); 48057dacad5SJay Sternberg 4810e98719bSChristoph Hellwig int nvme_get_log(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, u8 lsp, 4820e98719bSChristoph Hellwig void *log, size_t size, u64 offset); 483d558fb51SMatias Bjørling 48433b14f67SHannes Reinecke extern const struct attribute_group *nvme_ns_id_attr_groups[]; 48532acab31SChristoph Hellwig extern const struct block_device_operations nvme_ns_head_ops; 48632acab31SChristoph Hellwig 48732acab31SChristoph Hellwig #ifdef CONFIG_NVME_MULTIPATH 48866b20ac0SMarta Rybczynska static inline bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl) 48966b20ac0SMarta Rybczynska { 49066b20ac0SMarta Rybczynska return ctrl->ana_log_buf != NULL; 49166b20ac0SMarta Rybczynska } 49266b20ac0SMarta Rybczynska 493b9156daeSSagi Grimberg void nvme_mpath_unfreeze(struct nvme_subsystem *subsys); 494b9156daeSSagi Grimberg void nvme_mpath_wait_freeze(struct nvme_subsystem *subsys); 495b9156daeSSagi Grimberg void nvme_mpath_start_freeze(struct nvme_subsystem *subsys); 496a785dbccSKeith Busch void nvme_set_disk_name(char *disk_name, struct nvme_ns *ns, 497a785dbccSKeith Busch struct nvme_ctrl *ctrl, int *flags); 49832acab31SChristoph Hellwig void nvme_failover_req(struct request *req); 49932acab31SChristoph Hellwig void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl); 50032acab31SChristoph Hellwig int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl,struct nvme_ns_head *head); 5010d0b660fSChristoph Hellwig void nvme_mpath_add_disk(struct nvme_ns *ns, struct nvme_id_ns *id); 50232acab31SChristoph Hellwig void nvme_mpath_remove_disk(struct nvme_ns_head *head); 5030d0b660fSChristoph Hellwig int nvme_mpath_init(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id); 5040d0b660fSChristoph Hellwig void nvme_mpath_uninit(struct nvme_ctrl *ctrl); 5050d0b660fSChristoph Hellwig void nvme_mpath_stop(struct nvme_ctrl *ctrl); 5060157ec8dSSagi Grimberg bool nvme_mpath_clear_current_path(struct nvme_ns *ns); 5070157ec8dSSagi Grimberg void nvme_mpath_clear_ctrl_paths(struct nvme_ctrl *ctrl); 50832acab31SChristoph Hellwig struct nvme_ns *nvme_find_path(struct nvme_ns_head *head); 509479a322fSSagi Grimberg 510479a322fSSagi Grimberg static inline void nvme_mpath_check_last_path(struct nvme_ns *ns) 511479a322fSSagi Grimberg { 512479a322fSSagi Grimberg struct nvme_ns_head *head = ns->head; 513479a322fSSagi Grimberg 514479a322fSSagi Grimberg if (head->disk && list_empty(&head->list)) 515479a322fSSagi Grimberg kblockd_schedule_work(&head->requeue_work); 516479a322fSSagi Grimberg } 517479a322fSSagi Grimberg 5180d0b660fSChristoph Hellwig extern struct device_attribute dev_attr_ana_grpid; 5190d0b660fSChristoph Hellwig extern struct device_attribute dev_attr_ana_state; 52075c10e73SHannes Reinecke extern struct device_attribute subsys_attr_iopolicy; 5210d0b660fSChristoph Hellwig 52232acab31SChristoph Hellwig #else 5230d0b660fSChristoph Hellwig static inline bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl) 5240d0b660fSChristoph Hellwig { 5250d0b660fSChristoph Hellwig return false; 5260d0b660fSChristoph Hellwig } 527a785dbccSKeith Busch /* 528a785dbccSKeith Busch * Without the multipath code enabled, multiple controller per subsystems are 529a785dbccSKeith Busch * visible as devices and thus we cannot use the subsystem instance. 530a785dbccSKeith Busch */ 531a785dbccSKeith Busch static inline void nvme_set_disk_name(char *disk_name, struct nvme_ns *ns, 532a785dbccSKeith Busch struct nvme_ctrl *ctrl, int *flags) 533a785dbccSKeith Busch { 534a785dbccSKeith Busch sprintf(disk_name, "nvme%dn%d", ctrl->instance, ns->head->instance); 535a785dbccSKeith Busch } 536a785dbccSKeith Busch 53732acab31SChristoph Hellwig static inline void nvme_failover_req(struct request *req) 53832acab31SChristoph Hellwig { 53932acab31SChristoph Hellwig } 54032acab31SChristoph Hellwig static inline void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl) 54132acab31SChristoph Hellwig { 54232acab31SChristoph Hellwig } 54332acab31SChristoph Hellwig static inline int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl, 54432acab31SChristoph Hellwig struct nvme_ns_head *head) 54532acab31SChristoph Hellwig { 54632acab31SChristoph Hellwig return 0; 54732acab31SChristoph Hellwig } 5480d0b660fSChristoph Hellwig static inline void nvme_mpath_add_disk(struct nvme_ns *ns, 5490d0b660fSChristoph Hellwig struct nvme_id_ns *id) 55032acab31SChristoph Hellwig { 55132acab31SChristoph Hellwig } 55232acab31SChristoph Hellwig static inline void nvme_mpath_remove_disk(struct nvme_ns_head *head) 55332acab31SChristoph Hellwig { 55432acab31SChristoph Hellwig } 5550157ec8dSSagi Grimberg static inline bool nvme_mpath_clear_current_path(struct nvme_ns *ns) 5560157ec8dSSagi Grimberg { 5570157ec8dSSagi Grimberg return false; 5580157ec8dSSagi Grimberg } 5590157ec8dSSagi Grimberg static inline void nvme_mpath_clear_ctrl_paths(struct nvme_ctrl *ctrl) 56032acab31SChristoph Hellwig { 56132acab31SChristoph Hellwig } 562479a322fSSagi Grimberg static inline void nvme_mpath_check_last_path(struct nvme_ns *ns) 563479a322fSSagi Grimberg { 564479a322fSSagi Grimberg } 5650d0b660fSChristoph Hellwig static inline int nvme_mpath_init(struct nvme_ctrl *ctrl, 5660d0b660fSChristoph Hellwig struct nvme_id_ctrl *id) 5670d0b660fSChristoph Hellwig { 56814a1336eSChristoph Hellwig if (ctrl->subsys->cmic & (1 << 3)) 56914a1336eSChristoph Hellwig dev_warn(ctrl->device, 57014a1336eSChristoph Hellwig "Please enable CONFIG_NVME_MULTIPATH for full support of multi-port devices.\n"); 5710d0b660fSChristoph Hellwig return 0; 5720d0b660fSChristoph Hellwig } 5730d0b660fSChristoph Hellwig static inline void nvme_mpath_uninit(struct nvme_ctrl *ctrl) 5740d0b660fSChristoph Hellwig { 5750d0b660fSChristoph Hellwig } 5760d0b660fSChristoph Hellwig static inline void nvme_mpath_stop(struct nvme_ctrl *ctrl) 5770d0b660fSChristoph Hellwig { 5780d0b660fSChristoph Hellwig } 579b9156daeSSagi Grimberg static inline void nvme_mpath_unfreeze(struct nvme_subsystem *subsys) 580b9156daeSSagi Grimberg { 581b9156daeSSagi Grimberg } 582b9156daeSSagi Grimberg static inline void nvme_mpath_wait_freeze(struct nvme_subsystem *subsys) 583b9156daeSSagi Grimberg { 584b9156daeSSagi Grimberg } 585b9156daeSSagi Grimberg static inline void nvme_mpath_start_freeze(struct nvme_subsystem *subsys) 586b9156daeSSagi Grimberg { 587b9156daeSSagi Grimberg } 58832acab31SChristoph Hellwig #endif /* CONFIG_NVME_MULTIPATH */ 58932acab31SChristoph Hellwig 590c4699e70SKeith Busch #ifdef CONFIG_NVM 5913dc87dd0SMatias Bjørling int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, int node); 592b0b4e09cSMatias Bjørling void nvme_nvm_unregister(struct nvme_ns *ns); 59333b14f67SHannes Reinecke extern const struct attribute_group nvme_nvm_attr_group; 59484d4add7SMatias Bjørling int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, unsigned long arg); 595c4699e70SKeith Busch #else 596b0b4e09cSMatias Bjørling static inline int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, 5973dc87dd0SMatias Bjørling int node) 598c4699e70SKeith Busch { 599c4699e70SKeith Busch return 0; 600c4699e70SKeith Busch } 601c4699e70SKeith Busch 602b0b4e09cSMatias Bjørling static inline void nvme_nvm_unregister(struct nvme_ns *ns) {}; 60384d4add7SMatias Bjørling static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, 60484d4add7SMatias Bjørling unsigned long arg) 60584d4add7SMatias Bjørling { 60684d4add7SMatias Bjørling return -ENOTTY; 60784d4add7SMatias Bjørling } 6083dc87dd0SMatias Bjørling #endif /* CONFIG_NVM */ 6093dc87dd0SMatias Bjørling 61040267efdSSimon A. F. Lund static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev) 61140267efdSSimon A. F. Lund { 61240267efdSSimon A. F. Lund return dev_to_disk(dev)->private_data; 61340267efdSSimon A. F. Lund } 614ca064085SMatias Bjørling 61557dacad5SJay Sternberg #endif /* _NVME_H */ 616