1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2023 Realtek Corporation 3 */ 4 5 #include "phy.h" 6 #include "reg.h" 7 8 static const struct rtw89_ccx_regs rtw89_ccx_regs_be = { 9 .setting_addr = R_CCX, 10 .edcca_opt_mask = B_CCX_EDCCA_OPT_MSK_V1, 11 .measurement_trig_mask = B_MEASUREMENT_TRIG_MSK, 12 .trig_opt_mask = B_CCX_TRIG_OPT_MSK, 13 .en_mask = B_CCX_EN_MSK, 14 .ifs_cnt_addr = R_IFS_COUNTER, 15 .ifs_clm_period_mask = B_IFS_CLM_PERIOD_MSK, 16 .ifs_clm_cnt_unit_mask = B_IFS_CLM_COUNTER_UNIT_MSK, 17 .ifs_clm_cnt_clear_mask = B_IFS_COUNTER_CLR_MSK, 18 .ifs_collect_en_mask = B_IFS_COLLECT_EN, 19 .ifs_t1_addr = R_IFS_T1, 20 .ifs_t1_th_h_mask = B_IFS_T1_TH_HIGH_MSK, 21 .ifs_t1_en_mask = B_IFS_T1_EN_MSK, 22 .ifs_t1_th_l_mask = B_IFS_T1_TH_LOW_MSK, 23 .ifs_t2_addr = R_IFS_T2, 24 .ifs_t2_th_h_mask = B_IFS_T2_TH_HIGH_MSK, 25 .ifs_t2_en_mask = B_IFS_T2_EN_MSK, 26 .ifs_t2_th_l_mask = B_IFS_T2_TH_LOW_MSK, 27 .ifs_t3_addr = R_IFS_T3, 28 .ifs_t3_th_h_mask = B_IFS_T3_TH_HIGH_MSK, 29 .ifs_t3_en_mask = B_IFS_T3_EN_MSK, 30 .ifs_t3_th_l_mask = B_IFS_T3_TH_LOW_MSK, 31 .ifs_t4_addr = R_IFS_T4, 32 .ifs_t4_th_h_mask = B_IFS_T4_TH_HIGH_MSK, 33 .ifs_t4_en_mask = B_IFS_T4_EN_MSK, 34 .ifs_t4_th_l_mask = B_IFS_T4_TH_LOW_MSK, 35 .ifs_clm_tx_cnt_addr = R_IFS_CLM_TX_CNT_V1, 36 .ifs_clm_edcca_excl_cca_fa_mask = B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK, 37 .ifs_clm_tx_cnt_msk = B_IFS_CLM_TX_CNT_MSK, 38 .ifs_clm_cca_addr = R_IFS_CLM_CCA_V1, 39 .ifs_clm_ofdmcca_excl_fa_mask = B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK, 40 .ifs_clm_cckcca_excl_fa_mask = B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK, 41 .ifs_clm_fa_addr = R_IFS_CLM_FA_V1, 42 .ifs_clm_ofdm_fa_mask = B_IFS_CLM_OFDM_FA_MSK, 43 .ifs_clm_cck_fa_mask = B_IFS_CLM_CCK_FA_MSK, 44 .ifs_his_addr = R_IFS_HIS_V1, 45 .ifs_t4_his_mask = B_IFS_T4_HIS_MSK, 46 .ifs_t3_his_mask = B_IFS_T3_HIS_MSK, 47 .ifs_t2_his_mask = B_IFS_T2_HIS_MSK, 48 .ifs_t1_his_mask = B_IFS_T1_HIS_MSK, 49 .ifs_avg_l_addr = R_IFS_AVG_L_V1, 50 .ifs_t2_avg_mask = B_IFS_T2_AVG_MSK, 51 .ifs_t1_avg_mask = B_IFS_T1_AVG_MSK, 52 .ifs_avg_h_addr = R_IFS_AVG_H_V1, 53 .ifs_t4_avg_mask = B_IFS_T4_AVG_MSK, 54 .ifs_t3_avg_mask = B_IFS_T3_AVG_MSK, 55 .ifs_cca_l_addr = R_IFS_CCA_L_V1, 56 .ifs_t2_cca_mask = B_IFS_T2_CCA_MSK, 57 .ifs_t1_cca_mask = B_IFS_T1_CCA_MSK, 58 .ifs_cca_h_addr = R_IFS_CCA_H_V1, 59 .ifs_t4_cca_mask = B_IFS_T4_CCA_MSK, 60 .ifs_t3_cca_mask = B_IFS_T3_CCA_MSK, 61 .ifs_total_addr = R_IFSCNT_V1, 62 .ifs_cnt_done_mask = B_IFSCNT_DONE_MSK, 63 .ifs_total_mask = B_IFSCNT_TOTAL_CNT_MSK, 64 }; 65 66 static const struct rtw89_physts_regs rtw89_physts_regs_be = { 67 .setting_addr = R_PLCP_HISTOGRAM, 68 .dis_trigger_fail_mask = B_STS_DIS_TRIG_BY_FAIL, 69 .dis_trigger_brk_mask = B_STS_DIS_TRIG_BY_BRK, 70 }; 71 72 const struct rtw89_phy_gen_def rtw89_phy_gen_be = { 73 .cr_base = 0x20000, 74 .ccx = &rtw89_ccx_regs_be, 75 .physts = &rtw89_physts_regs_be, 76 }; 77 EXPORT_SYMBOL(rtw89_phy_gen_be); 78