1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_PHY_H__ 6 #define __RTW89_PHY_H__ 7 8 #include "core.h" 9 10 #define RTW89_PHY_ADDR_OFFSET 0x10000 11 12 #define get_phy_headline(addr) FIELD_GET(GENMASK(31, 28), addr) 13 #define PHY_HEADLINE_VALID 0xf 14 #define get_phy_target(addr) FIELD_GET(GENMASK(27, 0), addr) 15 #define get_phy_compare(rfe, cv) (FIELD_PREP(GENMASK(23, 16), rfe) | \ 16 FIELD_PREP(GENMASK(7, 0), cv)) 17 18 #define get_phy_cond(addr) FIELD_GET(GENMASK(31, 28), addr) 19 #define get_phy_cond_rfe(addr) FIELD_GET(GENMASK(23, 16), addr) 20 #define get_phy_cond_pkg(addr) FIELD_GET(GENMASK(15, 8), addr) 21 #define get_phy_cond_cv(addr) FIELD_GET(GENMASK(7, 0), addr) 22 #define phy_div(a, b) ({typeof(b) _b = (b); (_b) ? ((a) / (_b)) : 0; }) 23 #define PHY_COND_BRANCH_IF 0x8 24 #define PHY_COND_BRANCH_ELIF 0x9 25 #define PHY_COND_BRANCH_ELSE 0xa 26 #define PHY_COND_BRANCH_END 0xb 27 #define PHY_COND_CHECK 0x4 28 #define PHY_COND_DONT_CARE 0xff 29 30 #define RA_MASK_CCK_RATES GENMASK_ULL(3, 0) 31 #define RA_MASK_OFDM_RATES GENMASK_ULL(11, 4) 32 #define RA_MASK_SUBCCK_RATES 0x5ULL 33 #define RA_MASK_SUBOFDM_RATES 0x10ULL 34 #define RA_MASK_HT_1SS_RATES GENMASK_ULL(19, 12) 35 #define RA_MASK_HT_2SS_RATES GENMASK_ULL(31, 24) 36 #define RA_MASK_HT_3SS_RATES GENMASK_ULL(43, 36) 37 #define RA_MASK_HT_4SS_RATES GENMASK_ULL(55, 48) 38 #define RA_MASK_HT_RATES GENMASK_ULL(55, 12) 39 #define RA_MASK_VHT_1SS_RATES GENMASK_ULL(21, 12) 40 #define RA_MASK_VHT_2SS_RATES GENMASK_ULL(33, 24) 41 #define RA_MASK_VHT_3SS_RATES GENMASK_ULL(45, 36) 42 #define RA_MASK_VHT_4SS_RATES GENMASK_ULL(57, 48) 43 #define RA_MASK_VHT_RATES GENMASK_ULL(57, 12) 44 #define RA_MASK_HE_1SS_RATES GENMASK_ULL(23, 12) 45 #define RA_MASK_HE_2SS_RATES GENMASK_ULL(35, 24) 46 #define RA_MASK_HE_3SS_RATES GENMASK_ULL(47, 36) 47 #define RA_MASK_HE_4SS_RATES GENMASK_ULL(59, 48) 48 #define RA_MASK_HE_RATES GENMASK_ULL(59, 12) 49 50 #define CFO_TRK_ENABLE_TH (2 << 2) 51 #define CFO_TRK_STOP_TH_4 (30 << 2) 52 #define CFO_TRK_STOP_TH_3 (20 << 2) 53 #define CFO_TRK_STOP_TH_2 (10 << 2) 54 #define CFO_TRK_STOP_TH_1 (00 << 2) 55 #define CFO_TRK_STOP_TH (2 << 2) 56 #define CFO_SW_COMP_FINE_TUNE (2 << 2) 57 #define CFO_PERIOD_CNT 15 58 #define CFO_TP_UPPER 100 59 #define CFO_TP_LOWER 50 60 #define CFO_COMP_PERIOD 250 61 #define CFO_COMP_WEIGHT 8 62 #define MAX_CFO_TOLERANCE 30 63 64 #define CCX_MAX_PERIOD 2097 65 #define CCX_MAX_PERIOD_UNIT 32 66 #define MS_TO_4US_RATIO 250 67 #define ENV_MNTR_FAIL_DWORD 0xffffffff 68 #define ENV_MNTR_IFSCLM_HIS_MAX 127 69 #define PERMIL 1000 70 #define PERCENT 100 71 #define IFS_CLM_TH0_UPPER 64 72 #define IFS_CLM_TH_MUL 4 73 #define IFS_CLM_TH_START_IDX 0 74 75 #define TIA0_GAIN_A 12 76 #define TIA0_GAIN_G 16 77 #define LNA0_GAIN (-24) 78 #define U4_MAX_BIT 3 79 #define U8_MAX_BIT 7 80 #define DIG_GAIN_SHIFT 2 81 #define DIG_GAIN 8 82 83 #define LNA_IDX_MAX 6 84 #define LNA_IDX_MIN 0 85 #define TIA_IDX_MAX 1 86 #define TIA_IDX_MIN 0 87 #define RXB_IDX_MAX 31 88 #define RXB_IDX_MIN 0 89 90 #define IGI_RSSI_MAX 110 91 #define PD_TH_MAX_RSSI 70 92 #define PD_TH_MIN_RSSI 8 93 #define CCKPD_TH_MIN_RSSI (-18) 94 #define PD_TH_BW160_CMP_VAL 9 95 #define PD_TH_BW80_CMP_VAL 6 96 #define PD_TH_BW40_CMP_VAL 3 97 #define PD_TH_BW20_CMP_VAL 0 98 #define PD_TH_CMP_VAL 3 99 #define PD_TH_SB_FLTR_CMP_VAL 7 100 101 #define PHYSTS_MGNT BIT(RTW89_RX_TYPE_MGNT) 102 #define PHYSTS_CTRL BIT(RTW89_RX_TYPE_CTRL) 103 #define PHYSTS_DATA BIT(RTW89_RX_TYPE_DATA) 104 #define PHYSTS_RSVD BIT(RTW89_RX_TYPE_RSVD) 105 #define PPDU_FILTER_BITMAP (PHYSTS_MGNT | PHYSTS_DATA) 106 107 enum rtw89_phy_c2h_ra_func { 108 RTW89_PHY_C2H_FUNC_STS_RPT, 109 RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT, 110 RTW89_PHY_C2H_FUNC_TXSTS, 111 RTW89_PHY_C2H_FUNC_RA_MAX, 112 }; 113 114 enum rtw89_phy_c2h_class { 115 RTW89_PHY_C2H_CLASS_RUA, 116 RTW89_PHY_C2H_CLASS_RA, 117 RTW89_PHY_C2H_CLASS_DM, 118 RTW89_PHY_C2H_CLASS_BTC_MIN = 0x10, 119 RTW89_PHY_C2H_CLASS_BTC_MAX = 0x17, 120 RTW89_PHY_C2H_CLASS_MAX, 121 }; 122 123 enum rtw89_env_monitor_result_level { 124 RTW89_PHY_ENV_MON_CCX_FAIL = 0, 125 RTW89_PHY_ENV_MON_NHM = BIT(0), 126 RTW89_PHY_ENV_MON_CLM = BIT(1), 127 RTW89_PHY_ENV_MON_FAHM = BIT(2), 128 RTW89_PHY_ENV_MON_IFS_CLM = BIT(3), 129 RTW89_PHY_ENV_MON_EDCCA_CLM = BIT(4), 130 }; 131 132 #define CCX_US_BASE_RATIO 4 133 enum rtw89_ccx_unit { 134 RTW89_CCX_4_US = 0, 135 RTW89_CCX_8_US = 1, 136 RTW89_CCX_16_US = 2, 137 RTW89_CCX_32_US = 3 138 }; 139 140 enum rtw89_phy_status_ie_type { 141 RTW89_PHYSTS_IE00_CMN_CCK = 0, 142 RTW89_PHYSTS_IE01_CMN_OFDM = 1, 143 RTW89_PHYSTS_IE02_CMN_EXT_AX = 2, 144 RTW89_PHYSTS_IE03_CMN_EXT_SEG_1 = 3, 145 RTW89_PHYSTS_IE04_CMN_EXT_PATH_A = 4, 146 RTW89_PHYSTS_IE05_CMN_EXT_PATH_B = 5, 147 RTW89_PHYSTS_IE06_CMN_EXT_PATH_C = 6, 148 RTW89_PHYSTS_IE07_CMN_EXT_PATH_D = 7, 149 RTW89_PHYSTS_IE08_FTR_CH = 8, 150 RTW89_PHYSTS_IE09_FTR_0 = 9, 151 RTW89_PHYSTS_IE10_FTR_PLCP_EXT = 10, 152 RTW89_PHYSTS_IE11_FTR_PLCP_HISTOGRAM = 11, 153 RTW89_PHYSTS_IE12_MU_EIGEN_INFO = 12, 154 RTW89_PHYSTS_IE13_DL_MU_DEF = 13, 155 RTW89_PHYSTS_IE14_TB_UL_CQI = 14, 156 RTW89_PHYSTS_IE15_TB_UL_DEF = 15, 157 RTW89_PHYSTS_IE16_RSVD16 = 16, 158 RTW89_PHYSTS_IE17_TB_UL_CTRL = 17, 159 RTW89_PHYSTS_IE18_DBG_OFDM_FD_CMN = 18, 160 RTW89_PHYSTS_IE19_DBG_OFDM_TD_CMN = 19, 161 RTW89_PHYSTS_IE20_DBG_OFDM_FD_USER_SEG_0 = 20, 162 RTW89_PHYSTS_IE21_DBG_OFDM_FD_USER_SEG_1 = 21, 163 RTW89_PHYSTS_IE22_DBG_OFDM_FD_USER_AGC = 22, 164 RTW89_PHYSTS_IE23_RSVD23 = 23, 165 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A = 24, 166 RTW89_PHYSTS_IE25_OFDM_TD_PATH_B = 25, 167 RTW89_PHYSTS_IE26_OFDM_TD_PATH_C = 26, 168 RTW89_PHYSTS_IE27_OFDM_TD_PATH_D = 27, 169 RTW89_PHYSTS_IE28_DBG_CCK_PATH_A = 28, 170 RTW89_PHYSTS_IE29_DBG_CCK_PATH_B = 29, 171 RTW89_PHYSTS_IE30_DBG_CCK_PATH_C = 30, 172 RTW89_PHYSTS_IE31_DBG_CCK_PATH_D = 31, 173 174 /* keep last */ 175 RTW89_PHYSTS_IE_NUM, 176 RTW89_PHYSTS_IE_MAX = RTW89_PHYSTS_IE_NUM - 1 177 }; 178 179 enum rtw89_phy_status_bitmap { 180 RTW89_TD_SEARCH_FAIL = 0, 181 RTW89_BRK_BY_TX_PKT = 1, 182 RTW89_CCA_SPOOF = 2, 183 RTW89_OFDM_BRK = 3, 184 RTW89_CCK_BRK = 4, 185 RTW89_DL_MU_SPOOFING = 5, 186 RTW89_HE_MU = 6, 187 RTW89_VHT_MU = 7, 188 RTW89_UL_TB_SPOOFING = 8, 189 RTW89_RSVD_9 = 9, 190 RTW89_TRIG_BASE_PPDU = 10, 191 RTW89_CCK_PKT = 11, 192 RTW89_LEGACY_OFDM_PKT = 12, 193 RTW89_HT_PKT = 13, 194 RTW89_VHT_PKT = 14, 195 RTW89_HE_PKT = 15, 196 197 RTW89_PHYSTS_BITMAP_NUM 198 }; 199 200 enum rtw89_dig_gain_type { 201 RTW89_DIG_GAIN_LNA_G = 0, 202 RTW89_DIG_GAIN_TIA_G = 1, 203 RTW89_DIG_GAIN_LNA_A = 2, 204 RTW89_DIG_GAIN_TIA_A = 3, 205 RTW89_DIG_GAIN_MAX = 4 206 }; 207 208 enum rtw89_dig_gain_lna_idx { 209 RTW89_DIG_GAIN_LNA_IDX1 = 1, 210 RTW89_DIG_GAIN_LNA_IDX2 = 2, 211 RTW89_DIG_GAIN_LNA_IDX3 = 3, 212 RTW89_DIG_GAIN_LNA_IDX4 = 4, 213 RTW89_DIG_GAIN_LNA_IDX5 = 5, 214 RTW89_DIG_GAIN_LNA_IDX6 = 6 215 }; 216 217 enum rtw89_dig_gain_tia_idx { 218 RTW89_DIG_GAIN_TIA_IDX0 = 0, 219 RTW89_DIG_GAIN_TIA_IDX1 = 1 220 }; 221 222 struct rtw89_txpwr_byrate_cfg { 223 enum rtw89_band band; 224 enum rtw89_nss nss; 225 enum rtw89_rate_section rs; 226 u8 shf; 227 u8 len; 228 u32 data; 229 }; 230 231 #define DELTA_SWINGIDX_SIZE 30 232 233 struct rtw89_txpwr_track_cfg { 234 const u8 (*delta_swingidx_5gb_n)[DELTA_SWINGIDX_SIZE]; 235 const u8 (*delta_swingidx_5gb_p)[DELTA_SWINGIDX_SIZE]; 236 const u8 (*delta_swingidx_5ga_n)[DELTA_SWINGIDX_SIZE]; 237 const u8 (*delta_swingidx_5ga_p)[DELTA_SWINGIDX_SIZE]; 238 const u8 *delta_swingidx_2gb_n; 239 const u8 *delta_swingidx_2gb_p; 240 const u8 *delta_swingidx_2ga_n; 241 const u8 *delta_swingidx_2ga_p; 242 const u8 *delta_swingidx_2g_cck_b_n; 243 const u8 *delta_swingidx_2g_cck_b_p; 244 const u8 *delta_swingidx_2g_cck_a_n; 245 const u8 *delta_swingidx_2g_cck_a_p; 246 }; 247 248 struct rtw89_phy_dig_gain_cfg { 249 const struct rtw89_reg_def *table; 250 u8 size; 251 }; 252 253 struct rtw89_phy_dig_gain_table { 254 const struct rtw89_phy_dig_gain_cfg *cfg_lna_g; 255 const struct rtw89_phy_dig_gain_cfg *cfg_tia_g; 256 const struct rtw89_phy_dig_gain_cfg *cfg_lna_a; 257 const struct rtw89_phy_dig_gain_cfg *cfg_tia_a; 258 }; 259 260 struct rtw89_phy_reg3_tbl { 261 const struct rtw89_reg3_def *reg3; 262 int size; 263 }; 264 265 #define DECLARE_PHY_REG3_TBL(_name) \ 266 const struct rtw89_phy_reg3_tbl _name ## _tbl = { \ 267 .reg3 = _name, \ 268 .size = ARRAY_SIZE(_name), \ 269 } 270 271 extern const u8 rtw89_rs_idx_max[RTW89_RS_MAX]; 272 extern const u8 rtw89_rs_nss_max[RTW89_RS_MAX]; 273 274 static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev, 275 u32 addr, u8 data) 276 { 277 rtw89_write8(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data); 278 } 279 280 static inline void rtw89_phy_write16(struct rtw89_dev *rtwdev, 281 u32 addr, u16 data) 282 { 283 rtw89_write16(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data); 284 } 285 286 static inline void rtw89_phy_write32(struct rtw89_dev *rtwdev, 287 u32 addr, u32 data) 288 { 289 rtw89_write32(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data); 290 } 291 292 static inline void rtw89_phy_write32_set(struct rtw89_dev *rtwdev, 293 u32 addr, u32 bits) 294 { 295 rtw89_write32_set(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, bits); 296 } 297 298 static inline void rtw89_phy_write32_clr(struct rtw89_dev *rtwdev, 299 u32 addr, u32 bits) 300 { 301 rtw89_write32_clr(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, bits); 302 } 303 304 static inline void rtw89_phy_write32_mask(struct rtw89_dev *rtwdev, 305 u32 addr, u32 mask, u32 data) 306 { 307 rtw89_write32_mask(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, mask, data); 308 } 309 310 static inline u8 rtw89_phy_read8(struct rtw89_dev *rtwdev, u32 addr) 311 { 312 return rtw89_read8(rtwdev, addr | RTW89_PHY_ADDR_OFFSET); 313 } 314 315 static inline u16 rtw89_phy_read16(struct rtw89_dev *rtwdev, u32 addr) 316 { 317 return rtw89_read16(rtwdev, addr | RTW89_PHY_ADDR_OFFSET); 318 } 319 320 static inline u32 rtw89_phy_read32(struct rtw89_dev *rtwdev, u32 addr) 321 { 322 return rtw89_read32(rtwdev, addr | RTW89_PHY_ADDR_OFFSET); 323 } 324 325 static inline u32 rtw89_phy_read32_mask(struct rtw89_dev *rtwdev, 326 u32 addr, u32 mask) 327 { 328 return rtw89_read32_mask(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, mask); 329 } 330 331 enum rtw89_rfk_flag { 332 RTW89_RFK_F_WRF = 0, 333 RTW89_RFK_F_WM = 1, 334 RTW89_RFK_F_WS = 2, 335 RTW89_RFK_F_WC = 3, 336 RTW89_RFK_F_DELAY = 4, 337 RTW89_RFK_F_NUM, 338 }; 339 340 struct rtw89_rfk_tbl { 341 const struct rtw89_reg5_def *defs; 342 u32 size; 343 }; 344 345 #define DECLARE_RFK_TBL(_name) \ 346 const struct rtw89_rfk_tbl _name ## _tbl = { \ 347 .defs = _name, \ 348 .size = ARRAY_SIZE(_name), \ 349 } 350 351 #define DECL_RFK_WRF(_path, _addr, _mask, _data) \ 352 {.flag = RTW89_RFK_F_WRF, \ 353 .path = _path, \ 354 .addr = _addr, \ 355 .mask = _mask, \ 356 .data = _data,} 357 358 #define DECL_RFK_WM(_addr, _mask, _data) \ 359 {.flag = RTW89_RFK_F_WM, \ 360 .addr = _addr, \ 361 .mask = _mask, \ 362 .data = _data,} 363 364 #define DECL_RFK_WS(_addr, _mask) \ 365 {.flag = RTW89_RFK_F_WS, \ 366 .addr = _addr, \ 367 .mask = _mask,} 368 369 #define DECL_RFK_WC(_addr, _mask) \ 370 {.flag = RTW89_RFK_F_WC, \ 371 .addr = _addr, \ 372 .mask = _mask,} 373 374 #define DECL_RFK_DELAY(_data) \ 375 {.flag = RTW89_RFK_F_DELAY, \ 376 .data = _data,} 377 378 void 379 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl); 380 381 #define rtw89_rfk_parser_by_cond(dev, cond, tbl_t, tbl_f) \ 382 do { \ 383 typeof(dev) __dev = (dev); \ 384 if (cond) \ 385 rtw89_rfk_parser(__dev, (tbl_t)); \ 386 else \ 387 rtw89_rfk_parser(__dev, (tbl_f)); \ 388 } while (0) 389 390 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, 391 const struct rtw89_phy_reg3_tbl *tbl); 392 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, 393 struct rtw89_channel_params *param, 394 enum rtw89_bandwidth dbw); 395 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 396 u32 addr, u32 mask); 397 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 398 u32 addr, u32 mask, u32 data); 399 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev); 400 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev); 401 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev); 402 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 403 u32 data, enum rtw89_phy_idx phy_idx); 404 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, 405 const struct rtw89_txpwr_table *tbl); 406 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, 407 const struct rtw89_rate_desc *rate_desc); 408 void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev, 409 struct rtw89_txpwr_limit *lmt, 410 u8 ntx); 411 void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev, 412 struct rtw89_txpwr_limit_ru *lmt_ru, 413 u8 ntx); 414 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, 415 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch); 416 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta); 417 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev); 418 void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta); 419 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, 420 struct ieee80211_vif *vif, 421 const struct cfg80211_bitrate_mask *mask); 422 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 423 u32 len, u8 class, u8 func); 424 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev); 425 void rtw89_phy_cfo_track_work(struct work_struct *work); 426 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, 427 struct rtw89_rx_phy_ppdu *phy_ppdu); 428 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev); 429 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev); 430 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 431 u32 val); 432 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev); 433 void rtw89_phy_dig(struct rtw89_dev *rtwdev); 434 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); 435 436 #endif 437